WO2023228635A1 - Dispositif à semi-conducteur et alimentation électrique à commutation - Google Patents

Dispositif à semi-conducteur et alimentation électrique à commutation Download PDF

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Publication number
WO2023228635A1
WO2023228635A1 PCT/JP2023/015759 JP2023015759W WO2023228635A1 WO 2023228635 A1 WO2023228635 A1 WO 2023228635A1 JP 2023015759 W JP2023015759 W JP 2023015759W WO 2023228635 A1 WO2023228635 A1 WO 2023228635A1
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Prior art keywords
voltage
boot
transistor
switch
output
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PCT/JP2023/015759
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English (en)
Japanese (ja)
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壮彦 今田
和樹 徳岡
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ローム株式会社
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents

Definitions

  • the present disclosure relates to a semiconductor device and a switching power supply using the same.
  • the present disclosure also relates to a gate drive circuit.
  • a bootstrap circuit is widely used as an internal power supply means for driving an N-channel type output transistor.
  • Patent Document 1 can be mentioned as an example of the conventional technology related to the above.
  • a gate drive circuit that drives each gate of a high-side transistor and a low-side transistor connected in series.
  • the high-side transistor as well as the low-side transistor is composed of an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • a so-called bootstrap is provided to drive the high-side transistor.
  • a boot capacitor for turning on a high-side transistor is used for the bootstrap (for example, Patent Document 2).
  • a semiconductor device includes a first driver configured to drive an output element forming a switch output stage, and a first driver that generates a boot voltage higher than a switch voltage output from the switch output stage. at least a portion of a bootstrap circuit configured to supply the voltage to the first driver; and when the output element is in an off state, a difference value between the boot voltage and the switch voltage is lower than a lower limit detection value.
  • a boot voltage detection circuit configured to charge the boot voltage by detecting that the boot voltage has turned off; and a controller configured to switch the boot voltage detection circuit between an operating state and a non-operating state. Be prepared.
  • a signal output section a second level shifter configured to be able to input the output of the first level shifter, a third level shifter configured to be able to input the high side gate control signal, and the output of the second level shifter and the third level shifter configured to input the output of the first level shifter; a first logic gate configured to be able to input the output of a level shifter; and a high side gate configured to generate a high side gate signal for driving the gate of the high side transistor based on the output of the first logic gate.
  • a signal output section, the first level shifter is configured to output the input voltage as a high level
  • the second level shifter and the third level shifter are configured such that the high side transistor and the low side transistor are connected to each other.
  • the high-side gate signal output section is configured to output a boot voltage generated at a second end of a boot capacitor having a first end connected to a connected node as a high level, and the high-side gate signal output section outputs the high-side gate signal as the high-side gate signal.
  • a boot voltage can be applied to the gate of the high-side transistor.
  • the configuration according to one aspect of the present disclosure it is possible to provide a semiconductor device that can prevent a drop in the boot voltage generated by a bootstrap circuit, and a switching power supply using the same.
  • the exemplary gate drive circuit of the present disclosure it is possible to shorten the dead time in a configuration using a boot capacitor.
  • FIG. 1 is a diagram showing the overall configuration of a switching power supply.
  • FIG. 2 is a diagram showing a first embodiment (first comparative example) of a switching power supply.
  • FIG. 3 is a diagram showing a second embodiment (second comparative example) of a switching power supply.
  • FIG. 4 is a diagram showing the switching operation of the second embodiment.
  • FIG. 5 is a diagram showing a third embodiment of the switching power supply.
  • FIG. 6 is a diagram showing the switching operation of the third embodiment.
  • FIG. 7 is a diagram showing a configuration example of a boot voltage detection circuit.
  • FIG. 8 is a diagram showing an example of the operation of the charge pump.
  • FIG. 9 is a diagram showing the configuration of a DC/DC converter according to a comparative example.
  • FIG. 9 is a diagram showing the configuration of a DC/DC converter according to a comparative example.
  • FIG. 10 is a diagram illustrating a configuration of a DC/DC converter according to an exemplary embodiment of the present disclosure.
  • FIG. 11 is a timing chart illustrating an example of operation in a gate drive circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 12 is a diagram showing the configuration of a DC/DC converter according to a modification.
  • FIG. 1 is a diagram showing the overall configuration of a switching power supply.
  • the switching power supply X0 of this configuration example is a step-down DC/DC converter that steps down the input voltage Vin (for example, 2.7 to 5.5V) to generate a desired output voltage Vout (for example, 0.6 to 4.0V). It is a DC converter.
  • the switching power supply X0 includes a semiconductor device 10, various discrete components externally attached thereto (capacitors C1 and C2, inductor L1, and resistors R1 and R2), Equipped with.
  • the semiconductor device 10 is a main body (so-called power supply control IC [integrated circuit]) that centrally controls the operation of the switching power supply X0.
  • the semiconductor device 10 includes a plurality of external terminals (pins 1 to 4 in this figure) as means for establishing electrical connection with the outside of the device.
  • the 1st pin is a power supply terminal VIN to which the input voltage Vin is applied.
  • the 2nd pin is a switch output terminal SW.
  • the third pin is a ground terminal GND.
  • the 4th pin is a feedback input terminal FB.
  • a first end of the capacitor C1 is connected to a power supply terminal VIN.
  • a second end of the capacitor C1 is connected to a ground end.
  • a first end of the inductor L1 is connected to the switch output terminal SW.
  • the second end of the inductor L1 and the first ends of the resistor R1 and capacitor C2 are all connected to the application end of the output voltage Vout.
  • the second terminals of the capacitor C2 and the resistor R2 are both connected to a ground terminal.
  • the inductor L1 and capacitor C2 function as an LC filter that rectifies and smoothes the rectangular waveform switch voltage Vsw to generate the output voltage Vout.
  • a speed-up capacitor may be connected in parallel between both ends of the resistor R1 so that the switching power supply X0 can start up smoothly.
  • the resistors R1 and R2 may be omitted and the output voltage Vout may be directly input to the feedback input terminal FB.
  • the semiconductor device 10 of this configuration example includes an error amplifier 11, a comparison circuit 12, an on-time setting circuit 13, a ripple generation circuit 14, an addition circuit 15, a drive control circuit 16, and a reference voltage generation circuit 17. , a charge pump 18, a zero-cross detection circuit 19, capacitors C3 and C4, a switch BS, an output element M1, and a synchronous rectifier M2 are integrated.
  • the error amplifier 11 generates an error voltage Vc according to the difference between the reference voltage Vref input to the non-inverting input terminal (+) and the feedback voltage Vfb input to the inverting input terminal (-). Note that the error voltage Vc increases when the feedback voltage Vfb is lower than the reference voltage Vref, and decreases when the feedback voltage Vfb is higher than the reference voltage Vref.
  • the comparison circuit 12 includes a first comparator 121 and a second comparator 122.
  • the first comparator 121 compares the slope voltage Vslp input to the inverting input terminal (-) and the error voltage Vc input to the non-inverting input terminal (+) to generate a comparison signal Sc1.
  • the comparison signal Sc1 becomes a high level when the slope voltage Vslp is lower than the error voltage Vc, and becomes a low level when the slope voltage Vslp is higher than the error voltage Vc.
  • the first comparator 121 may have a hysteresis characteristic.
  • the second comparator 122 compares the feedback voltage Vfb input to the inverting input terminal (-) and the error voltage Vc input to the non-inverting input terminal (+) to generate a comparison signal Sc2.
  • the comparison signal Sc2 becomes a high level when the feedback voltage Vfb is lower than the error voltage Vc, and becomes a low level when the feedback voltage Vfb is higher than the error voltage Vc.
  • the second comparator 122 may have hysteresis characteristics.
  • the timing at which the comparison signal Sc2 rises to high level is earlier than the timing at which the comparison signal Sc1 rises to high level.
  • the second comparator 122 may have lower responsiveness (current output capability) than the first comparator 121.
  • the on-time setting circuit 13 basically generates the switch control signal S0 so as to maintain the output element M1 in the on-state for the on-time Ton after the comparison signal Sc1 rises to a high level.
  • the on-time setting circuit 13 also has a function of ignoring the logic level of the comparison signal Sc1 for a predetermined mask period (for example, 100 ns) after the comparison signal Sc2 rises to a high level.
  • the ripple generation circuit 14 generates a ripple voltage Vr that simulates the ripple component of the output voltage Vout in synchronization with the switch control signal S0.
  • Adder circuit 15 adds ripple voltage Vr to feedback voltage Vfb to generate slope voltage Vslp.
  • the drive control circuit 16 includes a controller 161, a level shifter 162, and drivers 163 and 164 as its components.
  • the controller 161 As basic output feedback control, the controller 161 generates gate control signals S1 and S2 so that the output voltage Vout matches a desired target value using a bottom detection type on-time fixed method according to the switch control signal S0. do.
  • the controller 161 also has a function of stopping the switching drive of each of the output element M1 and the synchronous rectifier M2 when the load is light, according to the zero-crossing detection signal S9. For example, when the zero-cross detection signal S9 rises to a high level while the output element M1 is in the off state and the synchronous rectifier M2 is in the on state, the controller 161 detects that the switch voltage Vsw is at the zero-cross detection value (for example, GND ), the synchronous rectifier M2 may be turned off.
  • the zero-cross detection signal S9 rises to a high level while the output element M1 is in the off state and the synchronous rectifier M2 is in the on state
  • the controller 161 detects that the switch voltage Vsw is at the zero-cross detection value (for example, GND ), the synchronous rectifier M2 may be turned off.
  • the level shifter 162 level-shifts the gate control signal S1 to generate the gate control signal S1'.
  • the driver 163 drives the output element M1 by generating a gate drive signal G1 according to the gate control signal S1'.
  • the driver 164 drives the synchronous rectifier M2 by generating a gate drive signal G2 according to the gate control signal S2.
  • the charge pump 18 generates a boosted voltage Vcp higher than the input voltage Vin in accordance with the charge pump control signal CPON output from the controller 161, and applies this to the application terminal of the boot voltage Vb.
  • the charge pump 18 does not always maintain the boot voltage Vb at a voltage value higher than the input voltage Vin, but only needs to have a current capacity that can slightly raise the boot voltage Vb when it decreases. Therefore, as the charge pump 18, for example, an existing charge pump provided for the purpose of maintaining the boot voltage Vb during 100% duty driving of the switch output stage SWO may be used.
  • the zero cross detection circuit 19 detects synchronization by monitoring the voltage across the synchronous rectifier M2 (corresponding to the switch voltage Vsw) when the output element M1 is in the off state and the synchronous rectifier M2 is in the on state. A zero cross (reverse current) of the inductor current IL flowing through the rectifying element M2 is detected.
  • the capacitor C3 is connected between the output end of the error amplifier 11 and the ground end as a phase compensation means for preventing the error amplifier 11 from oscillating.
  • the output element M1 (for example, NMOSFET [N-channel type metal oxide semiconductor field effect transistor]) functions as an upper switch of the switch output stage SWO that generates the switch voltage Vsw from the input voltage Vin.
  • the drain of the output element M1 is connected to the power supply terminal VIN.
  • the source of the output element M1 is connected to the switch output terminal SW.
  • the gate of the output element M1 is connected to the application end of the gate drive signal G1.
  • the output element M1 is turned on when the gate drive signal G1 is at a high level, and is turned off when the gate drive signal G1 is at a low level.
  • the synchronous rectifier M2 (eg, NMOSFET) functions as a lower switch of the switch output stage SWO.
  • the drain of the synchronous rectifier M2 is connected to the switch output terminal SW.
  • the source of the synchronous rectifier M2 is connected to the ground terminal GND.
  • the gate of the synchronous rectifier M2 is connected to the application end of the gate drive signal G2.
  • the synchronous rectifier M2 is turned on when the gate drive signal G2 is at a high level, and is turned off when the gate drive signal G2 is at a low level.
  • a rectifier diode for example, a Schottky barrier diode whose cathode is connected to the switch output terminal SW and whose anode is connected to the ground terminal GND may be used instead of the synchronous rectifier M2.
  • the output element M1 and the synchronous rectifier M2 may be externally attached to the semiconductor device 10.
  • an external input terminal for the switch voltage Vsw and an external output terminal for each of the gate drive signals G1 and G2 are required.
  • a high voltage element such as an IGBT [insulated gate bipolar transistor], a SiC device, or a GaN device is used as the output element M1 and the synchronous rectifier M2. Good too.
  • the switch output stage SWO is driven in pulses between the input voltage Vin and the ground voltage PGND by complementarily turning on and off the output element M1 and the synchronous rectifier M2 connected to form a half bridge.
  • a rectangular waveform switch voltage Vsw is generated.
  • the word "complementary" in this specification refers to cases where the on/off states of output element M1 and synchronous rectifier M2 are completely reversed, as well as cases where there is a delay in the on/off transition timing of each.
  • the first end of the switch BS is connected to the power supply terminal VIN.
  • the second end of the switch BS and the first end of the capacitor C4 are both connected to the application end of the boot voltage Vb.
  • a second end of the capacitor C4 is connected to the switch output terminal SW.
  • the switch BS and capacitor C4 connected in this manner form a bootstrap circuit BST that generates a boot voltage Vb higher than the switch voltage Vsw by the voltage across the capacitor C4 and supplies it to the level shifter 162 and driver 163.
  • bootstrap circuit BST When the output element M1 is in the off state and the synchronous rectifier element M2 is in the on state, the switch BS is in the on state. Therefore, the capacitor C4 is charged by the current flowing from the application end of the input voltage Vin through the switch BS. At this time, the voltage across the capacitor C4 increases until it reaches approximately the same potential as the input voltage Vin.
  • the switch BS is in the off state. Therefore, the boot voltage Vb is raised to a potential ( ⁇ 2Vin) higher than the switch voltage Vsw ( ⁇ Vin) by the voltage across the capacitor C4 ( ⁇ Vin) in accordance with the law of conservation of charge of the capacitor C4.
  • switch BS for example, a PMOSFET [P-channel type MOSFET] configured such that the drain is connected to the power supply terminal VIN and the source is connected to the application terminal of the boot voltage Vb may be used, or , a diode configured such that its anode is connected to the power supply terminal VIN and its cathode is connected to the end to which the boot voltage Vb is applied may be used.
  • PMOSFET P-channel type MOSFET
  • the capacitor C4 is built into the semiconductor device 10. Therefore, the number of discrete components externally attached to the semiconductor device 10 can be reduced. However, compared to the case where the capacitor C4 is externally attached to the semiconductor device 10, the capacitance value of the capacitor C4 becomes smaller. Therefore, it is necessary to consider countermeasures for reducing the boot voltage Vb (details will be described later).
  • FIG. 2 is a diagram showing a first embodiment of the switching power supply X0 (corresponding to a first comparative example to be compared with a third embodiment described later).
  • the switching power supply X0 of this embodiment is based on the above-mentioned overall configuration (FIG. 1), but further includes a boot voltage detection circuit 20.
  • the boot voltage detection circuit 20 detects that the divided voltage Vbd of the boot voltage Vb has become lower than the lower limit detection voltage Vth, and generates the boot drop detection signal BU.
  • the boot voltage detection circuit 20 includes a comparator CMP and resistors R3 and R4.
  • the resistors R3 and R4 are connected in series between the application terminal of the boot voltage Vb and the ground terminal, and output a divided voltage Vbd of the boot voltage Vb from the connection node between them.
  • the comparator CMP compares the divided voltage Vbd input to the inverting input terminal (-) and the lower limit detection voltage Vth input to the non-inverting input terminal (+) to generate a boot drop detection signal BU.
  • the boot drop detection signal BU becomes a high level when the divided voltage Vbd is lower than the lower limit detection voltage Vth, and becomes a low level when the divided voltage Vbd is higher than the lower limit detection voltage Vth.
  • the comparator CMP may have a hysteresis characteristic.
  • the boot voltage detection circuit 20 of this embodiment is of a constant detection type using resistive voltage division, and a circuit current always flows from the boot voltage Vb application terminal to the ground terminal. Therefore, the boot voltage Vb tends to drop during the drive stop period of the switch output stage SWO.
  • the semiconductor device 10 reaches a high temperature (for example, 125° C. or higher), element leakage increases, so the boot voltage Vb tends to decrease.
  • a high temperature for example, 125° C. or higher
  • FIG. 3 is a diagram showing a second embodiment of the switching power supply X0 (corresponding to a second comparative example compared to a third embodiment described later).
  • the switching power supply X0 of this embodiment is based on the above-mentioned overall configuration (FIG. 1), but a gate monitoring function is added to the controller 161.
  • the controller 161 of this embodiment determines whether the gate drive signal G1 has risen to a potential sufficient to turn on the output element M1. It has a function of monitoring and detecting a drop in the boot voltage Vb.
  • the drive control circuit 16 includes a level shifter 165 configured to level shift the gate drive signal G1 to generate a gate drive signal G1' and output it to the controller 161. But that's fine.
  • FIG. 4 is a diagram showing the switching operation of the second embodiment, and in order from the top, the switch voltage Vsw (solid line), the boot voltage Vb (broken line), the gate control signal S1, the gate feedback signal G1fb, and the boot drop detection signal BU , as well as the gate control signal S2. Note that this figure shows an intermittent switching operation waveform at a light load.
  • the gate feedback signal G1fb is one of the internal signals of the controller 161. Specifically, the gate feedback signal G1fb becomes high level when the gate drive signal G1 rises to a potential sufficient to turn on the output element M1 after the gate control signal S1 rises to a high level. Furthermore, in this embodiment, the boot deterioration detection signal BU can also be understood as one of the internal signals of the controller 161.
  • the gate control signals S1 and S2 are both set to low level, so the output element M1 and the synchronous rectification element M2 are both turned off.
  • the boot voltage Vb decreases with the passage of time. Then, as shown from time t11 to t12, the boot voltage Vb eventually decreases to approximately the same potential as the switch voltage Vsw.
  • the boot voltage Vb tends to decrease.
  • the gate control signal S1 is raised to a high level.
  • the boot voltage Vb has decreased to approximately the same potential as the switch voltage Vsw
  • the gate drive signal G1 does not rise to a potential sufficient to turn on the output element M1.
  • the gate feedback signal G1fb remains at a low level.
  • the gate control signal S2 is raised to a high level as shown at times t13 to t14.
  • synchronous rectifier M2 is switched to the on state.
  • capacitor C4 is charged and boot voltage Vb increases. Therefore, from time t14 to time t15, the gate drive signal G1 can be raised to a high level due to the transition of the gate control signal S1 to a high level, so that the output element M1 is switched to the on state.
  • the ripple component of the output voltage Vout will increase.
  • the ripple component may increase significantly.
  • the gate-source voltage of the output element M1 may increase when the switch voltage Vsw decreases due to the insufficient ability of the driver 163.
  • the output element M1 may be turned on, and an excessive through current may flow through the switch output stage SWO.
  • FIG. 5 is a diagram showing a third embodiment of the switching power supply X0.
  • the switching power supply X0 of this embodiment is based on the first embodiment (FIG. 2) and second embodiment (FIG. 3), but the configuration and operation of the boot voltage detection circuit 20 are changed.
  • a boot normality detection signal BOK is generated to charge the boot voltage Vb upon detecting that it has become lower than the lower limit detection value Vdet.
  • the controller 161 drives the charge pump 18 to charge the boot voltage Vb when the boot normality detection signal BOK falls to a low level during the driving stop period of the switch output stage SWO.
  • the charge pump 18 generates a boosted voltage Vcp higher than the input voltage Vin in response to the charge pump control signal CPON output from the controller 161, and applies this to the application terminal of the boot voltage Vb. Apply.
  • the high level of the gate drive signal G1 can be raised to a potential sufficient to turn on the output element M1. Therefore, it becomes possible to restart the switching operation of the switch output stage SWO without any trouble.
  • the configuration uses the charge pump 18, there is no need to turn on the synchronous rectifier M2 extra in order to charge the boot voltage Vb. Therefore, the ripple component of the output voltage Vout can be suppressed to a small level.
  • the charge pump 18 for example, an existing charge pump provided for the purpose of maintaining the boot voltage Vb during 100% duty driving of the switch output stage SWO may be used. Such circuit sharing makes it possible to shrink the chip area of the semiconductor device 10.
  • the semiconductor device 10 does not include the charge pump 18, the synchronous rectifier M2 is turned on to charge the boot voltage Vb, as in the second embodiment (see FIGS. 3 and 4). Any configuration may be adopted.
  • the controller 161 has a function of generating a boot detection control signal BUON to switch the boot voltage detection circuit 20 between an operating state and a non-operating state.
  • the boot voltage detection circuit 20 is activated only when a certain condition (details will be described later) is met. Therefore, unlike the first embodiment (FIG. 2) described above, the circuit current does not always flow from the end to which the boot voltage Vb is applied toward the ground end, making it possible to suppress a drop in the boot voltage Vb. Further, it can also contribute to lower current consumption of the boot voltage detection circuit 20 (and by extension, the semiconductor device 10).
  • FIG. 6 is a diagram showing the switching operation of the third embodiment, and in order from the top, switch voltage Vsw (solid line), boot voltage Vb (broken line), comparison signals Sc2 and Sc1, wake signal WAKE, deep signal DEEP, boot A detection control signal BUON and a normal boot detection signal BOK are depicted.
  • the boot voltage Vb has a voltage value higher than the switch voltage Vsw by the voltage across the capacitor C4.
  • the switch BS of the bootstrap circuit BST is also in the on state. Therefore, the capacitor C4 is charged by the current flowing from the application end of the input voltage Vin through the switch BS, so that the boot voltage Vb increases.
  • the boot voltage Vb has a voltage value higher than the switch voltage Vsw by the voltage across the capacitor C4.
  • the boot voltage Vb decreases due to natural discharge or high temperature leakage.
  • the wake signal WAKE is a logic signal indicating whether the switching power supply X0 is in a light load state.
  • the deep signal DEEP is a logic signal that indicates whether the switching power supply X0 is in a no-load state (or a very light load state).
  • the deep signal DEEP is generated by the wake signal WAKE during the no-load determination period T2 after the zero cross of the inductor current IL flowing through the synchronous rectifier M2 is detected, as shown at time t21 to t22. It becomes high level when it is maintained at low level throughout.
  • the timing at which the comparison signal Sc2 rises to a high level is earlier than the timing at which the comparison signal Sc1 rises to a high level.
  • the controller 161 sets the boot voltage detection period T1 and puts the boot voltage detection circuit 20 into the operating state before switching the output element M1 to the on state. For example, in this figure, as shown from time t23 to t24 or from time t26 to t27, a boot voltage detection period T1 of a predetermined length (for example, 100 ns) is set after the comparison signal Sc2 rises to a high level, and the boot The detection control signal BUON is set at high level.
  • a boot voltage detection period T1 of a predetermined length for example, 100 ns
  • the method for setting the boot voltage detection period T1 is not limited to the above.
  • the controller 161 outputs the comparison signal Sc2 ( Furthermore, the boot voltage detection period T1 may be provided when the wake signal WAKE) rises to a high level.
  • the boot detection control signal BUON remains at a low level even after the comparison signal Sc2 rises to a high level, as shown at time t20.
  • the boot normality detection signal BOK falls to low level.
  • the boot normality detection signal BOK falls to a low level after a predetermined delay time d ( ⁇ T1) has elapsed after the boot detection control signal BUON rose to a high level.
  • the start of charging the boot voltage Vb is on standby until the boot voltage detection period T1 of a predetermined length expires after the boot normality detection signal BOK falls to a low level.
  • the charging start timing of the boot voltage Vb is not limited to this.
  • the charging operation of the boot voltage Vb may be started without delay when the boot normality detection signal BOK falls to a low level.
  • the controller 161 After starting charging the boot voltage Vb in response to a low level transition of the boot normal detection signal BOK, the controller 161 maintains the boot detection control signal BUON at a high level at least until the boot voltage Vb exceeds the lower limit detection value Vdet. It's good to do that. As a result, the boot voltage detection circuit 20 is maintained in an operating state, so that it is possible to continue monitoring whether the boot voltage Vb has recovered.
  • the series of reboot operations described above are not performed after a problem occurs in the on-transition of the output element M1, but when the boot voltage Vb and the switch voltage Vsw This is carried out by detecting that the difference value (Vb-Vsw) has become lower than the lower limit detection value Vdet. Therefore, compared to the previously mentioned second embodiment (FIG. 4), the on-timing of the output element M1 is less likely to be delayed, so that the amount of decrease in the output voltage Vout can be suppressed.
  • the synchronous rectifier M2 is turned on to charge the capacitor C4. It never happens. Therefore, compared to the previously mentioned second embodiment (FIG. 4), it is possible to further suppress a decrease in the output voltage Vout.
  • FIG. 7 is a diagram showing an example of the configuration of the boot voltage detection circuit 20.
  • the boot voltage detection circuit 20 of this configuration example includes transistors P1 to P7 (for example, PMOSFET), transistors N1 to N7 (for example, NMOSFET), inverters INV1 to INV4, and resistors R10 to R13.
  • resistor R10 corresponds to a gate resistor.
  • Resistors R11 and R12 correspond to a first resistance and a second resistance, respectively.
  • Transistors P1 and P2 correspond to a first transistor and a second transistor, respectively.
  • Transistors N1 and N2 correspond to a third transistor and a fourth transistor, respectively.
  • the first end of the resistor R11 is connected to the application end of the boot voltage Vb.
  • a second end of the resistor R11 is connected to the source of the transistor P1.
  • a first end of the resistor R10 is connected to an application end of the switch voltage Vsw.
  • a second end of the resistor R10 is connected to the gate of the transistor P1.
  • the drain of transistor P1 is connected to the drain of transistor N1.
  • the source of the transistor P2 and the gate of the transistor N1 are both connected to the application terminal of the input voltage Vin.
  • the drain of the transistor P2, the source of the transistor N1, and the first end of the resistor R12 are all connected to the application end of the node voltage Vx.
  • a second end of the resistor R12 is connected to the drain of the transistor N2.
  • the source of transistor N2 is connected to the ground terminal.
  • the input end of the inverter INV1 is connected to the application end of the boot detection control signal BUON.
  • the output end of the inverter INV1 is connected to the input end of the inverter INV2.
  • the output terminal of inverter INV3 is connected to the input terminal of inverter INV4.
  • the drain and gate of the transistor N3 and the sources of each of the transistors P5 to P7 are both connected to the application terminal of the input voltage Vin.
  • the source of transistor N3 and the drain of transistor P6 are both connected to the source of transistor P3.
  • the drain of transistor P3 is connected to the source of transistor P4.
  • the drains of the transistors P4 and N4, the gates of the transistors N6, N7, and P7, and the first end of the resistor R13 are all connected to the application end of the node voltage Vy.
  • the drain of transistor P5 is connected to the drain of transistor N6.
  • the sources of transistors N4 and N6 are both connected to the drain of transistor N5.
  • the sources of the transistors N5 and N7, the gate of the transistor P5, and the second end of the resistor R13 are all connected to the ground terminal.
  • the gates of transistors P3, P4, N4, and N5 are all connected to the terminal to which node voltage Vx is applied.
  • the gate of the transistor P6 and the drains of the transistors P7 and N7 are both connected to the application terminal of the boot normality detection signal BOK.
  • the controller 161 sets the boot detection control signal BUON to a low level when placing the boot voltage detection circuit 20 in a non-operating state.
  • the boot detection control signal BUON is at a low level
  • both gate voltages GP2 and GN2 are at a low level, so the transistor P2 is turned on and the transistor N2 is turned off. Become.
  • the transistor N1 is also turned off. In this way, when the boot detection control signal BUON is at a low level, a current path from the application terminal of the boot voltage Vb to the ground terminal via the resistor R11, transistor P1, transistor N1, resistor R12, and transistor N2 is established. Be cut off. As a result, a decrease in boot voltage Vb is suppressed.
  • the resistor R13 is used to fix the node voltage Vy to a low level in a situation where the terminal to which the node voltage Vy is applied may be floating in potential, and by extension, to fix the boot normality detection signal BOK to a high level. Functions as a pull-down resistor.
  • the controller 161 sets the boot detection control signal BUON to a high level when putting the boot voltage detection circuit 20 into the operating state.
  • the boot detection control signal BUON is at a high level
  • the gate voltages GP2 and GN2 are both at a high level, so the transistor P2 is turned off and the transistor N2 is turned on. .
  • the boot detection control signal BUON when the boot detection control signal BUON is at a high level, the current path from the application terminal of the boot voltage Vb to the ground terminal via the resistor R11, the transistor P1, the transistor N1, the resistor R12, and the transistor N2 becomes conductive. be done. That is, the detection operation of the boot voltage Vb is started.
  • the method for setting the lower limit detection value Vdet is not limited to the above, and, for example, the lower limit detection value Vdet may be set using only the diode connection of the transistor P1.
  • the node voltage Vx When the node voltage Vx is at a high level ( ⁇ I2 ⁇ R12), the node voltage Vy is at a low level, and as a result, the boot normality detection signal BOK is at a high level.
  • the node voltage Vx is at a low level ( ⁇ GND)
  • the node voltage Vy becomes a high level
  • the transistors P3 to P5 and N4 to N6 form an inverter with hysteresis. Therefore, the boot normality detection signal BOK is prevented from returning to the high level at the moment the boot normality detection signal BOK falls to a low level and the charge pump 18 starts charging the boot voltage Vb.
  • the transistor N1 functions as a breakdown voltage protection clamper for limiting the node voltage Vx to a predetermined upper limit value or less ( ⁇ Vin ⁇ Vgsn, where Vgsn is the on-threshold voltage of the transistor N1). Note that the transistor N1 has a high breakdown voltage between its drain and backgate, so it has a circuit configuration (so-called self-suspension) in which the backgate is connected to the source.
  • the transistor N3 functions as a breakdown voltage protection clamper to limit the drain voltage of the transistor P3 to a predetermined upper limit value or less ( ⁇ Vin ⁇ Vgsn, where Vgsn is the on-threshold voltage of the transistor N3). Note that the transistor N3 also requires a self-suspending high voltage element in accordance with the input range of the node voltage Vx.
  • the transistor P6 is turned off when the node voltage Vx is at a high level (and when the normal boot detection signal BOK is at a high level). On the other hand, when the node voltage Vx is at a low level, the transistor P6 is turned on to match the input range of the inverter with hysteresis that receives the node voltage Vx.
  • this figure illustrates the circuit specifications assuming a low-voltage type model, it can also be applied to a high-voltage type model.
  • FIG. 8 is a diagram showing an example of the operation of the charge pump 18. From the top, the output voltage Vout, the switch voltage Vsw, the boot voltage Vb, the wake signal WAKE, the deep signal DEEP, the comparison signals Sc2 and Sc1, and the boot detection control The signal BUON, the boot normality detection signal BOK, the charge pump control signal CPON, and the driving clock signal CLK of the charge pump 18 are depicted.
  • the charge pump control signal CPON rises to a high level without delay.
  • pulse driving of the drive clock signal CLK is started, and the charging operation of the boot voltage Vb by the charge pump 18 is performed.
  • FIG. 9 is a diagram showing the configuration of a DC/DC converter X according to a comparative example.
  • the DC/DC converter X shown in FIG. 9 is a step-down DC/DC converter that converts the input voltage PVIN to the output voltage Vout.
  • the DC/DC converter X includes a semiconductor device 1, a boot capacitor Cb, an inductor L, and an output capacitor Cout.
  • the boot capacitor Cb, the inductor L, and the output capacitor Cout are elements provided outside the semiconductor device 1.
  • the semiconductor device 1 includes an integrated gate drive circuit 9, a high-side transistor HM, and a low-side transistor LM.
  • the gate drive circuit 9 is a circuit for driving the gate of the high-side transistor HM and the gate of the low-side transistor LM.
  • the semiconductor device 1 includes an input voltage terminal Tin, a boot terminal Tb, a switch terminal Tsw, and a ground terminal Tgnd as external terminals for establishing electrical connection with the outside.
  • the gate drive circuit 9 includes a logic section 2, a level shifter 3, a high side driver 4, a low side driver 5, a switch voltage detection section 6, and a boot switch 7.
  • the high-side transistor HM and the low-side transistor LM are both constructed from NMOS transistors (N-channel MOSFETs).
  • the drain of the high-side transistor HM is connected to the application terminal of the input voltage PVIN via the input voltage terminal Tin.
  • the source of the high-side transistor HM is connected to the drain of the low-side transistor LM.
  • the source of the low-side transistor LM is connected to a ground potential application terminal via a ground terminal Tgnd. That is, the high-side transistor HM and the low-side transistor LM are connected in series between the input voltage PVIN and the ground potential.
  • a so-called half bridge is constituted by the high side transistor HM and the low side transistor LM.
  • a node Nsw to which the source of the high-side transistor HM and the drain of the low-side transistor LM are connected is connected to one end of the inductor L via the switch terminal Tsw.
  • the other end of the inductor L is connected to one end of the output capacitor Cout.
  • the other end of the output capacitor Cout is connected to a ground potential application end.
  • An output voltage Vout is generated at one end of the output capacitor Cout.
  • the logic section 2 includes an AND circuit 21 and an AND circuit 22.
  • a high side gate control input signal HGCTL_IN is input to a first input terminal of the AND circuit 21 .
  • a low-side gate signal LG applied to the gate of the low-side transistor LM is input to a second input terminal of the AND circuit 21 as a low-side feedback signal LGFB.
  • the AND circuit 21 performs a logical product of the high-side gate control input signal HGCTL_IN and the logically inverted low-side feedback signal LGFB, and outputs the high-side gate control signal HGCTL.
  • the level shifter 3 converts the level of the high-side gate control signal HGCTL into a level-shifted high-side gate control signal HGCTL_LVS in which the boot voltage BOOT is at a high level and the switch voltage SW is at a low level, and outputs the level-shifted high-side gate control signal HGCTL_LVS. Specifically, when the high-side gate control signal HGCTL is at a high level, the level-shifted high-side gate control signal HGCTL_LVS is at a high level, and when the high-side gate control signal HGCTL is at a low level, the level-shifted high-side gate control signal HGCTL_LVS is at a high level. The signal HGCTL_LVS becomes low level.
  • the high-side driver 4 generates a high-side gate signal HG to be applied to the gate of the high-side transistor HM based on the input level-shifted high-side gate control signal HGCTL_LVS. Specifically, when the level-shifted high-side gate control signal HGCTL_LVS is at a high level, the high-side gate signal HG of the boot voltage BOOT is applied as a high level to the gate of the high-side transistor HM, and the high-side transistor HM is turned on. becomes.
  • the high-side gate signal HG of the switch voltage SW is applied to the gate of the high-side transistor HM as a low level, and the high-side transistor HM is turned off.
  • a bootstrap is constructed from the boot capacitor Cb and the boot switch 7. One end of the boot capacitor Cb is connected to the switch terminal Tsw. The other end of boot capacitor Cb is connected to boot terminal Tb.
  • a boot switch 7 that can be turned on and off is connected between the input voltage terminal Tin and the boot terminal Tb.
  • the boot switch 7 When the low-side transistor LM is in the on state, the boot switch 7 is controlled to be in the on state, and the boot capacitor Cb is charged with the input voltage PVIN. When the low-side transistor LM is in the off state, the boot switch 7 is controlled to be in the off state.
  • the boot voltage BOOT is higher than the switch voltage SW generated at the switch terminal Tsw. Therefore, by applying the high-side gate signal HG set as the boot voltage BOOT to the gate of the high-side transistor HM by the high-side driver 4, the high-side transistor HM can be turned on.
  • a low-side gate control input signal LGCTL_IN is input to the first input terminal of the AND circuit 22.
  • a detection signal SWFB output from the switch voltage detection section 6 is input to a second input terminal of the AND circuit 22 .
  • the switch voltage detection section 6 is a circuit that detects the turn-off of the high-side transistor HM by detecting the switch voltage SW that decreases when the high-side transistor HM is turned off.
  • the AND circuit 22 performs a logical product of the low-side gate control input signal LGCTL_IN and the logically inverted detection signal SWFB, and outputs the low-side gate control signal LGCTL.
  • the low-side driver 5 generates a low-side gate signal LG to be applied to the gate of the low-side transistor LM based on the input low-side gate control signal LGCTL. Specifically, when the low-side gate control signal LGCTL is at a high level, the low-side gate signal LG of the input voltage PVIN at a high level is applied to the gate of the low-side transistor LM, and the low-side transistor LM is turned on. When the low-side gate control signal LGCTL is at the low level, the low-side gate signal LG at the ground potential is applied to the gate of the low-side transistor LM, and the low-side transistor LM is turned off.
  • the switching of the high-side transistor HM and the low-side transistor LM is controlled in a complementary manner.
  • Complementary means that one is in the on state while the other is in the off state. However, at the time of switching transition, a dead time (simultaneous off period) is provided.
  • the operation when the high-side transistor HM is in the off state and the low-side transistor LM is in the on state is transitioned to the high-side transistor HM in the on state and the low-side transistor LM in the off state.
  • the high-side gate control input signal HGCTL_IN switches from low level to high level
  • the low-side gate control input signal LGCTL_IN switches from high level to low level.
  • the low side gate signal LG falls to a low level (ground potential)
  • the low side transistor LM is turned off
  • the high side transistor HM and the low side transistor LM are both turned off, and dead time starts.
  • the high side gate control signal HGCTL output from the AND circuit 21 switches to high level, and the high side gate signal HG becomes high level. As a result, the high side transistor HM is turned on and the dead time ends.
  • FIG. 10 is a diagram illustrating a configuration of a DC/DC converter Y according to an exemplary embodiment of the present disclosure.
  • the differences between the configuration of the DC/DC converter Y and the configuration of the above-mentioned comparative example (FIG. 9) will be mainly explained.
  • the DC/DC converter Y includes a semiconductor device 1, an inductor L, and an output capacitor Cout.
  • the boot capacitor Cb is built into the semiconductor device 1, unlike the comparative example. As a result, the semiconductor device 1 is not provided with the boot terminal Tb.
  • the semiconductor device 1 has a built-in gate drive circuit 9.
  • the gate drive circuit 9 includes a logic section 2, a level shifter 3, a high side driver 4, a low side driver 5, a switch voltage detection section 6, a boot switch 7, and a level shifter 8.
  • the low-side driver 5 includes an AND circuit 51, an inverter 52, and a low-side gate signal output section 53.
  • a low-side gate control signal LGCTL output from the logic section 2 is input to a first input terminal of the AND circuit 51 .
  • a detection signal SWFB output from the switch voltage detection section 6 is input to a second input terminal of the AND circuit 51.
  • the AND circuit 51 performs a logical product of the low-side gate control signal LGCTL and the logically inverted detection signal SWFB, and outputs the low-side input signal LG_IN.
  • the inverter 52 inverts the level of the input low-side input signal LG_IN and outputs the low-side feedback signal XLGFB.
  • the low-side feedback signal XLGFB sets the input voltage PVIN to a high level and sets the ground potential to a low level.
  • the AND circuit 51 and the inverter 52 constitute a level shifter 5A.
  • the low-side gate signal output section 53 inverts the level of the low-side feedback signal XLGFB and outputs the low-side gate signal LG.
  • the low-side gate signal LG is applied to the gate of the low-side transistor LM.
  • the level shifter 8 converts the level of the low-side feedback signal XLGFB into a level-shifted low-side feedback signal XLGFB_LVS in which the boot voltage BOOT is at a high level and the switch voltage SW is at a low level, and outputs the level-shifted low-side feedback signal XLGFB_LVS. Specifically, when the low-side feedback signal XLGFB is at a high level, the level-shifted low-side feedback signal XLGFB_LVS is at a high level, and when the low-side feedback signal XLGFB is at a low level, the level-shifted low-side feedback signal XLGFB_LVS is at a low level.
  • the high-side driver 4 includes a logic gate 41, a high-side gate signal output section 42, an AND circuit 43, and a switch 44.
  • the logic gate 41 is composed of an AND circuit.
  • a level-shifted high-side gate control signal HGCTL_LVS output from the level shifter 3 is input to a first input terminal of the logic gate 41 .
  • a level-shifted low-side feedback signal XLGFB_LVS is input to the second input terminal of the logic gate 41.
  • Logic gate 41 outputs high side input signal HG_IN.
  • the high side gate signal output section 42 generates a high side gate signal HG based on the input high side input signal HG_IN.
  • High side gate signal HG is applied to the gate of high side transistor HM.
  • the high-side gate signal HG becomes the boot voltage BOOT at a high level
  • the high-side gate signal HG is The switch voltage SW becomes a low level.
  • the precharge function is a function that charges the gate of the high-side transistor HM in advance before turning on the high-side transistor HM, as will be described later.
  • the level-shifted high-side gate control signal HGCTL_LVS is input to the first input terminal of the AND circuit 43.
  • a high-side input signal HG_IN is input to the second input terminal of the AND circuit 43.
  • the AND circuit 43 performs a logical product of the level-shifted high-side gate control signal HGCTL_LVS and the logically inverted version of the high-side input signal HG_IN.
  • Switch 44 is connected between the application terminal of input voltage PVIN and the gate of high-side transistor HM. The switch 44 is turned on and off according to the output of the AND circuit 43.
  • FIG. 11 is a timing chart showing an example of operation in such a transition state.
  • the switch voltage SW high side gate control signal HGCTL, level shifted high side gate control signal HGCTL_LVS, low side gate control signal LGCTL, low side feedback signal XLGFB, low side gate signal LG, level shifted
  • the waveforms of the low-side feedback signal XLGFB_LVS, the high-side input signal HG_IN, and the high-side gate signal HG are shown.
  • the high-side gate control signal HGCTL switches from low level to high level
  • the low-side gate control signal LGCTL switches from high level to low level.
  • the low-side input signal LG_IN switches to low level
  • the low-side feedback signal XLGFB switches to high level.
  • the low-side feedback signal XLGFB rises to a high level at timing t2 delayed by delay time td3_1 from timing t1.
  • the delay time td3_1 is the delay time between input and output at the level shifter 5A.
  • the delay time td3_2 is a delay time between input and output at the low side gate signal output section 53.
  • the low-side transistor LM is turned off and enters the off state. Therefore, both the high-side transistor HM and the low-side transistor LM are turned off, and dead time DT starts from timing t3. Note that at this time, since the current flowing through the inductor L toward the load side flows through the body diode of the low-side transistor LM, the switch voltage SW decreases to a negative voltage.
  • the level-shifted high-side gate control signal HGCTL_LVS rises to a high level.
  • the level-shifted high-side gate control signal HGCTL_LVS rises to a high level at timing t4 delayed by delay time td1 from timing t1.
  • the delay time td1 is the delay time between input and output of the level shifter 3.
  • the output of the AND circuit 43 switches to a high level because the high-side input signal HG_IN is at a low level.
  • the switch 44 changes from the off state to the on state, and charging of the gate of the high-side transistor HM by the input voltage PVIN is started.
  • the high side gate signal HG rises to the input voltage PVIN.
  • the level-shifted low-side feedback signal XLGFB_LVS rises to a high level.
  • the level-shifted low-side feedback signal XLGFB_LVS rises at timing t5 delayed by delay time td2 from timing t2.
  • the delay time td2 is the delay time between input and output of the level shifter 8.
  • BOOT boot voltage
  • the high-side transistor HM turns on, and the switch voltage SW rises to the input voltage PVIN.
  • the dead time DT ends.
  • the delay time td4_2 from timing t6 to timing t7 when the high-side gate signal HG reaches the boot voltage BOOT is a delay time in the high-side gate signal output section 42.
  • the gate of the high-side transistor HM is charged in advance before the high-side transistor HM is turned on by the precharge function using the input voltage PVIN, charge loss in the boot capacitor Cb can be suppressed. Therefore, the capacitance of the boot capacitor Cb can be reduced, making it suitable for the boot capacitor Cb built into the semiconductor device 1.
  • the precharge function will not function unless the timing at which the level-shifted high-side gate control signal HGCTL_LVS rises to a high level is before the timing at which the level-shifted low-side feedback signal XLGFB_LVS rises to a high level. Therefore, it is necessary to satisfy td1 ⁇ td3_1+td2.
  • FIG. 12 is a diagram showing the configuration of a DC/DC converter Z according to a modification example of the present disclosure.
  • a delay circuit 45 is added to the high side driver 4 as a difference from the previously described embodiment (FIG. 10).
  • Delay circuit 45 is provided between AND circuit 43 and switch 44.
  • the switch 44 can be turned on at a timing delayed by a predetermined delay time after the level-shifted high-side gate control signal HGCTL_LVS rises to a high level, and precharging can be started. This allows the precharge start timing to be adjusted.
  • td3_1+td3_2 which determines the timing at which the low-side transistor LM turns off, becomes longer due to not only element delay but also wiring delay, the switch 44 is turned on in order to suppress simultaneous turning on of the high-side transistor HM and the low-side transistor LM. It would be useful to have the ability to adjust the timing.
  • a semiconductor device includes a first driver configured to drive an output element forming a switch output stage, and a boot voltage higher than a switch voltage output from the switch output stage. at least a portion of a bootstrap circuit configured to generate and supply the voltage to the first driver; and when the output element is in an off state, a difference value between the boot voltage and the switch voltage is lower than a lower limit detection value.
  • a boot voltage detection circuit configured to charge the boot voltage upon detecting that the boot voltage has become low; and a boot voltage detection circuit configured to switch the boot voltage detection circuit between an operating state and a non-operating state.
  • the configuration includes a controller (first configuration).
  • the controller provides a predetermined boot voltage detection period before switching the output element and the rectifier forming the switch output stage from an OFF state to an ON state.
  • a configuration (second configuration) may be adopted in which the boot voltage detection circuit is put into an operating state.
  • the controller is configured to provide the voltage detection period when both the output element and the rectifier are in an off state for a no-load determination period (a third configuration). configuration).
  • the controller may cause at least the boot voltage to exceed the lower limit detection value after charging of the boot voltage is started according to the detection result of the boot voltage detection circuit.
  • a configuration (fourth configuration) may be adopted in which the operating state of the boot voltage detection circuit is maintained until the operation.
  • the rectifying element may be a synchronous rectifying element configured to be driven complementary to the output element (fifth configuration). good.
  • the semiconductor device further includes a second driver configured to drive the synchronous rectifier, and the controller drives the output element and the synchronous rectifier in a complementary manner and outputs the output.
  • a second driver configured to drive the synchronous rectifier
  • the controller drives the output element and the synchronous rectifier in a complementary manner and outputs the output.
  • the boot voltage detection circuit detects that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value, and A configuration (seventh configuration) may be adopted in which the switch is turned on.
  • the boot voltage detection circuit detects that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value;
  • a configuration (eighth configuration) may be adopted in which a boosted voltage higher than the input voltage input to the switch output stage is applied to the boot voltage application terminal.
  • the boot voltage detection circuit includes a first resistor and a second resistor, a gate resistor, a P-channel type first transistor and a second transistor, and an N-channel type transistor. a third transistor and a fourth transistor, a first end of the first resistor is connected to the application end of the boot voltage, and a second end of the first resistor is connected to the first end of the first transistor. A first end of the gate resistor is connected to the application end of the switch voltage, a second end of the gate resistor is connected to the gate of the first transistor, and the second end of the gate resistor is connected to the gate of the first transistor.
  • the drain of the first transistor is connected to the drain of the third transistor, and the source of the second transistor and the gate of the third transistor are both applied to an input voltage input to the switch output stage.
  • the drain of the second transistor, the source of the third transistor, and the first end of the second resistor are all connected to a node voltage application terminal, and the drain of the second transistor is connected to the node voltage application terminal.
  • the second end is connected to the drain of the fourth transistor, the source of the fourth transistor is connected to the ground terminal, and the boot voltage detection circuit generates a boot normality detection signal according to the node voltage.
  • the controller is configured to turn off the second transistor and turn on the fourth transistor when the boot voltage detection circuit is in an operating state, and to set the second transistor in an on state when the boot voltage detection circuit is in an inactive state.
  • a configuration may be adopted in which the second transistor is in an on state and the fourth transistor is in an off state.
  • the switching power supply disclosed in this specification includes a semiconductor device according to any one of the first to ninth configurations, and drives the switch output stage to generate a desired output voltage from the input voltage.
  • the configuration (10th configuration) is as follows.
  • the gate drive circuit (2) includes a high-side transistor (HM) and a low-side transistor connected in series between an input voltage (PVIN) application end and a ground potential application end.
  • a low side gate signal output section (53) configured to generate a low side gate signal (LG) for driving the gate of the low side transistor, and a second level shifter (8) configured to be able to receive the output of the first level shifter.
  • a third level shifter (3) configured to be able to input a high side gate control signal (HGCTL), and a first logic gate configured to be configured to receive the output of the second level shifter and the output of the third level shifter.
  • a high-side gate signal output section (42) configured to generate a high-side gate signal (HG) for driving the gate of the high-side transistor based on the output of the first logic gate;
  • the first level shifter is configured to output the input voltage as a high level
  • the second level shifter and the third level shifter are configured to connect the high side transistor and the low side transistor to a node
  • the high-side gate signal output section is configured to output, as a high level, a boot voltage (BOOT) generated at a second end of a boot capacitor (Cb) having a first end connected to the high-side
  • the boot voltage can be applied to the gate of the high-side transistor as a gate signal (eleventh configuration).
  • the first level shifter (5A) further includes a switch voltage detection section (6) configured to detect a decrease in the switch voltage (SW) occurring at the node (Nsw). , a second logic gate (51) configured to be able to input the low side gate control signal (LGCTL) and the detection signal (SWFB) of the switch voltage detection section; and a second logic gate (51) configured to be able to input the output of the second logic gate. (12th configuration).
  • a third logic gate (43) configured to be able to input the output of the third level shifter (3) and the output of the first logic gate (41), and a power supply voltage a switch (44) connected between the application terminal of (PVIN) and the gate of the high-side transistor (HM) and configured to be turned on and off based on the output of the third logic gate; It is good also as a structure further provided (13th structure).
  • the power supply voltage is preferably the input voltage (PVIN) (fourteenth configuration).
  • a delay time between input and output in the first level shifter (5A) is td3_1
  • a delay time in the low side gate signal output section (53) is td3_2
  • a delay time in the third level shifter (5A) is td3_1. It is also possible to adopt a configuration in which td3_1+td3_2 ⁇ td1 holds, assuming that the delay time between input and output in (3) is td1 (fifteenth configuration).
  • the delay time between input and output at the first level shifter (5A) is td3_1
  • the delay time between input and output at the third level shifter (3) is td1.
  • the delay time between input and output of the second level shifter (8) may be td2, and a configuration may be adopted in which td1 ⁇ td3_1+td2 holds true (sixteenth configuration).
  • the second level shifter (8) and the third level shifter (3) may have the same configuration (seventeenth configuration).
  • a configuration may further include a delay circuit (45) connected between the third logic gate (43) and the switch (44). 18 configurations).
  • a semiconductor device (1) includes a built-in gate drive circuit (10) having any one of the thirteenth to eighteenth configurations and the boot capacitor (Cb). 19th configuration).
  • a DC/DC converter (Y) includes a gate drive circuit (10) having any of the first to eighth configurations, the high side transistor (HM), and the low side transistor. (LM), an inductor (L) having a first end connected to a node (Nsw) to which the high-side transistor and the low-side transistor are connected, and an output capacitor (L) connected to the second end of the inductor. Cout) and (20th configuration).
  • the present disclosure can be applied not only to a DC/DC converter but also to driving a transistor in an inverter circuit that performs DC/AC conversion.

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Un dispositif à semi-conducteur 10 comprend, par exemple, ce qui suit : un premier circuit d'attaque 163 configuré pour attaquer un élément de sortie M1 qui forme une étape de sortie de commutateur SWO ; au moins une partie d'un circuit d'amorçage BST configuré pour générer une tension de démarrage Vb qui est supérieure à une tension de commutation Vsw délivrée en sortie par l'étage de sortie de commutation SWO, et pour fournir la tension de démarrage au premier circuit d'attaque 163 ; un circuit de détection de tension de démarrage 20 configuré pour détecter qu'une valeur différentielle (= Vb-Vsw) entre la tension de démarrage Vb et la tension de commutation Vsw, lorsque l'élément de sortie M1 est dans un état éteint, est devenue inférieure à une valeur de détection de limite inférieure, et pour charger la tension de démarrage Vb ; et un dispositif de commande 161 configuré pour commuter le circuit de détection de tension de démarrage 20 entre un état de fonctionnement et un état de non-fonctionnement.
PCT/JP2023/015759 2022-05-25 2023-04-20 Dispositif à semi-conducteur et alimentation électrique à commutation WO2023228635A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
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JP2014023269A (ja) * 2012-07-18 2014-02-03 Renesas Electronics Corp 半導体集積回路およびその動作方法
JP2019134595A (ja) * 2018-01-31 2019-08-08 ローム株式会社 スイッチング回路、半導体装置、ｄｃ／ｄｃコンバータ
JP2019537417A (ja) * 2016-12-01 2019-12-19 エフィシエント パワー コンヴァーション コーポレーション ＧａＮトランジスタに基づく電力コンバータのためのブートストラップキャパシタ過電圧管理回路
JP2021090272A (ja) * 2019-12-03 2021-06-10 ローム株式会社 電源制御装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014023269A (ja) * 2012-07-18 2014-02-03 Renesas Electronics Corp 半導体集積回路およびその動作方法
JP2019537417A (ja) * 2016-12-01 2019-12-19 エフィシエント パワー コンヴァーション コーポレーション ＧａＮトランジスタに基づく電力コンバータのためのブートストラップキャパシタ過電圧管理回路
JP2019134595A (ja) * 2018-01-31 2019-08-08 ローム株式会社 スイッチング回路、半導体装置、ｄｃ／ｄｃコンバータ
JP2021090272A (ja) * 2019-12-03 2021-06-10 ローム株式会社 電源制御装置

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