WO2023228635A1 - Semiconductor device and switching power supply - Google Patents

Abstract

A semiconductor device 10 comprises, for example, the following: a first driver 163 configured to drive an output element M1 that forms a switch output stage SWO; at least a portion of a bootstrap circuit BST configured to generate a boot voltage Vb that is higher than a switch voltage Vsw output from the switch output stage SWO, and to supply the boot voltage to the first driver 163; a boot voltage detection circuit 20 configured to detect that a differential value (=Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw, when the output element M1 is in an off state, has become less than a lower limit detection value, and to charge the boot voltage Vb; and a controller 161 configured to switch the boot voltage detection circuit 20 between an operating state and a non-operating state.

Description

Semiconductor equipment, switching power supplies

The present disclosure relates to a semiconductor device and a switching power supply using the same. The present disclosure also relates to a gate drive circuit.

A bootstrap circuit is widely used as an internal power supply means for driving an N-channel type output transistor.

Incidentally, Patent Document 1 can be mentioned as an example of the conventional technology related to the above.

Furthermore, conventionally, a gate drive circuit is known that drives each gate of a high-side transistor and a low-side transistor connected in series.

In some cases, the high-side transistor as well as the low-side transistor is composed of an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor). In this case, a so-called bootstrap is provided to drive the high-side transistor. A boot capacitor for turning on a high-side transistor is used for the bootstrap (for example, Patent Document 2).

On the other hand, when the high-side transistor and the low-side transistor are in the ON state at the same time, a through current occurs, so a so-called dead time (simultaneous OFF period) may be provided when the high-side transistor and the low-side transistor are switched on and off.

Japanese Patent Application Publication No. 2018-133916 Japanese Patent Application Publication No. 2021-158720

However, there was room for improvement in preventing a drop in the boot voltage generated by the bootstrap circuit.

Additionally, during dead time, current flows through the body diode of the transistor, causing loss and reducing efficiency.

A semiconductor device according to one aspect of the present disclosure includes a first driver configured to drive an output element forming a switch output stage, and a first driver that generates a boot voltage higher than a switch voltage output from the switch output stage. at least a portion of a bootstrap circuit configured to supply the voltage to the first driver; and when the output element is in an off state, a difference value between the boot voltage and the switch voltage is lower than a lower limit detection value. a boot voltage detection circuit configured to charge the boot voltage by detecting that the boot voltage has turned off; and a controller configured to switch the boot voltage detection circuit between an operating state and a non-operating state. Be prepared.

Further, for example, a gate drive circuit according to one aspect of the present disclosure is a gate drive circuit for driving a high-side transistor and a low-side transistor connected in series between an input voltage application end and a ground potential application end. a first level shifter configured to be able to receive a low-side gate control signal; and a low-side gate configured to generate a low-side gate signal for driving the gate of the low-side transistor based on the output of the first level shifter. a signal output section, a second level shifter configured to be able to input the output of the first level shifter, a third level shifter configured to be able to input the high side gate control signal, and the output of the second level shifter and the third level shifter configured to input the output of the first level shifter; a first logic gate configured to be able to input the output of a level shifter; and a high side gate configured to generate a high side gate signal for driving the gate of the high side transistor based on the output of the first logic gate. a signal output section, the first level shifter is configured to output the input voltage as a high level, and the second level shifter and the third level shifter are configured such that the high side transistor and the low side transistor are connected to each other. The high-side gate signal output section is configured to output a boot voltage generated at a second end of a boot capacitor having a first end connected to a connected node as a high level, and the high-side gate signal output section outputs the high-side gate signal as the high-side gate signal. A boot voltage can be applied to the gate of the high-side transistor.

Note that other features, elements, steps, advantages, and characteristics will become clearer from the detailed description and accompanying drawings that follow.

According to the configuration according to one aspect of the present disclosure, it is possible to provide a semiconductor device that can prevent a drop in the boot voltage generated by a bootstrap circuit, and a switching power supply using the same.

Furthermore, according to the exemplary gate drive circuit of the present disclosure, it is possible to shorten the dead time in a configuration using a boot capacitor.

FIG. 1 is a diagram showing the overall configuration of a switching power supply. FIG. 2 is a diagram showing a first embodiment (first comparative example) of a switching power supply. FIG. 3 is a diagram showing a second embodiment (second comparative example) of a switching power supply. FIG. 4 is a diagram showing the switching operation of the second embodiment. FIG. 5 is a diagram showing a third embodiment of the switching power supply. FIG. 6 is a diagram showing the switching operation of the third embodiment. FIG. 7 is a diagram showing a configuration example of a boot voltage detection circuit. FIG. 8 is a diagram showing an example of the operation of the charge pump. FIG. 9 is a diagram showing the configuration of a DC/DC converter according to a comparative example. FIG. 10 is a diagram illustrating a configuration of a DC/DC converter according to an exemplary embodiment of the present disclosure. FIG. 11 is a timing chart illustrating an example of operation in a gate drive circuit according to an exemplary embodiment of the present disclosure. FIG. 12 is a diagram showing the configuration of a DC/DC converter according to a modification.

<Switching power supply>
FIG. 1 is a diagram showing the overall configuration of a switching power supply. The switching power supply X0 of this configuration example is a step-down DC/DC converter that steps down the input voltage Vin (for example, 2.7 to 5.5V) to generate a desired output voltage Vout (for example, 0.6 to 4.0V). It is a DC converter. To be more specific with reference to this figure, the switching power supply X0 includes a semiconductor device 10, various discrete components externally attached thereto (capacitors C1 and C2, inductor L1, and resistors R1 and R2), Equipped with.

The semiconductor device 10 is a main body (so-called power supply control IC [integrated circuit]) that centrally controls the operation of the switching power supply X0. The semiconductor device 10 includes a plurality of external terminals (pins 1 to 4 in this figure) as means for establishing electrical connection with the outside of the device.

Note that the 1st pin is a power supply terminal VIN to which the input voltage Vin is applied. The 2nd pin is a switch output terminal SW. The third pin is a ground terminal GND. The 4th pin is a feedback input terminal FB.

Next, external connections of the semiconductor device 10 will be explained. A first end of the capacitor C1 is connected to a power supply terminal VIN. A second end of the capacitor C1 is connected to a ground end. A first end of the inductor L1 is connected to the switch output terminal SW. The second end of the inductor L1 and the first ends of the resistor R1 and capacitor C2 are all connected to the application end of the output voltage Vout. The second end of the resistor R1 and the first end of the resistor R2 are both connected to the feedback input terminal FB (=the end to which the feedback voltage Vfb is applied). The second terminals of the capacitor C2 and the resistor R2 are both connected to a ground terminal.

The inductor L1 and capacitor C2 function as an LC filter that rectifies and smoothes the rectangular waveform switch voltage Vsw to generate the output voltage Vout.

The resistors R1 and R2 function as a feedback voltage generation circuit (voltage dividing circuit) that outputs a feedback voltage Vfb (=divided voltage of the output voltage Vout) according to the output voltage Vout from the connection node between them. Although not explicitly shown in this figure, a speed-up capacitor may be connected in parallel between both ends of the resistor R1 so that the switching power supply X0 can start up smoothly. Furthermore, if the output voltage Vout is within the input dynamic range of the semiconductor device 10, the resistors R1 and R2 may be omitted and the output voltage Vout may be directly input to the feedback input terminal FB.

<Semiconductor device>
Continuing with reference to FIG. 1, the internal configuration of the semiconductor device 10 will be described in detail. The semiconductor device 10 of this configuration example includes an error amplifier 11, a comparison circuit 12, an on-time setting circuit 13, a ripple generation circuit 14, an addition circuit 15, a drive control circuit 16, and a reference voltage generation circuit 17. , a charge pump 18, a zero-cross detection circuit 19, capacitors C3 and C4, a switch BS, an output element M1, and a synchronous rectifier M2 are integrated.

The error amplifier 11 generates an error voltage Vc according to the difference between the reference voltage Vref input to the non-inverting input terminal (+) and the feedback voltage Vfb input to the inverting input terminal (-). Note that the error voltage Vc increases when the feedback voltage Vfb is lower than the reference voltage Vref, and decreases when the feedback voltage Vfb is higher than the reference voltage Vref.

The comparison circuit 12 includes a first comparator 121 and a second comparator 122.

The first comparator 121 compares the slope voltage Vslp input to the inverting input terminal (-) and the error voltage Vc input to the non-inverting input terminal (+) to generate a comparison signal Sc1. The comparison signal Sc1 becomes a high level when the slope voltage Vslp is lower than the error voltage Vc, and becomes a low level when the slope voltage Vslp is higher than the error voltage Vc. Note that the first comparator 121 may have a hysteresis characteristic.

The second comparator 122 compares the feedback voltage Vfb input to the inverting input terminal (-) and the error voltage Vc input to the non-inverting input terminal (+) to generate a comparison signal Sc2. The comparison signal Sc2 becomes a high level when the feedback voltage Vfb is lower than the error voltage Vc, and becomes a low level when the feedback voltage Vfb is higher than the error voltage Vc. Note that the second comparator 122 may have hysteresis characteristics.

Further, the timing at which the feedback voltage Vfb falls below the error voltage Vc is earlier than the timing at which the slope voltage Vslp (=Vfb+Vr), which is the sum of the feedback voltage Vfb and the ripple voltage Vr, falls below the error voltage Vc. In other words, the timing at which the comparison signal Sc2 rises to high level is earlier than the timing at which the comparison signal Sc1 rises to high level.

Note that the second comparator 122 may have lower responsiveness (current output capability) than the first comparator 121.

The on-time setting circuit 13 basically generates the switch control signal S0 so as to maintain the output element M1 in the on-state for the on-time Ton after the comparison signal Sc1 rises to a high level. The on-time setting circuit 13 also has a function of ignoring the logic level of the comparison signal Sc1 for a predetermined mask period (for example, 100 ns) after the comparison signal Sc2 rises to a high level.

The ripple generation circuit 14 generates a ripple voltage Vr that simulates the ripple component of the output voltage Vout in synchronization with the switch control signal S0.

Adder circuit 15 adds ripple voltage Vr to feedback voltage Vfb to generate slope voltage Vslp.

The drive control circuit 16 includes a controller 161, a level shifter 162, and drivers 163 and 164 as its components.

As basic output feedback control, the controller 161 generates gate control signals S1 and S2 so that the output voltage Vout matches a desired target value using a bottom detection type on-time fixed method according to the switch control signal S0. do.

Note that the controller 161 also has a function of stopping the switching drive of each of the output element M1 and the synchronous rectifier M2 when the load is light, according to the zero-crossing detection signal S9. For example, when the zero-cross detection signal S9 rises to a high level while the output element M1 is in the off state and the synchronous rectifier M2 is in the on state, the controller 161 detects that the switch voltage Vsw is at the zero-cross detection value (for example, GND ), the synchronous rectifier M2 may be turned off.

The level shifter 162 level-shifts the gate control signal S1 to generate the gate control signal S1'. Referring to this diagram, the level shifter 162 sets the gate control signal S1' to a high level (=Vb) when the gate control signal S1 is at a high level (=Vin), and sets the gate control signal S1 to a low level (=Vb). =GND), the gate control signal S1' is set to low level (=Vsw).

The driver 163 drives the output element M1 by generating a gate drive signal G1 according to the gate control signal S1'. For example, the gate drive signal G1 becomes a high level (=Vb) when the gate control signal S1' is a high level, and becomes a low level (=Vsw) when the gate control signal S1' is a low level.

The driver 164 drives the synchronous rectifier M2 by generating a gate drive signal G2 according to the gate control signal S2. For example, the gate drive signal G2 becomes a high level (=Vin) when the gate control signal S2 is a high level, and becomes a low level (=GND) when the gate control signal S2 is a low level.

The reference voltage generation circuit 17 generates a predetermined reference voltage Vref (=target value of the feedback voltage Vfb, which in turn corresponds to the target value of the output voltage Vout).

The charge pump 18 generates a boosted voltage Vcp higher than the input voltage Vin in accordance with the charge pump control signal CPON output from the controller 161, and applies this to the application terminal of the boot voltage Vb.

It should be noted that the charge pump 18 does not always maintain the boot voltage Vb at a voltage value higher than the input voltage Vin, but only needs to have a current capacity that can slightly raise the boot voltage Vb when it decreases. Therefore, as the charge pump 18, for example, an existing charge pump provided for the purpose of maintaining the boot voltage Vb during 100% duty driving of the switch output stage SWO may be used.

The zero cross detection circuit 19 detects synchronization by monitoring the voltage across the synchronous rectifier M2 (corresponding to the switch voltage Vsw) when the output element M1 is in the off state and the synchronous rectifier M2 is in the on state. A zero cross (reverse current) of the inductor current IL flowing through the rectifying element M2 is detected.

The capacitor C3 is connected between the output end of the error amplifier 11 and the ground end as a phase compensation means for preventing the error amplifier 11 from oscillating.

The output element M1 (for example, NMOSFET [N-channel type metal oxide semiconductor field effect transistor]) functions as an upper switch of the switch output stage SWO that generates the switch voltage Vsw from the input voltage Vin. The drain of the output element M1 is connected to the power supply terminal VIN. The source of the output element M1 is connected to the switch output terminal SW. The gate of the output element M1 is connected to the application end of the gate drive signal G1. The output element M1 is turned on when the gate drive signal G1 is at a high level, and is turned off when the gate drive signal G1 is at a low level.

The synchronous rectifier M2 (eg, NMOSFET) functions as a lower switch of the switch output stage SWO. The drain of the synchronous rectifier M2 is connected to the switch output terminal SW. The source of the synchronous rectifier M2 is connected to the ground terminal GND. The gate of the synchronous rectifier M2 is connected to the application end of the gate drive signal G2. The synchronous rectifier M2 is turned on when the gate drive signal G2 is at a high level, and is turned off when the gate drive signal G2 is at a low level.

Note that as the rectifier, a rectifier diode (for example, a Schottky barrier diode) whose cathode is connected to the switch output terminal SW and whose anode is connected to the ground terminal GND may be used instead of the synchronous rectifier M2.

Furthermore, the output element M1 and the synchronous rectifier M2 may be externally attached to the semiconductor device 10. In that case, instead of the switch output terminal SW, an external input terminal for the switch voltage Vsw and an external output terminal for each of the gate drive signals G1 and G2 are required.

In addition, when a high voltage can be applied to the switch output stage SWO, a high voltage element such as an IGBT [insulated gate bipolar transistor], a SiC device, or a GaN device is used as the output element M1 and the synchronous rectifier M2. Good too.

The switch output stage SWO is driven in pulses between the input voltage Vin and the ground voltage PGND by complementarily turning on and off the output element M1 and the synchronous rectifier M2 connected to form a half bridge. A rectangular waveform switch voltage Vsw is generated.

Note that the word "complementary" in this specification refers to cases where the on/off states of output element M1 and synchronous rectifier M2 are completely reversed, as well as cases where there is a delay in the on/off transition timing of each. The term is used in a meaning that also includes the case where a simultaneous off period is provided (=a case where a simultaneous off period is provided).

The first end of the switch BS is connected to the power supply terminal VIN. The second end of the switch BS and the first end of the capacitor C4 are both connected to the application end of the boot voltage Vb. A second end of the capacitor C4 is connected to the switch output terminal SW.

The switch BS and capacitor C4 connected in this manner form a bootstrap circuit BST that generates a boot voltage Vb higher than the switch voltage Vsw by the voltage across the capacitor C4 and supplies it to the level shifter 162 and driver 163.

The operation of bootstrap circuit BST will be briefly explained. When the output element M1 is in the off state and the synchronous rectifier element M2 is in the on state, the switch BS is in the on state. Therefore, the capacitor C4 is charged by the current flowing from the application end of the input voltage Vin through the switch BS. At this time, the voltage across the capacitor C4 increases until it reaches approximately the same potential as the input voltage Vin.

On the other hand, when the output element M1 is in the on state and the synchronous rectifier element M2 is in the off state, the switch BS is in the off state. Therefore, the boot voltage Vb is raised to a potential (≈2Vin) higher than the switch voltage Vsw (≈Vin) by the voltage across the capacitor C4 (≈Vin) in accordance with the law of conservation of charge of the capacitor C4.

Note that as the switch BS, for example, a PMOSFET [P-channel type MOSFET] configured such that the drain is connected to the power supply terminal VIN and the source is connected to the application terminal of the boot voltage Vb may be used, or , a diode configured such that its anode is connected to the power supply terminal VIN and its cathode is connected to the end to which the boot voltage Vb is applied may be used.

Furthermore, in this embodiment, the capacitor C4 is built into the semiconductor device 10. Therefore, the number of discrete components externally attached to the semiconductor device 10 can be reduced. However, compared to the case where the capacitor C4 is externally attached to the semiconductor device 10, the capacitance value of the capacitor C4 becomes smaller. Therefore, it is necessary to consider countermeasures for reducing the boot voltage Vb (details will be described later).

<Switching power supply (second embodiment)>
FIG. 2 is a diagram showing a first embodiment of the switching power supply X0 (corresponding to a first comparative example to be compared with a third embodiment described later). The switching power supply X0 of this embodiment is based on the above-mentioned overall configuration (FIG. 1), but further includes a boot voltage detection circuit 20.

The boot voltage detection circuit 20 detects that the divided voltage Vbd of the boot voltage Vb has become lower than the lower limit detection voltage Vth, and generates the boot drop detection signal BU. Referring to the figure, the boot voltage detection circuit 20 includes a comparator CMP and resistors R3 and R4.

The resistors R3 and R4 are connected in series between the application terminal of the boot voltage Vb and the ground terminal, and output a divided voltage Vbd of the boot voltage Vb from the connection node between them.

The comparator CMP compares the divided voltage Vbd input to the inverting input terminal (-) and the lower limit detection voltage Vth input to the non-inverting input terminal (+) to generate a boot drop detection signal BU. The boot drop detection signal BU becomes a high level when the divided voltage Vbd is lower than the lower limit detection voltage Vth, and becomes a low level when the divided voltage Vbd is higher than the lower limit detection voltage Vth. Note that the comparator CMP may have a hysteresis characteristic.

The controller 161 controls the synchronous rectifier M2 and the switch BS when the boot drop detection signal BU rises to a high level during the drive stop period of the switch output stage SWO (=the off period of both the output element M1 and the synchronous rectifier M2). Turn on and charge the boot voltage Vb. Therefore, the high level of the gate drive signal G1 can be raised to a potential sufficient to turn on the output element M1.

However, the boot voltage detection circuit 20 of this embodiment is of a constant detection type using resistive voltage division, and a circuit current always flows from the boot voltage Vb application terminal to the ground terminal. Therefore, the boot voltage Vb tends to drop during the drive stop period of the switch output stage SWO.

In particular, when the capacitor C4 is built into the semiconductor device 10, it is difficult to ensure a sufficient capacitance value of the capacitor C4, so the above problem is likely to occur.

Further, when the semiconductor device 10 reaches a high temperature (for example, 125° C. or higher), element leakage increases, so the boot voltage Vb tends to decrease.

<Switching power supply (second embodiment)>
FIG. 3 is a diagram showing a second embodiment of the switching power supply X0 (corresponding to a second comparative example compared to a third embodiment described later). The switching power supply X0 of this embodiment is based on the above-mentioned overall configuration (FIG. 1), but a gate monitoring function is added to the controller 161.

Specifically, after the gate control signal S1 is raised to a high level, the controller 161 of this embodiment determines whether the gate drive signal G1 has risen to a potential sufficient to turn on the output element M1. It has a function of monitoring and detecting a drop in the boot voltage Vb.

For example, as shown in this figure, the drive control circuit 16 includes a level shifter 165 configured to level shift the gate drive signal G1 to generate a gate drive signal G1' and output it to the controller 161. But that's fine.

FIG. 4 is a diagram showing the switching operation of the second embodiment, and in order from the top, the switch voltage Vsw (solid line), the boot voltage Vb (broken line), the gate control signal S1, the gate feedback signal G1fb, and the boot drop detection signal BU , as well as the gate control signal S2. Note that this figure shows an intermittent switching operation waveform at a light load.

The gate feedback signal G1fb is one of the internal signals of the controller 161. Specifically, the gate feedback signal G1fb becomes high level when the gate drive signal G1 rises to a potential sufficient to turn on the output element M1 after the gate control signal S1 rises to a high level. Furthermore, in this embodiment, the boot deterioration detection signal BU can also be understood as one of the internal signals of the controller 161.

During the drive stop period of the switch output stage SWO (=before time t12), the gate control signals S1 and S2 are both set to low level, so the output element M1 and the synchronous rectification element M2 are both turned off. At this time, as shown before time t11, the boot voltage Vb decreases with the passage of time. Then, as shown from time t11 to t12, the boot voltage Vb eventually decreases to approximately the same potential as the switch voltage Vsw.

Note that, as described above, when the capacitor C4 is a built-in type and when the semiconductor device 10 is at a high temperature, the boot voltage Vb tends to decrease.

Between times t12 and t13, the gate control signal S1 is raised to a high level. However, as described above, since the boot voltage Vb has decreased to approximately the same potential as the switch voltage Vsw, the gate drive signal G1 does not rise to a potential sufficient to turn on the output element M1. As a result, the output element M1 cannot be correctly switched on. At this time, the gate feedback signal G1fb remains at a low level.

At time t13, since the gate feedback signal G1fb is at a low level, the boot drop detection signal BU is raised to a high level (=the logic level when detecting a drop in the boot voltage Vb).

Note that if the rise of the gate drive signal G1 is not detected and the boot drop detection signal BU is raised to a high level, the gate control signal S2 is raised to a high level as shown at times t13 to t14. synchronous rectifier M2 is switched to the on state. As a result, capacitor C4 is charged and boot voltage Vb increases. Therefore, from time t14 to time t15, the gate drive signal G1 can be raised to a high level due to the transition of the gate control signal S1 to a high level, so that the output element M1 is switched to the on state.

However, since the series of reboot operations described above are performed in response to the fact that the gate drive signal G1 does not rise sufficiently, the on-timing of the output element M1 is delayed from the original timing. Referring to this figure, the output element M1 is not turned on at the first switching time (=time t12), and the output element M1 is turned on at the second switching time (=time t14).

If the on-timing of the output element M1 is delayed, the output voltage Vout will fall below the bottom detection value, so the ripple component of the output voltage Vout will increase. In particular, in a configuration in which the synchronous rectifier M2 is turned on extra to charge the boot voltage Vb, charge is discarded from the terminal to which the output voltage Vout is applied. Therefore, the amount of decrease in the output voltage Vout becomes large, and as a result, the ripple component may increase significantly.

Further, if the synchronous rectifier M2 is turned on with the boot voltage Vb insufficient, the gate-source voltage of the output element M1 may increase when the switch voltage Vsw decreases due to the insufficient ability of the driver 163. As a result, not only the synchronous rectifying element M2 but also the output element M1 may be turned on, and an excessive through current may flow through the switch output stage SWO.

Note that the problems of the first embodiment (FIG. 2) and second embodiment (FIG. 3) described above also apply to the case where the diode rectification method is adopted in the switch output stage SWO.

A third embodiment that can solve these problems will be proposed below.

<Switching power supply (third embodiment)>
FIG. 5 is a diagram showing a third embodiment of the switching power supply X0. The switching power supply X0 of this embodiment is based on the first embodiment (FIG. 2) and second embodiment (FIG. 3), but the configuration and operation of the boot voltage detection circuit 20 are changed.

The boot voltage detection circuit 20 detects that the difference value (=Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw is in the drive stop period of the switch output stage SWO (=the off period of both the output element M1 and the synchronous rectifier M2). A boot normality detection signal BOK is generated to charge the boot voltage Vb upon detecting that it has become lower than the lower limit detection value Vdet.

Note that the boot normal detection signal BOK becomes a high level (=logic level when BOOTUVLO is not detected) when the difference value (Vb-Vsw) is higher than the lower limit detection value Vdet, and the difference value (Vb-Vsw) is higher than the lower limit detection value Vdet. When it is lower than the value Vdet, it becomes a low level (=logic level at the time of BOOTUVLO detection).

The controller 161 drives the charge pump 18 to charge the boot voltage Vb when the boot normality detection signal BOK falls to a low level during the driving stop period of the switch output stage SWO. Referring to this figure, the charge pump 18 generates a boosted voltage Vcp higher than the input voltage Vin in response to the charge pump control signal CPON output from the controller 161, and applies this to the application terminal of the boot voltage Vb. Apply.

Through such a reboot operation, the high level of the gate drive signal G1 can be raised to a potential sufficient to turn on the output element M1. Therefore, it becomes possible to restart the switching operation of the switch output stage SWO without any trouble.

Furthermore, if the configuration uses the charge pump 18, there is no need to turn on the synchronous rectifier M2 extra in order to charge the boot voltage Vb. Therefore, the ripple component of the output voltage Vout can be suppressed to a small level.

As mentioned above, as the charge pump 18, for example, an existing charge pump provided for the purpose of maintaining the boot voltage Vb during 100% duty driving of the switch output stage SWO may be used. Such circuit sharing makes it possible to shrink the chip area of the semiconductor device 10.

However, if the semiconductor device 10 does not include the charge pump 18, the synchronous rectifier M2 is turned on to charge the boot voltage Vb, as in the second embodiment (see FIGS. 3 and 4). Any configuration may be adopted.

Further, in the switching power supply X0 of this embodiment, the controller 161 has a function of generating a boot detection control signal BUON to switch the boot voltage detection circuit 20 between an operating state and a non-operating state.

In other words, the boot voltage detection circuit 20 is activated only when a certain condition (details will be described later) is met. Therefore, unlike the first embodiment (FIG. 2) described above, the circuit current does not always flow from the end to which the boot voltage Vb is applied toward the ground end, making it possible to suppress a drop in the boot voltage Vb. Further, it can also contribute to lower current consumption of the boot voltage detection circuit 20 (and by extension, the semiconductor device 10).

FIG. 6 is a diagram showing the switching operation of the third embodiment, and in order from the top, switch voltage Vsw (solid line), boot voltage Vb (broken line), comparison signals Sc2 and Sc1, wake signal WAKE, deep signal DEEP, boot A detection control signal BUON and a normal boot detection signal BOK are depicted.

First, the basic switching operation will be briefly explained with reference to times t24 to t25. When the output element M1 is in the on state and the synchronous rectifier element M2 is in the off state, the inductor current IL flows in the direction from the application end of the input voltage Vin to the application end of the output voltage Vout via the output element M1 and the inductor L1. flows. As a result, the output voltage Vout increases. Further, the switch voltage Vsw becomes a high level (=Vin-IL×Ron(M1), where Ron(M1) is the on-resistance of the output element M1).

Note that when the synchronous rectifier M2 is in the off state, the switch BS of the bootstrap circuit BST is also in the off state. Therefore, the boot voltage Vb has a voltage value higher than the switch voltage Vsw by the voltage across the capacitor C4.

On the other hand, when the output element M1 is in the off state and the synchronous rectifier M2 is in the on state, the inductor current IL flows from the ground terminal GND through the synchronous rectifier M2 and the inductor L1 due to the electromotive force induced in the inductor L1. It continues to flow in the direction toward the application end of the output voltage Vout. As a result, the output voltage Vout continues to rise. Further, the switch voltage Vsw becomes a low level (=GND-IL×Ron(M2), where Ron(M2) is the on-resistance of the synchronous rectifier M2).

Note that when the synchronous rectifier M2 is in the on state, the switch BS of the bootstrap circuit BST is also in the on state. Therefore, the capacitor C4 is charged by the current flowing from the application end of the input voltage Vin through the switch BS, so that the boot voltage Vb increases.

After that, at time t25, when the electromotive force of the inductor L1 becomes insufficient and a zero cross (reverse current) of the inductor current IL flowing through the synchronous rectifier M2 is detected, the synchronous rectifier M2 is turned off. As a result, both the output element M1 and the synchronous rectifier M2 are turned off, so that the switch output terminal SW is placed in a high impedance state. At this time, the switch voltage Vsw substantially matches the output voltage Vout.

Note that when the synchronous rectifier M2 is turned off, the switch BS of the bootstrap circuit BST is also turned off. Therefore, during the driving stop period of the switch output stage SWO, the boot voltage Vb has a voltage value higher than the switch voltage Vsw by the voltage across the capacitor C4. However, during the driving stop period of the switch output stage SWO, the boot voltage Vb decreases due to natural discharge or high temperature leakage.

Next, the wake signal WAKE and deep signal DEEP, which are internal signals of the controller 161, will be explained.

The wake signal WAKE is a logic signal indicating whether the switching power supply X0 is in a light load state. Referring to this figure, the wake signal WAKE goes low at the zero-cross detection timing of the inductor current IL flowing through the synchronous rectifying element M2 (=driving stop timing of the switch output stage SWO), as shown at times t21 and t25. level. Further, the wake signal WAKE becomes high level at the timing when the comparison signal Sc2 rises to high level (=start timing of the boot voltage detection period T1), as shown at time t23 or t26. Note that the wake signal WAKE is maintained at a high level unless a zero crossing of the inductor current IL is detected.

The deep signal DEEP is a logic signal that indicates whether the switching power supply X0 is in a no-load state (or a very light load state). Referring to this figure, the deep signal DEEP is generated by the wake signal WAKE during the no-load determination period T2 after the zero cross of the inductor current IL flowing through the synchronous rectifier M2 is detected, as shown at time t21 to t22. It becomes high level when it is maintained at low level throughout.

Note that focusing on the operating mode of the semiconductor device 10, when the wake signal WAKE is at a high level, the semiconductor device 10 is in the normal mode. On the other hand, when the wake signal WAKE is at a low level, the semiconductor device 10 shifts to a light load mode (=sleep mode) with lower current consumption than the normal mode. Further, when the wake signal WAKE is at a low level and the deep signal DEEP is at a high level, the semiconductor device 10 is in a no-load mode or an ultra-light load mode (= deep sleep mode) in which current consumption is lower than in the light-load mode. to move to.

Next, a method of setting the boot voltage detection period T1 will be explained. As mentioned above, the timing at which the comparison signal Sc2 rises to a high level is earlier than the timing at which the comparison signal Sc1 rises to a high level.

Therefore, by utilizing the above behavior of the comparison signals Sc1 and Sc2, the controller 161 sets the boot voltage detection period T1 and puts the boot voltage detection circuit 20 into the operating state before switching the output element M1 to the on state. For example, in this figure, as shown from time t23 to t24 or from time t26 to t27, a boot voltage detection period T1 of a predetermined length (for example, 100 ns) is set after the comparison signal Sc2 rises to a high level, and the boot The detection control signal BUON is set at high level.

However, the method for setting the boot voltage detection period T1 is not limited to the above. For example, it is also possible to establish a system by giving an appropriate delay to a single comparison signal, without forming the comparison circuit 12 with two first comparators 121 and two second comparators 122.

Furthermore, as a condition for raising the boot detection control signal BUON to a high level, it may be added that the wake signal WAKE and the deep signal DEEP are both at a high level. In other words, the controller 161 outputs the comparison signal Sc2 ( Furthermore, the boot voltage detection period T1 may be provided when the wake signal WAKE) rises to a high level.

For example, if the load on the switching power supply X0 becomes heavy and the switching period becomes short, the boot voltage Vb will not decrease so much. In such a situation, the above additional condition no longer holds true, so the boot detection control signal BUON remains at a low level even after the comparison signal Sc2 rises to a high level, as shown at time t20. Note that when the above additional condition is not satisfied, the boot normality detection signal BOK is preferably fixed at a high level (=logic level when BOOTUVLO is not detected). However, the above conditions are not mandatory.

Next, we will focus on the boot voltage detection operation. During the boot voltage detection period T1 from time t23 to time t24, the difference value (=Vb−Vsw) between the boot voltage Vb and the switch voltage Vsw exceeds the lower limit detection value Vdet. Therefore, since the boot normality detection signal BOK is maintained at a high level, the charging operation of the boot voltage Vb by the charge pump 18 is not performed. In this way, if the amount of decrease in the boot voltage Vb is small, the on-transition of the output element M1 will not be hindered even if the boot voltage Vb is not charged.

On the other hand, during the boot voltage detection period T1 from time t26 to t27, as the boot voltage Vb decreases during the driving stop period of the switch output stage SWO, the difference value (Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw is detected as the lower limit. It is below the value Vdet. Therefore, the boot normality detection signal BOK falls to low level. In this figure, the boot normality detection signal BOK falls to a low level after a predetermined delay time d (≦T1) has elapsed after the boot detection control signal BUON rose to a high level. As a result, the charging operation of the boot voltage Vb by the charge pump 18 is performed prior to the on-transition of the output element M1.

Note that in this figure, the start of charging the boot voltage Vb is on standby until the boot voltage detection period T1 of a predetermined length expires after the boot normality detection signal BOK falls to a low level. However, the charging start timing of the boot voltage Vb is not limited to this. For example, the charging operation of the boot voltage Vb may be started without delay when the boot normality detection signal BOK falls to a low level.

Further, after starting charging the boot voltage Vb in response to a low level transition of the boot normal detection signal BOK, the controller 161 maintains the boot detection control signal BUON at a high level at least until the boot voltage Vb exceeds the lower limit detection value Vdet. It's good to do that. As a result, the boot voltage detection circuit 20 is maintained in an operating state, so that it is possible to continue monitoring whether the boot voltage Vb has recovered.

Thereafter, when the boot voltage Vb exceeds the lower limit detection value Vdet, the output element M1 is switched to the on state at time t28. As a result, the switching operation of the switch output stage SWO is restarted.

Note that, unlike the second embodiment (FIG. 4) mentioned above, the series of reboot operations described above are not performed after a problem occurs in the on-transition of the output element M1, but when the boot voltage Vb and the switch voltage Vsw This is carried out by detecting that the difference value (Vb-Vsw) has become lower than the lower limit detection value Vdet. Therefore, compared to the previously mentioned second embodiment (FIG. 4), the on-timing of the output element M1 is less likely to be delayed, so that the amount of decrease in the output voltage Vout can be suppressed.

Furthermore, during the charging period of the boot voltage Vb (=time t27 to t28), unlike the second embodiment (time t13 to t14 in FIG. 4), the synchronous rectifier M2 is turned on to charge the capacitor C4. It never happens. Therefore, compared to the previously mentioned second embodiment (FIG. 4), it is possible to further suppress a decrease in the output voltage Vout.

<Boot voltage detection circuit>
FIG. 7 is a diagram showing an example of the configuration of the boot voltage detection circuit 20. The boot voltage detection circuit 20 of this configuration example includes transistors P1 to P7 (for example, PMOSFET), transistors N1 to N7 (for example, NMOSFET), inverters INV1 to INV4, and resistors R10 to R13.

Note that the resistor R10 corresponds to a gate resistor. Resistors R11 and R12 correspond to a first resistance and a second resistance, respectively. Transistors P1 and P2 correspond to a first transistor and a second transistor, respectively. Transistors N1 and N2 correspond to a third transistor and a fourth transistor, respectively.

The first end of the resistor R11 is connected to the application end of the boot voltage Vb. A second end of the resistor R11 is connected to the source of the transistor P1. A first end of the resistor R10 is connected to an application end of the switch voltage Vsw. A second end of the resistor R10 is connected to the gate of the transistor P1. The drain of transistor P1 is connected to the drain of transistor N1. The source of the transistor P2 and the gate of the transistor N1 are both connected to the application terminal of the input voltage Vin. The drain of the transistor P2, the source of the transistor N1, and the first end of the resistor R12 are all connected to the application end of the node voltage Vx. A second end of the resistor R12 is connected to the drain of the transistor N2. The source of transistor N2 is connected to the ground terminal.

The input end of the inverter INV1 is connected to the application end of the boot detection control signal BUON. The output end of the inverter INV1 is connected to the input end of the inverter INV2. The output terminal of the inverter INV2 (=the terminal to which the gate voltage GP2 is applied) is connected to the input terminal of the inverter INV3 and the gate of the transistor P2. The output terminal of inverter INV3 is connected to the input terminal of inverter INV4. The output end of the inverter INV4 (=the end to which gate voltage GN2 is applied) is connected to the gate of the transistor N2.

The drain and gate of the transistor N3 and the sources of each of the transistors P5 to P7 are both connected to the application terminal of the input voltage Vin. The source of transistor N3 and the drain of transistor P6 are both connected to the source of transistor P3. The drain of transistor P3 is connected to the source of transistor P4. The drains of the transistors P4 and N4, the gates of the transistors N6, N7, and P7, and the first end of the resistor R13 are all connected to the application end of the node voltage Vy. The drain of transistor P5 is connected to the drain of transistor N6. The sources of transistors N4 and N6 are both connected to the drain of transistor N5. The sources of the transistors N5 and N7, the gate of the transistor P5, and the second end of the resistor R13 are all connected to the ground terminal. The gates of transistors P3, P4, N4, and N5 are all connected to the terminal to which node voltage Vx is applied. The gate of the transistor P6 and the drains of the transistors P7 and N7 are both connected to the application terminal of the boot normality detection signal BOK.

The controller 161 sets the boot detection control signal BUON to a low level when placing the boot voltage detection circuit 20 in a non-operating state. Referring to this diagram, when the boot detection control signal BUON is at a low level, both gate voltages GP2 and GN2 are at a low level, so the transistor P2 is turned on and the transistor N2 is turned off. Become.

At this time, since the node voltage Vx is fixed at a high level (≈Vin), the transistor N1 is also turned off. In this way, when the boot detection control signal BUON is at a low level, a current path from the application terminal of the boot voltage Vb to the ground terminal via the resistor R11, transistor P1, transistor N1, resistor R12, and transistor N2 is established. Be cut off. As a result, a decrease in boot voltage Vb is suppressed.

Transistors P3 to P5 and N4 to N6 form an inverter with hysteresis. Therefore, when the node voltage Vx is fixed at a high level (≈Vin), the node voltage Vy, which is an inversion of the logic level of the node voltage Vx, is fixed at a low level (≈GND). As a result, the boot normality detection signal BOK, which is the logic level of the node voltage Vy further inverted, is fixed at a high level (=the logic level when BOOTUVLO is not detected).

Note that the resistor R13 is used to fix the node voltage Vy to a low level in a situation where the terminal to which the node voltage Vy is applied may be floating in potential, and by extension, to fix the boot normality detection signal BOK to a high level. Functions as a pull-down resistor.

On the other hand, the controller 161 sets the boot detection control signal BUON to a high level when putting the boot voltage detection circuit 20 into the operating state. Referring to this diagram, when the boot detection control signal BUON is at a high level, the gate voltages GP2 and GN2 are both at a high level, so the transistor P2 is turned off and the transistor N2 is turned on. .

In this way, when the boot detection control signal BUON is at a high level, the current path from the application terminal of the boot voltage Vb to the ground terminal via the resistor R11, the transistor P1, the transistor N1, the resistor R12, and the transistor N2 becomes conductive. be done. That is, the detection operation of the boot voltage Vb is started.

At this time, the node voltage Vx is determined depending on whether the difference value (=Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw is higher or lower than the lower limit detection value Vdet. Specifically, when Vb-Vsw>Vdet, current I1 flows through resistor R11, and in turn, current I2 flows through resistor R12. Therefore, the node voltage Vx becomes high level (≈I2×R12). On the other hand, when Vb-Vsw<Vdet, current I1 does not flow through resistor R11, and by extension, current I2 does not flow through resistor R12. Therefore, the node voltage Vx becomes low level (≈GND).

Note that, assuming that the on-threshold voltage of the transistor P1 is Vgsp, the lower limit detection value Vdet is expressed as Vdet=Vgsp+I1×R11. In this way, by combining the on-threshold voltage Vgsp with negative temperature characteristics and the resistor R11 with positive temperature characteristics, the temperature characteristics of the lower limit detection value Vdet can be adjusted to be flat.

However, the method for setting the lower limit detection value Vdet is not limited to the above, and, for example, the lower limit detection value Vdet may be set using only the diode connection of the transistor P1.

When the node voltage Vx is at a high level (≈I2×R12), the node voltage Vy is at a low level, and as a result, the boot normality detection signal BOK is at a high level. On the other hand, when the node voltage Vx is at a low level (≈GND), the node voltage Vy becomes a high level, and as a result, the boot normality detection signal BOK becomes a low level (=logic level at the time of BOOTUVLO detection).

Note that, as mentioned earlier, the transistors P3 to P5 and N4 to N6 form an inverter with hysteresis. Therefore, the boot normality detection signal BOK is prevented from returning to the high level at the moment the boot normality detection signal BOK falls to a low level and the charge pump 18 starts charging the boot voltage Vb.

Other circuit elements will also be briefly explained. The transistor N1 functions as a breakdown voltage protection clamper for limiting the node voltage Vx to a predetermined upper limit value or less (≦Vin−Vgsn, where Vgsn is the on-threshold voltage of the transistor N1). Note that the transistor N1 has a high breakdown voltage between its drain and backgate, so it has a circuit configuration (so-called self-suspension) in which the backgate is connected to the source.

The transistor N3 functions as a breakdown voltage protection clamper to limit the drain voltage of the transistor P3 to a predetermined upper limit value or less (≦Vin−Vgsn, where Vgsn is the on-threshold voltage of the transistor N3). Note that the transistor N3 also requires a self-suspending high voltage element in accordance with the input range of the node voltage Vx.

The transistor P6 is turned off when the node voltage Vx is at a high level (and when the normal boot detection signal BOK is at a high level). On the other hand, when the node voltage Vx is at a low level, the transistor P6 is turned on to match the input range of the inverter with hysteresis that receives the node voltage Vx.

The resistance value of the resistor R12 is preferably set in consideration of the leakage characteristics of the transistor P1 and the voltage fluctuation time of the node voltage Vx. If the resistance value of the resistor R12 is set too small, the voltage fluctuation of the node voltage Vx becomes faster, but when the boot voltage detection circuit 20 is in the operating state, the current I1 flows from the end to which the boot voltage Vb is applied toward the ground end. (=I2=Vx/R12) increases.

Note that the boot voltage detection circuit 20 operates only in a certain temperature range (=a temperature range where a decrease in the boot voltage Vb may become a problem due to an increase in the leakage current of the capacitor C4 built in the semiconductor device 10). In this way, since the boot voltage detection circuit 20 has a limited operating area, it is relatively easy to shrink the circuit area.

In addition, although this figure illustrates the circuit specifications assuming a low-voltage type model, it can also be applied to a high-voltage type model.

<Charge pump>
FIG. 8 is a diagram showing an example of the operation of the charge pump 18. From the top, the output voltage Vout, the switch voltage Vsw, the boot voltage Vb, the wake signal WAKE, the deep signal DEEP, the comparison signals Sc2 and Sc1, and the boot detection control The signal BUON, the boot normality detection signal BOK, the charge pump control signal CPON, and the driving clock signal CLK of the charge pump 18 are depicted.

As shown in this figure, at time t31, when the boot normality detection signal BOK falls to a low level, the charge pump control signal CPON rises to a high level without delay. In response to this, pulse driving of the drive clock signal CLK is started, and the charging operation of the boot voltage Vb by the charge pump 18 is performed.

On the other hand, at time t32, when the boot normality detection signal BOK rises to a high level, the charge pump control signal CPON falls to a low level without delay. As a result, the pulse drive of the drive clock signal CLK is stopped, and the charging operation of the boot voltage Vb by the charge pump 18 is ended.

Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

<1. Comparative example>
Here, before describing the embodiments of the present disclosure, a comparative example will be described for comparison. This makes clear the problems of the embodiments of the present disclosure.

FIG. 9 is a diagram showing the configuration of a DC/DC converter X according to a comparative example. The DC/DC converter X shown in FIG. 9 is a step-down DC/DC converter that converts the input voltage PVIN to the output voltage Vout. The DC/DC converter X includes a semiconductor device 1, a boot capacitor Cb, an inductor L, and an output capacitor Cout. The boot capacitor Cb, the inductor L, and the output capacitor Cout are elements provided outside the semiconductor device 1.

The semiconductor device 1 includes an integrated gate drive circuit 9, a high-side transistor HM, and a low-side transistor LM. The gate drive circuit 9 is a circuit for driving the gate of the high-side transistor HM and the gate of the low-side transistor LM.

Further, the semiconductor device 1 includes an input voltage terminal Tin, a boot terminal Tb, a switch terminal Tsw, and a ground terminal Tgnd as external terminals for establishing electrical connection with the outside.

The gate drive circuit 9 includes a logic section 2, a level shifter 3, a high side driver 4, a low side driver 5, a switch voltage detection section 6, and a boot switch 7.

The high-side transistor HM and the low-side transistor LM are both constructed from NMOS transistors (N-channel MOSFETs). The drain of the high-side transistor HM is connected to the application terminal of the input voltage PVIN via the input voltage terminal Tin. The source of the high-side transistor HM is connected to the drain of the low-side transistor LM. The source of the low-side transistor LM is connected to a ground potential application terminal via a ground terminal Tgnd. That is, the high-side transistor HM and the low-side transistor LM are connected in series between the input voltage PVIN and the ground potential. A so-called half bridge is constituted by the high side transistor HM and the low side transistor LM.

A node Nsw to which the source of the high-side transistor HM and the drain of the low-side transistor LM are connected is connected to one end of the inductor L via the switch terminal Tsw. The other end of the inductor L is connected to one end of the output capacitor Cout. The other end of the output capacitor Cout is connected to a ground potential application end. An output voltage Vout is generated at one end of the output capacitor Cout.

The logic section 2 includes an AND circuit 21 and an AND circuit 22. A high side gate control input signal HGCTL_IN is input to a first input terminal of the AND circuit 21 . A low-side gate signal LG applied to the gate of the low-side transistor LM is input to a second input terminal of the AND circuit 21 as a low-side feedback signal LGFB. The AND circuit 21 performs a logical product of the high-side gate control input signal HGCTL_IN and the logically inverted low-side feedback signal LGFB, and outputs the high-side gate control signal HGCTL.

The level shifter 3 converts the level of the high-side gate control signal HGCTL into a level-shifted high-side gate control signal HGCTL_LVS in which the boot voltage BOOT is at a high level and the switch voltage SW is at a low level, and outputs the level-shifted high-side gate control signal HGCTL_LVS. Specifically, when the high-side gate control signal HGCTL is at a high level, the level-shifted high-side gate control signal HGCTL_LVS is at a high level, and when the high-side gate control signal HGCTL is at a low level, the level-shifted high-side gate control signal HGCTL_LVS is at a high level. The signal HGCTL_LVS becomes low level.

The high-side driver 4 generates a high-side gate signal HG to be applied to the gate of the high-side transistor HM based on the input level-shifted high-side gate control signal HGCTL_LVS. Specifically, when the level-shifted high-side gate control signal HGCTL_LVS is at a high level, the high-side gate signal HG of the boot voltage BOOT is applied as a high level to the gate of the high-side transistor HM, and the high-side transistor HM is turned on. becomes. When the level-shifted high-side gate control signal HGCTL_LVS is at a low level, the high-side gate signal HG of the switch voltage SW is applied to the gate of the high-side transistor HM as a low level, and the high-side transistor HM is turned off.

A bootstrap is constructed from the boot capacitor Cb and the boot switch 7. One end of the boot capacitor Cb is connected to the switch terminal Tsw. The other end of boot capacitor Cb is connected to boot terminal Tb. A boot switch 7 that can be turned on and off is connected between the input voltage terminal Tin and the boot terminal Tb.

When the low-side transistor LM is in the on state, the boot switch 7 is controlled to be in the on state, and the boot capacitor Cb is charged with the input voltage PVIN. When the low-side transistor LM is in the off state, the boot switch 7 is controlled to be in the off state. The boot voltage BOOT is higher than the switch voltage SW generated at the switch terminal Tsw. Therefore, by applying the high-side gate signal HG set as the boot voltage BOOT to the gate of the high-side transistor HM by the high-side driver 4, the high-side transistor HM can be turned on.

A low-side gate control input signal LGCTL_IN is input to the first input terminal of the AND circuit 22. A detection signal SWFB output from the switch voltage detection section 6 is input to a second input terminal of the AND circuit 22 . The switch voltage detection section 6 is a circuit that detects the turn-off of the high-side transistor HM by detecting the switch voltage SW that decreases when the high-side transistor HM is turned off. The AND circuit 22 performs a logical product of the low-side gate control input signal LGCTL_IN and the logically inverted detection signal SWFB, and outputs the low-side gate control signal LGCTL.

The low-side driver 5 generates a low-side gate signal LG to be applied to the gate of the low-side transistor LM based on the input low-side gate control signal LGCTL. Specifically, when the low-side gate control signal LGCTL is at a high level, the low-side gate signal LG of the input voltage PVIN at a high level is applied to the gate of the low-side transistor LM, and the low-side transistor LM is turned on. When the low-side gate control signal LGCTL is at the low level, the low-side gate signal LG at the ground potential is applied to the gate of the low-side transistor LM, and the low-side transistor LM is turned off.

With such a configuration, the switching of the high-side transistor HM and the low-side transistor LM is controlled in a complementary manner. Complementary means that one is in the on state while the other is in the off state. However, at the time of switching transition, a dead time (simultaneous off period) is provided.

Here, the operation when the high-side transistor HM is in the off state and the low-side transistor LM is in the on state is transitioned to the high-side transistor HM in the on state and the low-side transistor LM in the off state.

Assume that the high-side gate control input signal HGCTL_IN switches from low level to high level, and the low-side gate control input signal LGCTL_IN switches from high level to low level. Then, the low side gate signal LG falls to a low level (ground potential), the low side transistor LM is turned off, the high side transistor HM and the low side transistor LM are both turned off, and dead time starts.

Since the low side gate signal LG is at low level, the high side gate control signal HGCTL output from the AND circuit 21 switches to high level, and the high side gate signal HG becomes high level. As a result, the high side transistor HM is turned on and the dead time ends.

However, in this configuration, if the delay time between input and output in the level shifter 3 is td1, and the delay time between input and output in the high-side driver 4 is td4, dead time=td1+td4. Therefore, since the dead time is expressed by adding delay times, it is difficult to minimize the dead time.

<2. Embodiments of the present disclosure>
FIG. 10 is a diagram illustrating a configuration of a DC/DC converter Y according to an exemplary embodiment of the present disclosure. Here, the differences between the configuration of the DC/DC converter Y and the configuration of the above-mentioned comparative example (FIG. 9) will be mainly explained.

The DC/DC converter Y includes a semiconductor device 1, an inductor L, and an output capacitor Cout. The boot capacitor Cb is built into the semiconductor device 1, unlike the comparative example. As a result, the semiconductor device 1 is not provided with the boot terminal Tb.

The semiconductor device 1 has a built-in gate drive circuit 9. The gate drive circuit 9 includes a logic section 2, a level shifter 3, a high side driver 4, a low side driver 5, a switch voltage detection section 6, a boot switch 7, and a level shifter 8.

The low-side driver 5 includes an AND circuit 51, an inverter 52, and a low-side gate signal output section 53. A low-side gate control signal LGCTL output from the logic section 2 is input to a first input terminal of the AND circuit 51 . A detection signal SWFB output from the switch voltage detection section 6 is input to a second input terminal of the AND circuit 51. The AND circuit 51 performs a logical product of the low-side gate control signal LGCTL and the logically inverted detection signal SWFB, and outputs the low-side input signal LG_IN.

The inverter 52 inverts the level of the input low-side input signal LG_IN and outputs the low-side feedback signal XLGFB. The low-side feedback signal XLGFB sets the input voltage PVIN to a high level and sets the ground potential to a low level.

The AND circuit 51 and the inverter 52 constitute a level shifter 5A.

The low-side gate signal output section 53 inverts the level of the low-side feedback signal XLGFB and outputs the low-side gate signal LG. The low-side gate signal LG is applied to the gate of the low-side transistor LM.

The level shifter 8 converts the level of the low-side feedback signal XLGFB into a level-shifted low-side feedback signal XLGFB_LVS in which the boot voltage BOOT is at a high level and the switch voltage SW is at a low level, and outputs the level-shifted low-side feedback signal XLGFB_LVS. Specifically, when the low-side feedback signal XLGFB is at a high level, the level-shifted low-side feedback signal XLGFB_LVS is at a high level, and when the low-side feedback signal XLGFB is at a low level, the level-shifted low-side feedback signal XLGFB_LVS is at a low level.

The high-side driver 4 includes a logic gate 41, a high-side gate signal output section 42, an AND circuit 43, and a switch 44.

The logic gate 41 is composed of an AND circuit. A level-shifted high-side gate control signal HGCTL_LVS output from the level shifter 3 is input to a first input terminal of the logic gate 41 . A level-shifted low-side feedback signal XLGFB_LVS is input to the second input terminal of the logic gate 41. Logic gate 41 outputs high side input signal HG_IN. The high side gate signal output section 42 generates a high side gate signal HG based on the input high side input signal HG_IN. High side gate signal HG is applied to the gate of high side transistor HM.

Specifically, when the high-side input signal HG_IN is at a high level, the high-side gate signal HG becomes the boot voltage BOOT at a high level, and when the high-side input signal HG_IN is at a low level, the high-side gate signal HG is The switch voltage SW becomes a low level.

AND circuit 43 and switch 44 are provided for a precharge function. The precharge function is a function that charges the gate of the high-side transistor HM in advance before turning on the high-side transistor HM, as will be described later.

The level-shifted high-side gate control signal HGCTL_LVS is input to the first input terminal of the AND circuit 43. A high-side input signal HG_IN is input to the second input terminal of the AND circuit 43. The AND circuit 43 performs a logical product of the level-shifted high-side gate control signal HGCTL_LVS and the logically inverted version of the high-side input signal HG_IN. Switch 44 is connected between the application terminal of input voltage PVIN and the gate of high-side transistor HM. The switch 44 is turned on and off according to the output of the AND circuit 43.

The operation of the gate drive circuit 9 according to the embodiment of the present disclosure having such a configuration will be described. Here, a description will be given of the operation when the high-side transistor HM is in an off state and the low-side transistor LM is in an on-state, and then the high-side transistor HM is in an on-state and the low-side transistor LM is in an off state. FIG. 11 is a timing chart showing an example of operation in such a transition state.

In FIG. 11, from the top, the switch voltage SW, high side gate control signal HGCTL, level shifted high side gate control signal HGCTL_LVS, low side gate control signal LGCTL, low side feedback signal XLGFB, low side gate signal LG, level shifted The waveforms of the low-side feedback signal XLGFB_LVS, the high-side input signal HG_IN, and the high-side gate signal HG are shown.

First, at timing t1, the high-side gate control signal HGCTL switches from low level to high level, and the low-side gate control signal LGCTL switches from high level to low level.

Then, the low-side input signal LG_IN switches to low level, and the low-side feedback signal XLGFB switches to high level. The low-side feedback signal XLGFB rises to a high level at timing t2 delayed by delay time td3_1 from timing t1. The delay time td3_1 is the delay time between input and output at the level shifter 5A.

Since the low-side feedback signal XLGFB switches to high level, the low-side gate signal LG falls from high level to ground potential (low level). There is a delay time td3_2 from timing t2 when the low-side feedback signal XLGFB switches to high level to timing t3 when the low-side gate signal LG falls to the ground potential. The delay time td3_2 is a delay time between input and output at the low side gate signal output section 53.

As a result, the low-side transistor LM is turned off and enters the off state. Therefore, both the high-side transistor HM and the low-side transistor LM are turned off, and dead time DT starts from timing t3. Note that at this time, since the current flowing through the inductor L toward the load side flows through the body diode of the low-side transistor LM, the switch voltage SW decreases to a negative voltage.

On the other hand, as the high-side gate control signal HGCTL rises to a high level, the level-shifted high-side gate control signal HGCTL_LVS rises to a high level. The level-shifted high-side gate control signal HGCTL_LVS rises to a high level at timing t4 delayed by delay time td1 from timing t1. The delay time td1 is the delay time between input and output of the level shifter 3.

When the level-shifted high-side gate control signal HGCTL_LVS rises to a high level, the output of the AND circuit 43 switches to a high level because the high-side input signal HG_IN is at a low level. As a result, the switch 44 changes from the off state to the on state, and charging of the gate of the high-side transistor HM by the input voltage PVIN is started. As a result, the high side gate signal HG rises to the input voltage PVIN.

Here, since the low-side feedback signal XLGFB rises to a high level at timing t2, the level-shifted low-side feedback signal XLGFB_LVS rises to a high level. At this time, the level-shifted low-side feedback signal XLGFB_LVS rises at timing t5 delayed by delay time td2 from timing t2. The delay time td2 is the delay time between input and output of the level shifter 8.

Then, at timing t6 delayed from timing t5 by delay time td4_1 in the logic gate 41, the high-side input signal HG_IN rises to a high level. Then, the output of the AND circuit 43 becomes low level, the switch 44 is turned off, and charging by the input voltage PVIN is stopped.

On the other hand, the high side gate signal output section 42 causes the high side gate signal HG to rise to the boot voltage BOOT (BOOT=PVIN+PVIN). As a result, the high-side transistor HM turns on, and the switch voltage SW rises to the input voltage PVIN. At this time, the dead time DT ends. Note that the delay time td4_2 from timing t6 to timing t7 when the high-side gate signal HG reaches the boot voltage BOOT is a delay time in the high-side gate signal output section 42.

From the above, the time TH (timings t1 to t7) from when the high-side gate control signal HGCTL rises to high level until the high-side gate signal HG rises to the boot voltage BOOT is TH=td3_1+td2+td4_1+td4_2. On the other hand, the time TL (timings t1 to t3) from when the low side gate control signal LGCTL falls to low level to when the low side gate signal LG falls to low level is TL=td3_1+td3_2.

Therefore, the dead time DT is DT=TH−TL=td2+td4_1+td4_2−td3_2, which is expressed by adding and subtracting the delay time. Accordingly, it is sufficient to adopt a circuit configuration such that td2+td4_1+td4_2−td3_2≧0, and it becomes easy to minimize the dead time DT as much as possible.

Furthermore, since the gate of the high-side transistor HM is charged in advance before the high-side transistor HM is turned on by the precharge function using the input voltage PVIN, charge loss in the boot capacitor Cb can be suppressed. Therefore, the capacitance of the boot capacitor Cb can be reduced, making it suitable for the boot capacitor Cb built into the semiconductor device 1.

Note that as a constraint on the delay time td1, since precharging is started after the delay time td1 has elapsed, it is necessary to set td3_1+td3_2<td1 in order to avoid simultaneous turning on of the high-side transistor HM and the low-side transistor LM. .

Furthermore, the precharge function will not function unless the timing at which the level-shifted high-side gate control signal HGCTL_LVS rises to a high level is before the timing at which the level-shifted low-side feedback signal XLGFB_LVS rises to a high level. Therefore, it is necessary to satisfy td1<td3_1+td2. Here, when td1=td2, td3_1>0, and the condition is automatically satisfied only by the circuit delay. Therefore, it is preferable that the level shifter 3 and the level shifter 8 have the same configuration so that td1=td2.

<3. Modified example>
FIG. 12 is a diagram showing the configuration of a DC/DC converter Z according to a modification example of the present disclosure. In this modification, a delay circuit 45 is added to the high side driver 4 as a difference from the previously described embodiment (FIG. 10). Delay circuit 45 is provided between AND circuit 43 and switch 44.

Thereby, the switch 44 can be turned on at a timing delayed by a predetermined delay time after the level-shifted high-side gate control signal HGCTL_LVS rises to a high level, and precharging can be started. This allows the precharge start timing to be adjusted. In the case where td3_1+td3_2, which determines the timing at which the low-side transistor LM turns off, becomes longer due to not only element delay but also wiring delay, the switch 44 is turned on in order to suppress simultaneous turning on of the high-side transistor HM and the low-side transistor LM. It would be useful to have the ability to adjust the timing.

<Additional notes>
Below, the various embodiments described above will be described in general.

For example, a semiconductor device according to one aspect of the present disclosure includes a first driver configured to drive an output element forming a switch output stage, and a boot voltage higher than a switch voltage output from the switch output stage. at least a portion of a bootstrap circuit configured to generate and supply the voltage to the first driver; and when the output element is in an off state, a difference value between the boot voltage and the switch voltage is lower than a lower limit detection value. a boot voltage detection circuit configured to charge the boot voltage upon detecting that the boot voltage has become low; and a boot voltage detection circuit configured to switch the boot voltage detection circuit between an operating state and a non-operating state. The configuration includes a controller (first configuration).

In the semiconductor device according to the first configuration, the controller provides a predetermined boot voltage detection period before switching the output element and the rectifier forming the switch output stage from an OFF state to an ON state. A configuration (second configuration) may be adopted in which the boot voltage detection circuit is put into an operating state.

In the semiconductor device according to the second configuration, the controller is configured to provide the voltage detection period when both the output element and the rectifier are in an off state for a no-load determination period (a third configuration). configuration).

In the semiconductor device according to the second or third configuration, the controller may cause at least the boot voltage to exceed the lower limit detection value after charging of the boot voltage is started according to the detection result of the boot voltage detection circuit. A configuration (fourth configuration) may be adopted in which the operating state of the boot voltage detection circuit is maintained until the operation.

In the semiconductor device according to any one of the second to fourth configurations, the rectifying element may be a synchronous rectifying element configured to be driven complementary to the output element (fifth configuration). good.

The semiconductor device according to the fifth configuration further includes a second driver configured to drive the synchronous rectifier, and the controller drives the output element and the synchronous rectifier in a complementary manner and outputs the output. A configuration in which the synchronous rectifier is turned off by detecting that the switch voltage has become higher than a zero-cross detection value when the element is in the off state and the synchronous rectifier is in the on state (sixth configuration) ).

In the semiconductor device according to the fifth or sixth configuration, the boot voltage detection circuit detects that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value, and A configuration (seventh configuration) may be adopted in which the switch is turned on.

In the semiconductor device according to any one of the first to sixth configurations, the boot voltage detection circuit detects that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value; A configuration (eighth configuration) may be adopted in which a boosted voltage higher than the input voltage input to the switch output stage is applied to the boot voltage application terminal.

In the semiconductor device according to any one of the first to eighth configurations, the boot voltage detection circuit includes a first resistor and a second resistor, a gate resistor, a P-channel type first transistor and a second transistor, and an N-channel type transistor. a third transistor and a fourth transistor, a first end of the first resistor is connected to the application end of the boot voltage, and a second end of the first resistor is connected to the first end of the first transistor. A first end of the gate resistor is connected to the application end of the switch voltage, a second end of the gate resistor is connected to the gate of the first transistor, and the second end of the gate resistor is connected to the gate of the first transistor. The drain of the first transistor is connected to the drain of the third transistor, and the source of the second transistor and the gate of the third transistor are both applied to an input voltage input to the switch output stage. The drain of the second transistor, the source of the third transistor, and the first end of the second resistor are all connected to a node voltage application terminal, and the drain of the second transistor is connected to the node voltage application terminal. The second end is connected to the drain of the fourth transistor, the source of the fourth transistor is connected to the ground terminal, and the boot voltage detection circuit generates a boot normality detection signal according to the node voltage. The controller is configured to turn off the second transistor and turn on the fourth transistor when the boot voltage detection circuit is in an operating state, and to set the second transistor in an on state when the boot voltage detection circuit is in an inactive state. A configuration (ninth configuration) may be adopted in which the second transistor is in an on state and the fourth transistor is in an off state.

Further, for example, the switching power supply disclosed in this specification includes a semiconductor device according to any one of the first to ninth configurations, and drives the switch output stage to generate a desired output voltage from the input voltage. The configuration (10th configuration) is as follows.

For example, the gate drive circuit (2) according to one aspect of the present disclosure includes a high-side transistor (HM) and a low-side transistor connected in series between an input voltage (PVIN) application end and a ground potential application end. A gate drive circuit (10) for driving a transistor (LM), comprising a first level shifter (5A) configured to be able to input a low side gate control signal (LGCTL), and a gate drive circuit (10) based on the output of the first level shifter. A low side gate signal output section (53) configured to generate a low side gate signal (LG) for driving the gate of the low side transistor, and a second level shifter (8) configured to be able to receive the output of the first level shifter. ), a third level shifter (3) configured to be able to input a high side gate control signal (HGCTL), and a first logic gate configured to be configured to receive the output of the second level shifter and the output of the third level shifter. (41); and a high-side gate signal output section (42) configured to generate a high-side gate signal (HG) for driving the gate of the high-side transistor based on the output of the first logic gate; The first level shifter is configured to output the input voltage as a high level, and the second level shifter and the third level shifter are configured to connect the high side transistor and the low side transistor to a node ( The high-side gate signal output section is configured to output, as a high level, a boot voltage (BOOT) generated at a second end of a boot capacitor (Cb) having a first end connected to the high-side The boot voltage can be applied to the gate of the high-side transistor as a gate signal (eleventh configuration).

Further, in the eleventh configuration, the first level shifter (5A) further includes a switch voltage detection section (6) configured to detect a decrease in the switch voltage (SW) occurring at the node (Nsw). , a second logic gate (51) configured to be able to input the low side gate control signal (LGCTL) and the detection signal (SWFB) of the switch voltage detection section; and a second logic gate (51) configured to be able to input the output of the second logic gate. (12th configuration).

Further, in the eleventh or twelfth configuration, a third logic gate (43) configured to be able to input the output of the third level shifter (3) and the output of the first logic gate (41), and a power supply voltage a switch (44) connected between the application terminal of (PVIN) and the gate of the high-side transistor (HM) and configured to be turned on and off based on the output of the third logic gate; It is good also as a structure further provided (13th structure).

Furthermore, in the thirteenth configuration, the power supply voltage is preferably the input voltage (PVIN) (fourteenth configuration).

Further, in the thirteenth or fourteenth configuration, a delay time between input and output in the first level shifter (5A) is td3_1, a delay time in the low side gate signal output section (53) is td3_2, and a delay time in the third level shifter (5A) is td3_1. It is also possible to adopt a configuration in which td3_1+td3_2<td1 holds, assuming that the delay time between input and output in (3) is td1 (fifteenth configuration).

Further, in any one of the thirteenth to fifteenth configurations, the delay time between input and output at the first level shifter (5A) is td3_1, and the delay time between input and output at the third level shifter (3) is td1. , the delay time between input and output of the second level shifter (8) may be td2, and a configuration may be adopted in which td1<td3_1+td2 holds true (sixteenth configuration).

Furthermore, in the sixteenth configuration, the second level shifter (8) and the third level shifter (3) may have the same configuration (seventeenth configuration).

Further, in any one of the thirteenth to seventeenth configurations, a configuration may further include a delay circuit (45) connected between the third logic gate (43) and the switch (44). 18 configurations).

Further, a semiconductor device (1) according to an aspect of the present disclosure includes a built-in gate drive circuit (10) having any one of the thirteenth to eighteenth configurations and the boot capacitor (Cb). 19th configuration).

Further, a DC/DC converter (Y) according to one aspect of the present disclosure includes a gate drive circuit (10) having any of the first to eighth configurations, the high side transistor (HM), and the low side transistor. (LM), an inductor (L) having a first end connected to a node (Nsw) to which the high-side transistor and the low-side transistor are connected, and an output capacitor (L) connected to the second end of the inductor. Cout) and (20th configuration).

<Other variations>
Note that the various technical features disclosed in this specification can be modified in addition to the above-described embodiments without departing from the gist of the technical creation. In other words, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present disclosure is defined by the claims, and the technical scope of the present disclosure is defined by the claims. It should be understood that all changes that come within the meaning and range of equivalence of the claims are included.

For example, the present disclosure can be applied not only to a DC/DC converter but also to driving a transistor in an inverter circuit that performs DC/AC conversion.

1 Semiconductor device 2 Logic section 3 Level shifter 4 High side driver 5 Low side driver 6 Switch voltage detection section 7 Boot switch 8 Level shifter 9 Gate drive circuit 10 Semiconductor device (power supply control IC)
11 Error amplifier 12 Comparison circuit 121 First comparator 122 Second comparator 13 On-time setting circuit 14 Ripple generation circuit 15 Addition circuit 16 Drive control circuit 161 Controller 162, 165 Level shifter 163, 164 Driver 17 Reference voltage generation circuit 18 Charge pump 19 Zero cross Detection circuit 20 Boot voltage detection circuit 21 AND circuit 22 AND circuit 41 Logic gate 42 High side gate signal output section 43 AND circuit 44 Switch 45 Delay circuit 5A Level shifter 51 AND circuit 52 Inverter 53 Low side gate signal output section BS switch BST Bootstrap circuit C1-C4 Capacitor Cb Boot capacitor Cout Output capacitor CMP Comparator HM High-side transistor INV1-INV4 Inverter L1, L Inductor LM Low-side transistor M1 Output element (NMOSFET)
M2 synchronous rectifier (NMOSFET)
N1~N7 Transistor (NMOSFET)
P1~P7 Transistor (PMOSFET)
R1 to R4, R10 to R13 Resistor SWO Switch output stage Tb Boot terminal Tgnd Ground terminal Tin Input voltage terminal Tsw Switch terminal X0 Switching power supply X, Y, Z DC/DC converter

Claims (10)

1. a first driver configured to drive an output element forming a switch output stage;
   at least a portion of a bootstrap circuit configured to generate and supply a boot voltage higher than a switch voltage output from the switch output stage to the first driver;
   A boot voltage detection circuit configured to charge the boot voltage by detecting that a difference value between the boot voltage and the switch voltage has become lower than a lower limit detection value when the output element is in an off state. and,
   a controller configured to switch the boot voltage detection circuit between an active state and a non-active state;
   A semiconductor device comprising:
2. The controller provides a predetermined boot voltage detection period to bring the boot voltage detection circuit into an operating state before switching the output element and the rectifier forming the switch output stage from an OFF state to an ON state. The semiconductor device according to claim 1.
3. The semiconductor device according to claim 2, wherein the controller provides the voltage detection period when both the output element and the rectifier are in an off state over a no-load determination period.
4. The controller maintains the operating state of the boot voltage detection circuit at least until the boot voltage exceeds the lower limit detection value after charging of the boot voltage is started according to the detection result of the boot voltage detection circuit. The semiconductor device according to claim 2 or 3.
5. 5. The semiconductor device according to claim 2, wherein the rectifying element is a synchronous rectifying element configured to be driven complementary to the output element.
6. further comprising a second driver configured to drive the synchronous rectifier,
   The controller drives the output element and the synchronous rectifier in a complementary manner, and the switch voltage becomes higher than a zero-cross detection value when the output element is in an off state and the synchronous rectifier is in an on state. 6. The semiconductor device according to claim 5, wherein said synchronous rectifying element is turned off by detecting that said synchronous rectifying element is turned off.
7. The boot voltage detection circuit detects that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value and turns on the synchronous rectifier. The semiconductor device described.
8. The boot voltage detection circuit detects that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value, and outputs a boosted voltage higher than the input voltage input to the switch output stage. 7. The semiconductor device according to claim 1, wherein the boot voltage is applied to the application terminal.
9. The boot voltage detection circuit includes a first resistor and a second resistor, a gate resistor, a P-channel type first transistor and a second transistor, and an N-channel type third transistor and a fourth transistor,
   A first end of the first resistor is connected to an application end of the boot voltage,
   a second end of the first resistor is connected to a source of the first transistor;
   A first end of the gate resistor is connected to an application end of the switch voltage,
   A second end of the gate resistor is connected to the gate of the first transistor,
   The drain of the first transistor is connected to the drain of the third transistor,
   The source of the second transistor and the gate of the third transistor are both connected to an application terminal of an input voltage input to the switch output stage,
   The drain of the second transistor, the source of the third transistor, and the first end of the second resistor are all connected to a node voltage application end,
   a second end of the second resistor is connected to a drain of the fourth transistor,
   The source of the fourth transistor is connected to a ground terminal,
   The boot voltage detection circuit outputs a boot normality detection signal according to the node voltage,
   The controller is configured to turn off the second transistor and turn on the fourth transistor when the boot voltage detection circuit is in an active state, and to turn off the second transistor when the boot voltage detection circuit is in an inactive state. 9. The semiconductor device according to claim 1, wherein the fourth transistor is turned on and the fourth transistor is turned off.
10. A switching power supply comprising the semiconductor device according to any one of claims 1 to 9, which drives the switch output stage to generate a desired output voltage from an input voltage.

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