JP2002281743A - Semiconductor integrated circuit and portable electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a conventional common synchronous rectification type switching regulator, where a power loss is small when a load is relatively heavy but the power loss is large when the load is light. SOLUTION: In a synchronous rectification type switching regulator which has a pair of switches (SW1 and SW2) whose ON/OFF operations are complementarily controlled to supply a current to an inductor, a reverse current detection circuit (22) which detects a reverse direction current supplied to the voltage input terminal side switch (SW1) is provided and, when the reverse current is detected, the reference potential side switch (SW2) is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for improving the conversion efficiency of a switching regulator, and more particularly, to a case where the conversion efficiency is improved by switching the ON / OFF timing of a switch element according to the size of a load in a step-down switching regulator. The present invention relates to a technology which is effective when applied, for example, a technology which is effective when used in a switching power supply circuit mounted on a portable electronic device.

[0002]

2. Description of the Related Art As shown in FIG. 11, a step-down switching regulator has a switch connected in series between a voltage input terminal VIN to which a power supply voltage supplied from a battery or the like is applied and a reference voltage terminal GND. An element SW1 and a reverse diode D1, and an inductance element L1 connected between a connection node n1 between the switch element SW1 and the diode D1 and an output terminal VOUT;
The switch element SW1 is turned on and off to supply current to the capacitive load CL and the resistive load RL via the inductance element L1, thereby outputting a voltage corresponding to the duty ratio of the control pulse Pc of the switch element.

In such a switching regulator, when the switch element SW1 is in an off state, a current flows from the reference voltage terminal GND to the inductance element L1 through the diode D1, but at this time, a loss occurs in the forward voltage VF of the diode D1. Therefore, as shown in FIG. 12, a synchronous rectification type switching regulator has been developed in which the diode D1 is replaced with a switch SW2 and the loss is reduced by performing on / off control complementary to SW1.

[0004]

In the synchronous rectification type switching regulator shown in FIG. 12, when the load is relatively heavy (when the load resistance RL is small), the power loss is small, but the load is light. When the load resistance RL increases, the power loss increases. Considering the direction of the current flowing through the inductance element L1, when the load is heavy, as shown in FIG. 13B, the current flowing through the inductance element L1 is always the output terminal VOU.
Although the direction is a current (positive) toward T, when the load is reduced, as shown in FIG. 13C, the direction of the current flowing through the inductance element L is reversed, and the current flows from the inductance element L1 to the reference voltage terminal GND through the switch element SW2. This is because a current (negative) flowing toward the portion is generated, and the portion indicated by hatching a becomes a loss. The reason that the portion does not cause a loss in b is that the current in this portion is the switch SW.
Voltage input terminal V through a parasitic diode on one substrate
This is a current flowing toward IN, which is a current for charging the battery.

In order to reduce the above-mentioned loss, there has been proposed an invention in which a light load state in which a reverse current flows through the inductance element L1 is detected to turn off the ground-side switch element SW2. (Japanese Patent Laid-Open No. 200
No. 0-92824). However, the prior invention detects the current flowing to the ground side and detects the switching element SW2.
Is turned off.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit for forming a synchronous rectification type switching regulator capable of detecting a reverse flow flowing through an inductance element by a method different from the conventional one and reducing power loss at a light load. And a switching power supply circuit using the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

In a synchronous rectification type switching regulator, attention is paid to a period (dead time) in which a switch element on a voltage input terminal side and a switch element on a reference potential terminal (ground) side are both turned off. ,
During this period, when the load is heavy and the current of the inductance element is not reversed, the potential of the intermediate node of the switch element is slightly lower than the reference potential, and when the load is light and the current of the inductance element is reversed. Is that the potential of the intermediate node of the switch element is higher than the input voltage. That is, a significant difference occurs in the potential of the intermediate node of the switch element during the dead time due to the presence or absence of the backflow. Therefore, the presence or absence of the backflow can be detected extremely easily and reliably by detecting the potential of the intermediate node.

The present invention has been made based on such knowledge, and has a first switch element and a second switch element connected in series between a voltage input terminal and a reference potential terminal, which are turned on and off complementarily. A voltage that is controlled to cause a current to flow through an inductance element connected between an intermediate connection node of the first and second switch elements and an output terminal to reduce the voltage applied to the voltage input terminal. A pulse generation circuit for generating ON / OFF control pulses for the first and second switch elements, and a clock signal required for generating pulses in the pulse generation circuit. The intermediate connection node based on the potential of the intermediate connection node during a period in which both the first and second switch elements are turned off. A detection circuit for detecting a current flowing from the input terminal to the voltage input terminal, when the detection circuit detects the current, at least during a period in which the second switch element is to be turned on. A switching control circuit for preventing the second switch element from being turned on.

According to the above-described means, the presence or absence of a reverse current (current flowing from the intermediate connection node toward the voltage input terminal) causes a remarkable difference in the potential of the intermediate node of the switch element during the dead time, so that it is extremely easy. In addition, the presence or absence of a reverse current can be reliably detected. However,
Instead of detecting the potential of the intermediate connection node, a current detection circuit for detecting a current flowing from the intermediate connection node to the voltage input terminal may be provided. A clock signal required for generating a pulse in the pulse generation circuit may be supplied from outside the chip.

Further, the detection circuit is constituted by a comparator for detecting a potential difference between both terminals of the first switch element. As a result, the reverse current detection circuit can be configured with an existing simple circuit.

Further, the detection circuit detects a resistance element connected in series with the first switch element between the voltage input terminal and the intermediate connection node, and detects a potential difference between both terminals of the resistance element. And a comparator. Although the potential difference between both terminals of the switch element is relatively small and hard to detect, a reverse current can be reliably detected by connecting a resistor in series with the switch element and detecting the voltage between both terminals.

Further, the detection circuit is provided with offset means for applying an offset to the potential on the intermediate connection node side and applying the offset to the input terminal of the comparator. This makes it possible to increase the difference between the detection potential of the comparator and the comparison potential both when the reverse current flows and when the reverse current does not flow, to reliably detect the reverse current, Can be faster.

[0014] The detection circuit is configured to determine a potential between the potential of the intermediate connection node when a current flows toward the output terminal and the potential of the intermediate connection node when a current flows toward the voltage input terminal. And a comparator for comparing the voltage generated by the stop voltage generating circuit with the potential of the intermediate connection node to detect a backflow. Even in this case, the difference between the detection potential of the comparator and the comparison potential is increased in both cases when the backflow is flowing and when the backflow is not flowing, and the reverse current can be reliably detected.

More preferably, the clock generation circuit has an oscillation circuit, and the oscillation circuit is configured to reduce the oscillation frequency when the detection circuit detects a backflow. As a result, the current flowing through the inductance element can be reduced, and the time itself during which the reverse current flows can be reduced.

A portable electronic device according to the present invention includes a semiconductor integrated circuit having the above-described configuration, and the first switch element and the second switch element that are turned on and off by a control pulse output from the semiconductor integrated circuit. A switching element, an inductance element having one terminal coupled to an intermediate connection node of these switching elements, and a capacitance element connected between the other terminal of the inductance element and a constant potential point. A switching power supply device is provided in which a switching element, the inductance element, and the capacitance element are connected as external elements to the semiconductor integrated circuit.
As a result, power loss of the switching power supply device at light load can be reduced, battery consumption can be reduced, and a portable electronic device that can be driven for a long time by a battery can be obtained.

According to another aspect of the present invention, a first switch element and a second switch element connected in series between a voltage input terminal and a reference potential terminal are complementarily turned on and off. A current flowing through an inductance element connected between an intermediate connection node of the first and second switch elements and an output terminal to output a voltage obtained by stepping down a voltage applied to the voltage input terminal; A semiconductor integrated circuit according to claim 1, wherein said first and second switch elements;
A pulse generation circuit for generating ON / OFF control pulses for these switch elements, a clock generation circuit for generating a clock signal required for generating a pulse in the pulse generation circuit, and the first and second switch elements are both A detection circuit for detecting a current flowing through the inductance element based on a potential of the intermediate connection node during a period in which the second connection node is turned off; and when the detection circuit detects the current, at least the second And a switching control circuit for preventing the second switch element from being turned on during a period when the switch element is to be turned on.

According to the above-described means, a significant difference occurs in the potential of the intermediate node of the switch element during the dead time depending on the presence or absence of the reverse current, so that the presence or absence of the reverse current can be detected very easily and reliably. Moreover, unlike the first invention, the first and second switch elements are provided on the same semiconductor chip as the switching control circuit, so that the number of external elements, that is, the number of components is small, and the mounting density is low. Can be enhanced. However, instead of detecting the potential of the intermediate connection node, a current detection circuit for directly detecting a current flowing from the intermediate connection node to the voltage input terminal may be provided. A clock signal required for generating a pulse in the pulse generation circuit may be supplied from outside the chip.

Further, the detection circuit comprises a comparator for detecting a potential difference between both terminals of the first switch element. As a result, the reverse current detection circuit can be configured with an existing simple circuit.

Further, the detection circuit detects a resistance element connected in series with the first switch element between the voltage input terminal and the intermediate connection node, and detects a potential difference between both terminals of the resistance element. And a comparator. Although the potential difference between both terminals of the switch element is relatively small and hard to detect, a reverse current can be reliably detected by connecting a resistor in series with the switch element and detecting the voltage between both terminals.

Further, the detection circuit is provided with offset means for giving an offset to the potential on the intermediate connection node side and applying the offset to one input terminal of the comparator.
Thus, the difference between the detection potential of the comparator and the comparison potential is increased in both cases when the reverse current flows and when the reverse current does not flow, and the reverse current can be reliably detected.

[0022] The detection circuit is configured to determine a potential between the potential of the intermediate connection node when a current flows toward the output terminal and the potential of the intermediate connection node when a current flows toward the voltage input terminal. , And a comparator that compares the voltage generated by the stop voltage generating circuit with the potential of the intermediate connection node to detect a reverse current. Even in this case, the difference between the detection potential of the comparator and the comparison potential is increased in both cases when the reverse current is flowing and when the reverse current is not flowing, and the reverse current can be reliably detected.

More preferably, the clock generation circuit has an oscillation circuit, and the oscillation circuit is configured to lower the oscillation frequency when the detection circuit detects a current. As a result, the current flowing through the inductance element can be reduced, and the time itself during which the reverse current flows can be reduced.

A portable electronic device according to the present invention is a semiconductor integrated circuit having the above configuration, and an inductance element having one terminal coupled to an intermediate connection node between the first switch element and the second switch element. And a capacitance element connected between the other terminal of the inductance element and the constant potential point, wherein the inductance element and the capacitance element are connected to the semiconductor integrated circuit as external elements. It is provided. Thereby, the power loss of the switching power supply device at the time of light load can be reduced, the battery consumption can be reduced, and a portable electronic device that can be driven for a long time by a battery can be obtained.
Since the first and second switch elements are formed on the same semiconductor chip as the switching control circuit, the number of components constituting the switching power supply device is small, and the size of the portable electronic device can be reduced.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a step-down switching regulator to which the present invention is applied. In FIG. 1, a circuit portion surrounded by a chain line 10 is formed on one semiconductor chip such as single crystal silicon. Elements other than the circuit 10 are configured by discrete electronic components. Among these elements, a circuit such as a semiconductor integrated circuit (IC) that operates by receiving a voltage from the switching regulator of the present embodiment is shown as a resistive load RL. What is indicated as the capacitive load CL is
This is a smoothing capacitor that suppresses fluctuations in the output voltage. The circuit portion surrounded by the broken line 11 instead of the dashed line 10 may be formed as a semiconductor integrated circuit on one semiconductor chip.

The switching regulator of this embodiment is connected in series between the control semiconductor integrated circuit 10, a voltage input terminal VIN to which a DC voltage supplied from a battery or the like is input, and a reference potential terminal GND. MOSFE
Switches SW1 and SW2 made of T
An inductance element L1 connected between the intermediate node n1 of the first and second switches SW1 and SW2 and the output terminal VOUT;
And a grounding point, a smoothing capacitor CL, a switching control circuit 20 that is applied to the gates of the switches SW1 and SW2 to generate a signal (control pulse) for turning on and off the switches SW1 and SW2, And a clock generation circuit 30 that generates a clock signal required for generation (hereinafter, simply referred to as a clock).

Although not particularly limited, in this embodiment, the switch SW1 is a p-channel type MOSFET.
T, and the switch SW2 is an n-channel MOSFET
It is composed of These switch MOSFETs S
When W1 and SW2 are composed of separate components from the semiconductor integrated circuit including the switching control circuit 20 (broken line 11), SW1 and SW2 are each composed of separate components (power MOSF).
ET), but p-channel type MOS
Since an IC in which the FET and the n-channel type MOSFET are enclosed in one package is also provided, it may be used.

The switching control circuit 20 receives a reference clock CLK and generates a control pulse generation circuit 21 for generating a clock / CLK1 for controlling the switch SW1 and a clock / CLK2 for controlling the switch SW2. And a reverse current detecting circuit 22 for detecting a reverse current flowing from the inductance element L1 to the voltage input terminal VIN.
And a NAND gate circuit 23 which takes the logical product of the output signal DT of the reverse current detection circuit 22 and the clock / CLK1
A flip-flop 24 that receives the output of the NAND gate circuit 23 at a set terminal S and receives the clock / CLK1 at a reset terminal R to perform a set / reset operation;
NAND gate circuit 25 which takes the logical product of inverted output / Q of flip-flop 24 and clock / CLK2
And an inverter 26 that inverts the output of the NAND gate circuit 25 and applies the inverted output to the gate of the switch SW2.

The control pulse generation circuit 21 includes a switch S
W1 and SW2 are simultaneously turned on to generate control clocks / CLK1 and / CLK2 including a dead time for preventing a through current from flowing. The flip-flop 24 is set when the reverse current detection circuit 22 detects the reverse current in the dead time, controls the NAND gate 25, and controls the clock CLK2 in the next stage.
Is not supplied to the gate of the MOSFET SW2 and the switch SW2 is turned off.
Although not particularly limited, the output Q of the flip-flop 24 is output to the clock generation circuit 30 as the light load detection signal LLD.

The clock generation circuit 30 generates an oscillation circuit 31 for outputting a signal of a predetermined frequency, and a waveform for shaping a signal (triangular wave) output from the oscillation circuit 31 to generate and output a reference clock CLK composed of a rectangular pulse. It comprises a shaping comparator 32 and an output level detecting comparator 33 for detecting whether or not the output voltage VOUT has dropped below a predetermined level. Then, when the output level detection comparator 33 detects a decrease in the level of the output voltage VOUT, the output changes, so that the comparison voltage of the waveform shaping comparator 32 changes. As a result, the level for discriminating the output signal of the oscillation circuit 31 is changed, and the pulse width of the generated clock CLK is switched. That is,
The duty ratio of the generated clock CLK switches according to the level of the output voltage VOUT.

The oscillation circuit 31 has a frequency switched based on the light load detection signal LLD from the switching control circuit 20, and forms and outputs a clock having a different frequency according to the load. Specifically, as described later, when the load is light, the oscillation frequency of the oscillation circuit 31 decreases, and the clock generation circuit 30 generates and outputs a reference clock CLK having a lower frequency than when the load is heavy.

Next, the specific operation of the switching regulator of the above embodiment will be described with reference to the timing chart of FIG.

The pulse generation circuit 21 receives the reference clock CL
2B and 2C, a clock / CLK2 that changes to a low level in response to the rise of the reference clock CLK, and when a predetermined delay time TDB elapses after the / CLK2 changes to a low level. And a clock / CLK1 that changes to a low level. Clock / CL
Since the clock / CLK2 changes to low level before K1 changes to low level, the switches SW1 and SW2 are changed.
Are both turned off. In this specification, this period TDB is called dead time.

In the dead time TDB, when the load is heavy, the current IL flowing toward the output terminal VOUT is always applied to the inductance element L1 as shown in FIG. 2D (the current in this direction is defined as positive in this specification). When the load is light, the current IL flowing through the inductance element L1 changes between positive and negative as shown in FIG. That is, the direction of the current changes. And, accordingly, the inductance element L
2 is connected to the potential Vc of the intermediate node n1 to which
Significant differences occur as shown in (E) and (G). this is,
This is because the nature of the inductance element L1 has an effect of continuously maintaining the current flowing therethrough.

That is, when the load is heavy and the direction of the current flowing through the inductance element L1 is always positive as shown in FIG. 2D, when the switch SW2 is turned off at the timing t1, the diode parasitic on the base of the switch SW2. The current IL flowing to the inductance element L1 through D2 is supplied. The switch S on the voltage input terminal side
The parasitic diode D1 is also present on the substrate of W1, but since the diode D1 is oriented in the opposite direction toward the output terminal, the current flowing through the inductance element L1 is blocked in order to block the current flowing toward the inductance element L1. IL is supplied through a diode D2 which is parasitic on the base of the switch SW2.

The current flowing through the inductance element L1 is changed to a diode D2 which is parasitic on the base of the switch SW2.
In order to flow toward the output terminal VOUT through the gate, the potential of the intermediate node n1 must be lower than the potential of the ground terminal GND (for example, 0 V). Therefore, when the load is heavy, the potential Vc of the intermediate node n1 is maintained at a potential lower than the ground potential GND by the forward voltage VF of the diode D2 during the dead time TDB as shown in FIG. Becomes

On the other hand, when the load is light, the switch SW1
Is turned off and the direction of the current IL flowing through the inductance element L1 while the switch SW2 is turned on is switched from positive to negative as shown in FIG. Then, when the switches SW1 and SW2 are turned off at the timing t1, the current flowing toward the ground through the switch SW2 is cut off, but the inductance element L1 tries to continue to flow the current in that direction (negative). Then, the current flows toward the voltage input terminal VIN through the diode D1 parasitic on the base of the switch SW1 in the forward direction with respect to the current. At this time, the parasitic diode D2 of the switch SW2 on the ground terminal side has a direction opposite to that of the current flowing from the output terminal to the intermediate node n1, and thus blocks the current flowing toward the ground terminal.

Then, a current flowing through the inductance element L1 is changed to a diode D1 which is parasitic on the base of the switch SW1.
In order to flow toward the voltage input terminal VIN through the gate, the potential of the intermediate node n1 must be higher than the potential of the voltage input terminal VIN. Therefore, when the load is light, the potential Vc of the intermediate node n1 is maintained at a potential higher than the potential of the voltage input terminal VIN by the forward voltage VF of the diode D1 during the dead time TDB as shown in FIG. Will be done. In FIG. 2, it is apparent from a comparison between potential Vc (E) of intermediate node n1 when the load of dead time TDB is heavy and potential Vc (G) of intermediate node n1 when the load of dead time TDB is light. Are very different because they are divided into a positive voltage and a negative voltage, and the potential difference is large.

In the switching regulator of the present invention, the reverse current in the dead time TDB or the difference in the potential Vc of the intermediate node n1 caused by the reverse current is detected by the reverse current detection circuit 22. FIG. 3 shows the output DT of the backflow detection circuit 22 and the output / Q of the flip-flop 24 latched thereby.
And the clock / supplied to the gate of the switch SW2
The waveform of CLK2 'is shown. However, since the dead time TDB is relatively short, it is omitted in FIG.

As shown in FIG. 3, when a backflow (negative current) occurs in the current flowing through the inductance element L1, the backflow is detected by the backflow detection circuit 22 and its output DT is detected.
Changes to a high level (timing t2). Then
Clock / CLK1 controlling gate of switch SW1
The flip-flop 24 is set at the rising timing t3, and its output / Q changes to low level. As a result, the pulse generation circuit 21 outputs the NAND gate 2
5, The clock / CLK2 supplied to the gate of the switch SW2 via the inverter 26 is cut off, and the transition of the switch SW2 to the ON state in the next stage is not performed. As a result, the reverse current flowing through the inductance element L1 is cut.

Since the reverse current detection circuit 22 does not detect the reverse current in the cycle in which the reverse current is cut, its output DT is kept at a low level, and the rising timing t4 of the clock CLK at the start of the next cycle.
Resets the flip-flop 24 and outputs / Q
Changes to a high level. As a result, the clock / CLK2 from the pulse generation circuit 21 is again applied to the NAND gate 2
(5) The power is supplied to the gate of the switch SW2 via the inverter 26, and the switch SW2 is turned on.

In this embodiment, the inductance element L1
The switching control circuit 20 is configured such that when the backflow of the current flowing through the switch is detected by the backflow detection circuit 22, the pulse of the clock / CLK2 for turning on the switch SW2 on the ground side is cut only once in the next stage. However, the pulse of the clock / CLK2 is output twice or three times.
It is also possible to configure to cut more than once.

FIG. 4 shows a more specific embodiment of the backflow detecting circuit 22 provided in the switching control circuit 20. In this embodiment, the switch S on the voltage input terminal side is used.
A resistor Rd for current-voltage conversion is provided between W1 and an intermediate node n1 to which the inductance element L1 is connected, and a comparator CMP for detecting a voltage between both terminals of the resistor Rd is provided. . Other configurations are the same as those of the switching control circuit of the embodiment of FIG.

The terminal voltage V of the resistor Rd on the switch SW1 side
a indicates a potential V of the intermediate node n1 when a forward current flowing toward the output terminal is flowing through the inductance element L1.
However, in the dead time TDB when both the switches SW1 and SW2 are turned off, the potential becomes lower than the potential Vc of the intermediate node n1 by the forward voltage VF of the diode. The comparator CMP detects the reversal of the potential and outputs a high-level detection signal.

The current flowing through the resistor Rd when the current flows backward is smaller than the current when the current flows in the forward direction, and the potential difference between the two terminals of the resistor Rd when the potential is reversed is relatively small. Node n1 and comparator CMP
Between the non-inverting input terminal and the potential V of the intermediate node n1.
Offset means for increasing c by ΔV and supplying it to the comparator CMP is provided. The offset amount ΔV given by the offset means is, for example, a resistance Rd
Let r be the resistance value of i and i be the average current in the forward direction.
/ 2 or less is desirable. Further, the resistance Rd
May be provided not between the switch SW1 and the intermediate node n1, but between the voltage input terminal VIN and the switch SW1.

FIG. 5 shows another embodiment of the backflow detecting circuit 22 provided in the switching control circuit 20. In this embodiment, the comparator CM detects the voltage between the source and the drain of the switch SW1 on the voltage input terminal side.
P is provided. Also in this embodiment, the potential Vc of the intermediate node n1 is increased by ΔV between the intermediate node n1 and the non-inverting input terminal of the comparator CMP so that the detection by the comparator CMP can be reliably performed. An offset means for supplying is provided. The offset amount ΔV provided by the offset means in this embodiment is, for example, の of the potential difference generated between the source and the drain due to the ON resistance of the switch SW1 when a current flows toward the output terminal.
It is desirable to set the following. The offset means can be constituted by, for example, a level shifter.

FIG. 6 shows still another embodiment of the backflow detecting circuit 22 provided in the switching control circuit 20. This embodiment is provided with a reference voltage circuit for generating a reference voltage VTH, and a comparator CCMP for comparing the potential Vc of the intermediate node n1 to which the inductance element L1 is connected with the reference voltage VTH to detect occurrence of a backflow. It is. The reference voltage VTH applied to the non-inverting force terminal of the comparator CCMP is equal to the potential Vc1 of the intermediate node n1 when the current flows toward the output terminal and the potential of the intermediate node n1 when the reverse current flows. It is desirable to set the potential to an intermediate potential (Vc1 + Vc2) / 2 with respect to the potential Vc2.

In this embodiment, if the potential Vc of the intermediate node n1 is constantly detected by the comparator CCMP, the potential Vc of the intermediate node n1 changes continuously, so that it is detected in addition to the dead time TDB. Since a signal may be output, a clocked comparator that performs comparison in synchronization with a clock is used as the comparator CCMP, and a positive signal having a uniform phase required for the clocked comparator CCMP based on the reference clock CLK. A phase alignment circuit 28 for generating clocks CLK ′ and / CLK ′ having a phase opposite to that of the phase is provided.

In this embodiment, the flip-flop 24 for latching the output of the backflow detection circuit 22 is omitted, and the NAND gate 2 for shutting off the clock / CLK2 for controlling the switch SW2 by the backflow detection signal.
5, a NOR gate 25 'is used, and the clock / C
The inverter 26 for inverting LK2 is connected to the NOR gate 2
It is provided not in the next stage of 5 'but in the preceding stage. However, a configuration similar to the embodiment of FIG. 1 is also possible.

FIG. 7 shows a specific example of the phase alignment circuit 28 in the embodiment of FIG. As shown in FIG. 7, the phase aligning circuit 28 includes an inverter 81 for inverting the input clock CLK, and NAND gates 82 and 83.
And a flip-flop using the clock CLK before inversion as an input signal. By using a circuit having such a configuration, the positive-phase clock CL
The phase of the clock / CLK ′ on the opposite phase to K ′ can be matched, and the clocks CLK ′ and / CLK ′ of the normal phase and the opposite phase
Comparator CCMP that operates in synchronization with
However, malfunction due to a clock phase shift can be prevented.

FIG. 8 shows a specific example of the clocked comparator CCMP in the embodiment of FIG. 8A shows a circuit suitable for static operation,
FIG. 8B illustrates a circuit suitable for dynamic operation using stray capacitance. The circuit in FIG. 8B requires fewer elements and consumes less power than the circuit in FIG. 8A. However, when the operation of the comparator is not performed frequently, the charge of the stray capacitance leaks. Therefore, there is a possibility that the accuracy may be reduced, so that it is necessary to select the value according to the system to be used.

The circuit shown in FIG. 8A includes a comparator CMP
The master flip-flop M-FF is connected to the subsequent stage via the transmission switch TS1, and the slave flip-flop S-FF is connected to the subsequent stage via the transmission switch TS2.
The comparison result of the comparator CMP during the period when the clock / CLK 'is at a high level is latched and output by controlling the ON / OFF of the clock / CLK' and the clock CLK 'having the opposite phase to the clock / CLK'. Can be.

The circuit shown in FIG. 8B is a comparator CMP
At the subsequent stage via the transmission switch TS1 and the inverter INV
1 and an inverter INV2 connected to the subsequent stage via a transmission switch TS2. The transmission switch TS1 is turned on by a clock / CLK ', and the transmission switch TS2 is turned on by a clock CLK' having an opposite phase to the clock / CLK '. By performing the off control, the comparison result of the comparator CMP during the period when the clock / CLK ′ is at the high level can be held in the stray capacitance Cs and output.

FIG. 9 shows a specific example of the oscillation circuit 31 constituting the clock generation circuit 30. The oscillation circuit of this embodiment comprises a capacitor 311, a constant current source 312 for charging the capacitor 311, and a pair of parallel constant current sources 313 a and 31 for discharging the capacitor 311.
3b, a comparator 314 that compares the charging voltage of the capacitor 311 with the reference voltage Vr, and is connected between the charging side terminal of the capacitor 311 and the constant current sources 313a and 313b, and is turned on and off by an output signal of the comparator 314. A controlled switch 315 and a constant current source 313
b and a switch 316 that is connected in series and is turned on and off by a light load detection signal LLD from the switching control circuit 20. The comparator 314 having a hysteresis characteristic is used.

The operation of the oscillation circuit 31 and the waveform shaping comparator 32 having the above configuration will be described with reference to FIG. First, consider a state in which the switch 315 is off and the switch 316 is on. In this state, the capacitor 311 is charged by the current of the constant current source 312, and the voltage Vb gradually increases as in a period Ta in FIG. 10A, and when the voltage reaches the reference voltage Vr, the output of the comparator 314 is inverted. Then, the switch 316 is turned on. Then, the current of the constant current sources 313a and 313b causes
1 is withdrawn, and the voltage Vb drops rapidly as in the period Tb in FIG. As a result, the output of the comparator 314 is inverted, the switch 315 is turned off, the capacitor 311 is charged again by the current of the constant current source 312, and the voltage Vb gradually increases. By repeating this, the oscillation circuit 31 outputs the signal shown in FIG.
An oscillation signal of a triangular wave is output.

In the circuit of FIG. 9, the switch 316 is turned off by a light load detection signal LLD from the switching control circuit 20 which is output when a light load is detected. When the switch 316 is turned off, the capacitor 31
Since only the constant current source 313a is used as the extraction current at the time of the discharge of 1, the change in the voltage Vb becomes gentle as in the period Tc in FIG. This lowers the frequency of the output signal of the oscillation circuit.

In the normal state, the waveform shaping comparator 32 is supplied with a discrimination voltage V1 having a level as shown by a dashed line in FIG.
10 (b) by discriminating the oscillation output Vb of FIG.
A rectangular pulse as shown in (e) is output. On the other hand, when the comparator 33 shown in FIG. 1 detects a decrease in the output voltage VOUT, the discrimination voltage V1 of the comparator 32 is switched to a lower voltage such as V2.

As a result, the comparator 32 operates as shown in FIG.
A rectangular pulse having a wider pulse width, that is, a larger duty ratio than the pulse of (b), such as 0 (c) and (f), is output to the switching control circuit 20 as the reference clock CLK. As a result, the period during which the switch SW1 is turned on becomes longer, and the output voltage VOUT rises.

If the switch SW1 is turned on in response to the high level period of the reference clock CLK,
The output voltage VOUT is determined by the input voltage VIN and the duty ratio Du of the reference clock CLK, and can be expressed by VOUT ≒ VIN ・ Du. However, strictly speaking, the on-duty of the switch SW1 depends on the switch SW1 and the inductance element L1.
It depends on the load such as the internal resistance and the resistance of the wiring, but it can be seen that it does not depend on the load macroscopically.

Next, the condition of the synchronous rectification type switching regulator as to whether or not a reverse current flows through the inductance, that is, whether or not the present invention is applied will be described.

In the switching regulator of FIG. 11, the inductance of the inductance element L1 is L, L
Assuming that the voltage between both terminals of the switch 1 is VL and the switching frequency of the switch SW1 is fsw, VL = Ldi / dt (1) VL = VIN-VOUT (2) Then, the above equation (2) shows that VOUT ≒ VI
By substituting N · Du, the following equation is obtained: VL = VIN (1−Du) (3)

Since the current flowing through the inductance element L1 during the ON period ton of the switch SW1 is a constant current (when L1 is not saturated), the equation (1) can be modified as follows. That is, VL · dt = L · di VL · ton = L · IL (4) Here, when the equation (3) is substituted into the equation (4), the following equation is obtained: VIN (1−Du) · ton = L · IL (5)

In FIG. 11, assuming that the load capacitance CL is sufficiently large, the current IL flowing through the inductance element L1 can be macroscopically expressed as IL = VOUT / RL.
Equation (5) can be expanded as follows. That is, VIN (1-Du)） ton = L ・ VOUT / RL = L ・ VIN ・ Dut / RL. Therefore, L = VIN (1−Du) · ton · RL / VIN · Du = RL · ton (1 / Du−1) (6)

The inductance L is calculated based on the above equation (6).
FIG. 14 is a graph showing the relationship between the load resistance RL and the load resistance RL. FIG. 14 shows the case where the switching frequency fsw is 500 kHz and 1 MHz when the input voltage VIN is 4 V, the output voltage VOUT is 2 V, the average current flowing through the inductance element is 0.1 A, and the duty is 50%. This shows the relationship between L and RL. In FIG. 14, the characteristic α is obtained when fsw is 500 kHz, and the characteristic β
Is a case where fsw is 1 MHz, and the lower side of each line is a commutation region where a backflow occurs in the inductance element.

From FIG. 14, it can be seen that when the load resistance RL and the duty are constant, the backflow does not occur even if the inductance L is reduced, so that the switching frequency fsw
It can be seen that it is sufficient to increase However, if the switching frequency fsw is set too high, the loss at the switch SW1 increases. Considering the loss in the switch SW1, the switching frequency fsw is 1M because it is too high at 1MHz.
Hz or less, and preferably about 500 kHz.

Here, the switching frequency fsw is 500
Considering the case of kHz, from FIG. 14, it can be seen from FIG. 14 that when the load resistance RL is 100Ω, a reverse current is generated with an inductance of 50 μH, so that an inductance of 100 μH or more is generated. It can be seen that when the load resistance RL is 10Ω, an inductance of 5 μH causes a reverse current, so that an inductance of 10 μH or more must be used.

Incidentally, in an electronic device such as a mobile phone which requires a reduction in size, it is desirable that the inductance element be as small as possible. For example, as an IC that operates by receiving the voltage of a switching regulator, a load resistor R
It can be seen from FIG. 14 that in a device where L is 10Ω or more and a device of 5 μH must be used as an inductance element, it is impossible to prevent backflow from FIG. Therefore, in such a case, the switch S is detected by detecting the reverse flow of the inductance element.
It can be seen that it is desirable to apply the synchronous rectification type switching regulator of the above embodiment that can turn off W2.

By using such a technique, it is relatively easy to determine whether to apply the present invention or to use a switching regulator to which the present invention is applied in designing or selecting a switching regulator. Becomes possible. When the clock duty is other than 50%, or when the input voltage VIN and the output voltage V
If the current flowing through OUT and the inductance is different from the above, a graph similar to that shown in FIG. 14 may be created using equation (6), and the determination may be made with reference to this graph.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above embodiment, the length of the dead time TDB is not mentioned, but a shorter time is preferable as long as it prevents the through current between the switches SW1 and SW2 and detects the backflow. Further, this time may be set according to the magnitude of the load.

Further, in the above embodiment, when the backflow detecting circuit 22 detects the backflow, the control pulse generating circuit 2
The clock signal / CLK2 supplied from 1 to the gate terminal of the switch element SW2 on the ground side is cut off by a NAND gate, a NOR gate, etc.
Although W2 is not turned on, the switching element S
It is also possible to provide a switch for pull-down between the gate terminal of W2 and the ground point and forcibly reduce the gate voltage to the ground potential to turn off the switch element SW2.

In the above description, an independent switching regulator which mainly uses the invention made by the present inventor as a power supply device of a portable electronic device, which is a background of application, has been described. It can be widely used for regulators and DC-DC converters.

[0073]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a synchronous rectification type switching regulator capable of detecting the reverse flow flowing through the inductance element and reducing the power loss at the time of light load can be constituted. As a result, the power loss of the power supply device can be reduced and the battery consumption can be reduced. And a portable electronic device that can be driven for a long time by a battery can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a step-down switching regulator to which the present invention is applied.

FIG. 2 is a waveform diagram showing a clock for turning on / off a switch and a voltage change of an intermediate node in the switching regulator of the embodiment.

FIG. 3 is a timing chart showing timings of signals of a switching control circuit in the switching regulator of the embodiment.

FIG. 4 is a circuit configuration diagram showing a more specific configuration example of a backflow detection circuit provided in the switching control circuit of the embodiment.

FIG. 5 is a circuit diagram showing another configuration example of the backflow detection circuit provided in the switching control circuit of the embodiment.

FIG. 6 is a circuit configuration diagram showing still another configuration example of the backflow detection circuit provided in the switching control circuit of the embodiment.

FIG. 7 is a circuit diagram showing a specific example of a phase alignment circuit in the switching control circuit of the embodiment of FIG. 6;

8 is a circuit configuration diagram showing a specific example of a clocked comparator in the switching control circuit of the embodiment of FIG.

FIG. 9 is a circuit diagram showing one embodiment of an oscillation circuit used in the switching control circuit of the embodiment.

FIG. 10 is an operation timing chart of the oscillation circuit of FIG. 9;

FIG. 11 is a circuit diagram showing a configuration example of a conventional basic step-down switching regulator.

FIG. 12 is a circuit diagram showing a configuration example of a conventional step-down rectification type switching regulator.

FIG. 13 is an operation timing chart of a conventional step-down rectification type switching regulator.

14 is a graph showing a relationship between an inductance L and a load resistance RL in the switching regulator of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor chip (semiconductor integrated circuit) 20 Switching control circuit 21 Control pulse generation circuit 22 Backflow detection circuit 30 Clock generation circuit SW1, SW2 Switch element L1 Inductance element RL Resistive load CL Capacitive load D1, D2 Parasitic diode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiichi Tokunaga 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Reihiko Kanoda Omikamachi, Hitachi City, Ibaraki 7-1-1 1-1 F-term in Hitachi Research Laboratory, Hitachi, Ltd. (Reference) 2G035 AA11 AA20 AB06 AB07 AC02 AC12 AC13 AC16 AD03 AD10 AD18 AD23 AD25 AD27 AD47 AD51 AD54 AD56 5H730 AA14 BB13 BB57 DD04 DD26 EE13 FD51 FD01 FD21 FD51 FD01 FG05

Claims (18)

[Claims] A first switch element and a second switch element which are connected in series between a voltage input terminal and a reference potential terminal, are controlled to turn on and off in a complementary manner, so that the first and second switch elements are turned on and off. A semiconductor integrated circuit for supplying a current to an inductance element connected between an intermediate connection node of a switch element and an output terminal to output a voltage obtained by stepping down a voltage applied to the voltage input terminal. A pulse generation circuit for generating an on / off control pulse for the first and second switch elements, a clock generation circuit for generating a clock signal required for generating a pulse in the pulse generation circuit, A detection circuit for detecting a current flowing toward the voltage input terminal, and when the detection circuit detects the current, at least the second switch The semiconductor integrated circuit characterized in that pitch elements and a switching control circuit so as not to turn on the second switching element during a period to be turned on. 2. A first switch element and a second switch element connected in series between a voltage input terminal and a reference potential terminal are complementarily turned on and off to control the first and second switch elements. A semiconductor integrated circuit for supplying a current to an inductance element connected between an intermediate connection node of a switch element and an output terminal to output a voltage obtained by stepping down a voltage applied to the voltage input terminal. A pulse generation circuit for generating an on / off control pulse for the first and second switch elements, a clock generation circuit for generating a clock signal required for generating a pulse in the pulse generation circuit; 2 based on the potential of the intermediate connection node during a period in which both switch elements are turned off. If the detection circuit detects the current, at least the second switch element should not be turned on at least during the next period when the second switch element should be turned on. And a switching control circuit. 3. The semiconductor integrated circuit according to claim 2, wherein said detection circuit comprises a comparator for detecting a potential difference between both terminals of said first switch element. 4. The detection circuit detects a resistance element connected in series with the first switch element between the voltage input terminal and the intermediate connection node, and detects a potential difference between both terminals of the resistance element. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit comprises: 5. The semiconductor according to claim 3, wherein the detection circuit has offset means for applying an offset to the potential on the intermediate connection node side and applying the offset to one input terminal of the comparator. Integrated circuit. 6. The detecting circuit according to claim 1, wherein a potential of the intermediate connection node when a current flows toward the output terminal is equal to a potential of the intermediate connection node when a current flows toward the voltage input terminal. A constant voltage generating circuit for generating a potential between the two, and a comparator for detecting a current by comparing the voltage generated by the stop voltage generating circuit with the potential of the intermediate connection node. The semiconductor integrated circuit according to claim 2. 7. The clock generating circuit according to claim 1, wherein said clock generating circuit has an oscillating circuit, and said oscillating circuit is configured to reduce an oscillating frequency when said detecting circuit detects a current. A semiconductor integrated circuit according to any one of the above. 8. A semiconductor integrated circuit according to claim 1, wherein said first switch element and said second switch element are turned on and off by a control pulse output from said semiconductor integrated circuit. And an inductance element having one terminal coupled to an intermediate connection node of these switch elements, and a capacitance element connected between the other terminal of the inductance element and a constant potential point. A portable electronic device comprising a switching power supply device in which the inductance element and the capacitance element are connected as external elements to the semiconductor integrated circuit. 9. A first switch element and a second switch element connected in series between a voltage input terminal and a reference potential terminal are complementarily turned on and off to control the first and second switch elements. A semiconductor integrated circuit for supplying a current to an inductance element connected between an intermediate connection node of a switch element and an output terminal to output a voltage obtained by stepping down a voltage applied to the voltage input terminal. A first and a second switch element, a pulse generation circuit for generating ON / OFF control pulses for these switch elements, and a clock generation circuit for generating a clock signal required for generating a pulse in the pulse generation circuit. A detection circuit for detecting a current flowing from the intermediate connection node toward the voltage output terminal, and when the detection circuit detects the current, The semiconductor integrated circuit is characterized in that a switching control circuit so as not to turn on the second switching element to the next period to be turned on the second switching element is also. 10. A first switch element and a second switch element connected in series between a voltage input terminal and a reference potential terminal are complementarily turned on and off to control the first and second switch elements. A semiconductor integrated circuit for supplying a current to an inductance element connected between an intermediate connection node of a switch element and an output terminal to output a voltage obtained by stepping down a voltage applied to the voltage input terminal. A first and a second switch element, a pulse generation circuit for generating ON / OFF control pulses for these switch elements, and a clock generation circuit for generating a clock signal required for generating a pulse in the pulse generation circuit. , The first
And a detection circuit for detecting a current flowing from the intermediate connection node toward the voltage input terminal based on the potential of the intermediate connection node during a period in which the second switch element and the second switch element are both turned off. A switching control circuit for preventing the second switch element from being turned on during a period when the second switch element is to be turned on when the current is detected. . 11. The semiconductor integrated circuit according to claim 10, wherein said detection circuit comprises a comparator for detecting a potential difference between both terminals of said first switch element. 12. The detection circuit detects a resistance element connected in series with the first switch element between the voltage input terminal and the intermediate connection node, and detects a potential difference between both terminals of the resistance element. The semiconductor integrated circuit according to claim 10, further comprising: 13. The semiconductor according to claim 11, wherein the detection circuit has offset means for applying an offset to the potential of the intermediate connection node and applying the offset to one input terminal of the comparator. Integrated circuit. 14. The detection circuit according to claim 1, wherein a potential of the intermediate connection node when a current flows toward the output terminal is equal to a potential of the intermediate connection node when a current flows toward the voltage input terminal. A constant voltage generating circuit for generating a potential between the two, and a comparator for detecting a current by comparing the voltage generated by the stop voltage generating circuit with the potential of the intermediate connection node. A semiconductor integrated circuit according to claim 10. 15. The clock generating circuit according to claim 9, wherein the clock generating circuit has an oscillating circuit, and the oscillating circuit is configured to lower the oscillating frequency when the detecting circuit detects a current. A semiconductor integrated circuit according to any one of the above. 16. A semiconductor integrated circuit according to claim 9, further comprising: an inductance element having one terminal coupled to an intermediate connection node between said first switch element and said second switch element. A switching power supply including a capacitance element connected between the other terminal of the inductance element and the constant potential point, wherein the inductance element and the capacitance element are connected as external elements to the semiconductor integrated circuit; A portable electronic device characterized by the above-mentioned. 17. A first switch element and a second switch element connected in series between a voltage input terminal and a reference potential terminal are complementarily turned on and off to control the first switch element and the second switch element. A semiconductor integrated circuit that supplies a current to an inductance element connected between a connection node with the second switch element and an output terminal and outputs a voltage obtained by stepping down a voltage applied to the voltage input terminal. A pulse generating circuit for generating a pulse for controlling ON / OFF of the first switch element and the second switch element, and a detection circuit for detecting a current flowing from the connection node toward the voltage input terminal. In the case where the detection circuit detects the current, the second switch element is not turned on at least during a period when the second switch element is to be turned on next. The semiconductor integrated circuit is characterized in that a switching control circuit for controlling the pulse generator. 18. A first switch element and a second switch element connected in series between a voltage input terminal and a reference potential terminal are complementarily turned on and off to control the first switch element and the second switch element. A semiconductor integrated circuit that supplies a current to an inductance element connected between a connection node with the second switch element and an output terminal and outputs a voltage obtained by stepping down a voltage applied to the voltage input terminal. And a pulse generation circuit for generating a pulse for controlling on / off of the first switch element and the second switch element, and both the first switch element and the second switch element are turned off. A detection circuit that detects a current flowing from the connection node toward the voltage input terminal based on a potential of the connection node during a period, wherein the detection circuit detects the current. And a switching control circuit for controlling the pulse generation circuit so as not to turn on the second switch element at least during a period when the second switch element is to be turned on next. Semiconductor integrated circuit.