Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/42—Plated through-holes or plated via connections

Definitions

• the present invention relates to a printed circuit board and a method for manufacturing the same.
• a high frequency filter having conductor vias for shielding is known (for example, see Patent Document 1).
• printed circuit boards are required to have peeling resistance in component mounting areas.
• the present inventors conducted intensive studies and found that the above-mentioned problems could be solved, and completed the present invention having the following gist. That is, the present invention includes the following.
• a wiring section having a signal line, a component mounting section for mounting electronic components electrically connected to the signal line;
• a printed circuit board comprising: The wiring section further includes a plurality of shielding conductor vias arranged along the signal line, and a conductor layer electrically connected to the plurality of shielding conductor vias and extending to the component mounting section; an insulating layer interposed between the signal line and the conductor layer,
• the component mounting section has a reinforcing via electrically connected to the conductor layer in the component mounting section. Wired circuit board.
• the ratio (G/R) of the interval (G) between the plurality of shielding conductor vias arranged along the signal line and the diameter (R) of the shielding conductor via is 1.5 to 1.
• the insulating layer extends to the component mounting section, Formation of the plurality of shielding conductor vias is performed by filling via holes formed in the insulating layer with a conductor, The reinforcing via is formed by filling a via hole formed in the insulating layer extending to the component mounting section with a conductor, Filling the via hole with the conductor when forming the plurality of shielding conductor vias and filling the via hole with the conductor when forming the reinforcing via are performed simultaneously; A method for manufacturing printed circuit boards.
• the present invention it is possible to provide a wired circuit board that has excellent shielding properties for signal lines and excellent peeling resistance in component mounting areas. Further, according to the present invention, it is possible to provide a method for manufacturing a printed circuit board that can efficiently manufacture the printed circuit board of the present invention.
• FIG. 1A shows the crosstalk measurement results of Example 1 and Example 2.
• FIG. 1B shows the radiation noise measurement results of Example 1 and Example 2.
• FIG. 2A is a schematic diagram (top view) of one embodiment of the printed circuit board viewed from the third direction (thickness direction).
• Figure 2B is a cross-sectional view taken along line A-A' of the printed circuit board in Figure 2A.
• FIG. 2C is a cross-sectional view taken along line B-B' of the printed circuit board of FIG. 2A.
• FIG. 2D is a cross-sectional view taken along the line C-C' of the printed circuit board of FIG. 2A.
• FIG. 3A is a diagram (part 1) for explaining one embodiment of a method for manufacturing a printed circuit board.
• FIG. 1A shows the crosstalk measurement results of Example 1 and Example 2.
• FIG. 1B shows the radiation noise measurement results of Example 1 and Example 2.
• FIG. 2A is a schematic diagram (top view) of one embodiment of the printed circuit board viewed
• FIG. 3B is a diagram for explaining an embodiment of a method for manufacturing a printed circuit board (part 2).
• FIG. 3C is a diagram for explaining an embodiment of a method for manufacturing a printed circuit board (part 3).
• FIG. 3D is a diagram for explaining an embodiment of a method for manufacturing a printed circuit board (part 4).
• FIG. 3E is a diagram for explaining an embodiment of a method for manufacturing a printed circuit board (Part 5).
• FIG. 3F is a diagram for explaining an embodiment of a method for manufacturing a printed circuit board (Part 6).
• FIG. 3G is a diagram for explaining one embodiment of a method for manufacturing a printed circuit board (part 7).
• FIG. 3H is a diagram for explaining an embodiment of a method for manufacturing a printed circuit board (Part 8).
• the printed circuit board of the present invention includes a wiring section and a component mounting section.
• the wiring section has a signal line.
• the component mounting section is a section for mounting electronic components electrically connected to the signal line.
• the wiring section further includes a plurality of shield conductor vias, a conductor layer, and an insulating layer.
• the plurality of shielding conductor vias are arranged along the signal line in the wiring section.
• the conductor layer is electrically connected to the plurality of shielding conductor vias. Further, the conductor layer extends to the component mounting section.
• the insulating layer is interposed between the signal line and the conductor layer.
• the component mounting section has reinforcing vias electrically connected to the conductor layer in the component mounting section.
• the wiring portion has a plurality of shielding conductor vias arranged along the signal line, shielding performance for the signal line is improved. Furthermore, since the component mounting portion has reinforcing vias, the component mounting portion has excellent peeling resistance.
• peeling resistance refers to the fact that the electronic component is difficult to peel off from the component mounting area.
• the material of the signal line is not particularly limited, and examples thereof include copper, iron, silver, gold, aluminum, nickel, and alloys thereof (for example, stainless steel and bronze). Preferably, copper is used.
• the width of the signal line is not particularly limited, and is, for example, 0.05 mm or more, preferably 0.1 mm or more, and, for example, 3 mm or less, preferably 2 mm or less. Note that the width of the signal line corresponds to the length in the second direction (width direction) in FIGS. 2A to 2C.
• the thickness of the signal line is not particularly limited, and is, for example, 5 ⁇ m or more, preferably 10 ⁇ m or more, and, for example, 100 ⁇ m or less, preferably 80 ⁇ m or less. Note that the thickness of the signal line corresponds to the length in the third direction (thickness direction) in FIGS. 2A to 2C.
• the material of the shield conductor via is not particularly limited, and examples thereof include copper, iron, silver, gold, aluminum, nickel, and alloys thereof (for example, stainless steel and bronze). Preferably, copper is used.
• the size of the shielding conductor via is not particularly limited, but the diameter (R) is, for example, preferably 50 ⁇ m or more, more preferably 75 ⁇ m or more, and preferably 300 ⁇ m or less, more preferably 200 ⁇ m or less.
• the ratio (G/R) between the interval (G) between the plurality of shielding conductor vias arranged along the signal line and the diameter (R) of the shielding conductor via is, for example, 1.1 to 10.0. Yes, and preferably 1.5 to 5.0.
• the ratio (G/R) When the ratio (G/R) is 5.0 or less, the shielding characteristics are more excellent. On the other hand, if the ratio (G/R) is 1.5 or more, the plurality of shield conductor vias will not be too close to each other, and high precision via processing will not be required, making via processing easier. Further, when the ratio (G/R) is 1.5 or more, the wiring portion is less likely to be damaged. Note that the locations where the distance (G) and diameter (R) are measured will be described when explaining FIG. 2C. In addition, if the cross-sectional shape of the shielding conductor via (the cross-sectional shape in the plane perpendicular to the third direction (thickness direction) in FIGS. 2A to 2D) is not circular, the diameter (R) means the equivalent diameter.
• the equivalent diameter means the diameter of a circle when the cross-sectional area of the shielding conductor via is defined as the area of the circle. If the cross section is other than a circle, calculate the area of the cross section and use the formula for the area of a circle ((r'/2) 2 ⁇ ⁇ ) (r' is the diameter of the circle) to find the equivalent r'. It is the diameter.
• Example 1 is the measurement result of a sample having a diameter (R) of 150 ⁇ m, a spacing (G) of 1 mm, and a ratio (G/R) of 6.7.
• Example 2 is the measurement result of a sample having a diameter (R) of 100 ⁇ m, a spacing (G) of 0.3 mm, and a ratio (G/R) of 3.0. It can be seen from FIGS. 1A and 1B that Example 2 has better crosstalk characteristics and radiation noise characteristics than Example 1.
• the material of the conductor layer is not particularly limited, and examples thereof include copper, iron, silver, gold, aluminum, nickel, and alloys thereof (for example, stainless steel and bronze). Preferably, copper is used.
• the thickness of the conductor layer is not particularly limited, and is, for example, 5 ⁇ m or more, preferably 10 ⁇ m or more, and, for example, 100 ⁇ m or less, preferably 80 ⁇ m or less. Note that the thickness of the conductor layer corresponds to the length in the third direction (thickness direction) in FIGS. 2A to 2C.
• Examples of the material of the insulating layer include resin.
• the type of resin is not limited.
• Examples of the resin include polycarbonate resin, polyimide resin, fluorinated polyimide resin, epoxy resin, phenol resin, urea resin, melamine resin, diallyl phthalate resin, silicone resin, thermosetting urethane resin, fluororesin, liquid crystal polymer, etc. It will be done.
• Preferred examples include polyimide resin and liquid crystal polymer.
• a porous insulating layer is preferable.
• the porous insulating layer is porous.
• the porous insulating layer has closed cells and/or open cells.
• the porosity in the porous insulating layer is, for example, 50% or more, preferably 60% or more, more preferably 70% or more, and still more preferably 80% or more. Note that the porosity of the porous insulating layer is, for example, less than 100%, and further, 99% or less.
• the porosity of the porous insulating layer is determined by calculation based on the following formula when the material of the porous insulating layer is polyimide resin.
• Relative permittivity of porous insulating layer Relative permittivity of air x porosity + Relative permittivity of polyimide x (1 - porosity)
• the relative permittivity of air is 1, and the relative permittivity of polyimide resin is 3.5, so
• Relative dielectric constant of porous insulating layer porosity + 3.5 (1 - porosity)
• Porosity (%) [(3.5-relative permittivity of porous insulating layer)/2.5] x 100
• the relative dielectric constant of the porous insulating layer at a frequency of 60 GHz is, for example, 2.5 or less, preferably 1.9 or less, more preferably 1.6 or less, and, for example, more than 1.0.
• the dielectric constant of the porous insulating layer is actually measured by a resonator method using a frequency of 60 GHz.
• the dielectric loss tangent of the porous insulating layer at a frequency of 60 GHz is, for example, 0.006 or less, and is, for example, more than 0.
• the dielectric loss tangent of the porous insulating layer is actually measured by a resonator method using a frequency of 60 GHz.
• the thickness of the insulating layer is not particularly limited, and is, for example, 5 ⁇ m or more, preferably 10 ⁇ m or more, and, for example, 100 ⁇ m or less, preferably 80 ⁇ m or less. Note that the thickness of the insulating layer corresponds to the length in the third direction (thickness direction) in FIGS. 2A to 2C.
• the material of the reinforcing via is not particularly limited, and examples include conductors.
• the conductor include copper, iron, silver, gold, aluminum, nickel, and alloys thereof (eg, stainless steel and bronze).
• copper is used.
• the size of the reinforcing via is not particularly limited, but the diameter is, for example, preferably 50 ⁇ m or more, more preferably 75 ⁇ m or more, and preferably 300 ⁇ m or less, more preferably 200 ⁇ m or less.
• the diameter of the reinforcing via is, for example, similar to the diameter of the shielding conductor via, as described in the explanation of FIG. It is measured in
• the reinforcing vias are preferably arranged in a grid pattern in the component mounting area.
• lattice-like refers to a state (shape) in which a plurality of vertical lines and horizontal lines intersect, like a so-called lattice stripe.
• the vertical line and the horizontal line intersect at 90°.
• the area occupied by the reinforcing vias in the component mounting portion is 3% to 50% of the area of the mounting portion. By doing so, the reinforcing vias are arranged with high density, and the peeling resistance in the component mounting area is further improved.
• the mounting part means a part of the component mounting part where an electronic component is mounted.
• the area occupied by the reinforcing vias in the component mounting portion can be determined by dividing the total cross-sectional area of the reinforcing vias in the entire component mounting portion by the area of the mounting portion viewed from the third direction (thickness direction).
• the cross-sectional area of the reinforcing via is measured in a plane perpendicular to the third direction (thickness direction) and in which the signal line exists.
• the area occupied by the reinforcing vias in the component mounting section is 2% to 15% of the area of the component mounting section.
• the area occupied by the reinforcing vias in the component mounting portion can be determined by dividing the total cross-sectional area of the reinforcing vias by the area of the component mounting portion viewed from the third direction (thickness direction).
• the cross-sectional area of the reinforcing via is measured in a plane perpendicular to the third direction (thickness direction) and in which the signal line exists.
• the printed circuit board may have an adhesive layer, a cover insulating layer, and the like.
• the cover insulating layer covers the conductor layer, for example.
• the cover insulating layer may cover the conductor layer via an adhesive layer.
• Examples of the material of the cover insulating layer include the materials of the insulating layer described above.
• the material for the adhesive layer is not particularly limited, and includes various types of adhesives such as hot melt adhesives and thermosetting adhesives. Specifically, acrylic adhesives, epoxy adhesives, Examples include silicone adhesives. Preferably, an acrylic adhesive is used.
• the thickness of the adhesive layer is, for example, 2 ⁇ m or more, preferably 5 ⁇ m or more, and, for example, 50 ⁇ m or less, preferably 25 ⁇ m or less.
• Examples of electronic components mounted on the component mounting portion of the printed circuit board include surface mount connectors.
• the plurality of shielding conductor vias and reinforcing vias are formed at the same time.
• the method for manufacturing a circuit wiring board of the present invention is preferably a manufacturing method that satisfies the following (I) to (IV).
• the reinforcing via is formed by filling the via hole formed in the insulating layer extending to the component mounting portion with a conductor.
• FIG. 2A is a schematic diagram (top view) of the printed circuit board 1 viewed from the third direction (thickness direction).
• the printed circuit board 1 includes a wiring section 2 and two component mounting sections 3. One of the two component mounting sections 3 is located at one end of the wiring section 2 in the first direction (longitudinal direction), and the other of the two component mounting sections 3 is located at one end of the wiring section 2 in the first direction (longitudinal direction). direction).
• the two component mounting sections 3 have a longer length in the second direction (width direction) than the wiring section 2. In other words, the widths of the two component mounting sections 3 are wider than the width of the wiring section 2.
• the wiring section 2 has two signal lines 4.
• the two signal lines 4 extend in the first direction (longitudinal direction) of the wiring section 2 .
• the two signal lines 4 electrically connect the two component mounting sections 3.
• the wiring section 2 further includes a plurality of shielding conductor vias 5, a conductor layer 6 (described with reference to FIGS. 2B and 2C), and an insulating layer 7.
• a plurality of shielding conductor vias 5 are arranged along the signal line 4 in the wiring section 2 .
• the component mounting section 3 has reinforcing vias 11 that are electrically connected to the conductor layer in the component mounting section 3 .
• the signal line 4, the shielding conductor via 5, and the reinforcing via 11 are shown by broken lines. This is because, as shown in FIGS. 2B to 2D, in the printed circuit board 1, the signal line 4, the shielding conductor via 5, and the reinforcing via 11 are present inside the wiring section 2 and the component mounting section 3. However, this is because it is usually not visible from the third direction (thickness direction). Note that in FIGS. 2A to 2D, the first direction, the second direction, and the third direction are orthogonal to each other.
• FIG. 2B is a sectional view taken along the line AA' of the printed circuit board 1 in FIG. 2A.
• FIG. 2B is a cross-sectional view of the wiring section 2.
• the wiring part 2 includes a cover insulating layer 8, a conductor layer 6, an insulating layer 7, an adhesive layer 9, an insulating layer 7, and a conductor layer 6 from the other side to the one side in the third direction (thickness direction). , and cover insulating layer 8 in this order.
• the signal line 4 is buried in the adhesive layer 9 .
• the shielding conductor via 5 is provided in the third direction (thickness direction) so as to electrically connect the conductor layer 6 on one side and the conductor layer 6 on the other side in the third direction (thickness direction). It penetrates the insulating layer 7 on one side, the adhesive layer 9, and the insulating layer 7 on the other side in the third direction (thickness direction).
• FIG. 2C is a BB' cross-sectional view of the printed circuit board 1 of FIG. 2A.
• FIG. 2C is a cross-sectional view of the wiring section 2.
• the wiring section 2 includes a cover insulating layer 8, a conductor layer 6, an insulating layer 7, an adhesive layer 9, It has an insulating layer 7, a conductor layer 6, and a cover insulating layer 8 in this order.
• the shield conductor via 5 electrically connects the conductor layer 6 on one side and the conductor layer 6 on the other side in the third direction (thickness direction). As shown in FIG.
• the interval (G) between the plurality of shield conductor vias 5 arranged along the signal line 4 is 3.0 times the diameter (R) of the shield conductor vias. That is, G/R is 3.0. Note that the distance (G) and diameter (R) are measured, for example, on a plane perpendicular to the third direction (thickness direction) and on which the signal line 4 is present.
• FIG. 2D is a cross-sectional view taken along the line CC' of the printed circuit board 1 in FIG. 2A.
• FIG. 2D is a cross-sectional view of the component mounting section 3.
• the component mounting section 3 includes a cover insulating layer 8, a conductor layer 6, an insulating layer 7, an adhesive layer 9, an insulating layer 7, a conductor layer from the other side to the one side in the third direction (thickness direction). 6 and a cover insulating layer 8 in this order.
• the insulating cover layer 8 , the conductor layer 6 , the insulating layer 7 , the adhesive layer 9 , the insulating layer 7 , the conductor layer 6 , and the insulating cover layer 8 extend from the wiring section 2 .
• the reinforcing vias 11 are provided in the third direction (thickness direction) so as to electrically connect the conductor layer 6 on one side and the conductor layer 6 on the other side in the third direction (thickness direction). It penetrates the insulating layer 7 on one side, the adhesive layer 9, and the insulating layer 7 on the other side in the third direction (thickness direction).
• the component mounting section 3 has a mounting portion 12 (a portion surrounded by a two-dot chain line in FIG. 2A) on which electronic components are mounted (FIG. 2A).
• the mounting portion 12 is a portion of the component mounting portion 3 where an electronic component is mounted.
• the mounting portion 12 in FIG. An electronic component having the same shape as the mounted mounting portion 12 is mounted.
• FIG. 3H are diagrams for explaining one embodiment of a method for manufacturing a printed circuit board.
• FIG. 3H corresponds to the cross-sectional view of FIG. 2B.
• a laminate is prepared in which a conductor layer 6A, an insulating layer 7, an adhesive layer 9A, and a signal line forming conductor layer 4A are laminated in this order (FIG. 3A).
• the material of the conductor layer 6A may be, for example, the same material as the conductor used to form the shielding conductor via. Copper is preferable as such a material.
• a laminate having a conductor layer, an adhesive layer or a skin layer, an insulating layer, an adhesive layer or a skin layer, and a signal line forming conductor layer may be used.
• the adhesive layer and skin layer used in these are used, for example, to improve the adhesive strength between the conductor layer and the insulating layer.
• a porous insulating layer is used as the insulating layer, for example, a non-porous insulating layer (for example, a non-porous polyimide layer) is used as the skin layer.
• the signal line 4 and the conductor 5A are formed by patterning the signal line forming conductor layer 4A by photolithography (for example, subtractive method) using a photoresist (FIG.
• the signal line 4 is formed to extend along the first direction (longitudinal direction), as shown in FIG. 2A.
• the conductor 5A is formed into a circular shape so as to become a part of the shielding conductor via 5 in a later step.
• a laminate is prepared in which the conductor layer 6A, the insulating layer 7, and the adhesive layer 9A are laminated in this order (FIG. 3C).
• the material of the conductor layer 6A may be, for example, the same material as the conductor used to form the shielding conductor via. Copper is preferable as such a material. Further, instead of the laminate shown in FIG.
• a laminate including a conductor layer, an adhesive layer or skin layer, an insulating layer, and an adhesive layer or skin layer may be used.
• the laminate shown in FIG. 3B and the laminate prepared in FIG. 3C are arranged so that the two adhesive layers 9A face each other, and the adhesive layers 9A are bonded together (FIG. 3D).
• a laminate having the conductor layer 6A, the insulating layer 7, the adhesive layer 9, the insulating layer 7, and the conductor layer 6A in this order from the other side to the one side in the third direction (thickness direction) is formed. obtained (Fig. 3E).
• the signal line 4 and the conductor 5A are buried in the adhesive layer 9.
• a hole 5B (via hole) reaching the conductor 5A is opened in the conductor layer 6A, insulating layer 7, and adhesive layer 9 from one side and the other side in the third direction (thickness direction) (FIG. 3F).
• drilling may be used.
• the drilling process include laser processing, drilling, and blasting.
• laser processing is used.
• the formed hole 5B may have a tapered shape in which the cross-sectional area gradually decreases from the surface of the conductor layer 6A toward the conductor 5A.
• the conductor layer 6A, the holes in the insulating layer 7 and the adhesive layer 9, and the surface of the conductor layer 6A are plated.
• the holes in the conductor layer 6A, the insulating layer 7, and the adhesive layer 9 are filled with the conductor, and the shielding conductor via 5 is formed.
• the conductor layer 6 is formed by combining the conductor layer 6A and the conductor layer formed by plating on the conductor layer 6A (FIG. 3G).
• the shielding conductor via 5 has a solid structure, but the shielding conductor via 5 may have a hollow structure formed on the inner peripheral surface of the hole in the insulating layer 7 and the adhesive layer 9. good.
• a cover insulating layer 8 is formed on each surface of the two conductor layers 6. Through the above steps, a printed circuit board is obtained (FIG. 3H).
• the component mounting section shown in FIG. 2D is obtained.
• the shielding conductor vias and the reinforcing vias can be formed at the same time.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Manufacturing & Machinery (AREA)
• Structure Of Printed Boards (AREA)
• Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
• Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=88919123

Family Applications (1)

Country Status (3)

Citations (3)

• 2022
  • 2022-05-25 JP JP2022085380A patent/JP2023173253A/ja active Pending
• 2023
  • 2023-04-18 WO PCT/JP2023/015444 patent/WO2023228626A1/ja unknown
  • 2023-05-11 TW TW112117481A patent/TW202415150A/zh unknown

Patent Citations (3)

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