WO2023225813A1 - 布线基板及电子装置 - Google Patents

布线基板及电子装置 Download PDF

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Publication number
WO2023225813A1
WO2023225813A1 PCT/CN2022/094526 CN2022094526W WO2023225813A1 WO 2023225813 A1 WO2023225813 A1 WO 2023225813A1 CN 2022094526 W CN2022094526 W CN 2022094526W WO 2023225813 A1 WO2023225813 A1 WO 2023225813A1
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WO
WIPO (PCT)
Prior art keywords
wiring substrate
pad
sub
openings
distance
Prior art date
Application number
PCT/CN2022/094526
Other languages
English (en)
French (fr)
Inventor
徐佳伟
许邹明
吴信涛
马亚军
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/094526 priority Critical patent/WO2023225813A1/zh
Priority to CN202280001391.1A priority patent/CN117441129A/zh
Publication of WO2023225813A1 publication Critical patent/WO2023225813A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Definitions

  • the present application relates to the field of display technology, and in particular to a wiring substrate and an electronic device.
  • Micro light-emitting diodes such as Mini-LED and Micro LED, are approximately less than 500 ⁇ m in size. Due to their smaller size, ultra-high brightness, long life and other advantages, their use in the display field has increased significantly.
  • a first aspect of embodiments of the present application provides a wiring substrate.
  • the wiring substrate includes a substrate and a shielded signal line provided on the substrate;
  • the substrate includes a functional area; the functional area is provided with a plurality of pad groups; the plurality of pad groups are respectively distributed in arrays along a first direction and a second direction, and the second direction and the first direction cross;
  • the first part and the second part form an integral structure.
  • the line width of the first portion is smaller than the size of the second portion in the first direction.
  • an orthographic projection of the second portion on the substrate covers at least two first openings within an orthographic projection of the substrate, and the at least two first openings arranged at intervals in the first direction.
  • the first part and the third part form an integral structure.
  • the line width of the first part is smaller than the size of the third part in the first direction; and/or the size of the third part in the second direction is smaller than the size of the third part in the second direction.
  • the size of the second part in the second direction is smaller than the size of the first part in the first direction.
  • the wiring substrate further includes an insulating layer located on a side of the shielded signal line facing away from the substrate, the insulating layer is provided with a plurality of first openings, and one of the third portions is located on the side of the shielded signal line away from the substrate.
  • the orthographic projection on the substrate covers the orthographic projection of at least one first opening on the substrate.
  • an orthographic projection of the third part on the substrate covers an orthographic projection of at least two first openings on the substrate; the at least two first openings are on the substrate. arranged at intervals in the first direction.
  • the pad group includes at least two sub-pads; the insulating layer is also provided with a plurality of second openings, and one second opening exposes one of the sub-pads;
  • the total area of the first openings corresponding to one of the third parts is greater than the total area of the second openings corresponding to the adjacent pad group.
  • the wiring substrate further includes a bonding area located on one side of the functional area; the pad group furthest from the bonding area among the plurality of pad groups arranged along the first direction Among the corresponding plurality of second openings, the distance from the second opening with the smallest distance from the binding area to the binding area is a first distance, and the edge of the second portion toward the binding area is The distance from the binding area is a second distance, and the distance from the edge of the third part toward the binding area to the binding area is a third distance;
  • the second distance is greater than or equal to the first distance; and/or the third distance is greater than or equal to the first distance.
  • the insulating layer includes an inorganic layer.
  • the wiring substrate further includes a plurality of signal lines provided on the substrate, and the wiring substrate further includes a binding area located on one side of the functional area;
  • At least one signal line is located on the side of the second part facing the binding area; in the first direction, the second part and the second part are located on the side of the second part facing the binding area.
  • the distance between the signal lines on one side of the binding area is greater than or equal to 200 microns;
  • At least one signal line is located on the side of the third part facing the binding area; in the first direction, the third part is connected to the third part on the side of the binding area.
  • the distance between the three signal lines facing the binding area is greater than or equal to 200 microns.
  • the pad group includes a plurality of sub-pads
  • the wiring substrate further includes a connecting wire
  • at least two sub-pads in the same pad group are connected through the connecting wire; in the first In both directions, the minimum distance between the second part and the adjacent connecting wires is greater than or equal to 200 microns; and/or, in the second direction, the minimum distance between the third part and all adjacent connecting wires is The minimum distance between the above-mentioned connecting wires is greater than or equal to 200 microns.
  • the pad group includes a plurality of sub-pads, and the plurality of sub-pads are arranged on the same layer as the shielded signal line.
  • a second aspect of the embodiment of the present application provides an electronic device, which includes the above-mentioned wiring substrate and electronic components connected to the pad group.
  • Figure 1 is a schematic structural diagram of a wiring substrate provided by an exemplary embodiment of the present application.
  • Figure 2 is a partial structural schematic diagram of a wiring substrate provided by an exemplary embodiment of the present application.
  • Fig. 3 is a partial cross-sectional view along the AA direction of the wiring substrate shown in Fig. 2;
  • Figure 4 is a partial structural schematic diagram of an electronic device in which a wiring substrate is provided according to an exemplary embodiment of the present application
  • FIG. 5 is a partial structural cross-sectional view of the wiring substrate of the electronic device shown in FIG. 4 taken along the BB direction.
  • first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other.
  • first information may also be called second information, and similarly, the second information may also be called first information.
  • word “if” as used herein may be interpreted as "when” or “when” or “in response to determining.”
  • Embodiments of the present application provide a wiring substrate and an electronic device.
  • the wiring substrate and electronic device in the embodiment of the present application will be described in detail below with reference to the accompanying drawings.
  • Features in the embodiments described below may complement each other or be combined with each other unless they conflict.
  • the wiring substrate includes a substrate and a shielded signal line 40 provided on the substrate.
  • the substrate includes a functional area 101 provided with a plurality of pad groups 30 .
  • the plurality of pad groups 30 are respectively distributed in an array along a first direction X and a second direction Y, and the second direction Y intersects the first direction X.
  • the shielded signal line 40 includes a first part 41 surrounding all the pad groups 30 and a second part 42 connected to the first part 41.
  • the second part 42 is located adjacent to the second direction Y. between the two pad groups 30.
  • Each pad group 30 includes a plurality of sub-pads 311 .
  • the wiring substrate includes an insulating layer 50 located on the side of the shielded signal line 40 facing away from the substrate 10 .
  • the insulating layer 50 can cover the conductive layer of the wiring substrate. In most areas, it prevents water and oxygen intrusion and improves the reliability of the wiring substrate.
  • the insulating layer 50 includes an inorganic layer.
  • the inorganic layer has a better effect of blocking water and oxygen, which helps improve the reliability of the wiring substrate.
  • the material of the insulating layer is an inorganic material, and the inorganic material may include at least one of silicon nitride, silicon oxide, or silicon oxynitride.
  • the insulating layer 50 may include one inorganic layer, or may include multiple inorganic layers, or may include a stacked structure of organic layers and inorganic layers.
  • the insulating layer 50 is provided with a plurality of second openings 52 , and one second opening 52 exposes one of the sub-pads 311 . That is to say, the area of the conductive layer of the wiring substrate exposed by the second opening 52 is the sub-pad 311 .
  • the wiring substrate In the manufacturing process of the electronic device where the wiring substrate is located, due to changes in process conditions in the previous and subsequent processes, the wiring substrate needs to be transferred from the previous process to the next process.
  • the attachment and removal of the protective film will be involved. Specifically, after the wiring substrate is prepared with each circuit film layer, and before the area where the sub-pad is located is subjected to anti-oxidation treatment through the nickel-gold process, the protective film will be attached and removed; After the area where the solder pad is located is subjected to anti-oxidation treatment, and before the reflective material layer is placed on the wiring substrate, the protective film will be attached and removed.
  • the material of the insulating layer 50 is an inorganic material.
  • electrostatic charges will be injected into the sub-pads 311 of the pad group 30, and the electrostatic charges accumulated in the sub-pads 311 cannot be effectively discharged. , will cause the problem of electrostatic breakdown between adjacent sub-pads 311.
  • the wiring substrate provided by the embodiment of the present application includes a second part 42 by arranging the shielded signal line 40.
  • the second part 42 is located between two adjacent pad groups 30 in the second direction Y, and the second part 42 can
  • the electrostatic charge accumulated in the sub-pads 311 of the adjacent pad groups 30 is derived to improve the ability of the shielded signal line 40 to derive electrostatic charges, thereby improving the problem of electrostatic breakdown between adjacent sub-pads 311 and improving Product yield of wiring substrates.
  • first direction X and the second direction Y are perpendicular to each other.
  • first direction X is the column direction
  • second direction Y is the row direction.
  • the plurality of pad groups 30 provided in the functional area 101 may be arranged in multiple rows and multiple columns.
  • Each row pad group includes a plurality of pad groups 30 that are spaced apart in the row direction
  • each column pad group includes a plurality of pad groups 30 that are spaced apart in the column direction.
  • the substrate may further include a frame area 102 , and the frame area 102 may surround the functional area 101 .
  • the first portion 41 of the shielded signal line 40 may be located in the frame area 102 .
  • Border area 102 may include binding area 1021.
  • the binding area 1021 is provided with a flexible circuit board.
  • the wiring substrate further includes a plurality of signal lines provided on the substrate.
  • the plurality of signal lines include, for example, a common voltage line GND and a driving voltage line VLED. , source power line PWR, source address line DI, etc.
  • Each signal line is electrically connected to the flexible circuit board in the binding area 1021.
  • the flexible circuit board provides signals for the shielded signal line 40 and the plurality of signal lines.
  • the flexible circuit board can provide the same signal for the common voltage line GND and the shielded signal line 40 .
  • the sub-pads 311 of the pad group 30 are used for soldering to electronic components.
  • the electronic components may include inorganic light-emitting diodes with a size of one hundred microns and below, and the electronic components may also include driver chips with a size of one hundred microns and below.
  • inorganic light-emitting diodes of hundreds of microns and below can be mini LEDs or micro LEDs.
  • the size range of mini LED is about 100 ⁇ m ⁇ 500 ⁇ m, and the size of micro LED is less than 100 ⁇ m.
  • the driver chip may be a chip used to provide signals to the inorganic light-emitting diodes to cause the inorganic light-emitting diodes to emit light.
  • each pad group 30 includes a first sub-pad group 31 and a second sub-pad group 32 .
  • the first sub-pad group 31 includes at least two sub-pads 311 , and the sub-pads 311 of the first sub-pad group 31 are used for soldering with the inorganic light-emitting diode.
  • an inorganic light-emitting diode may include two pins corresponding to the two sub-pads 311 of the first sub-pad group 31 , one of the two sub-pads 311 is an anode pad and the other is a cathode pad.
  • the second sub-pad group 32 includes at least two sub-pads 311, and the sub-pads 311 of the second sub-pad group 32 are used for soldering to the driver chip.
  • a driver chip includes four pins, and its corresponding second sub-pad group 32 includes four sub-pads, namely address pad Di, power pad Pwr, common voltage pad Gnd, and Output pad Out.
  • the output pad Out of the second sub-pad group 32 is connected to at least one sub-pad 311 of the first sub-pad group 31; the common voltage pad Gnd of the second sub-pad group 32 is connected to at least one sub-pad 311 of the first sub-pad group 31.
  • the common voltage line GND is connected to receive the common voltage (eg ground voltage) transmitted by the common voltage line GND; the power pad Pwr of the second sub-pad group 32 is connected to the source power line PWR.
  • the driving voltage line VLED is connected to one sub-pad 311 of a first sub-pad group 31.
  • the source address line DI is connected to the address pad Di soldered to the first-level driver chip in each column pad group, and is configured to transmit an address signal to the first-level driver chip soldered to each column pad group.
  • one pad group 30 may include four first sub-pad groups 31 and one second sub-pad group 32, that is, four inorganic light-emitting diodes may be driven by one driver chip.
  • the first sub-pad group 31 electrically connected to the driving voltage line VLED is used as the starting point of the series connection of the four first sub-pad groups 31 .
  • the first sub-pad group 31 to which the second sub-pad group 32 is electrically connected serves as the end point of the series connection of the four inorganic light-emitting diodes.
  • the number of the first sub-pad groups 31 of each pad group 30 is not limited and can be any number such as five, six, seven, eight, etc., and Not limited to four.
  • the wiring substrate further includes a connecting wire, and at least two sub-pads in the same pad group are connected through the connecting wire.
  • the sub-pads 311 of the adjacent first sub-pad group 31 in the same pad group 30 are connected in series through the connecting wires 60 .
  • the wiring substrate further includes an insulating material layer 82 located between the substrate 10 and the sub-pad 311 , and the insulating material layer 82 is provided with a plurality of third openings.
  • hole 801 each sub-pad 311 is at least partially located within the third opening 801
  • the orthographic projection of each third opening 801 on the substrate 10 falls on one of the second openings 52 within the orthographic projection on the substrate 10 .
  • the sub-pad 311 is at least partially located within the third opening 801, that is, at least part of the sub-pad 311 is recessed downward within the third opening 801; the orthographic projection of the third opening 801 on the substrate falls on the second
  • the opening 52 is in the orthographic projection on the substrate so that the sub-pad 311 exposes the insulating layer 50 .
  • the electronic component 90 includes an electronic component body 91 and a pin 92 on one side of the electronic component body 91. During the process of soldering the pin 92 of the electronic component 90 to the sub-pad 311, the solder covering the surface of the pin 92 melts. The flow toward the third opening 801 drives each pin 92 to move toward the sub-pad 311 to which it is welded.
  • the movement of the pin 92 toward the sub-pad 311 can improve the deflection of the electronic component 90 relative to its welding position. , so that the pin 92 and the corresponding sub-pad 311 are effectively welded, avoiding the problem of virtual welding between the pin 92 and the sub-pad 311 caused by the offset of the electronic components, and improving the product yield.
  • the insulating material layer 82 includes a first organic layer 821.
  • the thickness of the first organic layer 821 ranges from 2 ⁇ m to 4 ⁇ m. Such an arrangement can not only ensure that the process is easy to implement, but also prevent the thickness of the first organic layer 821 from being too large, resulting in a larger thickness of the array substrate. In some embodiments, the thickness of the first organic layer 821 is, for example, 2 ⁇ m, 2.5 ⁇ m, 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m, etc.
  • the first organic layer 821 is a single film layer, or the first organic layer 821 includes multiple sub-organic layers, that is, the first organic layer 821 is formed through multiple coating processes.
  • the material of the first organic layer 821 may be organic resin.
  • the wiring substrate further includes a passivation protection layer 81 located between the substrate 10 and the insulating material layer 82 .
  • the passivation protection layer 81 can be in direct contact with the substrate 10 .
  • the passivation protective layer 81 can protect the substrate 10 and prevent the substrate 10 from being damaged when the film layer above the substrate 10 is etched.
  • the material of the passivation protection layer 81 may be an inorganic material, such as silicon nitride, silicon oxide or silicon oxynitride. In one embodiment, as shown in FIG.
  • the second portion 42 is located farthest from the bonding area 1021 among the plurality of pad groups 30 arranged along the first direction X and in the second between two adjacent pad groups 30 in the direction Y. Since the area of the conductive layer used to conduct static charges away near the pad group 30 farthest from the bonding area 1021 among the plurality of pad groups 30 arranged along the first direction The problem of electrostatic breakdown is more likely to occur.
  • the second part 42 is disposed between two adjacent pad groups 30 in these pad groups 30, which can more effectively improve the problem of sub-pads 311 of these pad groups 30. Problems with electrostatic breakdown due to accumulation of static charges.
  • the second portion 42 is disposed between the disk groups 30 .
  • Such an arrangement is more helpful in improving the problem of electrostatic breakdown caused by accumulation of electrostatic charge in the sub-pad 311 in the pad group 30 farthest from the bonding area 1021 in the wiring substrate.
  • the first part 41 and the second part 42 form an integrated structure.
  • the line width of the first portion 41 is smaller than the size of the second portion 42 in the first direction.
  • the first portion 41 includes a first section extending along the first direction X and a second section extending along the second direction Y; the line width of the first section refers to the line width of the first section in the second direction Y.
  • the line width of the second section refers to the width of the second section in the first direction X.
  • the amount of electrostatic charges is conducted away more, and the impedance of the shielded signal line 40 can be effectively reduced, thereby improving the ability of the shielded signal line 40 to conduct away electrostatic charges.
  • the electrostatic charges are more conducive to improving the electrostatic charge on the neutron pad 311 of the wiring substrate. Problems with electrostatic breakdown caused by accumulation.
  • the insulating layer 50 is provided with a plurality of first openings 51 , and an orthographic projection of the second portion 42 on the substrate covers at least one of the first openings 51 .
  • the orthographic projection of the first opening 51 on the substrate 10 That is, a partial area of the second portion 42 is exposed by the first opening 51 .
  • part of the electrostatic charge introduced during the process of applying the protective film will be dispersed to the area of the second part 42 exposed by the first opening 51, and then the sub-pad 311 adjacent to the second part 42 will be The amount of injected electrostatic charges is reduced, which can further improve the problem of electrostatic breakdown caused by the accumulation of electrostatic charges on the sub-pad 311 in the wiring substrate.
  • the shape of the first opening 51 may be rectangular, square, circular, etc.
  • the area of the first opening 51 is larger than the area of the second opening 52 .
  • the orthographic projection of one second portion 42 on the substrate covers at least two first openings 51 within the orthographic projection on the substrate, and the The at least two first openings 51 are arranged at intervals in the first direction X.
  • the first openings 51 corresponding to the second part 42 are well dispersed in the first direction X, and are introduced into each sub-pad 311 adjacent to the second part 42 during the process of applying the protective film. The amount of electrostatic charge dispersed by the second part 42 is greater.
  • the total area of each first opening 51 corresponding to one second portion 42 is greater than the total area of each second opening 52 corresponding to an adjacent pad group 30 .
  • the orthographic projection of the second portion 42 on the substrate covers the orthographic projection of its corresponding first opening 51 on the substrate.
  • the shielded signal line 40 further includes a third part 43 connected to the first part 41 ; the third part 43 is disposed on the side of the functional area 101 The side of the angular position pad group 30 that is not adjacent to other pad groups 30 in the second direction Y.
  • the bonding pad group 30 at the corner position refers to that there are no other bonding pad groups 30 between the bonding pad group 30 and the first section of the first portion 41 extending along the first direction X, and the bonding pad group 30 There is no pad group 30 disposed between the second section away from the bonding area 1021 .
  • the third part 43 can conduct away the electrostatic charge accumulated in the pad group 30 at the corner position, thereby improving the problem of electrostatic breakdown occurring in adjacent sub-pads 311 in the pad group 30. .
  • the shielded signal line 40 may include two opposite third portions 43 , and the two third portions 43 are located on opposite sides of the functional area 101 .
  • the first part 41 and the third part 43 form an integrated structure.
  • the line width of the first part 41 is smaller than the size of the third part 43 in the first direction X.
  • Such an arrangement can make the area of the third part 43 larger, the third part 43 can conduct more electrostatic charges accumulated on the adjacent sub-pads 311 , and can effectively reduce the impedance of the shielded signal line 40 , improving the ability of the shielded signal line 40 to conduct away electrostatic charges, and further helping to improve the problem of electrostatic breakdown caused by the accumulation of electrostatic charges in the neutron pad 311 of the wiring substrate.
  • the line width of the first part 41 is smaller than the size of the third part 43 in the second direction Y, so as to further increase the area of the third part 43 .
  • the size of the third part 43 in the second direction Y is smaller than the size of the second part 42 in the second direction Y.
  • the third portion 43 occupies a smaller space in the second direction Y, and the arrangement of the third portion 43 has less impact on the size of the wiring substrate in the second direction Y.
  • an orthographic projection of the third portion 43 on the substrate covers at least one orthographic projection of the first opening 51 on the substrate. That is, a partial area of the third portion 43 is exposed by the first opening 51 .
  • part of the electrostatic charge introduced during the process of applying the protective film will be dispersed to the area of the third portion 43 exposed by the first opening 51 , and the sub-pad 311 adjacent to the third portion 43 will The reduction in the amount of electrostatic charges injected onto the sub-pad 311 on the wiring substrate can further improve the problem of electrostatic breakdown caused by the accumulation of electrostatic charges in the sub-pad 311 of the wiring substrate.
  • the orthographic projection of one third portion 43 on the substrate covers the orthographic projection of at least two first openings 51 on the substrate; the at least two first openings 51 are arranged at intervals in the first direction X.
  • the first openings 51 corresponding to the third part 43 are well dispersed in the first direction X, and are introduced into each sub-pad 311 adjacent to the third part 43 during the process of applying the protective film. The amount of electrostatic charge dispersed by the third part 43 is greater.
  • the total area of each first opening 51 corresponding to one of the third portions 43 is greater than the total area of each second opening 52 corresponding to one of the adjacent pad groups 30 .
  • the orthographic projection of the third part 43 on the substrate covers the orthographic projection of its corresponding first openings 51 on the substrate.
  • the distance from the second opening 52 with the smallest distance from the binding area 1021 to the binding area 1021 is the first distance
  • the distance from the edge of the second portion 42 toward the binding area 1021 to the binding area 1021 is the second distance
  • the distance from the edge of the third portion 43 toward the binding area 1021 to the binding area 1021 is the third distance.
  • the second distance is greater than or equal to the first distance.
  • the second part 42 does not exceed the sub-pad 311 of the pad group adjacent to it in the first direction X, and the arrangement of the second part 42 does not affect the orientation of the pad group 30 adjacent to the second part.
  • the third distance is greater than or equal to the first distance. In this way, the third part 43 does not exceed the sub-pad 311 of the adjacent pad group in the first direction X, and the arrangement of the third part 43 will not affect the pad group 30 adjacent to the third part 43 Arrangement of signal lines toward bonding area 1021.
  • At least one signal line is located on the side of the second portion 42 facing the binding area 1021; in the first direction X, the The distance between the second portion 42 and the signal line located on the side of the second portion 42 facing the binding area 1021 is greater than or equal to 200 microns.
  • the distance between the second part 42 and the signal line located on the side of the second part 42 facing the binding area 1021 refers to the distance between the second part 42 and the signal line located on the side of the second part 42 facing the binding area 1021 .
  • the minimum distance between signal lines on both sides As shown in FIG.
  • the signal lines located on the side of the second part 42 facing the binding area 1021 include the common voltage line GND, the source power line PWR, the source address line DI, etc., and the signal lines between the common voltage line GND and the second part 42 The distance is the smallest.
  • the distance between the second part 42 and the common voltage line GND located on the side of the second part 42 facing the binding area 1021 is d1, and d1 is greater than or equal to 200 microns.
  • Such an arrangement can avoid signal crosstalk caused by too small a distance between the second portion 42 and the signal line located on the side of the second portion 42 facing the binding area 1021 .
  • At least one signal line is located on the side of the third part 43 facing the binding area 1021; in the first direction X, the The distance between the third part 43 and the signal line located on the side of the third part 43 facing the binding area 1021 is greater than or equal to 200 microns.
  • the distance between the third part 43 and the signal line located on the side of the third part 43 facing the binding area 1021 refers to the distance between the third part 43 and the signal line located on the side of the third part 43 facing the binding area 1021 .
  • the signal line located on the side of the third part 43 facing the binding area 1021 includes the driving voltage line VLED.
  • the distance between the driving voltage line VLED and the third part 43 is d2, and d2 is greater than or equal to 200 microns. .
  • Such an arrangement can avoid signal crosstalk caused by too small a distance between the third portion 43 and the signal line located on the side of the third portion 43 facing the binding area 1021 .
  • connection wires 60 are connected through the connection wires 60 .
  • the minimum distance between the second portion 42 and the adjacent connecting wire 60 is greater than or equal to 200 microns.
  • the minimum distance between the second portion 42 and the adjacent connecting wire 60 is d3, and d3 is greater than or equal to 200 microns. This arrangement can avoid signal crosstalk between the second portion 42 and the adjacent connecting wire 60 .
  • the minimum distance between the third portion 43 and the adjacent connecting wire 60 is greater than or equal to 200 microns. As shown in FIG. 2 , in the second direction Y, the minimum distance between the third part 43 and the adjacent connecting wire 60 is d4, and d4 is greater than or equal to 200 microns. This arrangement can avoid signal crosstalk between the third part 43 and the adjacent connecting wire 60 .
  • the wiring substrate further includes a reflective material layer 83 located on the side of the insulating layer 50 facing away from the substrate 10 , and the reflective material layer 83 covers the first opening 51 .
  • the reflective material layer 83 is provided with an opening, and the inorganic light-emitting diode welded to the first sub-pad group is exposed through the opening.
  • the arrangement of the reflective material layer can increase the amount of light emitted by the inorganic light-emitting diode.
  • the reflective material layer covering the first opening 51 can prevent water and oxygen from intruding into the shielded signal line 40 through the first opening 51 and causing the shielded signal line 40 to be corroded, which helps to improve the reliability of the wiring substrate.
  • the material of the reflective material layer can be white ink, and specific components include resin (for example, epoxy resin, polytetrafluoroethylene resin), titanium dioxide (chemical formula TiO2) and organic solvent (for example, dipropylene glycol Methyl ether) etc.
  • resin for example, epoxy resin, polytetrafluoroethylene resin
  • titanium dioxide chemical formula TiO2
  • organic solvent for example, dipropylene glycol Methyl ether
  • the wiring substrate further includes a stress matching layer 70 located between the substrate 10 and the shielded signal line 40 and each signal line.
  • the stress matching layer 70 can reduce the stress difference between the substrate 10 and the shielded signal line 40 and each signal line to prevent film layer warpage.
  • the material of the stress matching layer 70 may be silicon nitride, silicon oxide or silicon oxynitride.
  • An embodiment of the present application also provides an electronic device, which includes the wiring substrate described in any of the above embodiments and an electronic component connected to the pad group. Specifically, in the die-bonding process, each pin of the electronic component can be bonded to each sub-pad through soldering metal S, and then in the reflow soldering process, each pin of the electronic component is fixed to each sub-pad. connect.
  • the electronic components may include inorganic light-emitting diodes with dimensions on the order of hundreds of microns and below, and the electronic components may also include driver chips with dimensions on the order of hundreds of microns and below.
  • inorganic light-emitting diodes of hundreds of microns and below can be mini LEDs or micro LEDs.
  • the size range of mini LED is about 100 ⁇ m ⁇ 500 ⁇ m, and the size of micro LED is less than 100 ⁇ m.
  • the driver chip may be a chip used to provide signals to the inorganic light-emitting diodes to cause the inorganic light-emitting diodes to emit light.
  • each pad group 30 includes a first sub-pad group 31 and a second sub-pad group 32 .
  • the sub-pads 311 of the first sub-pad group 31 are welded to the inorganic light-emitting diodes.
  • the sub-pads 311 of the second sub-pad group 32 are welded to the driver chip.
  • the electronic device can be used as a backlight source of a liquid crystal display panel.
  • the electronic device may be a liquid crystal display device, and the liquid crystal display device further includes a liquid crystal panel, and the liquid crystal panel is located on a side of the electronic component facing away from the substrate.
  • the liquid crystal display device can have more uniform backlight brightness and better display contrast.
  • each inorganic light-emitting diode serves as a sub-pixel.
  • display devices which can be televisions, laptops, tablets, wearable display devices, mobile phones, car displays, navigation, e-books, digital photo frames, advertising light boxes, and any other device with display functions. product or part.

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Abstract

本申请提供一种布线基板及电子装置。所述布线基板包括衬底及设置在所述衬底上的屏蔽信号线。所述衬底包括功能区；所述功能区设置有多个焊盘组；所述多个焊盘组分别沿第一方向和第二方向阵列分布，所述第二方向与所述第一方向交叉。所述屏蔽信号线包括环绕所有焊盘组的第一部以及与所述第一部连接的第二部，所述第二部位于在所述第二方向上相邻的两个焊盘组之间。所述电子装置包括所述布线基板及与所述焊盘组连接的电子元件。

Description

布线基板及电子装置 技术领域
本申请涉及显示技术领域，特别涉及一种布线基板及电子装置。
背景技术
微型发光二极管，例如Mini-LED和Micro LED，其尺寸大约小于500μm，由于其具有更小的尺寸和超高的亮度、寿命长等优势，因此在显示领域使用趋势明显增大。
发明内容
本申请实施例的第一方面，提供了一种布线基板。所述布线基板包括衬底及设置在所述衬底上的屏蔽信号线；
所述衬底包括功能区；所述功能区设置有多个焊盘组；所述多个焊盘组分别沿第一方向和第二方向阵列分布，所述第二方向与所述第一方向交叉；
所述屏蔽信号线包括环绕所有焊盘组的第一部以及与所述第一部连接的第二部，所述第二部位于在所述第二方向上相邻的两个焊盘组之间。
在一个实施例中，所述布线基板还包括位于所述功能区一侧的绑定区，所述第二部位于沿所述第一方向排布的多个焊盘组中最远离所述绑定区且在所述第二方向上相邻的两个焊盘组之间。
在一个实施例中，所述第一部与所述第二部构成一体结构。
在一个实施例中，所述第一部的线宽小于所述第二部在所述第一方向上的尺寸。
在一个实施例中，所述布线基板还包括位于所述屏蔽信号线背离所述衬底一侧的绝缘层，所述绝缘层设有多个第一开孔，一个所述第二部在所述衬底上的正投影覆盖至少一个所述第一开孔在所述衬底上的正投影。
在一个实施例中，一个所述第二部在所述衬底上的正投影覆盖至少两个第一开孔在所述衬底上的正投影内，且所述至少两个第一开孔在所述第一方向上间隔排布。
在一个实施例中，所述焊盘组至少包括两个子焊盘；所述绝缘层还设有多个第二开孔，一个所述第二开孔暴露一个所述子焊盘；一个所述第二部对应的各所述第一开孔的总面积大于与其相邻的一个焊盘组对应的各第二开孔的总面积。
在一个实施例中，所述屏蔽信号线还包括与所述第一部连接的第三部；
所述第三部设置在位于所述功能区的边角位置的焊盘组在所述第二方向上未与其他焊盘组相邻的一侧。
在一个实施例中，所述第一部与所述第三部构成一体结构。
在一个实施例中，所述第一部的线宽小于所述第三部在所述第一方向上的尺寸；和/或，所述第三部在所述第二方向上的尺寸小于所述第二部在所述第二方向上的尺寸。
在一个实施例中，所述布线基板还包括位于所述屏蔽信号线背离所述衬底一侧的绝缘层，所述绝缘层设有多个第一开孔，一个所述第三部在所述衬底上的正投影覆盖至少一个所述第一开孔在所述衬底上的正投影。
在一个实施例中，一个所述第三部在所述衬底上的正投影覆盖至少两个第一开孔在所述衬底上的正投影；所述至少两个第一开孔在所述第一方向上间隔排布。
在一个实施例中，所述焊盘组至少包括两个子焊盘；所述绝缘层还设有多个第二开孔，一个所述第二开孔暴露一个所述子焊盘；
一个所述第三部对应的各第一开孔的总面积大于与其相邻的一个所述焊盘组对应的各第二开孔的总面积。
在一个实施例中，所述布线基板还包括位于所述功能区一侧的绑定区；沿所述第一方向排布的多个焊盘组中最远离所述绑定区的焊盘组对应的多个第二开孔中，与所述绑定区距离最小的第二开孔到所述绑定区的距离为 第一距离，所述第二部朝向所述绑定区的边缘到所述绑定区的距离为第二距离，所述第三部朝向所述绑定区的边缘到所述绑定区的距离为第三距离；
所述第二距离大于或等于所述第一距离；和/或，所述第三距离大于或等于所述第一距离。
在一个实施例中，所述绝缘层包括无机层。
在一个实施例中，所述布线基板还包括位于所述绝缘层背离所述衬底一侧的反射材料层，所述反射材料层覆盖所述第一开孔。
在一个实施例中，所述布线基板还包括设置在所述衬底上的多条信号线，所述布线基板还包括位于所述功能区一侧的绑定区；
所述多条信号线中，至少一条信号线位于所述第二部朝向所述绑定区的一侧；在所述第一方向上，所述第二部与位于所述第二部朝向所述绑定区的一侧的信号线之间的距离大于或等于200微米；
和/或，所述多条信号线中，至少一条信号线位于所述第三部朝向所述绑定区的一侧；在所述第一方向上，所述第三部与位于所述第三部朝向所述绑定区一侧的信号线之间的距离大于或等于200微米。
在一个实施例中，所述焊盘组包括多个子焊盘，所述布线基板还包括连接导线，同一所述焊盘组中的至少两个子焊盘通过所述连接导线连接；在所述第二方向上，所述第二部与相邻的所述连接导线之间的最小距离大于或等于200微米；和/或，在所述第二方向上，所述第三部与相邻的所述连接导线之间的最小距离大于或等于200微米。
在一个实施例中，所述焊盘组包括多个子焊盘，所述多个子焊盘与所述屏蔽信号线同层设置。
本申请实施例的第二方面，提供了一种电子装置，所述电子装置包括上述的布线基板及与所述焊盘组连接的电子元件。
本申请实施例提供的布线基板及电子装置，通过设置屏蔽信号线包括第二部，第二部位于在第二方向上相邻的两个焊盘组之间，则第二部可将与其相邻的焊盘组的子焊盘积累的静电荷导出，提升屏蔽信号线导出静电 荷的能力，进而改善相邻子焊盘之间发生的静电击穿的问题，提升布线基板的产品良率。
附图说明
图1是本申请一示例性实施例提供的布线基板的结构示意图；
图2是本申请一示例性实施例提供的布线基板的局部结构示意图；
图3是图2所示的布线基板沿AA方向的局部剖视图；
图4是本申请一示例性实施例提供的布线基板所在的电子装置的局部结构示意图；
图5是图4所示的电子装置沿BB方向得到的布线基板的局部结构剖视图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施例并不代表与本申请相一致的所有实施例。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境， 如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
本申请实施例提供了一种布线基板及电子装置。下面结合附图，对本申请实施例中的布线基板及电子装置进行详细说明。在不冲突的情况下，下述的实施例中的特征可以相互补充或相互组合。
本申请实施例提供了一种布线基板。如图1及图2所示，所述布线基板包括衬底及设置在所述衬底上的屏蔽信号线40。所述衬底包括功能区101，所述功能区101设置有多个焊盘组30。所述多个焊盘组30分别沿第一方向X和第二方向Y阵列分布，所述第二方向Y与所述第一方向X交叉。所述屏蔽信号线40包括环绕所有焊盘组30的第一部41以及与所述第一部41连接的第二部42，所述第二部42位于在所述第二方向Y上相邻的两个焊盘组30之间。每一焊盘组30包括多个子焊盘311。
在一个实施例中，如图3所示，所述布线基板包括位于所述屏蔽信号线40背离所述衬底10一侧的绝缘层50，所述绝缘层50可覆盖布线基板的导电层的大部分区域，防止水氧入侵，提升布线基板的信赖性。
在一些实施例中，所述绝缘层50包括无机层。无机层阻隔水氧的效果较好，更有助于提升布线基板的信赖性。在一示例性实施例中，所述绝缘层的材料为无机材料，无机材料可包括氮化硅、氧化硅或氮氧化硅中的至少一种。所述绝缘层50可包括一层无机层，或者可包括多层无机层，或可以包括有机层和无机层的叠层结构。
在一个实施例中，如图2所示，所述绝缘层50设有多个第二开孔52，一个所述第二开孔52暴露一个所述子焊盘311。也即是布线基板的导电层被第二开孔52暴露的区域即为子焊盘311。
在布线基板所在的电子装置的制程中，因前后工序的工艺条件发生变化，需要将布线基板从上一工序转送到下一工序，在一些实施例中会涉及保护膜的贴附和撕除。具体来说，在布线基板制备完成各个线路膜层后，通过化镍金工艺对子焊盘所在的区域进行防氧化处理之前，会涉及保护膜 的贴附和撕除；通过化镍金工艺对子焊盘所在的区域进行防氧化处理之后，在布线基板上设置反射材料层之前，会涉及保护膜的贴附和撕除。绝缘层50的材料为无机材料，在将保护膜贴附在绝缘层50上的过程中会导致静电荷注入至焊盘组30的子焊盘311，子焊盘311积累的静电荷无法有效导出，会引起相邻子焊盘311之间发生静电击穿的问题。
本申请实施例提供的布线基板，通过设置屏蔽信号线40包括第二部42，第二部42位于在第二方向Y上相邻的两个焊盘组30之间，则第二部42可将与其相邻的焊盘组30的子焊盘311积累的静电荷导出，提升屏蔽信号线40导出静电荷的能力，进而改善相邻子焊盘311之间发生的静电击穿的问题，提升布线基板的产品良率。
在一个实施例中，所述第一方向X与第二方向Y互相垂直。例如，第一方向X为列方向，第二方向Y为行方向。
在一个实施例中，所述功能区101设置的多个焊盘组30可布置为多行多列。每一行焊盘组包括多个在行方向上间隔排布的焊盘组30，每一列焊盘组包括多个在列方向上间隔排布的焊盘组30。
在一个实施例中，所述衬底还可包括边框区102，边框区102可环绕功能区101。屏蔽信号线40的第一部41可位于边框区102。边框区102可包括绑定区1021。绑定区1021设有柔性电路板。
在一个实施例证，如图1及图2所示，所述布线基板还包括设置在所述衬底上的多条信号线，所述多条信号线例如包括公共电压线GND、驱动电压线VLED、源电源线PWR、源地址线DI等。各信号线与绑定区1021的柔性电路板电连接。柔性电路板为屏蔽信号线40和所述多条信号线提供信号，例如柔性电路板可为公共电压线GND和屏蔽信号线40提供相同的信号。
在一个实施例中，所述焊盘组30的子焊盘311用于与电子元件焊接。所述电子元件可包括尺寸在百微米及以下量级的无机发光二极管，所述电子元件也可包括尺寸在百微米及以下量级的驱动芯片。其中百微米及以下 量级的无机发光二极管可以是mini LED，也可以是micro LED。mini LED的尺寸范围约为100μm～500μm，micro LED的尺寸小于100μm。驱动芯片可以是用来向无机发光二极管提供信号使无机发光二极管发光的芯片。
在一些实施例中，如图1、图2及图4所示，每一焊盘组30包括第一子焊盘组31和第二子焊盘组32。第一子焊盘组31包括至少两个子焊盘311，第一子焊盘组31的子焊盘311用于与无机发光二极管焊接。例如一个无机发光二极管可包括两个引脚，对应第一子焊盘组31的两个子焊盘311，该两个子焊盘311中的一个为阳极焊盘，一个为阴极焊盘。第二子焊盘组32包括至少两个子焊盘311，第二子焊盘组32的子焊盘311用于与驱动芯片焊接。如图4所示，一个驱动芯片包括四个引脚，其对应的第二子焊盘组32包括四个子焊盘，分别为地址焊盘Di、电源焊盘Pwr、公共电压焊盘Gnd、以及输出焊盘Out。同一焊盘组中，第二子焊盘组32的输出焊盘Out至少与一个第一子焊盘组31的一个子焊盘311连接；第二子焊盘组32的公共电压焊盘Gnd与公共电压线GND连接，以接收公共电压线GND传输的公共电压(例如接地电压)；第二子焊盘组32的电源焊盘Pwr与源电源线PWR连接。驱动电压线VLED与一个第一子焊盘组31的一个子焊盘311连接。源地址线DI与每列焊盘组中与第一级驱动芯片焊接的地址焊盘Di相连，被配置为向每列焊盘组焊接的第一级驱动芯片传输地址信号。
在一个实施例中，一个焊盘组30可包括四个第一子焊盘组31和一个第二子焊盘组32，也即是四个无机发光二极管可由一个驱动芯片驱动。如图2所示，该四个第一子焊盘组31中，以与驱动电压线VLED电连接的第一子焊盘组31作为这四个第一子焊盘组31串联的起点，与第二子焊盘组32电连接的第一子焊盘组31作为这四个无机发光二极管串联的终点。需要说明的是，本申请的实施例中，每个焊盘组30的第一子焊盘组31的数量不受限制，可以为五个、六个、七个、八个等任意数量，而不限于四个。
在一个实施例中，所述布线基板还包括连接导线，同一所述焊盘组中 的至少两个子焊盘通过所述连接导线连接。例如，同一焊盘组30中相邻第一子焊盘组31的子焊盘311通过连接导线60串联。
在一个实施例中，所述屏蔽信号线40、所述焊盘组30的各子焊盘311以及所述多条信号线位于同一层。也即是单层导电层既可以用来制作多个子焊盘以及连接相邻子焊盘的走线，同时还可以用来制作多条信号线以将相应的电信号传输至与第二子焊盘组的子焊盘焊接的驱动芯片和与第一子焊盘组的子焊盘焊接的无机发光二极管，如此有助于简化布线基板的膜层结构，简化制备成本。在本申请中，术语“A与B位于同一层”是指A与B位于同一膜层的表面之上且均与该表面直接接触。在一些实施例中，A与B由同一膜层通过采用同一工艺形成。在一些实施例中，A与B位于同一膜层的表面之上且均与该表面直接接触，并且A与B具有基本相同的高度或厚度。
在一个实施例中，如图5所示，所述布线基板还包括位于所述衬底10与子焊盘311之间的绝缘材料层82，所述绝缘材料层82设有多个第三开孔801，每一子焊盘311至少部分位于所述第三开孔801内，每一所述第三开孔801在所述衬底10上的正投影落在一个所述第二开孔52在所述衬底10上的正投影内。子焊盘311至少部分位于第三开孔801内，也即是子焊盘311的至少部分在第三开孔801内向下凹陷；第三开孔801在衬底上的正投影落在第二开孔52在衬底上的正投影内，使得子焊盘311露出绝缘层50。电子元件90包括电子元件本体91及为电子元件本体91一侧的引脚92，在将电子元件90的引脚92与子焊盘311焊接的过程中，引脚92表面包覆的焊料熔化后向第三开孔801流动，带动各引脚92向与其进行焊接的子焊盘311移动，引脚92向子焊盘311的移动可使得电子元件90相对于其焊接位置发生的偏移得到改善，使引脚92与对应的子焊盘311有效焊接，避免电子元件的偏移导致引脚92与子焊盘311出现虚焊的问题，提升产品的良率。
在一个实施例中，如图5所示，所述绝缘材料层82包括第一有机层 821。
进一步地，第一有机层821的厚度范围为2μm～4μm。如此设置，既可保证工艺易于实现，也可避免第一有机层821的厚度太大，导致阵列基板的厚度较大。在一些实施例中，第一有机层821的厚度例如为2μm、2.5μm、3μm、3.5μm、4μm等。
在一个实施例中，第一有机层821为单层膜层，或者第一有机层821包括多个子有机层，也即是第一有机层821通过多次涂覆工艺形成。第一有机层821的材料可以为有机树脂。
在一个实施例中，如图5所示，所述布线基板还包括位于所述衬底10与绝缘材料层82之间的钝化保护层81，钝化保护层81可与衬底10直接接触。钝化保护层81可保护衬底10，防止在对衬底10上方的膜层进行刻蚀时损伤衬底10。钝化保护层81的材料可以是无机材料，例如为氮化硅、氧化硅或氮氧化硅。在一个实施例中，如图1所示，所述第二部42位于沿所述第一方向X排布的多个焊盘组30中最远离所述绑定区1021且在所述第二方向Y上相邻的两个焊盘组30之间。由于沿第一方向X排布的多个焊盘组30中最远离绑定区1021的焊盘组30附近用于将静电荷导走的导电层的面积较小，相邻子焊盘311之间更容易发生静电击穿的问题，第二部42设置在这些焊盘组30中相邻的两个焊盘组30之间，可更有效地改善由于这些焊盘组30的子焊盘311由于静电荷积累导致的静电击穿的问题。
在一些实施例中，如图1所示，沿所述第一方向X排布的多个焊盘组30中最远离所述绑定区1021的一行焊盘组30中，任相邻的两个焊盘组30之间均设有第二部42。如此设置，更有助于改善布线基板中距离绑定区1021最远的焊盘组30中的子焊盘311由于静电荷积累导致的静电击穿的问题。
在一个实施例中，所述第一部41与所述第二部42构成一体结构。
在一个实施例中，所述第一部41的线宽小于所述第二部42在所述第一方向上的尺寸。其中，第一部41包括沿第一方向X延伸的第一区段及 沿第二方向Y延伸的第二区段；第一区段的线宽指的是第一区段在第二方向Y上的宽度，第二区段的线宽指的是第二区段在第一方向X上的宽度。通过设置第二部42在第一方向X上的尺寸大于第一部41的线宽，可使得第二部42的面积较大，第二部42能将相邻的子焊盘311上积累的静电荷导走的量更多，且可有效减小屏蔽信号线40的阻抗，提升屏蔽信号线40导走静电荷的能力，静电荷更有助于改善布线基板中子焊盘311由于静电荷积累导致的静电击穿的问题。
在一个实施例中，如图2及图3所示，所述绝缘层50设有多个第一开孔51，一个所述第二部42在所述衬底上的正投影覆盖至少一个所述第一开孔51在所述衬底10上的正投影。也即是第二部42的部分区域被第一开孔51暴露。如此设置，在贴覆保护膜的过程中引入的静电荷中部分静电荷会分散至第二部42被第一开孔51暴露的区域，则与第二部42相邻的子焊盘311被注入的静电荷的量减少，可进一步改善布线基板中子焊盘311的静电荷积累导致的静电击穿的问题。其中，第一开孔51的形状可为矩形、正方形、圆形等。
在一个实施例中，如图2所示，所示第一开孔51的面积大于第二开孔52的面积。如此设置，在贴覆保护膜的过程中引入的静电荷更易于注入至面积较大的第一开孔51，从而更有助于减小与第二部42相邻的子焊盘311注入的静电荷的量。
在一个实施例中，如图2所示，一个所述第二部42在所述衬底上的正投影覆盖至少两个第一开孔51在所述衬底上的正投影内，且所述至少两个第一开孔51在所述第一方向X上间隔排布。如此设置，第二部42对应的各第一开孔51在第一方向X上分散性较好，在贴覆保护膜的过程中引入至与该第二部42相邻的各子焊盘311的静电荷被该第二部42分散的量更多。
在一个实施例中，一个所述第二部42对应的各所述第一开孔51的总面积大于与其相邻的一个焊盘组30对应的各第二开孔52的总面积。第二 部42在衬底上的正投影覆盖其对应的各第一开孔51在衬底上的正投影。如此设置，在贴覆保护膜的过程中引入的静电荷大部分注入至第二部42被第一开孔51暴露的区域并通过屏蔽信号线导走，可更有效地减小与该第二部42相邻的子焊盘311注入的静电荷的量。
在一个实施例中，如图2所示，所述屏蔽信号线40还包括与所述第一部41连接的第三部43；所述第三部43设置在位于所述功能区101的边角位置的焊盘组30在所述第二方向Y上未与其他焊盘组30相邻的一侧。边角位置的焊盘组30指的是该焊盘组30与第一部41的沿第一方向X延伸的第一区段之间未设有其他焊盘组30，且该焊盘组30与背离绑定区1021的第二区段之间未设有焊盘组30。通过设置第三部43，第三部43可将该边角位置处的焊盘组30积累的静电荷导走，改善该焊盘组30中相邻子焊盘311发生的静电击穿的问题。
在一个实施例中，所述屏蔽信号线40可包括两个相对设置的第三部43，该两个第三部43位于功能区101的相对两侧。
在一个实施例中，所述第一部41与所述第三部43构成一体结构。
在一个实施例中，所述第一部41的线宽小于所述第三部43在所述第一方向X上的尺寸。如此设置，可使得第三部43的面积较大，第三部43能将相邻的子焊盘311上积累的静电荷导走的量更多，且可有效减小屏蔽信号线40的阻抗，提升屏蔽信号线40导走静电荷的能力，更有助于改善布线基板中子焊盘311由于静电荷积累导致的静电击穿的问题。进一步地，所述第一部41的线宽小于所述第三部43在所述第二方向Y上的尺寸，以进一步增大第三部43的面积。
在一个实施例中，所述第三部43在所述第二方向Y上的尺寸小于所述第二部42在所述第二方向Y上的尺寸。如此设置，第三部43在第二方向Y上所占的空间较小，第三部43的设置对布线基板在第二方向Y上的尺寸影响较小。
在一个实施例中，一个所述第三部43在所述衬底上的正投影覆盖至少 一个所述第一开孔51在所述衬底上的正投影。也即是第三部43的部分区域被第一开孔51暴露。如此设置，在贴覆保护膜的过程中引入的静电荷中部分静电荷会分散至第三部43被第一开孔51暴露的区域，则与该第三部43相邻的子焊盘311上被注入的静电荷的量减少，可进一步改善布线基板中子焊盘311由于静电荷积累导致的静电击穿的问题。
在一个实施例中，一个所述第三部43在所述衬底上的正投影覆盖至少两个第一开孔51在所述衬底上的正投影；所述至少两个第一开孔51在所述第一方向X上间隔排布。如此设置，第三部43对应的各第一开孔51在第一方向X上分散性较好，在贴覆保护膜的过程中引入至与该第三部43相邻的各子焊盘311的静电荷被该第三部43分散走的量更多静电荷。
在一个实施例中，一个所述第三部43对应的各第一开孔51的总面积大于与其相邻的一个所述焊盘组30对应的各第二开孔52的总面积。第三部43在衬底上的正投影覆盖其对应的各第一开孔51在衬底上的正投影。如此设置，在贴覆保护膜的过程中引入的静电荷大部分注入至第三部43被第一开孔51暴露的区域并通过屏蔽信号线导走，可更有效地减小与第三部43相邻的子焊盘311注入的静电荷的量。
在一个实施例中，沿所述第一方向X排布的多个焊盘组30中最远离所述绑定区1021的焊盘组30对应的多个第二开孔52中，与所述绑定区1021距离最小的第二开孔52到所述绑定区1021的距离为第一距离，所述第二部42朝向所述绑定区1021的边缘到所述绑定区1021的距离为第二距离，所述第三部43朝向所述绑定区1021的边缘到所述绑定区1021的距离为第三距离。
在一些实施例中，所述第二距离大于或等于所述第一距离。如此设置，第二部42在第一方向X不超出与其相邻的焊盘组的子焊盘311，第二部42的设置不会影响位于与该第二部相邻的焊盘组30朝向绑定区1021一侧的信号线的布置。
在一些实施例中，所述第三距离大于或等于所述第一距离。如此设置， 第三部43在第一方向X不超出与其相邻的焊盘组的子焊盘311，第三部43的设置不会影响位于与该第三部43相邻的焊盘组30朝向绑定区1021的信号线的布置。
在一个实施例中，布线基板的所述多条信号线中，至少一条信号线位于所述第二部42朝向所述绑定区1021的一侧；在所述第一方向X上，所述第二部42与位于所述第二部42朝向所述绑定区1021的一侧的信号线之间的距离大于或等于200微米。其中，第二部42与位于第二部42朝向所述绑定区1021的一侧的信号线之间的距离指的是，第二部42与位于第二部42朝向绑定区1021的一侧的信号线之间的最小距离。如图2所示，位于第二部42朝向绑定区1021一侧的信号线包括公共电压线GND、源电源线PWR及源地址线DI等，公共电压线GND与第二部42之间的距离最小，所述第二部42与位于所述第二部42朝向绑定区1021的一侧的公共电压线GND之间的距离为d1，则d1大于或等于200微米。如此设置，可避免第二部42与位于该第二部42朝向绑定区1021一侧的信号线之间距离太小而产生信号串扰。
在一个实施例中，布线基板的所述多条信号线中，至少一条信号线位于所述第三部43朝向所述绑定区1021的一侧；在所述第一方向X上，所述第三部43与位于所述第三部43朝向所述绑定区1021一侧的信号线之间的距离大于或等于200微米。其中，第三部43与位于第三部43朝向所述绑定区1021的一侧的信号线之间的距离指的是，第三部43与位于第三部43朝向绑定区1021的一侧的信号线之间的最小距离。如图2所示，位于第三部43朝向绑定区1021一侧的信号线包括驱动电压线VLED，驱动电压线VLED与第三部43之间的距离为d2，则d2大于或等于200微米。如此设置，可避免第三部43与位于该第三部43朝向绑定区1021一侧的信号线之间距离太小而产生信号串扰。
在一个实施例中，同一所述焊盘组30中的至少两个子焊盘311通过所述连接导线60连接。在所述第二方向Y上，所述第二部42与相邻的所述 连接导线60之间的最小距离大于或等于200微米。如图2所示，在所述第二方向Y上，所述第二部42与相邻的所述连接导线60之间的最小距离为d3，则d3大于或等于200微米。如此设置，可避免第二部42与相邻的连接导线60之间产生信号串扰。
在一个实施例中，在所述第二方向Y上，所述第三部43与相邻的所述连接导线60之间的最小距离大于或等于200微米。如图2所示，在所述第二方向Y上，所述第三部43与相邻的所述连接导线60之间的最小距离为d4，则d4大于或等于200微米。如此设置，可避免第三部43与相邻的连接导线60之间产生信号串扰。
在一个实施例中，所述布线基板还包括位于所述绝缘层50背离所述衬底10一侧的反射材料层83，所述反射材料层83覆盖所述第一开孔51。反射材料层83设有开口，与第一子焊盘组焊接的无机发光二极管通过开口露出，反射材料层的设置可提升无机发光二极管发射的光线的出射量。反射材料层覆盖第一开孔51，可防止水氧通过第一开孔51入侵至屏蔽信号线40而导致屏蔽信号线40被腐蚀，有助于提升布线基板的信赖性。在一些实施例中，所述反射材料层的材料可为白色油墨，具体组分包括树脂(例如，环氧树脂、聚四氟乙烯树脂)、二氧化钛(化学式TiO2)以及有机溶剂(例如，二丙二醇甲醚)等。
在一个实施例中，如图3所示，所述布线基板还包括位于所述衬底10与屏蔽信号线40及各信号线之间的应力匹配层70。应力匹配层70可减小衬底10与屏蔽信号线40及各信号线之间的应力差，防止发生膜层翘曲。应力匹配层70的材料可为氮化硅、氧化硅或氮氧化硅。
本申请实施例还提供了一种电子装置，所述电子装置包括上述任一实施例所述的布线基板及与所述焊盘组连接的电子元件。具体的，在固晶工艺中，电子元件的各个引脚可以分别通过焊接金属S与各个子焊盘进行粘接，接着在回流焊工艺中，电子元件的各个引脚与各个子焊盘实现固定连接。
在一个实施例中，所述电子元件可包括尺寸在百微米及以下量级的无机发光二极管，所述电子元件也可包括尺寸在百微米及以下量级的驱动芯片。其中百微米及以下量级的无机发光二极管可以是mini LED，也可以是micro LED。mini LED的尺寸范围约为100μm～500μm，micro LED的尺寸小于100μm。驱动芯片可以是用来向无机发光二极管提供信号使无机发光二极管发光的芯片。
在一些实施例中，每一焊盘组30包括第一子焊盘组31和第二子焊盘组32。第一子焊盘组31的子焊盘311与无机发光二极管焊接。第二子焊盘组32的子焊盘311与驱动芯片焊接。
在一个实施例中，所述电子装置可作为液晶显示面板的背光源使用。
在另一实施例中，所述电子装置可以为液晶显示装置，液晶显示装置还包括液晶面板，液晶面板位于电子元件背离衬底的一侧。该液晶显示装置可以具有更均匀的背光亮度，具有更好的显示对比度。
在另一实施例中，所述电子装置作为显示装置时，每一无机发光二极管作为一个子像素。
本申请对于显示装置的适用不做具体限制，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备、手机、车载显示、导航、电子书、数码相框、广告灯箱等任何具有显示功能的产品或部件。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适 应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (20)

  1. 一种布线基板，其特征在于，包括衬底及设置在所述衬底上的屏蔽信号线；
    所述衬底包括功能区；所述功能区设置有多个焊盘组；所述多个焊盘组分别沿第一方向和第二方向阵列分布，所述第二方向与所述第一方向交叉；
    所述屏蔽信号线包括环绕所有焊盘组的第一部以及与所述第一部连接的第二部，所述第二部位于在所述第二方向上相邻的两个焊盘组之间。
  2. 根据权利要求1所述的布线基板，其特征在于，所述布线基板还包括位于所述功能区一侧的绑定区，所述第二部位于沿所述第一方向排布的多个焊盘组中最远离所述绑定区且在所述第二方向上相邻的两个焊盘组之间。
  3. 根据权利要求2所述的布线基板，其特征在于，所述第一部与所述第二部构成一体结构。
  4. 根据权利要求2所述的布线基板，其特征在于，所述第一部的线宽小于所述第二部在所述第一方向上的尺寸。
  5. 根据权利要求1所述的布线基板，其特征在于，所述布线基板还包括位于所述屏蔽信号线背离所述衬底一侧的绝缘层，所述绝缘层设有多个第一开孔，一个所述第二部在所述衬底上的正投影覆盖至少一个所述第一开孔在所述衬底上的正投影。
  6. 根据权利要求5所述的布线基板，其特征在于，一个所述第二部在所述衬底上的正投影覆盖至少两个第一开孔在所述衬底上的正投影内，且所述至少两个第一开孔在所述第一方向上间隔排布。
  7. 根据权利要求5所述的布线基板，其特征在于，所述焊盘组至少包括两个子焊盘；所述绝缘层还设有多个第二开孔，一个所述第二开孔暴露一个所述子焊盘；一个所述第二部对应的各所述第一开孔的总面积大于与 其相邻的一个焊盘组对应的各第二开孔的总面积。
  8. 根据权利要求1所述的布线基板，其特征在于，所述屏蔽信号线还包括与所述第一部连接的第三部；
    所述第三部设置在位于所述功能区的边角位置的焊盘组在所述第二方向上未与其他焊盘组相邻的一侧。
  9. 根据权利要求8所述的布线基板，其特征在于，所述第一部与所述第三部构成一体结构。
  10. 根据权利要求8所述的布线基板，其特征在于，所述第一部的线宽小于所述第三部在所述第一方向上的尺寸；和/或，所述第三部在所述第二方向上的尺寸小于所述第二部在所述第二方向上的尺寸。
  11. 根据权利要求8所述的布线基板，其特征在于，所述布线基板还包括位于所述屏蔽信号线背离所述衬底一侧的绝缘层，所述绝缘层设有多个第一开孔，一个所述第三部在所述衬底上的正投影覆盖至少一个所述第一开孔在所述衬底上的正投影。
  12. 根据权利要求11所述的布线基板，其特征在于，一个所述第三部在所述衬底上的正投影覆盖至少两个第一开孔在所述衬底上的正投影；所述至少两个第一开孔在所述第一方向上间隔排布。
  13. 根据权利要求11所述的布线基板，其特征在于，所述焊盘组至少包括两个子焊盘；所述绝缘层还设有多个第二开孔，一个所述第二开孔暴露一个所述子焊盘；
    一个所述第三部对应的各第一开孔的总面积大于与其相邻的一个所述焊盘组对应的各第二开孔的总面积。
  14. 根据权利要求11所述的布线基板，其特征在于，所述布线基板还包括位于所述功能区一侧的绑定区；沿所述第一方向排布的多个焊盘组中最远离所述绑定区的焊盘组对应的多个第二开孔中，与所述绑定区距离最小的第二开孔到所述绑定区的距离为第一距离，所述第二部朝向所述绑定区的边缘到所述绑定区的距离为第二距离，所述第三部朝向所述绑定区的 边缘到所述绑定区的距离为第三距离；
    所述第二距离大于或等于所述第一距离；和/或，所述第三距离大于或等于所述第一距离。
  15. 根据权利要求5或11所述的布线基板，其特征在于，所述绝缘层包括无机层。
  16. 根据权利要求5或11所述的布线基板，其特征在于，所述布线基板还包括位于所述绝缘层背离所述衬底一侧的反射材料层，所述反射材料层覆盖所述第一开孔。
  17. 根据权利要求8所述的布线基板，其特征在于，所述布线基板还包括设置在所述衬底上的多条信号线，所述布线基板还包括位于所述功能区一侧的绑定区；
    所述多条信号线中，至少一条信号线位于所述第二部朝向所述绑定区的一侧；在所述第一方向上，所述第二部与位于所述第二部朝向所述绑定区的一侧的信号线之间的距离大于或等于200微米；
    和/或，所述多条信号线中，至少一条信号线位于所述第三部朝向所述绑定区的一侧；在所述第一方向上，所述第三部与位于所述第三部朝向所述绑定区一侧的信号线之间的距离大于或等于200微米。
  18. 根据权利要求8所述的布线基板，其特征在于，所述焊盘组包括多个子焊盘，所述布线基板还包括连接导线，同一所述焊盘组中的至少两个子焊盘通过所述连接导线连接；在所述第二方向上，所述第二部与相邻的所述连接导线之间的最小距离大于或等于200微米；和/或，在所述第二方向上，所述第三部与相邻的所述连接导线之间的最小距离大于或等于200微米。
  19. 根据权利要求1所述的布线基板，其特征在于，所述焊盘组包括多个子焊盘，所述多个子焊盘与所述屏蔽信号线同层设置。
  20. 一种电子装置，其特征在于，所述电子装置包括权利要求1至19中任一项所述的布线基板及与所述焊盘组连接的电子元件。
PCT/CN2022/094526 2022-05-23 2022-05-23 布线基板及电子装置 WO2023225813A1 (zh)

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CN102856280A (zh) * 2012-09-20 2013-01-02 格科微电子（上海）有限公司 焊盘和芯片
CN103792710A (zh) * 2012-10-30 2014-05-14 三星显示有限公司 制造液晶显示器的方法
CN104615322A (zh) * 2015-02-03 2015-05-13 上海天马微电子有限公司 触控结构、基板、阵列基板及显示装置
CN110890873A (zh) * 2019-11-27 2020-03-17 湖南嘉业达电子有限公司 一种压电陶瓷滤波器
CN114333615A (zh) * 2020-09-30 2022-04-12 合肥鑫晟光电科技有限公司 衬底母板及其制备方法、驱动基板和显示装置

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Publication number Priority date Publication date Assignee Title
CN102856280A (zh) * 2012-09-20 2013-01-02 格科微电子（上海）有限公司 焊盘和芯片
CN103792710A (zh) * 2012-10-30 2014-05-14 三星显示有限公司 制造液晶显示器的方法
CN104615322A (zh) * 2015-02-03 2015-05-13 上海天马微电子有限公司 触控结构、基板、阵列基板及显示装置
CN110890873A (zh) * 2019-11-27 2020-03-17 湖南嘉业达电子有限公司 一种压电陶瓷滤波器
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