WO2023225810A1 - 像素单元、显示基板及其驱动方法和显示装置 - Google Patents

像素单元、显示基板及其驱动方法和显示装置 Download PDF

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Publication number
WO2023225810A1
WO2023225810A1 PCT/CN2022/094523 CN2022094523W WO2023225810A1 WO 2023225810 A1 WO2023225810 A1 WO 2023225810A1 CN 2022094523 W CN2022094523 W CN 2022094523W WO 2023225810 A1 WO2023225810 A1 WO 2023225810A1
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Prior art keywords
signal
light
control
circuit
pixel
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PCT/CN2022/094523
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English (en)
French (fr)
Inventor
谷其兵
胡国锋
李秀玲
付宝
黄文杰
时凌云
陈明
Original Assignee
京东方科技集团股份有限公司
京东方晶芯科技有限公司
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Priority to PCT/CN2022/094523 priority Critical patent/WO2023225810A1/zh
Priority to US18/245,040 priority patent/US12073763B2/en
Priority to CN202280001371.4A priority patent/CN117546224A/zh
Publication of WO2023225810A1 publication Critical patent/WO2023225810A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel unit, a display substrate, a driving method thereof, and a display device.
  • Mini-LED Min Light Emitting Diode, mini light-emitting diode
  • sub-millimeter light-emitting diode refers to LEDs with a grain size of about 100 microns or less.
  • Mini-LED is between traditional LED and Micro-LED (Micro-LED).
  • Light Emitting Diode, micro light-emitting diode) to put it simply, it is an improvement on the basis of traditional LED backlight.
  • a pixel unit includes N light-emitting devices and a pixel driving chip.
  • the pixel driving chip includes: a data signal terminal, a power signal terminal and N signal channel terminals.
  • the data signal terminal is used to receive data signals
  • the power signal terminal is used to receive power signals
  • the N signal channel terminals are connected to the N light-emitting terminals.
  • Devices correspond one to one.
  • the first pole of the first light-emitting device among the N light-emitting devices is configured to be coupled to the power signal terminal
  • the second pole of the n-th light-emitting device among the N light-emitting devices is connected to the second pole of the first light-emitting device.
  • the first pole of the n+1th light emitting device is coupled to the nth signal channel end among the N signal channel ends.
  • N is a positive integer greater than 1
  • n is a positive integer greater than 1 or equal to 1, and less than or equal to N.
  • the pixel driving chip further includes a light-emitting control circuit coupled to the N signal channel terminals, the power signal terminal, and the data signal terminal, and the light-emitting control circuit is configured to, according to The brightness information of the N light-emitting devices controls the current transmitted to the N light-emitting devices and the lighting duration of each light-emitting device, so as to control the actual light emitting brightness of each light-emitting device.
  • the lighting control circuit includes: a modulation circuit and a constant current source circuit. One end of the modulation circuit is coupled to the power signal end, and the other end of the modulation circuit is coupled to the constant current source circuit. coupling.
  • the modulation circuit includes N modulation sub-circuits corresponding to N signal channel terminals, and each of the N modulation sub-circuits includes a control terminal, a first terminal and a second terminal. terminal, the first terminal of the first modulation sub-circuit among the N modulation sub-circuits is coupled to the power signal terminal, and the second terminal of the n-th modulation sub-circuit among the N modulation sub-circuits is coupled to The first end of the (n+1)th modulation sub-circuit is coupled to the n-th signal channel end among the N signal channel ends.
  • the pixel driving chip further includes: a control signal terminal, a reference signal terminal and a voltage signal terminal.
  • the control signal terminal is used to receive the control signal
  • the reference signal terminal is used to receive the reference signal
  • the voltage signal terminal is used to receive the first voltage signal.
  • the constant current source circuit of the lighting control circuit is also coupled to the reference signal terminal and the voltage signal terminal.
  • the pixel driving chip further includes a main processor coupled to the light emitting control circuit, the voltage signal terminal, the control signal terminal and the data signal terminal.
  • the main processor is configured to generate a current control signal and a plurality of pulse width modulation signals according to the brightness information of the N light-emitting devices contained in the data signal, and transmit the current control signal to the constant current
  • the source circuit transmits the plurality of pulse width modulation signals to the N modulation sub-circuits in one-to-one correspondence.
  • the main processor includes a processor and control circuitry.
  • the processor is coupled to the N modulation sub-circuits, and the processor is configured to generate a plurality of pulse width modulation signals and transmit the plurality of pulse width modulation signals to the N modulation sub-circuits in a one-to-one correspondence. subcircuit.
  • the processor is also coupled to the control circuit, the control circuit is coupled to the constant current source circuit, and the processor is further configured to generate a first signal according to the brightness information and convert the The first signal is transmitted to the control circuit, the control circuit is configured to generate a current control signal based on the first signal and transmit the current control signal to the constant current source circuit.
  • the main processor further includes an interface circuit coupled to the data signal terminal, the voltage signal terminal and the processor, and the interface circuit is configured to operate according to the The data signal at the data signal terminal and the identification signal transmitted by the voltage signal terminal generate a decoded signal required by the processor, and transmit the decoded signal to the processor.
  • the modulation subcircuit includes a switching element.
  • the N light-emitting devices include: red light-emitting devices, green light-emitting devices, and blue light-emitting devices.
  • the display substrate includes: a substrate, a plurality of pixel units, a plurality of power signal lines and a plurality of data signal lines.
  • Each of the plurality of pixel units is a pixel unit as described above, the plurality of pixel units are arranged on one side of the substrate, and the plurality of pixel units are arranged in an array along the first direction and the second direction. cloth, the first direction and the second direction cross each other.
  • a plurality of power signal lines are provided on one side of the substrate, and one of the plurality of power signal lines is connected to each pixel driver of a plurality of pixel units arranged in the first direction.
  • the power signal terminal of the chip is coupled.
  • a plurality of data signal lines are provided on one side of the substrate, and one of the plurality of data signal lines is connected to each pixel driver of a plurality of pixel units arranged in the first direction.
  • the data signal terminal of the chip is coupled.
  • the pixel unit includes a control signal terminal, a reference signal terminal and a voltage signal terminal.
  • the display substrate also includes: a plurality of control signal lines, a plurality of reference signal lines and a plurality of voltage signal lines.
  • a plurality of control signal lines are provided on one side of the substrate, and one of the plurality of control signal lines is connected to each pixel driver of a plurality of pixel units arranged in the second direction.
  • the control signal terminal of the chip is coupled.
  • a plurality of reference signal lines are provided on one side of the substrate, and one of the plurality of reference signal lines is connected to each pixel driver of a plurality of pixel units arranged in the first direction.
  • the reference signal terminal of the chip is coupled.
  • a plurality of voltage signal lines are provided on one side of the substrate, and one voltage signal line among the plurality of voltage signal lines is connected to each pixel driver of a plurality of pixel units arranged in the first direction.
  • the voltage signal terminal of the chip is coupled.
  • each of the control signal lines extends along the first direction and is arranged along the second direction, and the control signal lines are located in two adjacent rows of the control signal lines arranged along the second direction. in the gaps between pixel units.
  • Each of the power signal lines, each of the data signal lines, each of the voltage signal lines and each of the reference signal lines extend along the second direction and are arranged along the first direction. The power signal lines, The data signal line, the voltage signal line and the reference signal line are located in a gap between two adjacent rows of pixel units arranged along the first direction.
  • the display substrate further includes a control chip, the control chip is connected to the data signal line and the control signal line, the control chip is configured to provide a data signal to the data signal line, and A control signal is provided to the control signal line.
  • a method for driving a display substrate includes: a data signal setting phase and a display phase.
  • the data signal includes a current signal and a pulse width modulation signal.
  • the display substrate It includes a plurality of pixel units and a control chip, and each of the plurality of pixel units includes N light-emitting devices.
  • the data signal setting stage includes: the control chip receives the i-th frame image signal, and the i-th frame image signal includes: the N light-emitting devices of each pixel unit in the plurality of pixel units in the current frame image. The corresponding initial current signal and initial pulse width modulation signal.
  • the initial current signal includes N initial current sub-signals
  • the initial pulse width modulation signal includes N initial pulse width modulation sub-signals with the same number of bits.
  • the data signal setting stage also includes: the control chip processes the initial current signal to generate a current signal, where the current signal includes an initial current sub-signal with the largest current amplitude among the N initial current sub-signals;
  • the control chip processes the initial pulse width modulation signal to generate a pulse width modulation signal.
  • the pulse width modulation signal includes N pulse width modulation sub-signals with different bit numbers. Among them, i is a positive integer greater than or equal to 1, and N is a positive integer greater than 1.
  • the display stage includes: N light-emitting devices of each pixel unit in the plurality of pixel units emitting light according to the corresponding current signal and the pulse width modulation signal.
  • the display stage includes an address allocation stage and a data signal transmission stage
  • the display substrate includes a plurality of control signal lines and a plurality of data signal lines.
  • control information is input to each control signal line in turn
  • first data information is input to each data signal line.
  • the first data information includes addresses corresponding to a plurality of pixel units arranged in the second direction. information.
  • second data information is input to each data signal line respectively.
  • the second data information includes a plurality of sub-data information.
  • the sub-data information includes: address information corresponding to each pixel unit, and the address information corresponding to the pixel unit.
  • the address information corresponds to the current signal and the pulse width modulation signal corresponding to the pixel driving chip of the pixel unit coupled to the data signal line.
  • the display substrate includes a plurality of control signal lines and a plurality of data signal lines
  • the display stage includes: inputting control information to the mth control signal line; inputting data information to each data signal line,
  • the data information includes the current signal and the pulse width modulation signal corresponding to the pixel driving chip of the pixel unit coupled to the data signal line.
  • m represents any positive integer from 1 to M
  • M is the number of all control signal lines arranged in the second direction
  • the control chip sequentially inputs control to the first to Mth control signal lines. information.
  • a display device in another aspect, includes the display substrate as described above.
  • the display substrate includes a control chip
  • the display device further includes a system circuit coupled to the control chip.
  • the system circuit is configured to provide an initial current signal to the control chip. Initial pulse width modulated signal.
  • Figure 1 is a structural diagram of a display panel provided according to some embodiments.
  • Figure 2 is a structural diagram of a pixel unit provided according to some embodiments of the present disclosure.
  • Figure 3 is another structural diagram of a pixel unit provided according to some embodiments of the present disclosure.
  • Figure 4 is another structural diagram of a pixel unit provided according to some embodiments of the present disclosure.
  • Figure 5 is another structural diagram of a pixel unit provided according to some embodiments of the present disclosure.
  • Figure 6 is another structural diagram of a pixel unit provided according to some embodiments of the present disclosure.
  • Figure 7a is a waveform diagram of a pulse width modulation signal provided according to some embodiments of the present disclosure.
  • Figure 7b is a timing diagram of the rising edge period and the falling edge period of the level in the light-emitting phase according to some embodiments of the present disclosure
  • Figure 8 is another structural diagram of a pixel unit provided according to some embodiments of the present disclosure.
  • Figure 9 is a timing diagram of a driving method of a pixel unit provided according to some embodiments of the present disclosure.
  • Figure 10 is another timing diagram of a driving method of a pixel unit provided according to some embodiments of the present disclosure.
  • Figure 11 is a structural diagram of a display substrate provided according to some embodiments of the present disclosure.
  • Figure 12 is a timing diagram of a driving method for a display substrate according to some embodiments of the present disclosure.
  • Figure 13 is another timing diagram of a driving method for a display substrate according to some embodiments of the present disclosure.
  • Figure 14 is a signal diagram of the data signal setting phase I SET provided according to some embodiments of the present disclosure.
  • Figure 15 is a graph showing the relationship between brightness and current of a light-emitting device provided according to some embodiments of the present disclosure.
  • Figure 16 is a structural diagram of a display device provided according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • Mini-LED Mini Light Emitting Diode, mini light-emitting diode
  • backlight area dimming Lical Dimming
  • PM Passive Matrix, passive matrix
  • Mini-LED is applied to PCB (Printed Circuit Board) substrate, but the size of the LED cannot be made very small, which means that the resolution of Mini-LED display products on the PCB substrate cannot be effectively improved.
  • PM driving methods at this time is due to the insufficient thickness of the copper traces of the glass-based traces and the limitation of the number of layers.
  • Multi-channel demultiplexers must be used to Reduce the number of traces. However, multi-channel demultiplexers can lead to excessive product power.
  • the row control units each include 12 row driver chips with 16CH (ie, 16 channels), and each column control unit Includes 5 constant current chips with 48CH (ie, 48 channels).
  • each row driver chip and constant current chip can be connected to the peripheral circuit through SPI (Serial Peripheral Interface, serial peripheral interface) to receive the corresponding signal.
  • SPI Serial Peripheral Interface, serial peripheral interface
  • 16 row driver chips are connected to the peripheral circuit through SPI1
  • 5 A constant current chip is connected to the peripheral circuit through SPI2.
  • the number of traces that provide scanning signals and data signals to the display panel 100' increases, requiring a large number of row control units and column control units, which increases the area and size of the circuit board.
  • the number of layers increases the cost of the display panel 100'.
  • the row control unit and column control unit use a multi-channel demultiplexer solution.
  • the current transmitted in the signal line is large, and the overall power consumption of the display panel will increase.
  • the wiring voltage drop problem also needs to be considered.
  • display panels can only be spliced. For example, two 11.9-inch display panels can be spliced into 18-inch, 36-inch, 72-inch, and 144-inch display panels. In order to ensure seamless splicing, narrow borders and borderless designs are required, which will greatly increase the complexity of the process.
  • serial peripheral interfaces SPI
  • SPI serial peripheral interfaces
  • the pixel unit 10 includes N light-emitting devices L and a pixel driving chip 2 .
  • the pixel driver chip 2 includes: a data signal terminal DATA, a power signal terminal VH and N signal channel terminals CH.
  • the data signal terminal DATA is used to receive data signals
  • the power signal terminal VH is used to receive power signals
  • the N signal channel terminals CH and The N light-emitting devices L correspond one to one.
  • the first pole of the first light-emitting device L 1 among the N light-emitting devices L is configured to be coupled with the power signal terminal VH, and the second pole of the n-th light-emitting device L n among the N light-emitting devices L is connected to the power signal terminal VH.
  • the first pole of the n+1th light-emitting device Ln +1 is coupled to the nth signal channel terminal CHn among the N signal channel terminals CH, N is a positive integer greater than 1, n is greater than or equal to 1, And a positive integer less than or equal to N, that is, N>1, 1 ⁇ n ⁇ N. That is, in the pixel unit 10 provided in the above embodiment, N light-emitting devices L are connected end to end in sequence.
  • the three light-emitting devices L may be the first light-emitting device L 1 , the second light-emitting device L 2 and the third light-emitting device L 2 respectively.
  • There are three light-emitting devices L 3 the first light-emitting device L 1 is configured to emit red light, the second light-emitting device L 2 is configured to emit green light, and the third light-emitting device L 3 is configured to emit blue light.
  • the first pole of the first light-emitting device L 1 is coupled to the power signal terminal VH to receive the power signal.
  • the second pole of the first light-emitting device L 1 is connected to the first pole of the second light-emitting device L 2
  • the second pole of the second light-emitting device L 2 is connected to the first pole of the third light-emitting device L 3 , That is to say, the three light-emitting devices L are connected in sequence.
  • the pixel driving chip 2 includes three signal channel terminals CH.
  • the three signal channel terminals are the first signal channel terminal CH 1 , the second signal channel terminal CH 2 and the third signal channel terminal CH 2 respectively.
  • the first light-emitting device L 1 The second pole of the second light-emitting device L 2 is also connected to the first signal channel terminal CH 1
  • the second pole of the second light-emitting device L 2 is also connected to the second signal channel terminal CH 2
  • the second pole of the third light-emitting device L 3 is also connected to the second signal channel terminal CH 1 .
  • the three signal channel terminals CH 3 are connected.
  • the light emitting device L is a Mini-LED or Micro-LED.
  • This disclosure uses N light-emitting devices L connected end to end, and only the first light-emitting device L 1 is connected to the power signal terminal VH to receive the power signal.
  • the second pole of each light-emitting device L is connected to a signal channel terminal CH.
  • the structure of the pixel driving chip 2 can be simplified, so that the area occupied by the pixel driving chip can be reduced, which is beneficial to achieving high resolution and high PPI (Pixels Per Inch, pixel density unit) display.
  • the pixel driving chip 2 also includes a light-emitting control circuit 21.
  • the light-emitting control circuit 21 is coupled to the N signal channel terminals CH, the power signal terminal VH, and the data signal terminal DATA.
  • the light-emitting control circuit 21 is configured to control the magnitude of the current transmitted to the N light-emitting devices L and the lighting duration of each light-emitting device L according to the brightness information of the N light-emitting devices L, so as to control the actual light emission brightness of each light-emitting device L.
  • the light-emitting control circuit 21 is connected to three signal channel terminals CH, and the data signal received by the data signal terminal DATA of the pixel driving chip 2 includes brightness information of the three light-emitting devices L. Under the control of the brightness information, the light-emitting control circuit 21 of the pixel driving chip 2 controls the current flowing through the light-emitting devices L and controls the light-emitting duration of each light-emitting device L, thereby controlling the actual light emitting brightness of the three light-emitting devices L.
  • the present disclosure can directly drive N light-emitting devices L to emit light through the pixel driving chip 2 .
  • a signal also called current amplitude
  • the luminous intensity of the light-emitting devices L has a positive correlation with the magnitude of the current, that is, the greater the current, the greater the magnitude of the current.
  • a signal for controlling the lighting duration of each light-emitting device L can also be generated based on the brightness information.
  • the actual light emission brightness of the light-emitting device L is positively correlated with the emission duration of the light-emitting device L, that is, the longer the emission duration of the light-emitting device L, the greater the actual light emission brightness of the light-emitting device L; The shorter the lighting duration of L, the smaller the actual light emission brightness of the light-emitting device L is.
  • the light-emitting control circuit 21 generates a signal for controlling the current amplitude and light-emitting duration of the light-emitting devices L according to the brightness information, so as to adjust the actual light-emitting brightness of the N light-emitting devices L.
  • the lighting control circuit 21 includes a modulation circuit 211 and a constant current source circuit 212.
  • One end of the modulation circuit 211 is coupled to the power signal terminal VH, and the other end of the modulation circuit 211 is coupled to the constant current source.
  • Circuit 212 is coupled.
  • one end of the modulation circuit 211 and the first pole of the first light-emitting device L 1 are both connected to the power signal terminal VH, and receive the power signal generated by the power signal terminal VH.
  • the other end of the modulation circuit 211 is used to receive the current generated by the constant current source circuit 212 .
  • the constant current source circuit 212 is the module with the largest area in the pixel driver chip 2, and since the three light-emitting devices L are connected end-to-end, the three light-emitting devices L can share a constant current source circuit 212, effectively reducing the The area of the pixel driving chip 2 enables the design of a smaller area pixel driving chip 2 .
  • the modulation circuit 211 includes N modulation sub-circuits B that correspond one-to-one to the N signal channel terminals CH and are connected end-to-end.
  • Each modulation sub-circuit of the N modulation sub-circuits B Circuit B includes a control end, a first end and a second end. The first end of the first modulation sub-circuit B 1 among the N modulation sub-circuits is coupled to the power signal terminal VH.
  • the n-th modulation sub-circuit among the N modulation sub-circuits The second terminal of the modulation sub-circuit B n is coupled to the first terminal of the n+1-th modulation sub-circuit B n+1 and the n-th signal channel terminal CH n among the N signal channel terminals CH.
  • the modulation circuit 211 includes three modulation sub-circuits B corresponding to the three signal channel terminals CH, which are the first modulation sub-circuit B 1 , the second modulation sub-circuit B 2 and the third modulation sub-circuit B 2 respectively.
  • Three modulation sub-circuits B 3 , the three modulation sub-circuits B are connected in sequence.
  • the first end of the first modulation sub-circuit B 1 is connected to the power signal terminal VH
  • the second end of the first modulation sub-circuit B 1 is connected to the first end of the second modulation sub-circuit B 2 and the first signal channel end CH 1 .
  • the second end of the second modulation sub-circuit B 2 is connected to the first end of the third modulation sub-circuit B 3 and the second signal channel end CH 2 .
  • the second terminal of the third modulation sub-circuit B 3 is connected to the constant current source circuit 212 and the third signal channel terminal CH 3 .
  • the n-th modulation sub-circuit B n and the n-th light-emitting device L n are connected in parallel. Since the third modulation sub-circuit B 3 is connected to the constant current source circuit 212 and the third signal channel terminal CH 3 , and the second pole of the third light emitting device L 3 is connected to the third signal channel terminal CH 3 , then the constant current source Circuit 212 is connected to the second pole of the third light emitting device L3 .
  • the constant current source circuit 212 is used to control the current in the loop where the light-emitting device L is located.
  • the first light-emitting device L 1 , the second light-emitting device L 2 and the third light-emitting device L 3 are controlled by signals with the same current magnitude, and the signals generated by their respective corresponding modulation sub-circuits B ( Under the control of the pulse width modulation signal (PWM), the first light-emitting device L 1 , the second light-emitting device L 2 and the third light-emitting device L 3 have different light-emitting durations, so that the actual light emitting brightness of different light-emitting devices L is different.
  • PWM pulse width modulation signal
  • the first modulation sub-circuit B 1 when the first modulation sub-circuit B 1 is turned on, the first light-emitting device L 1 is short-circuited and does not emit light; when the first modulation sub-circuit B 1 is turned off, the first light-emitting device L 1 can The light emission is controlled by the signal of the turn-on and turn-off duration of the first modulation sub-circuit B 1 , thereby controlling the light-emitting duration of the first light-emitting device L 1 . Under the common control of the current size signal and the light-emitting duration signal of each light-emitting device L, the actual light emitting brightness of the first light-emitting device L 1 , the second light-emitting device L 2 and the third light-emitting device L 3 is adjusted. Purpose.
  • the modulation sub-circuit B corresponding to the first light-emitting device L 1 , the second light-emitting device L 2 and the third light-emitting device L 3 respectively refers to the modulation sub-circuit B connected in parallel with the light-emitting device L, for example, the One light-emitting device L 1 corresponds to the first modulation sub-circuit B 1 , the second light-emitting device L 2 corresponds to the second modulation sub-circuit B 2 , and the third light-emitting device L 3 corresponds to the third modulation sub-circuit B 3 .
  • the pixel driver chip 2 also includes: a control signal terminal DE, a reference signal terminal GND and a voltage signal terminal VCC.
  • the control signal terminal DE is used to receive the control signal
  • the reference signal terminal GND is used to receive the control signal.
  • the reference signal, the voltage signal terminal VCC is used to receive the first voltage signal V1.
  • the constant current source circuit 212 of the light emitting control circuit 21 is also coupled to the reference signal terminal GND and the voltage signal terminal VCC.
  • control signal may include address information of each pixel unit 10
  • the reference signal may be a ground signal
  • the first voltage signal V1 is used to control the voltage of each digital module circuit inside the pixel driving chip 2.
  • the pixel driving chip 2 further includes a main processor 22 , which is coupled to the lighting control circuit 21 , the voltage signal terminal VCC, the control signal terminal DE and the data signal terminal DATA. catch.
  • the main processor 22 is configured to generate a current control signal and a plurality of pulse width modulation signals PWM according to the brightness information of the N light-emitting devices L contained in the data signal, and transmit the current control signal to the constant current source circuit 212 to Multiple pulse width modulation signals PWM are transmitted to N modulation sub-circuits in one-to-one correspondence.
  • the constant current source circuit 212 controls the size of the current transmitted to the light-emitting device L according to the current control signal.
  • the second pulse width modulation sub-signal PWMG' is used to control the on and off of the second modulation sub-circuit B2 .
  • the third pulse width modulation sub-signal PWMB' is used to control the on and off of the third modulation sub-circuit B 3 .
  • the plurality of pulse width modulation signals PWM include three pulse width modulation sub-signals, which are the first pulse width modulation sub-signal PWMR', the second pulse width modulation sub-signal PWMG' and the third pulse width modulation sub-signal PWMR'. Sub-signal PWMB'.
  • the first light-emitting device L 1 , the second light-emitting device L 2 , and the third light-emitting device L 3 enter the light-emitting stage in sequence, that is, when the first light-emitting device L 1 When entering the light-emitting phase, the control terminal Gate1 of the first modulation sub-circuit B 1 receives the first pulse width modulation sub-signal PWMR' sent by the processor 22b, the control terminal Gate2 of the second modulation sub-circuit B 2 and the third modulation sub-circuit B The control terminal Gate3 of 3 receives the effective level signal sent by the processor 22b, so that the second light-emitting device L2 and the third light-emitting device L3 are short-circuited by the second modulation sub-circuit B2 and the third modulation sub-circuit B3 respectively.
  • the effective light-emitting duration of the first light-emitting device L 1 is determined by the duty cycle of the first pulse width modulation sub-signal PWMR'; when the second light-emitting device L 2 enters the light-emitting stage, the second modulation sub-circuit B 2
  • the control terminal Gate2 receives the second pulse width modulation sub-signal PWMG' sent by the processor 22b, and the control terminal Gate1 of the first modulation sub-circuit B1 and the control terminal Gate3 of the third modulation sub-circuit B3 receive the valid pulse width modulation sub-signal PWMG' sent by the processor 22b.
  • the effective lighting duration is determined by the duty cycle of the second pulse width modulation sub-signal PWMG'; when the third light-emitting device L 3 enters the lighting stage, the control terminal Gate3 of the third modulation sub-circuit B 3 receives the third signal sent by the processor 22b.
  • the pulse width modulation sub-signal PWMB', the control terminal Gate1 of the first modulation sub-circuit B 1 and the control terminal Gate2 of the second modulation sub-circuit B 2 receive the effective level signal sent by the processor 22b, so that the first light-emitting device L 1
  • the second light-emitting device L 2 is short-circuited by the first modulation sub-circuit B 1 and the second modulation sub-circuit B 2 and does not emit light.
  • the effective light-emitting duration of the third light-emitting device L 3 is determined by the third pulse width modulation sub-signal PWMB. ' is determined by the duty cycle. In one frame of display image, the duration of the light-emitting phase of the first light-emitting device L 1 , the second light-emitting device L 2 , and the third light-emitting device L 3 may be equal or unequal.
  • the main processor 22 includes a processor 22b and a control circuit 22a.
  • the processor 22b is coupled to N modulation sub-circuits B.
  • the processor 22b is configured to generate a plurality of pulse width modulation signal PWM, and transmit multiple pulse width modulation signals PWM to N modulation sub-circuits B in one-to-one correspondence.
  • the processor 22b is also coupled to the control circuit 22a, and the control circuit 22a is coupled to the constant current source circuit 212.
  • the processor 22b is also configured to generate a first signal according to the brightness information and transmit the first signal to the control circuit 22a,
  • the control circuit 22a is configured to generate a current control signal according to the first signal and transmit the current control signal to the constant current source circuit 212.
  • the first signal generated by the processor 22b according to the brightness information includes a brightness control signal, which is a digital signal, and the control circuit 22a generates a current control signal according to the brightness control signal, and the current control signal is an analog signal. , the control circuit 22a transmits the current control signal to the constant current source circuit 212.
  • the modulation circuit 211 includes three modulation sub-circuits B, namely the first modulation sub-circuit B 1 , the second modulation sub-circuit B 2 and the third modulation sub-circuit B 3 .
  • the processor 22b generates the first pulse width modulation sub-signal PWMR', the second pulse width modulation sub-signal PWMG' and the third pulse width modulation sub-signal PWMB', the first modulation sub-circuit B 1 , the second modulation sub-circuit B 2 and
  • the third modulation sub-circuit B 3 may be controlled by the first pulse width modulation sub-signal PWMR', the second pulse width modulation sub-signal PWMG' and the third pulse width modulation sub-signal PWMB' respectively.
  • each modulation sub-circuit can be controlled by adjusting the duty cycle of each pulse width modulation sub-signal, where the duty cycle refers to the effective level duration relative to the total duration within a pulse cycle.
  • the proportion is explained below.
  • the pulse width modulation signal PWM is a square wave signal, and its cycle length is T, t is the pulse width length, which can also be said to be the effective level length, and the duty cycle It is equal to the ratio of pulse width duration t to period duration T, that is, t/T.
  • the cycle duration T of each pulse width modulation signal PWM generated and transmitted by the processor 22b is fixed, and the pulse width duration t of different pulse width modulation signals PWM can be different, that is, the duty cycle can be different, thereby realizing the pulse width. modulation.
  • the first modulation sub-circuit when the first light-emitting device L1 enters the light-emitting stage, the first modulation sub-circuit is turned off. At this time, the second modulation sub-circuit and the third modulation sub-circuit Turn on, the second light-emitting device L 2 and the third light-emitting device L 3 are short-circuited and do not emit light. If the duty ratio of the first pulse width modulation sub-signal PWM1 is small, the first light-emitting device L 1 is modulated by the first pulse width modulation sub-signal PWM1.
  • the duration of the short-circuit is short, and the first light-emitting device L 1 emits light for a longer duration, and vice versa. Therefore, by adjusting the duty cycle of the pulse width modulation signal, the on and off duration of the corresponding modulation sub-circuit can be controlled, thereby controlling the emitting duration of the light-emitting device in parallel with the modulation sub-circuit, thereby adjusting the brightness of the light-emitting device. .
  • the period when the digital level changes from low level to high level is called the rising edge period fa
  • the period when the digital level changes from high level to low level is called the falling edge. period fb.
  • the duration t fa of the rising edge period fa and the duration t fb of the falling edge period fb account for a relatively high proportion of the total duration t f1 of the high-level period f1, that is, the value of (t fa + t fb ) /t f1 is relatively large.
  • the duration t fa of the rising edge period fa and the duration t fb of the falling edge period fb account for the lowest proportion of the total duration t f2 of the high level time f2, that is, the value of (t fa +t fb )/t f2 is small,
  • the time of the light-emitting phase of the light-emitting device 1 is relatively sufficient, so that the light-emitting brightness of the light-emitting device 1 can be relatively normal.
  • the pulse width modulation signal PWM is a digital signal, which occupies S number of bits (bits) S. S determines the adjustable accuracy of the duty cycle that the pixel driver chip 2 can generate. For example, when the number of bits occupied by the pulse width modulation signal PWM When (bit)S is 10 bits, the duty cycle of the pulse width modulation signal PWM has 1024 (2 10 ) adjustable ways. The larger the number of bits occupied by the pulse width modulation signal PWM, the finer the duty cycle adjustment.
  • the number of bits of the pulse width modulation signal is S means that within the period T of a pulse width modulation signal, the minimum duration of the pulse (high level time t) is 1/2 S of the period T.
  • the main processor 22 further includes an interface circuit 22c coupled to the data signal terminal DATA, the voltage signal terminal VCC and the processor 22b.
  • the interface circuit 22c is configured to operate according to the data signal.
  • the data signal at the DATA terminal and the identification signal transmitted at the voltage signal terminal VCC generate a decoded signal required by the processor 22b, and transmit the decoded signal to the processor 22b.
  • the interface circuit 22c converts the data signal into data corresponding to the requirements, decodes the valid information and transmits it to the processor 22b.
  • the interface circuit 22c decodes the brightness information and transmits it to the processor 22b.
  • the constant current source circuit 212 includes a plurality of current output sub-circuits 23 connected in parallel.
  • the plurality of current output sub-circuits 23 are configured to output current under the control of a current control signal, providing The current is expressed as I collect .
  • the constant current source circuit 212 provides the current I collect to the loop where the N light-emitting devices L are located.
  • the current size is the current provided by the current output sub-circuit 23 of the plurality of current output sub-circuits 23 that is opened under the control of current information. The sum of.
  • each current output sub-circuit 23 there are, for example, seven current output sub-circuits 23 , including a basic current output sub-circuit 230 , a first current output sub-circuit 231 , a second current output sub-circuit 232 , and a third current output sub-circuit 233 . , the fourth current output sub-circuit 234, the fifth current output sub-circuit 235 and the sixth current output sub-circuit 236.
  • the basic current output sub-circuit 230 is not controlled by the current control signal ISET and is in a normally open state. Whether the other current output sub-circuits 231 - 236 are turned on is controlled by the current control signal ISET.
  • the current control signal ISET is represented by D[M:0]. Each bit in D[M:0] is used to control the on and off of different current output sub-circuits.
  • the number of bits of the current control signal is M+ 1, thus M+1 current output sub-circuits 23 can be controlled, and the w-th bit of the current control signal (w is 0, 1, 2, 3...M) can take the value 0 or 1.
  • the working status of the current output sub-circuit 231-236 respectively depends on the value of the w-th bit of the current control signal.
  • D[ w] represents the w-th bit of the current control signal.
  • the sixth current output sub-circuit 236 is turned on, and the current signal I' provided by the sixth current output sub-circuit 236 is 2 5 Is (32 Is); when D[4] is 1, the sixth current output sub-circuit 236 is The fifth current output sub-circuit 235 is turned on, and the current signal I' provided by the fifth current output sub-circuit 235 is 2 4 Is (16 Is).
  • Any current output sub-circuit 23 among the plurality of current output sub-circuits 23 includes: a transistor T and a constant current source device Y.
  • the control electrode of the transistor T is used to receive the value of D[w] in the current control signal.
  • the first pole is connected to the first terminal of the constant current source device Y, and the second pole of the transistor T is coupled to the second terminal of the last modulation sub-circuit B among the plurality of modulation sub-circuits B. That is to say, the transistor T
  • the second pole is connected to the second terminal of the third modulation sub-circuit B3 .
  • the second end of the constant current source device Y is used to connect to the reference signal terminal GND.
  • the current provided by the constant current source device of each current output subcircuit is fixed.
  • Each constant current source device Y can provide constant current signals I' of different amplitudes.
  • the actual light emission brightness of the light emitting device L of the pixel unit 10 has a positive correlation with the following expression:
  • D[5:0] determines which transistors in the constant current source circuit are turned on
  • Is is the current level of the constant current source circuit
  • D[5:0]*Is is the one connected to the conductive transistor.
  • the sum of the current signals I' of the constant current source device Y is the I collect provided by the constant current source circuit.
  • PWM[9:0]/2 10 represents the duty cycle of the pulse width modulation signal PWM.
  • the pixel driving chip 2 further includes a decoder 24 coupled to the voltage signal terminal VCC and the interface circuit 22c.
  • the decoder 24 is configured to operate according to the voltage signal terminal VCC.
  • the first voltage signal V1 generates an identification signal and transmits the identification signal to the interface circuit 22c.
  • the pixel driving chip 2 further includes a voltage regulator 25, which is coupled to the voltage signal terminal VCC and the processor 22b.
  • the voltage regulator 25 is configured to generate a second voltage signal according to the first voltage signal V1 of the voltage signal terminal VCC. V2, and transmits the second voltage signal V2 to the processor 22b, and the second voltage signal V2 provides an operating voltage for the processor 22b.
  • the voltage regulator 25 is also coupled to the interface circuit 22c.
  • the voltage regulator 25 is further configured to generate a third voltage signal V3 according to the first voltage signal V1 of the voltage signal terminal VCC, and transmit the third voltage signal V3 to the interface circuit 22c.
  • the third voltage signal V3 provides an operating voltage for the interface circuit 22c.
  • the pixel driving chip 2 further includes a reference reference voltage circuit 26.
  • the reference reference voltage circuit 26 is coupled to the voltage signal terminal VCC and the constant current source circuit 212.
  • the reference reference voltage circuit 26 is configured to operate according to the first voltage signal V1 of the voltage signal terminal VCC.
  • the reference reference voltage V0 is generated and transmitted to the constant current source circuit 212 .
  • modulation subcircuit B includes switching elements.
  • the modulation subcircuit B uses a transistor.
  • the transistor includes a control pole, a first pole and a second pole.
  • the control pole of the transistor is the control end of the modulation subcircuit B and is used to receive the pulse width modulation PWM signal.
  • the first pole of the transistor modulates the subcircuit.
  • the first terminal of B is used to connect the first pole of the light-emitting device L
  • the second terminal of the transistor is the second terminal of the modulation sub-circuit B, used to connect the second pole of the light-emitting device L.
  • the above-mentioned transistor may be a MOS (metal-oxide semiconductor field-effect transistor) transistor, a triode, a field-effect transistor, a thin-film transistor, or other device with switching characteristics, and is not limited here.
  • MOS metal-oxide semiconductor field-effect transistor
  • Some embodiments of the present disclosure also provide a driving method for the pixel unit 10. As shown in Figure 9, the driving method includes an address allocation stage ID SET and a display stage Display.
  • Address allocation stage ID SET The control signal terminal DE of the pixel driving chip 2 receives the control information, and the pixel driving chip 2 of the pixel unit 10 is triggered.
  • the data signal terminal DATA of the pixel driving chip 2 receives the first data information, and the first data information includes the address information IDx of the pixel driving chip 2 .
  • Display stage Display: the data signal terminal DATA of the pixel driver chip 2 receives sub-data information, which includes address information IDx and brightness information.
  • the address information IDx in this sub-data signal corresponds to the address information IDx received in the address allocation stage ID SET.
  • the brightness information includes the current signal of the pixel driving chip 2 and the pulse width modulation signal PWM.
  • Each light-emitting device L of the pixel unit 10 emits light under the control of the current signal and the pulse width modulation signal PWM.
  • the driving method includes the display stage Display: the control signal terminal DE of the pixel driving chip 2 receives control information. Pixel driver chip 2 is triggered. Furthermore, the data signal terminal DATA of the pixel unit 10 receives data information, which includes a current signal and a pulse width modulation signal PWM corresponding to the pixel unit 10. Each light-emitting device L of the pixel unit 10 responds to the current signal and pulse width modulation signal. The light is emitted under the control of signal PWM.
  • the display substrate 100 includes: a substrate 3, a plurality of pixel units 10, a plurality of power signal lines VHL and a plurality of data signal lines DATAL.
  • Each pixel unit 10 in the plurality of pixel units 10 is the pixel unit 10 as described above.
  • the plurality of pixel units 10 are disposed on one side of the substrate 3 .
  • the plurality of pixel units 10 are in an array along the first direction X and the second direction Y. Arranged, the first direction X and the second direction Y cross each other.
  • a plurality of power signal lines VHL are provided on one side of the substrate 3 .
  • One of the plurality of power signal lines VHL is connected to the power signal terminal of each pixel driving chip 2 of the pixel unit 10 arranged in the first direction X. VH coupling.
  • a plurality of data signal lines DATAL are provided on one side of the substrate 3 .
  • One of the plurality of data signal lines DATAL is connected to the data signal terminal of each pixel driving chip 2 of the pixel unit 10 arranged in the first direction X. DATA coupling.
  • first direction X may be a row direction and the second direction Y may be a column direction; or the first direction
  • first direction X is the row direction
  • second direction Y is the column direction
  • a plurality of pixel units 10 arranged along the first direction X is called a pixel unit row 10 a
  • a plurality of pixel units 10 arranged along the second direction Y is called a pixel unit column. 10b.
  • the power signal lines VHL can be arranged in parallel with the pixel unit columns 10b, and each power signal line VHL is connected to the power signal terminal VH of each pixel driving chip 2 in a row of pixel unit columns 10b.
  • the data signal lines DATAL can be arranged in parallel with the pixel unit columns 10b, and each data signal line DATAL is connected to the data signal terminal DATA of each pixel driving chip 2 in a row of pixel unit columns 10b, but the embodiment of the present disclosure is not limited to this.
  • x data signal lines DATAL there are x data signal lines DATAL, and x is a positive integer greater than or equal to 1.
  • the first data signal line DATAL is represented by DATAL1
  • the second data signal line DATAL is represented by DATAL2
  • the x-th data signal line DATAL is represented by DATALx.
  • the value of x can be the same as the number of pixel unit columns 10b.
  • the pixel unit 10 includes a control signal terminal DE, a reference signal terminal GND, and a voltage signal terminal VCC.
  • the display substrate 100 also includes: a plurality of control signal lines DEL, a plurality of reference signal lines GNDL, and a plurality of voltage signal lines VCCL.
  • a plurality of control signal lines DEL are provided on one side of the substrate 3 .
  • One control signal line DEL among the plurality of control signal lines DEL is connected to the control signal terminal of each pixel driving chip 2 of the pixel unit 10 arranged in the second direction Y. DE coupling.
  • a plurality of reference signal lines GNDL are provided on one side of the substrate 3 .
  • One of the plurality of reference signal lines GNDL is connected to the reference signal terminal of each pixel driving chip 2 of the pixel unit 10 arranged in the first direction X. GND coupling.
  • a plurality of voltage signal lines VCCL are provided on one side of the substrate 3 .
  • One voltage signal line VCCL among the plurality of voltage signal lines VCCL is connected to the voltage signal terminal of each pixel driving chip 2 of the pixel unit 10 arranged in the first direction X. VCC coupling.
  • control signal lines DEL can be arranged in parallel with the pixel unit rows 10a, and each control signal line DEL is connected to the control signal terminal DE of each pixel driving chip 2 in a row of pixel unit rows 10a.
  • y control signal lines DEL There may be y control signal lines DEL, and y is a positive integer greater than or equal to 1.
  • the first control signal line DEL is represented by DEL1
  • the second control signal line DEL is represented by DEL2
  • the y-th control signal line DEL is represented by DELy.
  • the value of y can be the same as the mesh number of the pixel unit row 10a.
  • the reference signal lines GNDL can be arranged in parallel with the pixel unit columns 10b, and each reference signal line GNDL is connected to the reference signal terminal GND of each pixel driving chip 2 in a row of pixel unit columns 10b, but the embodiment of the present disclosure is not limited to this.
  • the voltage signal lines VCCL can be arranged in parallel with the pixel unit columns 10b, and each voltage signal line VCCL is connected to the voltage signal terminal VCC of each pixel driving chip 2 in a row of pixel unit columns 10b, but the embodiment of the present disclosure is not limited to this.
  • each control signal line DEL extends along the first direction X and is arranged along the second direction Y.
  • the control signal lines DEL are located in two adjacent rows of pixel units arranged along the second direction Y. in the gap between 10.
  • Each power signal line VHL, each data signal line DATAL, each voltage signal line VCCL and each reference signal line GNDL extend along the second direction Y and are arranged along the first direction X.
  • the power signal line VHL, the data signal line DATAL, the voltage signal line The line VCCL and the reference signal line GNDL are located in a gap between two adjacent rows of pixel units 10 arranged along the first direction X.
  • control signal line DEL is located in the gap between two adjacent rows of pixel unit rows 10a, and the power signal line VHL, the data signal line DATAL, the voltage signal line VCCL and the reference signal line GNDL are located in the gap. In the gap between two adjacent rows of pixel unit columns 10b. In this way, each signal line can be more easily connected to the pixel driving chip 2 of the corresponding row of pixel units 10, which facilitates wiring and prevents crossover between signal lines.
  • the display substrate 100 provided by the present disclosure greatly reduces the number of signal lines on the substrate 3, so that there is enough space on the display substrate 100 for wiring of signal lines, which can be Increase the width of the signal line and other wiring methods to reduce the resistance of the signal line. Without increasing the thickness of the signal line, the brightness of the light emitting device L can be increased, thereby reducing the power of the display substrate 100 .
  • the display substrate 100 provided by the present disclosure also reduces the number of signal lines, thereby reducing the width of the binding area and the difficulty of binding the binding area and the signal lines.
  • the signal lines include the control signal line DEL, the power signal line VHL, the data signal line DATAL, the voltage signal line VCCL, the reference signal line GNDL, etc.
  • the display substrate 100 further includes a control chip DDIC.
  • the control chip DDIC is connected to the data signal line DATAL and the control signal line DEL.
  • the control chip DDIC is configured to provide a data signal to the data signal line DATAL. , and provides control signals to the control signal line DEL.
  • the display substrate 100 includes a display area A and a peripheral area S surrounding the display area A.
  • the pixel unit 10 is located in the display area A, and the control chip DDIC may be disposed in the peripheral area S.
  • the control chip DDIC provides a control signal to the control signal line DEL, and the control signal terminal DE of the pixel driving chip 2 connected to the corresponding control signal line DEL receives the control signal, so that the pixel driving chip 2 is triggered.
  • the control chip DDIC provides a data signal to the data signal line DATAL, and the data signal terminal DATA of the pixel driving chip 2 connected to the corresponding data signal line DATAL receives the data signal.
  • the data signal includes the address of the pixel unit 10 where the pixel driving chip 2 is located. information, as well as current signals and pulse-width modulated signals.
  • each display frame Frame of the display substrate 100 includes: a data signal setting stage I SET and a display stage Display.
  • the data signal Including current signal and pulse width modulation signal.
  • the display substrate 100 includes a plurality of pixel units 10 and a control chip DDIC.
  • Each pixel unit 10 of the plurality of pixel units 10 includes N light-emitting devices L.
  • the data signal setting phase I SET includes:
  • Step 1 The control chip DDIC receives the i-th frame image signal Txi.
  • the i-th frame image signal Txi includes: the initial current signal corresponding to the N light-emitting devices L of each pixel unit 10 in the current frame image. and the initial pulse width modulation signal, the initial current signal includes N initial current sub-signals, and the initial pulse width modulation signal includes N initial pulse width modulation sub-signals with the same bit width.
  • Step 2 The control chip DDIC processes the initial current signal to generate a current signal.
  • the current signal includes the initial current sub-signal with the largest current amplitude among the N initial current sub-signals.
  • the control chip DDIC processes the initial pulse width modulation signal to generate a pulse width modulation signal.
  • the pulse width modulation signal includes N pulse width modulation sub-signals with different bit numbers. Among them, i is a positive integer greater than or equal to 1, and N is a positive integer greater than 1.
  • the initial current signal and the initial pulse width modulation signal in the i-th frame image signal Txi sent by the system circuit 200 are both Gamma corrected signals; that is, the current signal and pulse width
  • the modulation signal is generated by the control chip DDIC based on the received Gamma-corrected initial current signal and initial pulse width modulation signal.
  • the display stage Display includes: the N light-emitting devices L of each pixel unit 10 in the plurality of pixel units 10 emit light according to the control of the corresponding current signal and the pulse width modulation signal PWM.
  • the i-th frame image signal Txi includes the initial current signal corresponding to the current frame image of the three light-emitting devices L of each pixel unit 10 in the plurality of pixel units 10 and Initial pulse width modulation signal.
  • the three light-emitting devices L are respectively the first light-emitting device L 1 , the second light-emitting device L 2 and the third light-emitting device L 3 .
  • the first light-emitting device L 1 is configured to emit red light
  • the second light-emitting device L 2 is configured to emit green light
  • the third light emitting device L 3 is configured to emit blue light.
  • the initial current signal includes three initial current sub-signals.
  • the initial current sub-signal corresponding to the first light-emitting device L 1 is RISET
  • the initial current sub-signal corresponding to the second light-emitting device L 2 is GISET
  • the initial current sub-signal corresponding to the third light-emitting device L 3 is BISET.
  • the initial pulse width modulation signal includes three initial pulse width modulation sub-signals.
  • the initial pulse width modulation sub-signal corresponding to the first light-emitting device L 1 is PWMR
  • the initial pulse width modulation sub-signal corresponding to the second light-emitting device L 2 is PWMG.
  • the initial pulse width modulation sub-signal corresponding to the third light-emitting device L 3 is PWMB.
  • the bit widths of the three initial pulse width modulation sub-signals are the same, for example, 10 bits.
  • the sum of the number of bits of the initial pulse width modulation signal and the initial current signal is equal to the number of packet bits of the data signal. For example, if the number of packet bits of the data signal is 16 bits and the number of bits of the initial current signal is 6 bits, then the number of bits of the initial pulse width modulation signal is 10 bits.
  • the current amplitudes of the initial current sub-signals of the three light-emitting devices L can be determined according to the brightness curve of the first light-emitting device L 1 , the second light-emitting device L 2 and the third light-emitting device L 3
  • the brightness difference under the 16-bit digital current signal is determined.
  • the data signal-brightness relationship diagram of the three light-emitting devices L is shown in Figure 15. Specifically, the abscissa represents the 16-bit data signal in LSB, and the ordinate represents the brightness of the light-emitting device L in Nit. It can be seen from Figure 15 that the brightness of the first light-emitting device L 1 , the second light-emitting device L 2 and the third light-emitting device L 3 all increase as the value of the data signal increases.
  • the first light-emitting device L 1 , the second light-emitting device L 2 , and the third light-emitting device L 3 are respectively modulated by a 16-bit data signal (including the bit number of the 6-bit initial current signal and the 10-bit initial pulse width).
  • the luminous brightness is not necessarily the same; in some cases, when the pixel unit presents a preset brightness white, the luminous brightness of the first light-emitting device L 1 is greater than the luminous brightness of the second light-emitting device L 2 , and the second light-emitting device L 2 The luminous brightness of L 2 is greater than the luminous brightness of the third light-emitting device L 3 , wherein the luminous brightness of the first light-emitting device L 1 is its maximum achievable brightness.
  • the value of the data signal corresponding to each light-emitting device is obtained from the intersection points A, B, and C of the light-emitting brightness of each light-emitting device and the curve.
  • the duty cycle of the 10-bit initial pulse width modulation sub-signal PWMR is 100%, and the current value corresponding to the current information carried by the initial current sub-signal RISET is 64Is ( ((2 16 -1)+1)/2 10 );
  • the duty cycle of the 10-bit initial pulse width modulation sub-signal PWMG is 100%, and the initial current sub-signal
  • the current value corresponding to the current information carried by GISET is 16Is(((2 14 -1)+1)/2 10 ); corresponding to the 10-bit initial pulse width modulation sub-signal of the 16-bit data signal of the third light-emitting device L 3
  • the duty cycle of PWMB is 100%, and the current value corresponding to the current information carried by the initial current sub-signal BISET is 8Is(((2 13 -1)+1)/2 10 ).
  • the control chip DDIC processes the initial current signal to generate a current signal.
  • the initial current sub-signal RISET has the largest current amplitude among the three. Therefore, the current value of the current signal is 64Is.
  • the control chip DDIC processes the initial pulse width modulation signal to generate a pulse width modulation signal PWM.
  • the pulse width modulation signal PWM includes three pulse width modulation sub-signals PWMR', PWMG' and PWMB' with different numbers of effective bits.
  • the first light-emitting device L 1 , the second light-emitting device L 2 and the third light-emitting device L 3 belonging to the same pixel unit share a constant current source circuit 212 , that is, where each light-emitting device L is located.
  • the current amplitudes in the loop are all 64Is, so the control chip DDIC needs to generate corresponding current sub-signals based on the current amplitudes of the initial current sub-signals corresponding to the three light-emitting devices L belonging to the same pixel unit when they are independently controlled.
  • the pulse width modulation sub-signals PWMR', PWMG' and PWMB' with different numbers of effective bits ensure that the pixel unit can present the white color of the above-mentioned preset brightness.
  • the effective bits of a 10-bit PWMR' signal are still 10 bits, that is, the duty cycle of the PWMR' signal is 1.
  • the effective bits of the 10-bit PWMG' signal are only 8 bits.
  • the highest and second highest bits of the PWMG' signal are fixedly assigned to 0, that is, the occupancy of the PWMG' signal
  • the effective bits of the 10-bit PWMB' signal are only 7 bits.
  • the number of significant bits is the number of bits in a digital signal that can be assigned a value of "0" or "1".
  • the pulse width modulation sub-signals PWMR', PWMG' and PWMB' can have different duty cycles respectively, thereby making the pixel unit appear Produce white of different brightnesses.
  • the current signal generated by the control chip DDIC in the disclosed technical solution is the initial current sub-signal with the largest current amplitude among the initial current sub-signals, so that the total output current of the control chip DDIC is greatly reduced, and the system power consumption requirement is also greatly reduced. reduce.
  • the pixel unit presents a preset brightness of white
  • the first light-emitting device L 1 requires a current of 10 mA
  • the second light-emitting device L 2 requires a current of 5 mA
  • the third light-emitting device L 3 requires a current of 6 mA
  • the pixel unit presents the same preset brightness white, and the total output current required for the three light-emitting devices L is the maximum value of the current required by the three light-emitting devices L, that is, the total output A current of 10mA can meet the requirements and can effectively reduce power consumption.
  • Gamma correction needs to be performed on the data signal (initial current signal and initial pulse width modulation signal)-brightness curve provided in Figure 15 to ensure a smooth Gamma curve to improve the contrast of the display device. Therefore, it can be understood that when the display device is working normally, the initial current signal and the initial pulse width modulation signal received by the control chip DDIC are both the initial current signal and the initial pulse width modulation signal after Gamma correction.
  • a current gear setting stage Is is also included before the data signal setting stage I SET.
  • the current gear Is can be set by the constant current source circuit 212 of the pixel driving chip 2 .
  • the current gear Is can be 2uA, 3uA, or 5uA, etc., and there is no limit here.
  • the value of the current signal I' provided by the constant current source device Y of each current output sub-circuit 23 in the constant current source circuit 212 is related to the current gear Is set by the constant current source circuit 212.
  • the DDIC generates a 6-bit current signal.
  • control chip DDIC can directly set the current gear Is and fix the current gear Is.
  • the display stage Display includes: an address allocation stage ID SET and a lighting stage Emitting.
  • the display substrate 100 includes a plurality of control signal lines DEL and a plurality of data signal lines DATAL.
  • the control chip DDIC inputs control information to each control signal line DEL in turn.
  • the control chip DDIC inputs first data information to each data signal line DATAL.
  • the first data information includes address information ID corresponding to the pixel units 10 arranged in the second direction Y. It can be understood that the first frame after the display device is powered on needs to include the address allocation phase ID SET; and other subsequent frames do not need to include the address allocation phase ID SET.
  • the control chip DDIC inputs second data information to each data signal line DATAL respectively.
  • the second data information includes a plurality of sub-data information.
  • the sub-data information includes: the address information ID corresponding to each pixel unit 10, and the address information.
  • the information ID corresponds to the current signal and the pulse width modulation signal corresponding to the pixel driving chip 2 of the pixel unit 10 coupled to the data signal line DATAL.
  • the initial current signal and the initial pulse width modulation signal in the i-th frame image signal Txi sent by the system circuit 200 are both Gamma corrected signals; that is, the current signal and pulse width
  • the modulation signal is generated by the control chip DDIC based on the received Gamma-corrected initial current signal and initial pulse width modulation signal.
  • the control signal terminal DE of each pixel driving chip 2 of a row of pixel unit rows 10 a is connected to a control signal line DEL, and the control signal terminal DE of each pixel driving chip 2 of a row of pixel unit columns 10 b is connected.
  • the data signal terminal DATA is connected to a data signal line DATAL.
  • the control chip DDIC inputs first data information to each pixel driver chip 2 in the multi-row pixel unit column 10b through multiple data signal lines DATAL, and the control chip DDIC inputs first data information to the multi-row pixels through multiple control signal lines DEL.
  • Each pixel driving chip 2 in the unit row 10a inputs control information to control the data signal terminal DATA of each pixel driving chip 2 located in the same pixel unit row 10a to simultaneously receive the first data information transmitted from different data signal lines DATAL.
  • each control chip DDIC inputs second data information to each pixel driving chip 2 in the multiple rows of pixel unit columns 10b through multiple data signal lines DATAL.
  • Each second data information includes a plurality of sub-data information.
  • each sub-data information includes y sub-data information.
  • the address information ID included in each sub-data information corresponds to the address information ID received by each pixel driver chip 2 in the address allocation stage ID SET.
  • the second data information is transmitted to each pixel driving chip 2 in the same row of pixel unit column 10b through the data signal line DATAL.
  • Each pixel driving chip 2 decodes and matches the address information IDs in the plurality of sub-data information in the second data information.
  • the light-emitting device L in the pixel unit 10 emits light according to the current signal and the pulse width modulation signal.
  • the initial current signal and the initial pulse width modulation signal in the i-th frame image signal Txi sent by the system circuit 200 are both Gamma corrected signals; that is, the current signal and pulse width
  • the modulation signal is generated by the control chip DDIC based on the received Gamma-corrected initial current signal and initial pulse width modulation signal.
  • the display substrate 100 includes a plurality of control signal lines DEL and a plurality of data signal lines DATAL, and the emitting phase Emitting includes:
  • Control information is input to the mth control signal line DEL, and data information is input to each data signal line DATAL.
  • the data information includes the current signal and pulse width corresponding to the pixel driver chip 2 of the pixel unit 10 coupled to the data signal line DATAL.
  • Modulated signal Among them, m represents any positive integer from 1 to M, M is the number of all control signal lines DEL arranged in the second direction Y, and the control chip DDIC sequentially inputs to the first to Mth control signal lines control information.
  • the light-emitting devices L of each pixel unit 10 of a row of pixel unit rows 10a emit light at the same time. From the light-emitting devices L of each pixel unit 10 of the first row of pixel unit rows 10a to the last row of pixel unit rows 10a The light-emitting devices L of each pixel unit 10 emit light row by row, forming a display frame.
  • the first control signal line DEL controls the pixel driving chip 2 of each pixel unit 10 in the first row of pixel unit row 10a.
  • the signal terminal DE inputs a control signal, and the pixel driving chip 2 of each pixel unit 10 in the first row of pixel unit row 10a is triggered.
  • each data signal line DATAL inputs data information, and each pixel unit in the first row of pixel unit row 10a
  • the data signal terminal DATA of the pixel driving chip 2 of 10 receives the data information.
  • the light-emitting device L of each pixel unit 10 in the first row of pixel unit rows 10a emits light.
  • the light-emitting devices L of each pixel unit 10 in the first row of pixel unit rows 10a to the last row of pixel unit rows 10a are sequentially completed, that is, the display of one frame of image Frame is completed.
  • the beneficial effects of the above display substrate driving method are the same as the beneficial effects of the display substrate 100 provided by the above embodiments of the present disclosure, and will not be described again here.
  • the display device 1000 includes the display substrate 100 as described above.
  • the display substrate 100 includes a control chip DDIC.
  • the display device 1000 further includes a system circuit 200 coupled to the display substrate 100.
  • the system circuit 200 is configured to provide an initial current signal and an initial pulse width modulation signal to the control chip DDIC.
  • the system circuit 200 receives the initial signal Csi related to the display screen of the i-th frame image, performs a series of processes such as rendering and decoding on the initial signal Csi to generate the i-th frame image signal Txi, and based on The first frequency outputs the i-th frame image signal Txi.
  • the control chip DDIC After the input terminal of the control chip DDIC receives the i-th frame image signal Txi at the first frequency, it performs processing to generate the i-th drive control signal, and outputs the i-th drive control signal to each pixel unit 10 through each signal line based on the second frequency.
  • Pixel driver chip 2 includes data information, power signal, control signal, reference signal and first voltage signal V1.
  • the i-th frame image signal Txi includes data transmitted in SPI format, including electrical signal information required by all pixel units 10 .

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Abstract

一种像素单元（10），包括N个发光器件（L）以及像素驱动芯片（2）。像素驱动芯片（2）包括：数据信号端（DATA）、电源信号端（VH）和N个信号通道端（CH），数据信号端（DATA）用于接收数据信号，电源信号端（VH）用于接收电源信号，N个信号通道端（CH）与N个发光器件（L）一一对应。其中，N个发光器件（L）中的第一个发光器件（L 1）的第一极被配置为与电源信号端（VH）耦接，N个发光器件（L）中的第n个发光器件（L n）的第二极与第n+1个发光器件（L n+1）的第一极以及与N个信号通道端（CH）中的第n信号通道端（CH n）耦接。N为大于1的正整数，n为大于1小于等于N的正整数。

Description

像素单元、显示基板及其驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素单元、显示基板及其驱动方法和显示装置。
背景技术
Mini-LED(Mini Light Emitting Diode，迷你发光二极管)，又名“次毫米发光二极管”，指晶粒尺寸约在100微米或以下的LED，Mini-LED是介于传统LED与Micro-LED(Micro Light Emitting Diode，微型发光二极管)之间，简单来说，是在传统LED背光基础上的改良。
发明内容
一方面，提供一种像素单元，像素单元包括N个发光器件以及像素驱动芯片。所述像素驱动芯片包括：数据信号端、电源信号端和N个信号通道端，数据信号端用于接收数据信号，电源信号端用于接收电源信号，N个信号通道端与所述N个发光器件一一对应。其中，所述N个发光器件中的第一个发光器件的第一极被配置为与所述电源信号端耦接，所述N个发光器件中的第n个发光器件的第二极与所述第n+1个发光器件的第一极以及与所述N个信号通道端中的第n信号通道端耦接。N为大于1的正整数，n为大于1或等于1，且小于或等于N的正整数。
在一些实施例中，所述像素驱动芯片还包括发光控制电路，与所述N个信号通道端、所述电源信号端、所述数据信号端耦接，所述发光控制电路被配置为，根据所述N个发光器件的亮度信息，控制传输至所述N个发光器件的电流大小和各发光器件的发光时长，以控制各发光器件的实际出光亮度。
在一些实施例中，所述发光控制电路包括：调制电路和恒流源电路，所述调制电路的一端与所述电源信号端耦接，所述调制电路的另一端与所述恒流源电路耦接。
在一些实施例中，所述调制电路包括与N个信号通道端一一对应的N个调制子电路，所述N个调制子电路的每个调制子电路包括控制端、第一端和第二端，所述N个调制子电路中的第一个调制子电路的第一端与所述电源信号端耦接，所述N个调制子电路中的第n个调制子电路的第二端与第n+1个调制子电路的第一端、以及所述N个信号通道端中的第n信号通道端耦接。
在一些实施例中，所述像素驱动芯片还包括：控制信号端、参考信号端和电压信号端，控制信号端用于接收控制信号，参考信号端用于接收参考信 号，电压信号端用于接收第一电压信号。所述发光控制电路的所述恒流源电路还与所述参考信号端及所述电压信号端耦接。
在一些实施例中，所述像素驱动芯片还包括主处理器，主处理器与所述发光控制电路、所述电压信号端、所述控制信号端和所述数据信号端耦接。所述主处理器被配置为，根据所述数据信号所包含的N个发光器件的亮度信息，生成电流控制信号和多个脉宽调制信号，并将所述电流控制信号传输至所述恒流源电路，将所述多个脉宽调制信号一一对应传输至所述N个调制子电路。
在一些实施例中，所述主处理器包括处理器和控制电路。所述处理器与所述N个调制子电路耦接，所述处理器被配置为生成多个脉宽调制信号，并将所述多个脉宽调制信号一一对应传输至所述N个调制子电路。所述处理器还与所述控制电路耦接，所述控制电路与所述恒流源电路耦接，所述处理器还被配置为，根据所述亮度信息生成第一信号，并将所述第一信号传输至所述控制电路，所述控制电路被配置为根据所述第一信号生成电流控制信号，并将所述电流控制信号传输至所述恒流源电路。
在一些实施例中，所述主处理器还包括接口电路，所述接口电路与所述数据信号端、所述电压信号端和所述处理器耦接，所述接口电路被配置为根据所述数据信号端的数据信号和所述电压信号端传输的识别信号，生成所述处理器需要的解码信号，并将所述解码信号传输至所述处理器。
在一些实施例中，所述调制子电路包括开关元件。
在一些实施例中，所述N个发光器件包括：红色发光器件、绿色发光器件，以及蓝色发光器件。
另一方面，提供一种显示基板，显示基板包括：衬底、多个像素单元、多条电源信号线和多条数据信号线。所述多个像素单元中的每个像素单元为如上所述的像素单元，所述多个像素单元设置于所述衬底一侧，多个像素单元沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向相互交叉。多条电源信号线设置于所述衬底一侧，所述多条电源信号线中的一条电源信号线与在所述第一方向上排布的多个所述像素单元的各所述像素驱动芯片的电源信号端耦接。多条数据信号线设置于所述衬底一侧，所述多条数据信号线中的一条数据信号线与在所述第一方向上排布的多个所述像素单元的各所述像素驱动芯片的所述数据信号端耦接。
在一些实施例中，所述像素单元包括控制信号端、参考信号端和电压信号端。所述显示基板还包括：多条控制信号线、多条参考信号线和多条电压 信号线。多条控制信号线设置于所述衬底一侧，所述多条控制信号线中的一条控制信号线与在所述第二方向上排布的多个所述像素单元的各所述像素驱动芯片的控制信号端耦接。多条参考信号线设置于所述衬底一侧，所述多条参考信号线中的一条参考信号线与在所述第一方向上排布的多个所述像素单元的各所述像素驱动芯片的参考信号端耦接。多条电压信号线设置于所述衬底一侧，所述多条电压信号线中的一条电压信号线与在所述第一方向上排布的多个所述像素单元的各所述像素驱动芯片的电压信号端耦接。
在一些实施例中，各所述控制信号线沿所述第一方向延伸，并沿所述第二方向排列，所述控制信号线位于沿所述第二方向上排列的相邻两排所述像素单元之间的间隙中。各所述电源信号线、各所述数据信号线、各所述电压信号线和各所述参考信号线沿所述第二方向延伸，并沿所述第一方向排列，所述电源信号线、所述数据信号线、所述电压信号线和所述参考信号线位于沿所述第一方向上排列的相邻两排所述像素单元之间的间隙中。
在一些实施例中，显示基板还包括控制芯片，所述控制芯片与所述数据信号线以及所述控制信号线连接，所述控制芯片被配置为，向所述数据信号线提供数据信号，并向所述控制信号线提供控制信号。
又一方面，提供一种显示基板的驱动方法，所述显示基板的每一个显示帧包括：数据信号设定阶段和显示阶段，所述数据信号包括电流信号和脉宽调制信号，所述显示基板包括多个像素单元和控制芯片，所述多个像素单元中的每一个像素单元包括N个发光器件。
所述数据信号设定阶段包括：所述控制芯片接收第i帧图像信号，所述第i帧图像信号包括：所述多个像素单元中的每一个像素单元的N个发光器件在当前帧图像对应的初始电流信号和初始脉宽调制信号。所述初始电流信号包括N个初始电流子信号，所述初始脉宽调制信号包括N个比特位数相同的初始脉宽调制子信号。所述数据信号设定阶段还包括：所述控制芯片将所述初始电流信号处理生成电流信号，所述电流信号包括所述N个初始电流子信号中的电流幅值最大的初始电流子信号；所述控制芯片将所述初始脉宽调制信号处理生成脉宽调制信号，所述脉宽调制信号包括N个比特位数不同的脉宽调制子信号。其中，i为大于或等于1的正整数，N为大于1的正整数。
所述显示阶段包括：所述多个像素单元中每一个像素单元的N个发光器件根据对应的所述电流信号和所述脉宽调制信号进行发光。
在一些实施例中，所述显示阶段包括：地址分配阶段和数据信号传输阶段，所述显示基板包括多条控制信号线和多条数据信号线。在所述地址分配 阶段，依次向各控制信号线输入控制信息，向各数据信号线输入第一数据信息，所述第一数据信息包括在第二方向上排布的多个像素单元对应的地址信息。在所述数据信号传输阶段，向各数据信号线分别输入第二数据信息，所述第二数据信息包括多个子数据信息，所述子数据信息包括：各像素单元对应的地址信息，以及与该地址信息对应且与该数据信号线耦接的所述像素单元的像素驱动芯片对应的所述电流信号和所述脉宽调制信号。
在一些实施例中，所述显示基板包括多条控制信号线和多条数据信号线，所述显示阶段包括：向第m条控制信号线输入控制信息；并向各数据信号线输入数据信息，所述数据信息包括与该数据信号线耦接的所述像素单元的像素驱动芯片对应的所述电流信号和所述脉宽调制信号。其中，m代表1～M中的任意一个正整数，M为在第二方向上排列的所有控制信号线的个数，且所述控制芯片向第一个至第M个控制信号线依次输入控制信息。
又一方面，提供一种显示装置，显示装置包括如上所述的显示基板。
在一些实施例中，所述的显示基板包括控制芯片，所述显示装置还包括与所述控制芯片耦接的系统电路，所述系统电路被配置为，向所述控制芯片提供初始电流信号和初始脉宽调制信号。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例所提供的显示面板的结构图；
图2为根据本公开一些实施例所提供的像素单元的结构图；
图3为根据本公开一些实施例所提供的像素单元的另一种结构图；
图4为根据本公开一些实施例所提供的像素单元的又一种结构图；
图5为根据本公开一些实施例所提供的像素单元的又一种结构图；
图6为根据本公开一些实施例所提供的像素单元的又一种结构图；
图7a为根据本公开一些实施例所提供的脉宽调制信号的波形图；
图7b为根据本公开一些实施例所提供的发光阶段中电平的上升沿时段和下降沿时段的时序图；
图8为根据本公开一些实施例所提供的像素单元的又一种结构图；
图9为根据本公开一些实施例所提供的像素单元的驱动方法的时序图；
图10为根据本公开一些实施例所提供的像素单元的驱动方法的另一种时序图；
图11为根据本公开一些实施例所提供的显示基板的结构图；
图12为根据本公开一些实施例所提供的显示基板的驱动方法的时序图；
图13为根据本公开一些实施例所提供的显示基板的驱动方法的另一种时序图；
图14为根据本公开一些实施例所提供的数据信号设定阶段I SET的信号图；
图15为根据本公开一些实施例所提供的发光器件的亮度与电流的关系曲线图；
图16为根据本公开一些实施例所提供的显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
Mini-LED(Mini Light Emitting Diode，迷你发光二极管)最初应用于背光区域调光(Local Dimming)，采用的都是PM(Passive Matrix，无源矩阵)的驱动方式。随着Mini-LED的发展，Mini-LED渐渐应用于显示产品中，在Mini-LED显示产品中沿用PM的驱动方式。
Mini-LED一方面应用于PCB(Printed Circuit Board，印刷线路板)基板，但是LED的尺寸不能做到很小，也就是说PCB基板的Mini-LED显示产品分辨率不能得到有效的提升。随着玻璃基板Mini-LED产品大量开发，此时采用PM的驱动方式一方面是迫于玻璃基走线的铜走线的厚度不足和层数的限制，必须采用多通道的解复用器以降低走线数量。但是，多通道的解复用器会导 致产品功率过高的问题。
示例性的，如图1所示，对于分辨率为80*90的显示面板100'，行控制单元每个包括12个具有16CH(即，16个通道)的行驱动芯片，列控制单元每个包括5个具有48CH(即，48个通道)的恒流芯片。例如，各个行驱动芯片和恒流芯片可以通过SPI(Serial Peripheral Interface，串行外设接口)与外围电路连接，以接收相应的信号，例如，16个行驱动芯片通过SPI1与外围电路连接，5个恒流芯片通过SPI2与外围电路连接。随着显示面板100'分辨率的增加，向显示面板100'提供扫描信号和数据信号的走线数量随之增加，从而需要大量的行控制单元和列控制单元，这样会增加线路板的面积和层数，从而增加了显示面板100'的成本。此外，行控制单元和列控制单元采用多通道的解复用器方案，信号线中传输的电流大，显示面板的整体功耗会增加，同时还需要考虑走线压降的问题，为实现大尺寸显示面板，只能采用拼接的方式，例如使用两个11.9寸显示面板拼接成18寸、36寸、72寸和144寸等尺寸的显示面板。为了保证无缝拼接，需要采用窄边框和无边框的设计，会极大提高工艺复杂度。
总之，由于采用的行驱动芯片和恒流芯片的驱动方式，需要多组串行外设接口(SPI)，当多个显示面板拼接后被整体驱动时，需要更多的SPI信号，对系统驱动压力更大，甚至需要采用多系统的方案。
基于此，如图2所示，本公开的一些实施例提供一种像素单元10，像素单元10包括N个发光器件L，以及像素驱动芯片2。像素驱动芯片2包括：数据信号端DATA、电源信号端VH和N个信号通道端CH，数据信号端DATA用于接收数据信号，电源信号端VH用于接收电源信号，N个信号通道端CH与N个发光器件L一一对应。其中，N个发光器件L中的第一个发光器件L 1的第一极被配置为与电源信号端VH耦接，N个发光器件L中的第n个发光器件L n的第二极与第n+1个发光器件L n+1的第一极以及与N个信号通道端CH中的第n信号通道端CH n耦接，N为大于1的正整数，n为大于或等于1，且小于或等于N的正整数，即N>1，1≤n≤N。即在上述实施例提供的像素单元10中，N个发光器件L依次首尾连接。
在一些示例中，再次参见图2，像素单元10包括三个发光器件L，即N＝3，三个发光器件L可以分别第一个发光器件L 1、第二个发光器件L 2和第三个发光器件L 3，第一个发光器件L 1被配置为发红光，第二个发光器件L 2被配置为发绿光，第三个发光器件L 3被配置为发蓝光。其中，第一个发光器件L 1的第一极和电源信号端VH耦接，接收电源信号。第一个发光器件L 1的第二极和 第二个发光器件L 2的第一极连接，第二个发光器件L 2的第二极和第三个发光器件L 3的第一极连接，也就是说，三个发光器件L首尾顺次连接。
像素驱动芯片2包括三个信号通道端CH，三个信号通道端分别为第一信号通道端CH 1、第二信号通道端CH 2和第三信号通道端CH 2，第一个发光器件L 1的第二极还与第一信号通道端CH 1连接，第二个发光器件L 2的第二极还与第二信号通道端CH 2连接，第三个发光器件L 3的第二极与第三信号通道端CH 3连接。
在一些示例中，发光器件L为Mini-LED或Micro-LED。
本公开采用N个发光器件L首尾依次连接，且仅通过第一个发光器件L 1与电源信号端VH连接，接收电源信号，每个发光器件L的第二极与一个信号通道端CH连接，这样可以简化像素驱动芯片2的结构，使得像素驱动芯片所占据的面积减小，有利于实现高分辨率和高PPI(Pixels Per Inch，像素密度单位)的显示。
在一些实施例中，如图3所示，像素驱动芯片2还包括发光控制电路21，发光控制电路21与N个信号通道端CH、电源信号端VH、数据信号端DATA耦接，发光控制电路21被配置为，根据N个发光器件L的亮度信息，控制传输至N个发光器件L的电流大小和各发光器件L的发光时长，以控制各发光器件L的实际出光亮度。
在一些示例中，再次参见图3，发光控制电路21与三个信号通道端CH连接，像素驱动芯片2的数据信号端DATA接收的数据信号包括三个发光器件L的亮度信息。像素驱动芯片2的发光控制电路21在亮度信息的控制下，控制流经发光器件L的电流大小并控制各发光器件L的发光时长，从而控制三个发光器件L的实际出光亮度。
本公开可以通过像素驱动芯片2直接驱动N个发光器件L发光。并且，根据亮度信息可以生成用于控制传输至N个发光器件L的电流大小的信号(也称作电流幅值)，发光器件L的发光强度与电流的大小呈正相关的关系，即电流越大，发光器件L的发光强度越大；电流越小，发光器件L的发光强度越小。根据亮度信息还可以生成用于控制各发光器件L的发光时长的信号。在电流幅值一定的情况下，发光器件L的实际出光亮度与发光器件L的发光时长呈正相关的关系，即发光器件L的发光时长越长，发光器件L的实际出光亮度越大；发光器件L的发光时长越短，发光器件L的实际出光亮度就越小。发光控制电路21根据亮度信息生成用于控制发光器件L的电流幅值和发光时长的信号，达到调整N个发光器件L的实际出光亮度的目的。
在一些实施例中，如图4所示，发光控制电路21包括调制电路211和恒流源电路212，调制电路211的一端与电源信号端VH耦接，调制电路211的另一端与恒流源电路212耦接。
示例性的，再次参见图4，调制电路211的一端及第一个发光器件L 1的第一极均与电源信号端VH连接，接收电源信号端VH产生的电源信号。调制电路211的另一端用于接收恒流源电路212产生的电流。
由于恒流源电路212是像素驱动芯片2中面积占比最大的模块，由于三个发光器件L首尾顺次连接，因此三个发光器件L可以共用一个恒流源电路212，有效的减小了像素驱动芯片2的面积，实现更小面积的像素驱动芯片2的设计。
在一些实施例中，如图5所示，调制电路211包括与N个信号通道端CH一一对应且首尾顺次连接的N个调制子电路B，N个调制子电路B的每个调制子电路B包括控制端、第一端和第二端，N个调制子电路中的第一个调制子电路B 1的第一端与电源信号端VH耦接，N个调制子电路中的第n个调制子电路B n的第二端与第n+1个调制子电路B n+1的第一端、以及N个信号通道端CH中的第n信号通道端CH n耦接。
示例性的，再次参见图5，调制电路211包括与三个信号通道端CH一一对应的三个调制子电路B，分别为第一调制子电路B 1、第二调制子电路B 2和第三调制子电路B 3，三个调制子电路B首尾顺次连接。第一调制子电路B 1的第一端与电源信号端VH连接，第一调制子电路B 1的第二端与第二调制子电路B 2的第一端及第一信号通道端CH 1连接。第二调制子电路B 2的第二端与第三调制子电路B 3的第一端及第二信号通道端CH 2连接。第三调制子电路B 3的第二端与恒流源电路212及第三信号通道端CH 3连接。
也就是说，第n调制子电路B n和第n个发光器件L n并联。由于第三调制子电路B 3与恒流源电路212及第三信号通道端CH 3连接，第三个发光器件L 3的第二极与第三信号通道端CH 3连接，那么，恒流源电路212与第三个发光器件L 3的第二极连接。恒流源电路212用于控制发光器件L所在回路中的电流。
示例性的，第一个发光器件L 1、第二个发光器件L 2和第三个发光器件L 3在相同电流大小的信号的控制下，通过各自对应的调制子电路B所生成的信号(脉宽调制信号PWM)的控制，第一个发光器件L 1、第二个发光器件L 2和第三个发光器件L 3具有不同的发光时长，使得不同的发光器件L的实际出光亮度不同。例如，在第一调制子电路B 1导通的情况下，第一个发光器件L 1 被短路而不发光；在第一调制子电路B 1截止的情况下，第一个发光器件L 1可发光，通过第一调制子电路B 1导通和截止的时长的信号的控制，从而控制第一个发光器件L 1的发光时长。在各发光器件L的电流大小的信号和发光时长的信号的共同控制下，达到调整第一个发光器件L 1、第二个发光器件L 2和第三个发光器件L 3的实际出光亮度的目的。
其中，第一个发光器件L 1、第二个发光器件L 2和第三个发光器件L 3各自对应的调制子电路B是指，与该发光器件L并联的调制子电路B，例如，第一个发光器件L 1与第一调制子电路B 1对应，第二个发光器件L 2与第二调制子电路B 2对应，第三个发光器件L 3与第三调制子电路B 3对应。
在一些实施例中，再次参见图6，像素驱动芯片2还包括：控制信号端DE、参考信号端GND和电压信号端VCC，控制信号端DE用于接收控制信号，参考信号端GND用于接收参考信号，电压信号端VCC用于接收第一电压信号V1。发光控制电路21的恒流源电路212还与参考信号端GND及电压信号端VCC耦接。
示例性的，控制信号可以包括各像素单元10的地址信息，参考信号可以为接地信号，第一电压信号V1用于控制像素驱动芯片2内部的各数字模块电路的电压，具体参见下述内容，此处不再赘述。
在一些实施例中，再次参见图3～图6，像素驱动芯片2还包括主处理器22，主处理器22与发光控制电路21、电压信号端VCC、控制信号端DE和数据信号端DATA耦接。主处理器22被配置为，根据数据信号所包含的N个发光器件L的亮度信息，生成电流控制信号和多个脉宽调制信号PWM，并将电流控制信号传输至恒流源电路212，将多个脉宽调制信号PWM一一对应传输至N个调制子电路。
示例性的，再次参见图5，恒流源电路212根据电流控制信号控制传输至发光器件L的电流大小。
用于控制第一调制子电路B 1的导通和截止。第二脉宽调制子信号PWMG’用于控制第二调制子电路B 2的导通和截止。第三脉宽调制子信号PWMB’用于控制第三调制子电路B 3的导通和截止。
结合图6和图8，多个脉宽调制信号PWM包括三个脉宽调制子信号，分别为第一脉宽调制子信号PWMR’、第二脉宽调制子信号PWMG’和第三脉宽调制子信号PWMB’。示例性的，在全彩显示的情况下，第一个发光器件L 1，第二个发光器件L 2，第三个发光器件L 3顺次进入发光阶段，即在第一个发光器件L 1进入发光阶段时，第一调制子电路B 1的控制端Gate1接收处理器22b 发送的第一脉宽调制子信号PWMR’，第二调制子电路B 2的控制端Gate2和第三调制子电路B 3的控制端Gate3接收处理器22b发送的有效电平信号，使得第二个发光器件L 2和第三个发光器件L 3分别被第二调制子电路B 2短路和第三调制子电路B 3而不发光，第一个发光器件L 1的有效发光时长由第一脉宽调制子信号PWMR’的占空比决定；第二个发光器件L 2进入发光阶段时，第二调制子电路B 2的控制端Gate2接收处理器22b发送的第二脉宽调制子信号PWMG’，第一调制子电路B 1的控制端Gate1和第三调制子电路B 3的控制端Gate3接收处理器22b发送的有效电平信号，使得第一个发光器件L 1和第三个发光器件L 3分别被第一调制子电路B 1和第三调制子电路B 3短路而不发光，第二个发光器件L 2的有效发光时长由第二脉宽调制子信号PWMG’的占空比决定；第三个发光器件L 3进入发光阶段时，第三调制子电路B 3的控制端Gate3接收处理器22b发送的第三脉宽调制子信号PWMB’，第一调制子电路B 1的控制端Gate1和第二调制子电路B 2的控制端Gate2接收处理器22b发送的有效电平信号，使得第一个发光器件L 1和第二个发光器件L 2分别被第一调制子电路B 1和第二调制子电路B 2短路而不发光，第三个发光器件L 3的有效发光时长由第三脉宽调制子信号PWMB’的占空比决定。在一帧显示图像中，第一个发光器件L 1，第二个发光器件L 2，第三个发光器件L 3的发光阶段的时长可以相等，也可以不相等。
在一些实施例中，如图6所示，主处理器22包括处理器22b和控制电路22a，处理器22b与N个调制子电路B耦接，处理器22b被配置为生成多个脉宽调制信号PWM，并将多个脉宽调制信号PWM一一对应传输至N个调制子电路B。处理器22b还与控制电路22a耦接，控制电路22a与恒流源电路212耦接，处理器22b还被配置为，根据亮度信息生成第一信号，并将第一信号传输至控制电路22a，控制电路22a被配置为根据第一信号生成电流控制信号，并将电流控制信号传输至恒流源电路212。
示例性的，再次参见图6，处理器22b根据亮度信息生成的第一信号包括亮度控制信号，亮度控制信号为数字信号，控制电路22a根据亮度控制信号生成电流控制信号，电流控制信号为模拟信号，控制电路22a将电流控制信号传输至恒流源电路212。
调制电路211包括三个调制子电路B，分别为第一调制子电路B 1、第二调制子电路B 2和第三调制子电路B 3。处理器22b生成第一脉宽调制子信号PWMR’、第二脉宽调制子信号PWMG’和第三脉宽调制子信号PWMB’，第一调制子电路B 1、第二调制子电路B 2和第三调制子电路B 3可以分别被第一脉 宽调制子信号PWMR’、第二脉宽调制子信号PWMG’和第三脉宽调制子信号PWMB’中的控制。
具体地，可以通过调节各个脉宽调制子信号的占空比，实现对各个调制子电路的导通时长的控制，其中，占空比是指在一个脉冲循环内，有效电平时长相对于总时长所占的比例，具体解释见下述内容。
关于占空比，需要说明的是，如图7a所示，脉宽调制信号PWM为方波信号，其周期时长为T，t为脉宽时长，也可以说是有效电平时长，占空比等于脉宽时长t与周期时长T的比值，即t/T。由处理器22b生成并传输的每一个脉宽调制信号PWM的周期时长T是固定的，而不同的脉宽调制信号PWM的脉宽时长t可以不同，即占空比可以不同，从而实现脉冲宽度的调制。
例如，如图6所示，在全彩显示的情况下，当第一个发光器件L 1进入发光阶段，第一调制子电路关断，此时，第二调制子电路和第三调制子电路开启，第二个发光器件L 2和第三个发光器件L 3被短路不发光，若第一脉宽调制子信号PWM1的占空比较小，则第一个发光器件L 1被第一调制子电路短路的时长较短，第一个发光器件L 1发光时长较长，反之同理。因此通过调节脉宽调制信号的占空比，能够控制对应的调制子电路的导通和截止的时长，进而控制与该调制子电路并联的发光器件的发光时长，实现对发光器件的亮度的调节。
如图7b所示，在数字电路中，数字电平从低电平变为高电平的时段叫作上升沿时段fa，数字电平从高电平变为低电平的时段叫作下降沿时段fb。例如，上升沿时段fa的时长t fa和下降沿时段fb的时长t fb在高电平时间段f1的总时长t f1中占比较高，即(t fa+t fb)/t f1值偏大，会导致发光器件1处于发光阶段的时间不足，从而出现发光器件1出光亮度偏低的问题。例如，上升沿时段fa的时长t fa和下降沿时段fb的时长t fb在高电平时间f2的总时长t f2中占比较底，即(t fa+t fb)/t f2值较小，使得发光器件1的发光阶段的时间较为充足，可以使得发光器件1的出光亮度相对正常。脉宽调制信号PWM为数字信号，其占用S个比特数(bit)S，S决定了像素驱动芯片2能够产生的占空比的可调精度，例如，当脉宽调制信号PWM占用的比特数(bit)S为10bit时，脉宽调制信号PWM的占空比具有1024(2 10)种可调方式，脉宽调制信号PWM占用的比特数越大，占空比调节越精细。
其中，脉宽调制信号比特数为S是指，在一个脉宽调制信号的周期T内，脉冲(高电平时间t)的最小时长为周期T的1/2 S。
在一些实施例中，再次参见图6，主处理器22还包括接口电路22c，接 口电路22c与数据信号端DATA、电压信号端VCC和处理器22b耦接，接口电路22c被配置为根据数据信号端DATA的数据信号和电压信号端VCC传输的识别信号，生成处理器22b需要的解码信号，并将解码信号传输至处理器22b。
也就是说，接口电路22c把数据信号转换成对应要求的数据，将有效信息解码后传输至处理器22b，例如，接口电路22c将亮度信息进行解码传输至处理器22b。
在一些示例中，如图8所示，恒流源电路212包括并联的多个电流输出子电路23，多个电流输出子电路23被配置为，在电流控制信号的控制下输出电流，提供的电流表示为I collect，恒流源电路212将电流I collect提供给N个发光器件L所在回路，电流大小为多个电流输出子电路23中受电流信息控制打开的电流输出子电路23提供的电流的加和。
如图8所示，多个电流输出子电路23例如为7个，分别为基础电流输出子电路230、第一电流输出子电路231、第二电流输出子电路232、第三电流输出子电路233、第四电流输出子电路234、第五电流输出子电路235和第六电流输出子电路236。
如图8所示，基础电流输出子电路230不受电流控制信号ISET的控制，为常开状态，其余电流输出子电路231-236是否开启受到电流控制信号ISET的控制。电流控制信号ISET用D[M:0]表示，D[M:0]中的每一位分别用于控制不同电流输出子电路的导通和截止，其中，电流控制信号的比特数为M+1，从而可以控制M+1个电流输出子电路23，电流控制信号的第w位(w为0、1、2、3.....M)均可取值0或1。以M为5为例，即w为0、1、2、3、4、5，电流输出子电路231-236的工作状态分别取决于电流控制信号的第w位的取值，以下用D[w]表示电流控制信号的第w位。例如在D[5]为1时，第六电流输出子电路236打开，第六电流输出子电路236提供的电流信号I'为2 5Is(32Is)；在D[4]为1时，第五电流输出子电路235打开，第五电流输出子电路235提供的电流信号I'为2 4Is(16Is)，在D[4]为0时，第五电流输出子电路235关闭，第五电流输出子电路235不输出电流。如果电流控制信号仅控制恒流源电路212中的第五电流输出子电路235和第六电流输出子电路236打开，那么，恒流源电路212提供的电流I collect＝32Is+16Is+Is＝49Is。其中，Is为电流档位，电流档位是恒流源电路212能够输出的最小电流单位，可以为2uA、3uA或5uA等，此处并不设限。在一些实施例中，基础电流输出子电路230中包括的恒流源器件Y 0提供的电流大小为一个电流挡位值，即为Is。
多个电流输出子电路23中的任意一个电流输出子电路23包括：晶体管T和恒流源器件Y，晶体管T的控制极用于接收电流控制信号中D[w]的取值，晶体管T的第一极与恒流源器件Y的第一端连接，晶体管T的第二极与多个调制子电路B中的最后一个调制子电路B的第二端耦接，也就是说，晶体管T的第二极与第三调制子电路B 3的第二端连接。恒流源器件Y的第二端用于与参考信号端GND连接，每个电流输出子电路的恒流源器件所能提供的电流是固定的。
当晶体管T的控制极接收的电流控制信号使得晶体管T导通时，与该晶体管T连接的恒流源器件Y的电流信号I'传输至调制子电路B的第二端。每个恒流源器件Y可以提供恒定值的电流信号I'，其大小为I'＝Is×2 w，其中，w可以选择0、1、2、3、4、5。每个恒流源器件Y可以提供不同幅值的恒定电流信号I'。D[0]控制的晶体管T导通，则与该晶体管T连接的恒流源器件Y可提供的恒定电流信号I'＝Is；D[1]控制的晶体管T导通，则与该晶体管T连接的恒流源器件Y可提供的恒定电流信号I'＝2Is；D[2]控制的晶体管T导通，则与该晶体管T连接的恒流源器件Y可提供的恒定电流信号I'＝4Is；D[3]控制的晶体管T导通，则与该晶体管T连接的恒流源器件Y可提供的恒定电流信号I'＝8Is；D[4]控制的晶体管T导通，则与该晶体管T连接的恒流源器件Y可提供的恒定电流信号I'＝16Is；D[5]控制的晶体管T导通，则与该晶体管T连接的恒流源器件Y可提供的恒定电流信号I'＝32Is。
因此，恒流源电路212提供的电流I collect大小为，恒流源电路212中导通的晶体管T连接的恒流源器件Y的电流信号I'以及基础电流输出子电路230的电流信号Is的加和。那么，恒流源电路212可输出的最大电流I collect-max＝Is+Is×(2 M+1-1)＝Is×2 M。在M为5时，所有的晶体管T均导通，恒流源电路212可提供的最大电流I collect-max＝Is+Is+2Is+4Is+8Is+16Is+32Is＝Is×2 5＝64Is，此时所有的晶体管T均导通。
示例性的，在电流控制信号ISET为6bit、脉宽调制信号为10bit的情况下，本公开提供的像素单元10的发光器件L的实际出光亮度与下述表达式具有正相关关系：
D[5:0]*Is*PWM[9:0]/2 10
上述表达式中，D[5:0]决定了恒流源电路中哪些晶体管导通，Is为恒流源电路的电流档位，D[5:0]*Is即为与导通晶体管连接的恒流源器件Y的电流信号I'的加和，即为恒流源电路提供的I collect，PWM[9:0]/2 10表示脉宽调制信号PWM的占空比。
在一些示例中，再次参见图6，像素驱动芯片2还包括译码器24，译码器24与电压信号端VCC和接口电路22c耦接，译码器24被配置为根据电压信号端VCC的第一电压信号V1生成识别信号，并将识别信号传输至接口电路22c。
像素驱动芯片2还包括稳压器25，稳压器25与电压信号端VCC和处理器22b耦接，稳压器25被配置为根据电压信号端VCC的第一电压信号V1生成第二电压信号V2，并将第二电压信号V2传输至处理器22b，第二电压信号V2为处理器22b提供工作电压。
稳压器25还与接口电路22c耦接，稳压器25还被配置为根据电压信号端VCC的第一电压信号V1生成第三电压信号V3，并将第三电压信号V3传输至接口电路22c，第三电压信号V3为接口电路22c提供工作电压。
像素驱动芯片2还包括参考基准电压电路26，参考基准电压电路26与电压信号端VCC和恒流源电路212耦接，参考基准电压电路26被配置为根据电压信号端VCC的第一电压信号V1生成参考基准电压V0，并将参考基准电压V0传输至恒流源电路212。
在一些示例中，调制子电路B包括开关元件。
例如，调制子电路B采用晶体管，晶体管包括控制极、第一极和第二极，晶体管的控制极为调制子电路B控制端，用于接收脉宽调制PWM信号，晶体管的第一极为调制子电路B的第一端，用于连接发光器件L的第一极，晶体管的第二极为调制子电路B的第二端，用于连接发光器件L的第二极。
示例性的，上述晶体管可以为MOS(金属-氧化物半导体场效应晶体管)晶体管、三极管、场效应管、薄膜晶体管等具有开关特性的器件，此处并不设限。
本公开的一些实施例还提供一种像素单元10的驱动方法，如图9所示，该驱动方法包括地址分配阶段ID SET和显示阶段Display。
地址分配阶段ID SET：像素驱动芯片2的控制信号端DE接收控制信息，该像素单元10的像素驱动芯片2被触发。像素驱动芯片2的数据信号端DATA接收第一数据信息，该第一数据信息包括该像素驱动芯片2的地址信息IDx。
显示阶段Display：像素驱动芯片2的数据信号端DATA接收子数据信息，该子数据信息包括地址信息IDx和亮度信息。该子数据信号中的地址信息IDx与地址分配阶段ID SET中所接收的地址信息IDx相对应。 亮度信息包括该像素驱动芯片2的电流信号和脉宽调制信号PWM。该像素单元10的各发光器件L在电流信号和脉宽调制信号PWM的控制下发光。
本公开的一些实施例还提供另一种像素单元10的驱动方法，如图10所示，该驱动方法包括显示阶段Display：像素驱动芯片2的控制信号端DE接收控制信息，该像素单元10的像素驱动芯片2被触发。并且，该像素单元10的数据信号端DATA接收数据信息，该数据信息包括对应该像素单元10的电流信号和脉宽调制信号PWM，该像素单元10的各发光器件L在电流信号和脉宽调制信号PWM的控制下发光。
上述像素单元的驱动方法的有益效果与本公开的上述实施例所提供的像素单元10的有益效果相同，此处不再赘述。
本公开的一些实施例还提供一种显示基板100，如图11所示，显示基板100包括：衬底3、多个像素单元10、多条电源信号线VHL和多条数据信号线DATAL。多个像素单元10中的每个像素单元10为如上所述像素单元10，多个像素单元10设置于衬底3一侧，多个像素单元10沿第一方向X和第二方向Y呈阵列排布，第一方向X和第二方向Y相互交叉。多条电源信号线VHL设置于衬底3一侧，多条电源信号线VHL中的一条电源信号线VHL与在第一方向X上排布的像素单元10的各像素驱动芯片2的电源信号端VH耦接。多条数据信号线DATAL设置于衬底3一侧，多条数据信号线DATAL中的一条数据信号线DATAL与在第一方向X上排布的像素单元10的各像素驱动芯片2的数据信号端DATA耦接。
需要说明的是，第一方向X可以为行方向，第二方向Y可以为列方向；或者，第一方向X可以为列方向，第二方向Y可以为行方向，此处不做限定。为了便于说明，在本公开实施例中，第一方向X为行方向，第二方向Y为列方向。
在一些示例中，再次参见图11，沿第一方向X排布设置的多个像素单元10称为像素单元行10a，沿第二方向Y排布设置的多个像素单元10称为像素单元列10b。电源信号线VHL可以与像素单元列10b平行设置，每一条电源信号线VHL与一排像素单元列10b中的各像素驱动芯片2的电源信号端VH连接。数据信号线DATAL可以与像素单元列10b平行设置，每一条数据信号线DATAL与一排像素单元列10b中的各像素驱动芯片2的数据信号端DATA连接，但本公开实施方式对此不作限定。
示例性的，数据信号线DATAL为x条，x为大于或等于1的正整数。第一条数据信号线DATAL表示为DATAL1，第二条数据信号线DATAL表示为DATAL2，第x条数据信号线DATAL表示为DATALx，x的取值可以与像素单元列10b的数目相同。
在一些实施例中，再次参见图11，像素单元10包括控制信号端DE、参考信号端GND和电压信号端VCC。显示基板100还包括：多条控制信号线DEL、多条参考信号线GNDL和多条电压信号线VCCL。多条控制信号线DEL设置于衬底3一侧，多条控制信号线DEL中的一条控制信号线DEL与在第二方向Y上排布的像素单元10的各像素驱动芯片2的控制信号端DE耦接。多条参考信号线GNDL设置于衬底3一侧，多条参考信号线GNDL中的一条参考信号线GNDL与在第一方向X上排布的像素单元10的各像素驱动芯片2的参考信号端GND耦接。多条电压信号线VCCL设置于衬底3一侧，多条电压信号线VCCL中的一条电压信号线VCCL与在第一方向X上排布的像素单元10的各像素驱动芯片2的电压信号端VCC耦接。
示例性的，如图11所示，控制信号线DEL可以与像素单元行10a平行设置，每一条控制信号线DEL与一排像素单元行10a中的各像素驱动芯片2的控制信号端DE连接，但本公开实施方式对此不作限定。控制信号线DEL可以为y条，y为大于或等于1的正整数。第一条控制信号线DEL表示为DEL1，第二条控制信号线DEL表示为DEL2，第y条控制信号线DEL表示为DELy，y的取值可以与像素单元行10a的目数相同。
参考信号线GNDL可以与像素单元列10b平行设置，每一条参考信号线GNDL与一排像素单元列10b中的各像素驱动芯片2的参考信号端GND连接，但本公开实施方式对此不作限定。电压信号线VCCL可以与像素单元列10b平行设置，每一条电压信号线VCCL与一排像素单元列10b中的各像素驱动芯片2的电压信号端VCC连接，但本公开实施方式对此不作限定。
在一些实施例中，再次参见图11，各控制信号线DEL沿第一方向X延伸，并沿第二方向Y排列，控制信号线DEL位于沿第二方向Y上排列的相邻两排像素单元10之间的间隙中。各电源信号线VHL、各数据信号线DATAL、各电压信号线VCCL和各参考信号线GNDL沿第二方向Y延伸，并沿第一方向X排列，电源信号线VHL、数据信号线DATAL、电压信号线VCCL和参考信号线GNDL位于沿第一方向X上排列的相邻 两排像素单元10之间的间隙中。
示例性的，如图11所示，控制信号线DEL位于相邻的两排像素单元行10a之间的间隙中，电源信号线VHL、数据信号线DATAL、电压信号线VCCL和参考信号线GNDL位于相邻的两排像素单元列10b之间的间隙中。这样，可以使各信号线更容易与对应的一排像素单元10的像素驱动芯片2实现连接，便于布线，防止信号走线之间出现交叉。
与上述PM驱动方式的显示面板100'相比，本公开提供的显示基板100大幅减小了衬底3上信号线的数量，使得显示基板100上具有足够的空间进行信号线的布线，可以通过增加信号线的宽度等布线方式，降低信号线的电阻。在不增加信号线的厚度的情况下，可以增大发光器件L的亮度，从而降低了显示基板100的功率。同时，本公开提供的显示基板100还降低了信号线的数量，进而降低绑定区域的宽度以及绑定区域和信号线的绑定难度。其中，信号线包括控制信号线DEL、电源信号线VHL、数据信号线DATAL、电压信号线VCCL和参考信号线GNDL等。
在一些实施例中，再次参见图11，显示基板100还包括控制芯片DDIC，控制芯片DDIC与数据信号线DATAL以及控制信号线DEL连接，控制芯片DDIC被配置为，向数据信号线DATAL提供数据信号，并向控制信号线DEL提供控制信号。
示例性的，如图11所示，显示基板100包括显示区A以及围绕显示区A的周边区S，像素单元10位于显示区A，控制芯片DDIC可以设置于周边区S。
控制芯片DDIC向控制信号线DEL提供控制信号，与相应的控制信号线DEL连接的像素驱动芯片2的控制信号端DE接收该控制信号，使得该像素驱动芯片2被触发。控制芯片DDIC向数据信号线DATAL提供数据信号，与相应的数据信号线DATAL连接的像素驱动芯片2的数据信号端DATA接收该数据信号，该数据信号包括像素驱动芯片2所在的像素单元10的地址信息，以及电流信号和脉宽调制信号。
上述显示基板100的有益效果与本公开的上述实施例所提供的像素单元10的有益效果相同，此处不再赘述。
本公开的一些实施例还提供一种显示基板的驱动方法，如图12和图13所示，显示基板100的每一个显示帧Frame包括：数据信号设定阶段I SET和显示阶段Display，数据信号包括电流信号和脉宽调制信号。显示基板100 包括多个像素单元10和控制芯片DDIC，多个像素单元10中的每一个像素单元10包括N个发光器件L。
如图14所示，数据信号设定阶段I SET包括：
第一步：控制芯片DDIC接收第i帧图像信号Txi，第i帧图像信号Txi包括：多个像素单元10中的每一个像素单元10的N个发光器件L在当前帧图像对应的初始电流信号和初始脉宽调制信号，初始电流信号包括N个初始电流子信号，初始脉宽调制信号包括N个位宽相同的初始脉宽调制子信号。
第二步：控制芯片DDIC将初始电流信号处理生成电流信号，电流信号包括N个初始电流子信号中的电流幅值最大的初始电流子信号。控制芯片DDIC将初始脉宽调制信号处理生成脉宽调制信号，脉宽调制信号包括N个比特数(bit)不同的脉宽调制子信号。其中，i为大于或等于1的正整数，N为大于1的正整数。可以理解的是，在显示装置正常工作时，系统电路200发送的第i帧图像信号Txi中的初始电流信号和初始脉宽调制信号，均为经过Gamma校正后的信号；即电流信号和脉宽调制信号为控制芯片DDIC根据接收到的经过Gamma校正后的初始电流信号和初始脉宽调制信号而生成。
显示阶段Display包括：多个像素单元10中每一个像素单元10的N个发光器件L根据对应的电流信号和脉宽调制信号PWM的控制进行发光。
示例性的，再次参见图14，在第一步中，第i帧图像信号Txi包括多个像素单元10中的每一个像素单元10的三个发光器件L在当前帧图像对应的初始电流信号和初始脉宽调制信号。
三个发光器件L分别第一个发光器件L 1、第二个发光器件L 2和第三个发光器件L 3，第一个发光器件L 1被配置为发红光，第二个发光器件L 2被配置为发绿光，第三个发光器件L 3被配置为发蓝光。
初始电流信号包括三个初始电流子信号。对应第一个发光器件L 1的初始电流子信号为RISET，对应第二个发光器件L 2的初始电流子信号为GISET，对应第三个发光器件L 3的初始电流子信号为BISET。
初始脉宽调制信号包括三个初始脉宽调制子信号，对应第一个发光器件L 1的初始脉宽调制子信号为PWMR，对应第二个发光器件L 2的初始脉宽调制子信号为PWMG，对应第三个发光器件L 3的初始脉宽调制子信号为PWMB。三个初始脉宽调制子信号的位宽相同，例如，均为10bit。
需要说明的是，初始脉宽调制信号和初始电流信号的比特数的加和，等于数据信号的封包比特数。例如，数据信号的封包比特数为16bit，初始电流 信号的比特数为6bit，那么，初始脉宽调制信号的比特数为10bit。
在实现全彩显示时，三个发光器件L初始电流子信号的电流幅值，可以根据亮度曲线中，第一个发光器件L 1、第二个发光器件L 2和第三个发光器件L 3在16bit的数字电流信号下的亮度差异确定，三个发光器件L的数据信号-亮度的关系图如图15。具体的，横坐标表示16bit数据信号，单位为LSB，纵坐标表示发光器件L的亮度大小，单位为Nit。从图15中可以看出，第一个发光器件L 1、第二个发光器件L 2和第三个发光器件L 3的亮度均随着数据信号的数值增大而增大。
在像素单元中的第一个发光器件L 1、第二个发光器件L 2、第三个发光器件L 3分别被16bit数据信号(包括6bit的初始电流信号的比特数和10bit的初始脉宽调制信号)独立控制的情况下，以像素单元整体呈现出预设亮度的白色为例，像素单元中的第一个发光器件L 1、第二个发光器件L 2、第三个发光器件L 3的发光亮度并不一定相同；在一些情况下，在像素单元呈现预设亮度的白色时，第一个发光器件L 1的发光亮度大于第二个发光器件L 2的发光亮度，第二个发光器件L 2的发光亮度大于第三个发光器件L 3的发光亮度，其中，第一个发光器件L 1的发光亮度为其可达到的最大亮度。
根据图15中每个发光器件的数据信号-亮度曲线，由各发光器件的发光亮度与曲线的交点A、B、C，分别得到每个发光器件对应的数据信号的值。其中，对应第一个发光器件L 1的16bit数据信号中，10bit的初始脉宽调制子信号PWMR的占空比为100％，初始电流子信号RISET所携带的电流信息对应的电流值为64Is(((2 16-1)+1)/2 10)；对应第二个发光器件L 2的16bit数据信号中，10bit的初始脉宽调制子信号PWMG的占空比为100％，初始电流子信号GISET所携带的电流信息对应的电流值为16Is(((2 14-1)+1)/2 10)；对应第三个发光器件L 3的16bit数据信号中，10bit的初始脉宽调制子信号PWMB的占空比为100％，初始电流子信号BISET所携带的电流信息对应的电流值为8Is(((2 13-1)+1)/2 10)。
在第二步中，首先，控制芯片DDIC将初始电流信号处理生成电流信号，电流信号包括三个初始电流子信号中的电流幅值最大的初始电流子信号。例如，RISET＝64Is，GISET＝16Is，BISET＝8Is，初始电流子信号RISET为三者中电流幅值最大者，因此，电流信号的电流取值为64Is。其次，控制芯片DDIC将初始脉宽调制信号处理生成脉宽调制信号PWM，脉宽调制信号PWM包括三个有效比特位位数不同的脉宽调制子信号PWMR’，PWMG’和PWMB’。由于本公开实施例中，属于同一个像素单元的第一 个发光器件L 1、第二个发光器件L 2和第三个发光器件L 3共用一个恒流源电路212，即各发光器件L所在回路中的电流幅值均为64Is，因此控制芯片DDIC需要根据，属于同一个像素单元中三个发光器件L在被独立控制的情况下所对应的初始电流子信号的电流幅值，生成分别具有不同有效比特位数目的脉宽调制子信号PWMR’，PWMG’和PWMB’，确保像素单元能够呈现出上述预设亮度的白色。例如，10bit的PWMR’信号的有效比特位仍为10bit，即PWMR’信号的占空比为1。而10bit的PWMG’信号的有效比特位仅为8bit，在第二调制子电路采用P型晶体管实现的情况下，PWMG’信号的最高位和次高位被固定赋值为0，即PWMG’信号的占空比最大为0.25(GISET/RISET＝16/64)；在第二调制子电路采用N型晶体管实现的情况下，处理器22b会将PWMG’信号的最低位和次低位被固定赋值为1，即PWMG’信号的占空比最小为0.75(1-GISET/RISET＝1-16/64)。10bit的PWMB’信号的有效比特位仅为7bit，在第三调制子电路采用P型晶体管实现的情况下，处理器22b会将PWMB’信号最高位、次高位和第三高位均被固定赋值为0，即PWMB’信号的占空比最大为0.125(BISET/RISET＝8/64)；在第三调制子电路采用N型晶体管实现的情况下，处理器22b会将PWMB’信号最低位、次低位和第三低位均被固定赋值为1，即PWMB’信号的占空比最小为0.875(1-BISET/RISET＝1-8/64)。可以理解的是，有效比特位数为数字信号中可以被赋值为“0”或“1”的位的数目。通过对脉宽调制子信号PWMR’，PWMG’和PWMB’的有效比特位分别进行赋值，脉宽调制子信号PWMR’，PWMG’和PWMB’可以分别具有不同的占空比，从而使像素单元呈现出不同亮度的白色。
本公开技术方案中的控制芯片DDIC生成的电流信号为初始电流子信号中的电流幅值最大的初始电流子信号，使得控制芯片DDIC的总的输出电流大幅度降低，系统功耗需求也大幅度降低。例如，在相关技术中，像素单元呈现预设亮度的白色，第一个发光器件L 1需要10mA电流，第二个发光器件L 2需要5mA电流，第三个发光器件L 3需要6mA电流，那么，控制芯片DDIC的总的输出电流为三个发光器件L需要的电流的总和，即总的输出电流为10mA+5mA+6mA＝21mA。而在本公开设计的技术方案中，像素单元呈现相同的预设亮度的白色，对于三个发光器件L需要的总的输出电流为三个发光器件L所需电流的最大值，即总的输出电流为10mA即可满足要求，可以有效降低功耗。
可以理解是，在一些示例中，需要针对例如图15提供的数据信号(初始 电流信号和初始脉宽调制信号)-亮度曲线，进行Gamma校正，确保得到平滑的Gamma曲线，以提高显示装置的对比度；因此，可以理解的是，在显示装置正常工作时，控制芯片DDIC接收到的初始电流信号和初始脉宽调制信号，均为经过Gamma校正后的初始电流信号和初始脉宽调制信号。
在一些示例中，在数据信号设定阶段I SET之前，还包括电流档位Is设定阶段。
再次参见图8，电流档位Is可以由像素驱动芯片2的恒流源电路212进行设定，例如，电流档位Is可以为2uA、3uA或5uA等，此处并不设限。恒流源电路212中各电流输出子电路23的恒流源器件Y提供的电流信号I'的值与恒流源电路212设定的电流档位Is有关。如上所述，DDIC生成的6bit的电流信号，每个恒流源器件Y可以提供恒定值的电流信号I'大小为I'＝Is×2 w，w为大于或等于0且小于n的正整数，因此，每个恒流源器件Y可以提供恒定值的电流信号I'大小由w和电流档位Is决定，从而决定恒流源电路212提供的I collect电流大小。
在另一些示例中，可以由控制芯片DDIC直接设定电流档位Is，将电流档位Is固定。
在一些实施例中，如图12所示，显示阶段Display包括：地址分配阶段ID SET和发光阶段Emitting，显示基板100包括多条控制信号线DEL和多条数据信号线DATAL。
在地址分配阶段ID SET，控制芯片DDIC依次向各控制信号线DEL输入控制信息。控制芯片DDIC向各数据信号线DATAL输入第一数据信息，第一数据信息包括在第二方向Y上排布的像素单元10对应的地址信息ID。可以理解的是，在显示装置上电后的第一帧，需要包括地址分配阶段ID SET；而之后的其他帧，可以不包括地址分配阶段ID SET。
在发光阶段Emitting，控制芯片DDIC向各数据信号线DATAL分别输入第二数据信息，第二数据信息包括多个子数据信息，子数据信息包括：各像素单元10对应的地址信息ID，以及与该地址信息ID对应且与该数据信号线DATAL耦接的像素单元10的像素驱动芯片2对应的电流信号和脉宽调制信号。
可以理解的是，在显示装置正常工作时，系统电路200发送的第i帧图像信号Txi中的初始电流信号和初始脉宽调制信号，均为经过Gamma校正后的信号；即电流信号和脉宽调制信号为控制芯片DDIC根据接收到的经过Gamma校正后的初始电流信号和初始脉宽调制信号而生成。
示例性的，再次参见图11和图12，一排像素单元行10a的各像素驱动芯片2的控制信号端DE与一条控制信号线DEL连接，一排像素单元列10b的各像素驱动芯片2的数据信号端DATA与一条数据信号线DATAL连接。在地址分配阶段ID SET，控制芯片DDIC通过多根数据信号线DATAL向多排像素单元列10b中各像素驱动芯片2输入第一数据信息，控制芯片DDIC通过多根控制信号线DEL向多排像素单元行10a中各像素驱动芯片2输入控制信息，以控制位于同一像素单元行10a的各像素驱动芯片2的数据信号端DATA能够同时接收来自不同数据信号线DATAL传输的第一数据信息。
在发光阶段Emitting，在各控制信号线DEL传输的控制信息的控制下，控制芯片DDIC通过多根数据信号线DATAL向多排像素单元列10b中各像素驱动芯片2输入第二数据信息。每个第二数据信息包括多个子数据信息，例如，显示基板100包括y个像素单元行10a的情况下，每个子数据信息包括y个子数据信息。每一个子数据信息中包括的地址信息ID与地址分配阶段ID SET各像素驱动芯片2接收到的地址信息ID相对应。
第二数据信息通过数据信号线DATAL传输给同一排像素单元列10b的各像素驱动芯片2，各像素驱动芯片2通过对第二数据信息中的多个子数据信息中的地址信息ID进行解码匹配，选择性的接收与在地址分配阶段ID SET接收并存储的相同地址信息ID所对应的子数据信息，获取该子数据信息中的电流信号和脉宽调制信号。像素单元10中的发光器件L根据电流信号和脉宽调制信号发光。可以理解的是，在显示装置正常工作时，系统电路200发送的第i帧图像信号Txi中的初始电流信号和初始脉宽调制信号，均为经过Gamma校正后的信号；即电流信号和脉宽调制信号为控制芯片DDIC根据接收到的经过Gamma校正后的初始电流信号和初始脉宽调制信号而生成。
在一些实施例中，如图13所示，显示基板100包括多条控制信号线DEL和多条数据信号线DATAL，发光阶段Emitting包括：
向第m条控制信号线DEL输入控制信息，并向各数据信号线DATAL输入数据信息，数据信息包括与该数据信号线DATAL耦接的像素单元10的像素驱动芯片2对应的电流信号和脉宽调制信号。其中，m代表1～M中的任意一个正整数，M为在第二方向Y上排列的所有控制信号线DEL的个数，且控制芯片DDIC向第一个至第M个控制信号线依次输入控制 信息。
示例性的，再次参见图11和图13，显示基板100包括y个像素单元行10a的情况下，在第二方向Y上排列的所有控制信号线DEL的个数为y，即M＝y。在发光阶段Emitting，一排像素单元行10a的各像素单元10的发光器件L同时进行发光，自第一排像素单元行10a的各像素单元10的发光器件L至最后一排像素单元行10a的各像素单元10的发光器件L逐行发光，则构成一个显示帧Frame。
以第一排像素单元行10a中各像素单元10的发光器件L发光为例，例如，第一条控制信号线DEL向第一排像素单元行10a中各像素单元10的像素驱动芯片2的控制信号端DE输入控制信号，第一排像素单元行10a中各像素单元10的像素驱动芯片2被触发，此时，各数据信号线DATAL输入数据信息，第一排像素单元行10a中各像素单元10的像素驱动芯片2的数据信号端DATA接收数据信息，在数据信息包括的电流信号和脉宽调制信号的控制下，第一排像素单元行10a中各像素单元10的发光器件L进行发光。
依次完成第一排像素单元行10a，至最后一排像素单元行10a的各像素单元10的发光器件L的发光，即完成一帧图像Frame的显示。
上述显示基板的驱动方法的有益效果与本公开的上述实施例所提供的显示基板100的有益效果相同，此处不再赘述。
本公开的一些实施例还提供一种显示装置1000，如图16所示，显示装置1000包括如上所述的显示基板100。显示基板100包括控制芯片DDIC，显示装置1000还包括与显示基板100耦接的系统电路200，系统电路200被配置为向控制芯片DDIC提供初始电流信号和初始脉宽调制信号。
示例性的，再次参见图16，系统电路200接收与第i帧图像的显示画面相关的初始信号Csi，对初始信号Csi进行渲染、解码等一系列处理后生成第i帧图像信号Txi，并基于第一频率将第i帧图像信号Txi输出。控制芯片DDIC的输入端以第一频率接收第i帧图像信号Txi后，在进行处理生成第i驱动控制信号，并基于第二频率将第i驱动控制信号通过各信号线输出至各像素单元10的像素驱动芯片2。驱动控制信号包括数据信息、电源信号、控制信号、参考信号及第一电压信号V1。其中，第i帧图像信号Txi包括以SPI格式传输的数据，包括了所有像素单元10所需的电信号信息。
上述显示装置1000的有益效果与本公开的上述实施例所提供的显示基板100的有益效果相同，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种像素单元，包括：N个发光器件，以及像素驱动芯片；
    所述像素驱动芯片包括：
    数据信号端，用于接收数据信号；
    电源信号端，用于接收电源信号；
    N个信号通道端，与所述N个发光器件一一对应；
    其中，所述N个发光器件中的第一个发光器件的第一极被配置为与所述电源信号端耦接，所述N个发光器件中的第n个发光器件的第二极与所述第n+1个发光器件的第一极以及与所述N个信号通道端中的第n信号通道端耦接；N为大于1的正整数，n为大于或等于1，且小于或等于N的正整数。
  2. 根据权利要求1所述的像素单元，其中，所述像素驱动芯片还包括发光控制电路，与所述N个信号通道端、所述电源信号端、所述数据信号端耦接，所述发光控制电路被配置为，根据所述N个发光器件的亮度信息，控制传输至所述N个发光器件的电流大小和各发光器件的发光时长，以控制各发光器件的实际出光亮度。
  3. 根据权利要求2所述的像素单元，其中，所述发光控制电路包括：调制电路和恒流源电路，所述调制电路的一端与所述电源信号端耦接，所述调制电路的另一端与所述恒流源电路耦接。
  4. 根据权利要求3所述的像素单元，其中，所述调制电路包括与N个信号通道端一一对应的N个调制子电路，所述N个调制子电路的每个调制子电路包括控制端、第一端和第二端，所述N个调制子电路中的第一个调制子电路的第一端与所述电源信号端耦接，所述N个调制子电路中的第n个调制子电路的第二端与第n+1个调制子电路的第一端、以及所述N个信号通道端中的第n信号通道端耦接。
  5. 根据权利要求4所述的像素单元，其中，所述像素驱动芯片还包括：
    控制信号端，用于接收控制信号；
    参考信号端，用于接收参考信号；
    电压信号端，用于接收第一电压信号；
    所述发光控制电路的所述恒流源电路还与所述参考信号端及所述电压信号端耦接。
  6. 根据权利要求5所述的像素单元，其中，所述像素驱动芯片还包括：主处理器，与所述发光控制电路、所述电压信号端、所述控制信号端和所述数据信号端耦接；
    所述主处理器被配置为，根据所述数据信号所包含的N个发光器件的亮 度信息，生成电流控制信号和多个脉宽调制信号，并将所述电流控制信号传输至所述恒流源电路，将所述多个脉宽调制信号一一对应传输至所述N个调制子电路。
  7. 根据权利要求6所述的像素单元，其中，所述主处理器包括处理器和控制电路；
    所述处理器与所述N个调制子电路耦接，所述处理器被配置为生成多个脉宽调制信号，并将所述多个脉宽调制信号一一对应传输至所述N个调制子电路；
    所述处理器还与所述控制电路耦接，所述控制电路与所述恒流源电路耦接，所述处理器还被配置为，根据所述亮度信息生成第一信号，并将所述第一信号传输至所述控制电路；所述控制电路被配置为根据所述第一信号生成电流控制信号，并将所述电流控制信号传输至所述恒流源电路。
  8. 根据权利要求7所述的像素单元，其中，所述主处理器还包括：接口电路，所述接口电路与所述数据信号端、所述电压信号端和所述处理器耦接，所述接口电路被配置为根据所述数据信号端的数据信号和所述电压信号端传输的识别信号，生成所述处理器需要的解码信号，并将所述解码信号传输至所述处理器。
  9. 根据权利要求1～8任一项所述的像素单元，其中，所述调制子电路包括开关元件。
  10. 根据权利要求1～9任一项所述的像素单元，其中，所述N个发光器件包括：红色发光器件、绿色发光器件，以及蓝色发光器件。
  11. 一种显示基板，包括：
    衬底；
    多个像素单元，所述多个像素单元中的每个像素单元为如权利要求1～10任一项所述的像素单元，设置于所述衬底一侧；多个像素单元沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向相互交叉；
    多条电源信号线，设置于所述衬底一侧，所述多条电源信号线中的一条电源信号线与在所述第一方向上排布的多个所述像素单元的各所述像素驱动芯片的电源信号端耦接；
    多条数据信号线，设置于所述衬底一侧，所述多条数据信号线中的一条数据信号线与在所述第一方向上排布的多个所述像素单元的各所述像素驱动芯片的所述数据信号端耦接。
  12. 根据权利要求11所述的显示基板，其中，所述像素单元包括控制信 号端、参考信号端和电压信号端；
    所述显示基板还包括：
    多条控制信号线，设置于所述衬底一侧，所述多条控制信号线中的一条控制信号线与在所述第二方向上排布的多个所述像素单元的各所述像素驱动芯片的控制信号端耦接；
    多条参考信号线，设置于所述衬底一侧，所述多条参考信号线中的一条参考信号线与在所述第一方向上排布的多个所述像素单元的各所述像素驱动芯片的参考信号端耦接；
    多条电压信号线，设置于所述衬底一侧，所述多条电压信号线中的一条电压信号线与在所述第一方向上排布的多个所述像素单元的各所述像素驱动芯片的电压信号端耦接。
  13. 根据权利要求12所述的显示基板，其中，
    各所述控制信号线沿所述第一方向延伸，并沿所述第二方向排列；所述控制信号线位于沿所述第二方向上排列的相邻两排所述像素单元之间的间隙中；
    各所述电源信号线、各所述数据信号线、各所述电压信号线和各所述参考信号线沿所述第二方向延伸，并沿所述第一方向排列；所述电源信号线、所述数据信号线、所述电压信号线和所述参考信号线位于沿所述第一方向上排列的相邻两排所述像素单元之间的间隙中。
  14. 根据权利要求11～13任一项所述的显示基板，其中，还包括控制芯片，所述控制芯片与所述数据信号线以及所述控制信号线连接，所述控制芯片被配置为，向所述数据信号线提供数据信号，并向所述控制信号线提供控制信号。
  15. 一种显示基板的驱动方法，所述显示基板的每一个显示帧包括：数据信号设定阶段和显示阶段，所述数据信号包括电流信号和脉宽调制信号；所述显示基板包括多个像素单元和控制芯片，所述多个像素单元中的每一个像素单元包括N个发光器件；
    所述数据信号设定阶段包括：
    所述控制芯片接收第i帧图像信号，所述第i帧图像信号包括：所述多个像素单元中的每一个像素单元的N个发光器件在当前帧图像对应的初始电流信号和初始脉宽调制信号；所述初始电流信号包括N个初始电流子信号，所述初始脉宽调制信号包括N个比特位数相同的初始脉宽调制子信号；
    所述控制芯片将所述初始电流信号处理生成电流信号，所述电流信号包 括所述N个初始电流子信号中的电流幅值最大的初始电流子信号；所述控制芯片将所述初始脉宽调制信号处理生成脉宽调制信号，所述脉宽调制信号包括N个有效比特位位数不同的脉宽调制子信号；
    其中，i为大于或等于1的正整数，N为大于1的正整数；
    所述显示阶段包括：所述多个像素单元中每一个像素单元的N个发光器件根据对应的所述电流信号和所述脉宽调制子信号进行发光。
  16. 根据权利要求15所述的显示基板的驱动方法，其中，所述显示阶段包括：地址分配阶段和数据信号传输阶段，所述显示基板包括多条控制信号线和多条数据信号线；
    在所述地址分配阶段，依次向各控制信号线输入控制信息；向各数据信号线输入第一数据信息，所述第一数据信息包括在第二方向上排布的多个像素单元对应的地址信息；
    在所述数据信号传输阶段，向各数据信号线分别输入第二数据信息；所述第二数据信息包括多个子数据信息；所述子数据信息包括：各像素单元对应的地址信息，以及与该地址信息对应且与该数据信号线耦接的所述像素单元的像素驱动芯片对应的所述电流信号和所述脉宽调制信号。
  17. 根据权利要求15所述的显示基板的驱动方法，其中，所述显示基板包括多条控制信号线和多条数据信号线，所述显示阶段包括：
    向第m条控制信号线输入控制信息；并向各数据信号线输入数据信息，所述数据信息包括与该数据信号线耦接的所述像素单元的像素驱动芯片对应的所述电流信号和所述脉宽调制信号；
    其中，m代表1～M中的任意一个正整数，M为在第二方向上排列的所有控制信号线的个数，且所述控制芯片向第一个至第M个控制信号线依次输入控制信息。
  18. 一种显示装置，包括如权利要求11～14任一项所述的显示基板。
  19. 根据权利要求18所述的显示装置，其中，所述的显示基板包括控制芯片，所述显示装置还包括与所述控制芯片耦接的系统电路，所述系统电路被配置为，向所述控制芯片提供初始电流信号和初始脉宽调制信号。
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