WO2023221943A1 - 光学设备、激光光源及制作方法 - Google Patents

光学设备、激光光源及制作方法 Download PDF

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Publication number
WO2023221943A1
WO2023221943A1 PCT/CN2023/094301 CN2023094301W WO2023221943A1 WO 2023221943 A1 WO2023221943 A1 WO 2023221943A1 CN 2023094301 W CN2023094301 W CN 2023094301W WO 2023221943 A1 WO2023221943 A1 WO 2023221943A1
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WIPO (PCT)
Prior art keywords
layer
light source
metal layer
laser light
laser
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PCT/CN2023/094301
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English (en)
French (fr)
Inventor
孟凡理
李泽源
郭威
陈江博
孟虎
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023221943A1 publication Critical patent/WO2023221943A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0261—Non-optical elements, e.g. laser driver components, heaters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/42—Arrays of surface emitting lasers
    • H01S5/423—Arrays of surface emitting lasers having a vertical cavity

Definitions

  • the present disclosure relates to the field of laser technology, and in particular, to an optical device, a laser light source and a manufacturing method.
  • VSEL Vertical-Cavity Surface-Emitting Laser
  • VCSEL Vertical-Cavity Surface-Emitting Laser
  • the purpose of this disclosure is to provide an optical device, a laser light source and a manufacturing method.
  • This disclosure realizes dynamic control of the laser light source by driving the pixel circuit of the backplane, and provides a structural basis for forming line light sources, surface light sources, dynamic scanning, etc.
  • a laser light source including:
  • a driving backplane includes a first base substrate and a driving circuit layer provided on one side of the first base substrate, where the driving circuit layer includes a plurality of pixel circuits;
  • a laser layer is provided on the side of the driving circuit layer away from the first base substrate.
  • the laser layer includes a plurality of vertical cavity surface emitting lasers.
  • the vertical cavity surface emitting lasers are in conjunction with the pixel circuit.
  • a corresponding connection, the pixel circuit is used to drive the vertical cavity surface emitting laser to emit light.
  • the driving circuit layer includes:
  • a first active layer is provided on one side of the first base substrate
  • a first insulating layer is provided on a side of the first active layer away from the first base substrate, and the first insulating layer covers the first active layer;
  • a first metal layer is provided on a side of the first insulating layer away from the first base substrate, where the first metal layer includes a gate of a transistor;
  • An interlayer dielectric layer is provided on the side of the first metal layer away from the first base substrate, and the interlayer dielectric layer covers the first metal layer;
  • a second metal layer is provided on the side of the interlayer dielectric layer away from the first base substrate.
  • the second metal layer includes a source electrode and a drain electrode of a transistor.
  • the source electrode and drain electrode of the transistor are connected to the source electrode and the drain electrode of the transistor.
  • a first passivation layer is provided on the side of the second metal layer away from the first base substrate, and the first passivation layer covers the second metal layer;
  • a first conductive layer is provided on the side of the first passivation layer away from the first base substrate.
  • the first conductive layer includes a first conductive part and a second conductive part. The first conductive part and The source or drain of the transistor is connected, and the second conductive part is used to load the power supply voltage.
  • the driving backplane further includes:
  • a plurality of conductive pillars are provided on a side of the driving circuit layer away from the first base substrate.
  • the conductive pillars include a first conductive pillar and a second conductive pillar.
  • the first conductive pillar and the first conductive pillar are The conductive part is connected, and the second conductive pillar is connected to the second conductive part.
  • the first metal layer further includes a first plate of the capacitor
  • the second metal layer further includes a second plate of the capacitor
  • the driving circuit layer further includes a second insulating layer and a third metal layer located between the first metal layer and the interlayer dielectric layer and arranged in sequence in a direction away from the first base substrate.
  • the first metal layer also includes a first plate of the capacitor
  • the third metal layer includes a second plate of the capacitor.
  • the conductive pillar includes:
  • a barrier layer is provided on the side of the first conductive layer away from the first base substrate, and the barrier layer is connected to the first conductive layer;
  • a first soldering layer is provided on a side of the barrier layer away from the first base substrate, and the first soldering layer is in contact with the barrier layer.
  • the vertical cavity surface emitting laser includes a first reflector, an oxidation confinement layer, a second active layer, a second reflector, a second substrate, and a first electrode. and a second electrode;
  • the first reflective mirror, the oxidation limiting layer, the second active layer, the second reflective mirror and the second substrate are arranged in sequence in a direction away from the first substrate, so
  • the oxidation limiting layer includes an unoxidized region and an oxidized region located on the periphery of the unoxidized region;
  • the first electrode is connected to the first reflector, the second electrode is connected to the second reflector, and the first electrode and the second electrode are connected to the driving circuit layer.
  • the laser layer further includes a plurality of spaced-apart welding pieces, and the first electrode and the second electrode are connected to the driving circuit layer through the welding pieces.
  • a thermal hole is provided in the driving backplane, and the orthographic projection of the vertical cavity surface emitting laser on the driving backplane at least partially overlaps with the thermal hole;
  • the laser light source also includes a heat dissipation layer, and the heat dissipation layer is provided on a side of the first substrate away from the laser layer;
  • the thermal conductive holes are filled with thermal conductive members, and the thermal conductive members are connected to the heat dissipation layer.
  • the driving circuit layer includes a metal layer
  • the laser light source further includes a heat dissipation element
  • the heat dissipation element is distributed in the metal layer of the driving circuit layer, and the heat dissipation element is connected to The thermally conductive parts are connected.
  • the pixel circuit includes:
  • a data writing circuit connected to the scanning signal terminal, the data signal terminal and the first node, and configured to provide the data signal from the data signal terminal to the first node under the control of the scanning signal from the scanning signal terminal;
  • a storage capacitor connected to the first node and the first supply voltage terminal and configured to store a voltage difference between the first node and the first power supply voltage terminal;
  • a driving transistor connected to the first node, the first power supply voltage terminal and a second node, and the vertical cavity surface emitting laser connected to the second node and the second power supply voltage terminal;
  • the first node is connected to a control terminal of the driving transistor, and the driving transistor is configured to output a driving current to the vertical cavity surface emitting laser under the control of the first node.
  • the data writing circuit includes a second transistor, a gate electrode of the second transistor is connected to the scan signal terminal, and a first electrode of the second transistor is connected to the scan signal terminal.
  • the data signal terminal is connected, and the second pole of the second transistor is connected to the first node.
  • the driving circuit layer includes:
  • a first active layer is provided on one side of the first base substrate, the first active layer includes a plurality of semiconductor portion groups, and the semiconductor portion group includes a first semiconductor portion and a second semiconductor portion, so The first semiconductor portion includes an active layer of the second transistor, and the second semiconductor portion includes an active layer of the driving transistor;
  • a first metal layer is provided on a side of the first active layer away from the first base substrate.
  • the first metal layer includes a gate electrode of the second transistor, a gate electrode of the driving transistor and the first plate of the storage capacitor;
  • a second metal layer is provided on a side of the first metal layer away from the first base substrate, and the second metal layer includes a second plate of the storage capacitor.
  • the driving circuit layer further includes a plurality of scan lines and a plurality of data lines.
  • the scan lines extend along the first direction and are arranged along the second direction.
  • the data lines extend along the second direction.
  • the second direction extends and is arranged along the first direction;
  • the scan lines and the data lines intersect with each other to define a plurality of pixel areas, and the semiconductor portion groups are located in the pixel areas in one-to-one correspondence;
  • the gate of the second transistor is connected to the scan line, and the first electrode region of the active layer of the second transistor is connected to the data line;
  • the scan lines are distributed in the first metal layer or the second metal layer, and the data lines are distributed in the first metal layer or the second metal layer.
  • the driving circuit layer further includes a plurality of first A power supply voltage line, the first power supply voltage line extends along the second direction and is arranged along the first direction, and the first electrode region of the active layer of the driving transistor is connected to the first power supply voltage line;
  • the first power supply voltage line is distributed in the first metal layer or the second metal layer.
  • an orthographic projection of the vertical cavity surface emitting laser on the first substrate is different from an orthographic projection of the pixel circuit on the first substrate. overlapping.
  • a method for manufacturing a laser light source including:
  • a driving backplane including a first base substrate and a driving circuit layer provided on one side of the first base substrate, where the driving circuit layer includes a plurality of pixel circuits;
  • the laser layer including a plurality of vertical cavity surface emitting lasers
  • the driving backplane and the laser layer are connected so that the vertical cavity surface emitting laser is connected to the pixel circuit in a one-to-one correspondence.
  • the pixel circuit is used to drive the vertical cavity surface emitting laser to emit light.
  • a laser light source module including a plurality of driver chips and a plurality of laser light sources as described in the first aspect, the driver chip is connected to the laser light source, and the driver chip is connected to the laser light source.
  • the laser light sources are arranged alternately.
  • an optical device including the laser light source as described in the first aspect.
  • the laser layer is located on one side of the driving backplane.
  • the driving backplane includes multiple pixel circuits.
  • the laser layer includes multiple vertical cavity surface emitting lasers.
  • the pixel circuits and the vertical cavity surface emitting lasers are one by one.
  • the pixel circuit can drive the vertical cavity surface-emitting laser to emit light.
  • the laser light source provided by the present disclosure realizes dynamic control of the laser light source by driving the pixel circuit of the backplane, and provides a structural basis for forming line light sources, surface light sources, dynamic scanning, etc.
  • Figure 1 is a schematic structural diagram of a laser light source in an exemplary embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a laser light source in another exemplary embodiment of the present disclosure.
  • Figure 3 is an equivalent circuit diagram of a pixel circuit in an exemplary embodiment of the present disclosure
  • Figure 4 is a schematic plan view of a laser light source in an exemplary embodiment of the present disclosure
  • Figure 5 is a schematic plan view of a laser light source driving backplane in another exemplary embodiment of the present disclosure
  • Figure 6 is a schematic structural diagram of a laser module in an exemplary embodiment of the present disclosure.
  • the reference symbols of the main components in the figure are as follows: 1-First substrate substrate; 20-Buffer layer; 2-Drive circuit layer; 21-Thermal via; 211-First thermal via; 2112-Second thermal via; 22-Thermal conductive member; 23-Heating component; 210- First active layer; 211-semiconductor part group; 2111-first semiconductor part; 2112-second semiconductor part; 220-first insulating layer; 230-first metal layer; 231-first metal part; 232-th Two metal parts; 240-interlayer dielectric layer; 250-second metal layer; 251-first connection part; 252-second connection part; 253-third connection part; 254-fourth connection part; PVX1-first Passivation layer; 270-second insulating layer; 280-third metal layer; 290-first conductive layer; 291-first conductive part; 292-second conductive part; PVX2-second passivation layer; 3-laser layer; 30-vertical cavity surface emitting laser; 301-first reflector
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the present disclosure.
  • a structure When a structure is "on" another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” placed on the other structure, or that the structure is “indirectly” placed on the other structure through another structure. on other structures.
  • VCSEL Vertical-cavity surface-emitting laser
  • DOE diffractive Optical Elements
  • an embodiment of the present disclosure provides a laser light source, including a driving backplane and a laser layer 3 .
  • the driving backplane includes a first base substrate 1 and a driving circuit layer 2 provided on one side of the first base substrate 1.
  • the driving circuit layer 2 includes a plurality of pixel circuits.
  • the laser layer 3 is provided on the side of the driving circuit layer 2 away from the first base substrate 1.
  • the laser layer 3 includes a plurality of vertical cavity surface emitting lasers 30.
  • the vertical cavity surface emitting lasers 30 are connected to the pixel circuits in a one-to-one correspondence.
  • the pixels The circuit is used to drive the vertical cavity surface emitting laser 30 to emit light.
  • the laser layer 3 is provided on one side of the driving backplane.
  • the driving backplane includes multiple pixel circuits.
  • the laser layer 3 includes multiple vertical cavity surface emitting lasers 30.
  • the pixel circuit and the vertical cavity surface emitting laser The lasers 30 are connected in one-to-one correspondence, and the pixel circuit can drive the vertical cavity surface emitting laser 30 to emit light.
  • the laser light source provided by the present disclosure realizes dynamic control of the laser light source by driving the pixel circuit of the backplane, and provides a structural basis for forming line light sources, surface light sources, dynamic scanning, etc.
  • the present disclosure provides a laser light source, which includes a driving backplane and a laser layer 3 provided on one side of the driving backplane.
  • the laser light source can be applied to light-curing stereolithography light sources, 3D scanning light sources, lidar, laser projection, optical communications, etc., and the disclosure is not specifically limited.
  • the driving backplane includes a first base substrate 1 and a driving circuit layer 2 provided on one side of the first base substrate 1 .
  • the laser layer 3 is provided on the side of the driving circuit layer 2 away from the first base substrate 1 .
  • the driving circuit layer 2 includes a plurality of pixel circuits, and the laser layer 3 includes a plurality of vertical cavity surface emitting lasers 30 .
  • the pixel circuit is connected to the vertical cavity surface emitting laser 30 in a one-to-one correspondence to drive the vertical cavity surface emitting laser 30 to emit light.
  • the present disclosure drives the vertical cavity surface emitting laser 30 through the pixel circuit, which helps to achieve high-speed, high-power, high-pixel density array laser emission, and can control timing, emission intensity, etc. through the pixel circuit.
  • the first base substrate 1 may be a base substrate of inorganic material or a base substrate of organic material.
  • the material of the first substrate 1 is glass material such as soda-lime glass, quartz glass, sapphire glass, etc.
  • the driving circuit layer 2 is provided on one side of the first base substrate 1 , and the driving circuit layer 2 includes a plurality of pixel circuits. Multiple pixel circuits can be arranged in an array, and the number and arrangement of the pixel circuits are not limited in this disclosure. In some embodiments, the driving circuit layer 2 may include a row of multiple pixel circuits arranged along the row direction to provide a line light source, or may include multiple pixel circuits arranged in a matrix array of multiple rows and columns to provide an area light source. .
  • the pixel circuit may include transistors and capacitors, and the number of transistors and capacitors may be set according to actual circuit requirements.
  • the pixel circuit includes a data writing circuit 61 , a driving transistor T1 and a storage capacitor C.
  • the data writing circuit 61 connects the scanning signal terminal Gate, the data signal terminal Source and the first node N1, and is configured to provide the data signal from the data signal terminal Source to the first node under the control of the scanning signal from the scanning signal terminal Gate. N1.
  • the storage capacitor C is connected to the first node N1 and the first power supply voltage terminal Vdd, and is configured to store a voltage difference between the first node N1 and the first power voltage terminal Vdd.
  • the driving transistor T1 is connected to the first node N1, the first power supply voltage terminal Vdd and the second node N2, and the vertical cavity surface emitting laser 30 is connected to the second node N2 and the second power supply voltage terminal Vss.
  • the first node N1 is connected to the control terminal of the driving transistor T1
  • the driving transistor T1 is configured to connect to the control terminal of the first node N1.
  • the driving current is output to the vertical cavity surface emitting laser 30 under control.
  • the data writing circuit 61 includes a second transistor T2.
  • the gate of the second transistor T2 is connected to the scan signal terminal Gate, and specifically can be connected to the gate driver chip.
  • the first pole of the second transistor T2 is connected to the data signal terminal Source, and specifically can be connected to a data driver chip, such as a CMOS chip.
  • the second pole of the second transistor T2 is connected to the first node N1.
  • the gate electrode and the first electrode of the second transistor T2 can also be connected to the same driver chip, which integrates a gate driver chip and a data driver chip and can provide scanning signals and data signals for the pixel circuit.
  • the second transistor T2 and the driving transistor T1 are P-type transistors.
  • the pixel circuit is a 2T1C pixel circuit, including 2 transistors and 1 capacitor.
  • nTmC indicates that a pixel circuit includes n transistors (indicated by the letter “T") and m capacitors (indicated by the letter “C").
  • the pixel circuit can also be a pixel circuit such as 7T1C, 7T2C, 6T1C or 6T2C, which is not specifically limited in this disclosure.
  • the transistors used in the embodiments of the present disclosure may also be N-type transistors. It is only necessary to refer to each pole of the selected type of transistor to the respective poles of the corresponding transistor in the embodiments of the present disclosure. Just connect it accordingly and make the corresponding voltage terminal provide the corresponding high voltage or low voltage.
  • N-type transistor its input terminal is the drain and the output terminal is the source, and its control terminal is the gate
  • P-type transistor its input terminal is the source and the output terminal is the drain, and its control terminal is the gate. pole.
  • the levels of the control signals at their control terminals are also different.
  • N-type transistor when the control signal is high level, the N-type transistor is in the on state; and when the control signal is low level, the N-type transistor is in the off state.
  • P-type transistor when the control signal is low level, the P-type transistor is in the on state; and when the control signal is high level, the P-type transistor is in the off state.
  • the driving circuit layer 2 has a multi-layer film stack structure.
  • the film layer lamination structure of the driving circuit layer 2 of the present disclosure will be exemplified below with reference to the accompanying drawings.
  • the driving circuit layer 2 includes a first active layer 210, a first insulation layer 220, a first metal layer 230, an interlayer dielectric layer 240 and a second metal layer 250.
  • the first active layer 210 is provided on one side of the first base substrate 1 .
  • the first active layer 210 may be made of conductive materials such as polysilicon or IGZO (Indium Gallium Zinc Oxide).
  • the first insulating layer 220 is provided on the side of the first active layer 210 away from the first base substrate 1 , and the first insulating layer 220 covers the first Active layer 210.
  • the material of the first insulating layer 220 may be a single film layer such as silicon nitride, silicon oxide, or aluminum oxide, or a multi-film layer formed by a combination thereof.
  • the first metal layer 230 is provided on the side of the first insulating layer 220 away from the first base substrate 1 .
  • the first metal layer 230 includes the gate electrode of the transistor.
  • the first metal layer 230 may be a single-layer or multi-layer structure. It may be made of molybdenum (Mo), copper (Cu) or other metals to form a single-layer structure, or it may be made of titanium (Ti)/aluminum/(Al)/titanium. (Ti) and other metals form a multi-layer structure, which is not specifically limited in this disclosure.
  • the interlayer dielectric layer 240 is provided on the side of the first metal layer 230 away from the first base substrate 1 , and the interlayer dielectric layer 240 covers the first metal layer 230 .
  • the second metal layer 250 is provided on the side of the interlayer dielectric layer 240 away from the first base substrate 1 .
  • the second metal layer 250 includes the source and drain of the transistor.
  • the source and drain of the transistor are in contact with the first active layer. 210 connection.
  • the second metal layer 250 can also be a single-layer or multi-layer structure. It can be made of molybdenum, copper and other metals to form a single-layer structure, or it can be made of titanium (Ti)/aluminum/(Al)/titanium (Ti), MoTiNi alloy.
  • the present disclosure does not specifically limit the multi-layer structure formed by metals such as (MTD)/copper (Cu), titanium (Ti)/copper (Cu), or indium tin oxide (ITO)/silver (Ag).
  • the capacitance in the pixel circuit may be formed by different metal layers in the driving circuit layer.
  • the first metal layer 230 further includes a first plate C1 of the capacitor
  • the second metal layer 250 further includes a second plate C2 of the capacitor.
  • the driving circuit layer 2 further includes a second insulating layer 270 and a third metal layer disposed between the first metal layer 230 and the interlayer dielectric layer 240 in a direction away from the first substrate 1 .
  • Layer 280, the first metal layer 230 also includes a first plate C1 of the capacitor
  • the third metal layer 280 includes a second plate C2 of the capacitor.
  • the capacitor may be formed by the first metal layer 230, the interlayer dielectric layer 240 and the second metal layer 250, or may be formed by the first metal layer 230, the second insulating layer 270 and the third metal layer 280.
  • the material of the third metal layer 280 may refer to the first metal layer 230 or the second metal layer 250, and will not be described in detail here.
  • the patterns of the first active layer 210, the first metal layer 230, the second metal layer 250 and the third metal layer 280 can be designed according to the specific structure of the pixel circuit.
  • the first active layer 210 includes a plurality of semiconductor portions 211 , and the semiconductor portions 211 include a first semiconductor portion 2111 and a second semiconductor portion 2112 .
  • a semiconductor part 2111 includes an active layer of the second transistor T2, and a second semiconductor part 2112 includes an active layer of the driving transistor T1.
  • the plurality of semiconductor portion groups 211 may be arranged sequentially to form rows along the first direction X, or may be arranged along the second direction X. Arrange them in sequence toward Y to form columns.
  • the first semiconductor part 2111 and the second semiconductor part 2112 may be arranged along multiple directions, or may be generally arranged along the second direction Y, which is not specifically limited in this disclosure.
  • a plurality of semiconductor component groups 211 are arranged sequentially along the first direction X to form rows, and the driving circuit layer 2 only includes one row of semiconductor component groups 211 .
  • the first semiconductor part 2111 and the second semiconductor part 2112 in 211 may be arranged along the second direction Y. As shown in FIG.
  • multiple semiconductor portion groups 211 are arranged in an array along the first direction X and the second direction Y. At this time, the first semiconductor portion 2111 and the second semiconductor portion 2111 in the single semiconductor portion group 211 The two semiconductor parts 2112 may be arranged along the angle direction between the first direction X and the second direction Y.
  • the first metal layer 230 is provided on the side of the first active layer 210 away from the first base substrate 1 .
  • the first metal layer 230 includes the gate electrode of the second transistor T2 , the gate electrode of the driving transistor T1 and the third electrode of the storage capacitor C.
  • the first metal layer 230 may include a first metal part 231 and a second metal part 232.
  • the orthographic projection of the first metal part 231 on the first base substrate 1 is the same as the first semiconductor part 2111 on the first base substrate 1.
  • the overlapping portion of the orthographic projection on 1 is the gate of the second transistor T2.
  • the orthographic projection of the second metal portion 232 on the first base substrate 1 and the orthographic projection of the second semiconductor portion 2112 on the first base substrate 1 The overlapping part is the gate of the driving transistor T1.
  • the second metal part 232 also includes a first plate C1 of the capacitor.
  • the arrangement of the first metal part 231 and the second metal part 232 can be set according to the arrangement of the first semiconductor part 2111 and the second semiconductor part 2112, and the first plate C1 of the capacitor can be located at the gate of the second transistor T2 between the gate of the driving transistor T1 or other positions, the specific disclosure does not limit this.
  • the second metal layer 250 is provided on the side of the first metal layer 230 away from the first base substrate 1 .
  • the second metal layer 250 includes the second plate C2 of the storage capacitor C.
  • the second metal layer 250 includes a first connection part 251 , a second connection part 252 , a third connection part 253 and a fourth connection part 254 .
  • the first connection portion 251 is connected to the data signal terminal Source and is connected to the first electrode region T2S in which the active layer of the second transistor T2 is exposed outside the first metal layer 230 through a via hole.
  • the second connection portion 252 connects the second electrode region T2D in which the active layer of the second transistor T2 is exposed outside the first metal layer 230 and the first plate C1 of the storage capacitor C.
  • the third connection part 253 includes the second plate C2 of the storage capacitor C, and the third connection part 253 connects the first power supply voltage terminal Vdd and the first electrode region of the active layer of the driving transistor T1 exposed outside the first metal layer 230 T1S.
  • the fourth connection portion 254 is connected to the second electrode region T1D where the active layer of the driving transistor T1 is exposed outside the first metal layer 230 .
  • the fourth connection portion 254 may be used to connect to the vertical cavity surface emitting laser 30 .
  • the first connection part 251, the second connection part 252, The arrangement of the third connection portion 253 and the fourth connection portion 254 can be adjusted according to the pattern and position of the first active layer 210, the first metal layer 230, etc., and is not specifically limited in this disclosure.
  • the storage capacitor C formed by the second metal part 232 and the second connection part 252 is located on one side of the second transistor T2 along the first direction.
  • the storage capacitor C formed by the second metal part 232 and the second connection part 252 is located on one side of the second transistor T2 along the second direction.
  • the driving circuit layer 2 also includes a plurality of scan lines GL and a plurality of data lines DL.
  • the scan lines GL extend along the first direction X and are arranged along the second direction Y.
  • the data The lines DL extend along the second direction Y and are arranged along the first direction
  • the first electrode area T2S of the active layer of the second transistor T2 is connected to the data line DL; the scan line GL is distributed in the first metal layer 230 or the second metal layer 250, and the data line DL is distributed in the first metal layer 230 or the second metal layer 250.
  • the scan line GL is distributed in the first metal layer 230
  • the data line DL is distributed in the second metal layer 250.
  • the driving circuit layer 2 also includes a plurality of first power supply voltage lines VDL.
  • the first power supply voltage lines VDL extend along the second direction Y and are arranged along the first direction X.
  • the active layer of the driving transistor T1 The first electrode region T1S is connected to the first power supply voltage line VDL; the first power supply voltage line VDL is distributed in the first metal layer 230 or the second metal layer 250 . In a specific embodiment, the first power voltage line VDL is distributed in the second metal layer 250 .
  • the first power supply voltage line VDL may be located close to the data line DL.
  • the same row of pixel circuits can be connected to the same scan line GL, and the gate of the second transistor T2 in each pixel circuit It can be connected to the scanning signal terminal Gate through the scanning line GL.
  • Pixel circuits in the same column can be connected to the same data line DL, and the second transistor T2 in each pixel circuit can be connected to the data signal terminal Source through the data line DL.
  • the gate of the second transistor T2 of each pixel circuit can be directly wired to the sector area 7 and then connected to the scanning signal terminal Gate, without the need for the above-mentioned scanning line. GL;
  • the second transistor T2 of each pixel circuit can also be directly wired to the sector area 7 and then connected to the data signal terminal Source, without the above-mentioned data line DL.
  • the orthographic projection of the vertical cavity surface emitting laser 30 on the first substrate substrate 1 does not overlap with the orthographic projection of the pixel circuit on the first substrate substrate 1 . Specifically, the orthographic projection of the vertical cavity surface emitting laser 30 on the first substrate substrate 1 does not overlap with the orthographic projections of the driving transistor T1 , the second transistor T2 and the storage capacitor C on the first substrate substrate 1 . This setting helps dissipate heat from the laser light source.
  • the driving circuit layer 2 further includes a first passivation layer PVX1 and a first conductive layer 290 .
  • the first passivation layer PVX1 is provided on the side of the second metal layer 250 away from the first base substrate 1 , and the first passivation layer PVX1 covers the second metal layer 250 .
  • the material of the first passivation layer PVX1 can be silicon nitride and other materials, and its thickness can be
  • the first conductive layer 290 is provided on the side of the first passivation layer PVX1 away from the first base substrate 1 .
  • the first conductive layer 290 can be a single-layer or multi-layer structure.
  • the first conductive layer 290 includes a first conductive part 291 and a second conductive part 292.
  • the first conductive part 291 is connected to the source or drain of the transistor. Specifically, the first conductive part 291 may be connected to the second metal layer 250 through a via hole.
  • the second conductive portion 292 may be used to load a power supply voltage, such as a second power supply voltage.
  • the driving backplane further includes a plurality of conductive pillars 4, which are provided on the side of the driving circuit layer 2 away from the first substrate substrate 1.
  • the conductive pillars 4 include first conductive pillars 41 and second conductive pillars. 42.
  • the first conductive pillar 41 is connected to the first conductive part 291, and the second conductive pillar 42 is connected to the second conductive part 292.
  • the first conductive pillar 41 and the second conductive pillar 42 are used to connect the vertical cavity surface emitting laser 30 .
  • the conductive pillar 4 may be a multi-layer structure.
  • the conductive pillar 4 includes a barrier layer 43 and a first welding layer 44 .
  • the barrier layer 43 is disposed on the first conductive layer 290 away from the first base substrate 1 On one side, the barrier layer 43 is connected to the first conductive layer 290 .
  • the first soldering layer 44 is provided on the side of the barrier layer 43 away from the first base substrate 1 , and the first soldering layer 44 is in contact with the barrier layer 43 .
  • the barrier layer 43 can be a single-layer film or a multi-layer film structure.
  • the conductive pillar 4 can be formed by electroplating or a lift-off process. The specific manufacturing process can be performed with reference to existing process steps, which will not be described in detail here.
  • the driving circuit layer 2 also includes a second passivation layer PVX2 and a buffer layer 20 .
  • the second passivation layer PVX2 is provided on the first conductive layer 290 and the plurality of conductive pillars 4 between.
  • the material of the second passivation layer PVX2 can be silicon nitride and other materials, and its thickness can be
  • the plurality of conductive pillars 4 may be connected to the first conductive layer 290 through via holes.
  • the buffer layer 20 is provided between the first base substrate 1 and the driving circuit layer 2 .
  • the vertical cavity surface emitting laser 30 includes a first reflective mirror 301 , an oxidation confinement layer 302 , a second active layer 303 , a second reflective mirror 304 , and a first reflective mirror 301 .
  • the first reflective mirror 301, the oxidation limiting layer 302, the second active layer 303, the second reflective mirror 304 and the second base substrate 305 are arranged in sequence in the direction away from the first base substrate 1.
  • the first reflector 301 and the second reflector 304 can be distributed Bragg reflectors, which are formed by alternately stacking two materials with different refractive indexes.
  • the first reflective mirror 301 and the second reflective mirror 304 can generate strong reflected light at a certain wavelength, and the light is reflected between the first reflective mirror 301 and the second reflective mirror 304 to form a vertical cavity.
  • Both the first reflecting mirror 301 and the second reflecting mirror 304 have a high refractive index, wherein the refractive index of the first reflecting mirror 301 can be close to 100% to serve as a total reflection mirror of the resonant cavity.
  • the second reflecting mirror 304 may have a relatively low refractive index and serve as an exit mirror of the resonant cavity.
  • the second active layer 303 is an important component of the vertical cavity surface emitting laser 30, and it may adopt a quantum well structure.
  • the oxidation limiting layer 302 includes an unoxidized region 022 and an oxidized region 021 located at the periphery of the unoxidized region 022 .
  • the oxidation limitation layer 302 can be made of an aluminum gallium arsenide (AlGaAs) layer with a high aluminum composition and oxidized from the side periphery toward the center of the layer to form the oxidation limitation layer 302 having an oxidized region 021 and an unoxidized region 022 .
  • AlGaAs aluminum gallium arsenide
  • the refractive index of the oxidized region 021 of the oxidation confinement layer 302 is low, which can confine light in the unoxidized region 022 surrounded by the oxidized region 021 .
  • the second substrate 305 may be a GaAs substrate.
  • the second base substrate 305 has a groove 051 opening in a direction away from the first base substrate 1 , and the orthogonal projection of the groove 051 on the first base substrate 1 is consistent with the oxidation limiting layer 302 The orthographic projections of the non-oxidized regions 021 on the first substrate 1 at least partially overlap.
  • the groove 051 may correspond to a laser exit port.
  • the first electrode 306 is connected to the first reflector 301, and the second electrode 307 is connected to the second reflector 304. are connected, and the first electrode 306 and the second electrode 307 are connected to the driving circuit layer 2 .
  • Current may be injected into the vertical cavity surface emitting laser 30 through the first electrode 306 and the second electrode 307 .
  • the vertical cavity surface emitting laser 30 further includes an insulating film 308.
  • An insulating film 308 is provided between the first electrode 306 and the oxidation limiting layer 302, the second active layer 303 and the second reflecting mirror 304.
  • An insulating film 308 is provided between the second electrode 307 and the oxidation limiting layer 302, the second active layer 303 and the first reflecting mirror 301.
  • the laser layer 3 further includes a plurality of spaced-apart welding members 32 , and the first electrode 306 and the second electrode 307 are connected to the driving circuit layer 2 through the welding members 32 .
  • the welding member 32 may be located between the first electrode 306 and the first welding layer 44, or between the second electrode 307 and the first welding layer 44.
  • the material of the welding piece 32 can be metal materials such as indium (In), gold (Au), tin (Sn), etc.
  • the vertical cavity surface emitting laser 30 of the present disclosure and the driving circuit layer 2 can be connected through eutectic welding.
  • the welding process of eutectic welding refers to melting the contact surface between the welding piece 32 and the first welding layer 44 under a certain temperature and a certain pressure, forming a liquid phase from two solid phases, and then, Cooling, when the temperature is lower than the eutectic point of the two, the crystal grains formed by the liquid phase combine with each other to form a mechanical mixture, that is, the welding piece 32 - the first welding layer 44 eutectic crystals, such as gold-indium eutectic crystals, thereby making
  • the vertical cavity surface emitting laser 30 is firmly welded to the driving backplane and forms a good low-resistance ohmic contact.
  • the vertical cavity surface emitting laser 30 can be bonded to the driving backplane through mass transfer technology, and the vertical cavity surface emitting laser 30 can be bonded to the driving backplane in stages through steps such as picking up, transferring, and binding. board, or the wafer containing the vertical cavity surface emitting laser 30 can be bonded to the driving backplane at one time.
  • the specific bonding method is not limited in this disclosure. When wafers are bonded once, the gold-gold eutectic welding method can be used to improve the flatness of the bonding.
  • the driving backplane is provided with thermal holes 21, and the orthographic projection of the vertical cavity surface emitting laser 30 on the driving backplane is consistent with the heat conduction
  • the holes 21 at least partially overlap;
  • the laser light source also includes a heat dissipation layer 5, which is provided on the side of the first substrate 1 away from the laser layer 3;
  • the thermal hole 21 is filled with a thermal conductive member 22, and the thermal conductive member 22 and the heat dissipation layer 5 connect.
  • the arrangement of the thermal hole 21 and the heat dissipation layer 5 can improve the heat dissipation capability of the device, wherein the thermal conductive member 22 in the thermal hole 21 can conduct the heat generated by the vertical cavity surface emitting laser 30 to the heat dissipation layer 5. And dissipate heat to the outside through the heat dissipation layer 5 environment to improve the heat dissipation performance of the device.
  • the material of the heat dissipation layer 5 can be a metal material with good heat dissipation properties, such as copper.
  • the material of the thermal conductive member 22 can also be made of metal, which is not specifically limited in this disclosure.
  • the thermal via 21 may be disposed facing the vertical cavity surface emitting laser 30 in a direction perpendicular to the first substrate substrate 1 .
  • the thermal hole 21 may or may not penetrate the driving backplane.
  • the thermal hole 21 is opened on the side of the first substrate 1 away from the laser layer 3 to facilitate the connection between the thermal conductive member 22 and the heat dissipation layer 5 .
  • the thermal hole 21 is formed in the film layer structure of the second metal layer 250 of the driving backplane away from the laser layer 3 .
  • the heat conduction holes 21 can be arranged in various ways in the drive backplane.
  • the thermal via 21 includes a first thermal via 211 and a second thermal via 212, and the driving circuit layer 2 is located in a film layer on the side of the second metal layer 250 close to the first substrate 1
  • a first thermal conductive hole 211 is provided, and a second thermal conductive hole 212 is provided in the buffer layer 20 of the driving backplane and the first substrate substrate 1.
  • the orthographic projection of the second thermal conductive hole 212 on the first substrate substrate 1 is consistent with the second thermal conductive hole 211.
  • Thermal vias 212 at least partially overlap.
  • the second thermal hole 212 is opened on the side of the first base substrate 1 away from the laser layer 3 .
  • the same photolithography process can be used to form a connection in the film layer of the driver circuit layer 2 located on the side of the second metal layer 250 close to the first base substrate 1
  • the same photolithography process is used to etch the first insulating layer 220 and the interlayer dielectric layer 240 to form exposed active layer surfaces in the two layers. through holes, and the first thermal conductive hole 211.
  • This embodiment does not require additional photolithography processes, which helps reduce process costs.
  • the first thermal conductive holes 211 and the second thermal conductive holes 212 are both filled with thermal conductive members 22 .
  • the thermal conductive member 22 in the first thermal conductive hole 211 may be formed by the second metal layer 250
  • the thermal conductive member 22 in the second thermal conductive hole 212 may be formed by the heat dissipation layer 5 .
  • the first thermal conductive hole 211 and the second thermal conductive hole 212 are connected, and the thermal conductive member 22 in the first thermal conductive hole 211 can contact the thermal conductive member 22 in the second thermal conductive hole 212 to meet the heat conduction requirements, increase the heat conduction rate, and improve the heat dissipation rate.
  • the thermal conductive member 22 in the first thermal conductive hole 211 can also be formed of other film layers, such as the first metal layer 230 or the third metal layer 280 , or the first metal layer 230 or the second metal layer 280 . 250 or a combination of the third metal layer 280, which is not limited in this disclosure.
  • the laser light source also includes a heat dissipation element 23
  • the driving circuit layer 2 includes a metal layer
  • the heat dissipation element 23 is distributed on the metal layer of the driving circuit layer 2 .
  • the heat dissipation element 23 is connected to the thermal conductive member 22 through the thermal layer.
  • the heat dissipation elements 23 distributed in the metal layer of the driving circuit layer 2 can provide a heat conduction path in the horizontal direction and improve the heat dissipation efficiency.
  • the heat dissipation element 23 can be distributed in any metal layer of the driving circuit layer 2, such as the first metal layer 230, the second metal layer 250 or the third metal layer 280, which is not limited in this disclosure.
  • the heat dissipation element 23 can have various shapes, such as metal wires, metal sheets, or metal meshes.
  • the number of heat dissipation elements 23 can be multiple, and the arrangement of the heat dissipation elements 23 can also be multiple, which is not specifically limited in this disclosure.
  • the heat dissipation elements 23 are distributed on the second metal layer 250 .
  • the present disclosure also provides a laser module, including multiple driver chips 02 and multiple laser light sources 01 as in any of the above embodiments.
  • the driver chips 02 are connected to the laser light sources 01 for providing laser light.
  • Light source 01 provides the driving signal.
  • the driver chip 02 and the laser light source 01 are arranged alternately to prevent the concentration of multiple laser light sources 01 from causing excessive temperature in a certain area of the laser module and affecting the quality of the light source.
  • Multiple laser light sources 01 may share a first base substrate 1 .
  • the vertical cavity surface emitting laser 30 is bonded to the driving backplane to form a 1- or even 2-dimensional large-scale laser array light source.
  • the number of pixels can be greater than 10,000.
  • the laser array light source can Used in light-curing stereolithography, maskless lithography, multi-channel optical communications, etc.
  • the present disclosure also provides a method for manufacturing a laser light source, including:
  • Step S100 forming a driving backplane, including a first base substrate 1 and a driving circuit layer 2 provided on one side of the first base substrate 1.
  • the driving circuit layer 2 includes a plurality of pixel circuits;
  • Step S200 forming a laser layer 3, which includes a plurality of vertical cavity surface emitting lasers 30;
  • Step S300 connect the driving backplane and the laser layer 3 so that the vertical cavity surface emitting laser 30 is connected to the pixel circuit in a one-to-one correspondence.
  • the pixel circuit is used to drive the vertical cavity surface emitting laser 30 to emit light.
  • the present disclosure also provides an optical device, including the laser light source according to any embodiment of the present disclosure.
  • the optical device can be any product or component that uses a laser light source, such as a projector or scanner.

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Abstract

一种光学设备、激光光源及制作方法，属于激光技术领域。该激光光源包括驱动背板，包括第一衬底基板（1）和设于第一衬底基板（1）一侧的驱动电路层（2），驱动电路层（2）包括多个像素电路；激光层（3），设于驱动电路层（2）远离第一衬底基板（1）的一侧，激光层（3）包括多个垂直腔体表面发射激光器（30），垂直腔体表面发射激光器（30）与像素电路一一对应连接，像素电路用于驱动垂直腔体表面发射激光器（30）发光。激光光源，通过驱动背板的像素电路实现对激光光源的动态控制，为形成线光源、面光源和动态扫描等提供了结构基础。

Description

光学设备、激光光源及制作方法
交叉引用
本公开要求于2022年5月20日提交的申请号为202210555341.X名称为“光学设备、激光光源及制作方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及激光技术领域，尤其涉及一种光学设备、激光光源及制作方法。
背景技术
垂直腔体表面发射激光器(Vertical-Cavity Surface-Emitting Laser，VCSEL)，具有小体积、出光方向垂直于衬底、易二维集成、阈值电流小、圆形对称光斑、单纵模工作、调制速率高等优异的结构特性和物理特性，已经被广泛应用于大规模数据中心、人脸识别系统、光互联、光存储、光探测等领域，市场前景广阔。
随着技术的不断推进发展，各领域逐渐对VCSEL器件有了更高的应用需求。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种光学设备、激光光源及制作方法，本公开通过驱动背板的像素电路实现对激光光源的动态控制，为形成线光源、面光源和动态扫描等提供了结构基础。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种激光光源，包括：
驱动背板，包括第一衬底基板和设于所述第一衬底基板一侧的驱动电路层，所述驱动电路层包括多个像素电路；
激光层，设于所述驱动电路层远离所述第一衬底基板的一侧，所述激光层包括多个垂直腔体表面发射激光器，所述垂直腔体表面发射激光器与所述像素电路一一对应连接，所述像素电路用于驱动所述垂直腔体表面发射激光器发光。
在本公开的一种示例性实施例中，所述驱动电路层包括：
第一有源层，设于所述第一衬底基板的一侧；
第一绝缘层，设于所述第一有源层远离所述第一衬底基板的一侧，所述第一绝缘层覆盖所述第一有源层；
第一金属层，设于所述第一绝缘层远离所述第一衬底基板的一侧，所述第一金属层包括晶体管的栅极；
层间介质层，设于所述第一金属层远离所述第一衬底基板的一侧，所述层间介质层覆盖所述第一金属层；
第二金属层，设于所述层间介质层远离所述第一衬底基板的一侧，所述第二金属层包括晶体管的源极和漏极，所述晶体管的源极和漏极与所述第一有源层连接；
第一钝化层，设于所述第二金属层远离所述第一衬底基板的一侧，所述第一钝化层覆盖所述第二金属层；
第一导电层，设于所述第一钝化层远离所述第一衬底基板的一侧，所述第一导电层包括第一导电部和第二导电部，所述第一导电部与所述晶体管的源极或漏极连接，所述第二导电部用于加载电源电压。
在本公开的一种示例性实施例中，所述驱动背板还包括：
多个导电柱，设于所述驱动电路层远离所述第一衬底基板的一侧，所述导电柱包括第一导电柱和第二导电柱，所述第一导电柱与所述第一导电部连接，所述第二导电柱与所述第二导电部连接。
在本公开的一种示例性实施例中，所述第一金属层还包括电容的第一极板，所述第二金属层还包括电容的第二极板；或
所述驱动电路层还包括设于所述第一金属层和所述层间介质层之间的沿背离所述第一衬底基板方向依次设置的第二绝缘层和第三金属层，所述第一金属层还包括电容的第一极板，所述第三金属层包括电容的第二极板。
在本公开的一种示例性实施例中，所述导电柱包括：
阻挡层，设于所述第一导电层远离所述第一衬底基板的一侧，所述阻挡层与所述第一导电层连接；
第一焊接层，设于所述阻挡层远离所述第一衬底基板的一侧，所述第一焊接层与所述阻挡层相接触。
在本公开的一种示例性实施例中，所述垂直腔体表面发射激光器包括第一反射镜、氧化限制层、第二有源层、第二反射镜、第二衬底基板、第一电极和第二电极；
所述第一反射镜、所述氧化限制层、所述第二有源层、所述第二反射镜和所述第二衬底基板；沿远离所述第一衬底基板方向依次设置，所述氧化限制层包括未氧化区和位于所述未氧化区外围的氧化区；
所述第一电极与所述第一反射镜连接，所述第二电极与所述第二反射镜连接，且所述第一电极和所述第二电极与所述驱动电路层连接。
在本公开的一种示例性实施例中，所述激光层还包括多个间隔分布的焊接件，所述第一电极和所述第二电极通过所述焊接件与所述驱动电路层连接。
在本公开的一种示例性实施例中，所述驱动背板中设有导热孔，所述垂直腔体表面发射激光器在所述驱动背板上的正投影与所述导热孔至少部分重叠；
所述激光光源还包括散热层，所述散热层设于所述第一衬底基板远离所述激光层的一侧；
所述导热孔中填充有导热件，所述导热件与所述散热层连接。
在本公开的一种示例性实施例中，所述驱动电路层包括金属层，所述激光光源还包括散热元件，所述散热元件分布于所述驱动电路层的金属层，所述散热元件与所述导热件连接。
在本公开的一种示例性实施例中，所述像素电路包括：
数据写入电路，连接扫描信号端、数据信号端和第一节点，并配置为在来自扫描信号端的扫描信号的控制下将来自所述数据信号端的数据信号提供给所述第一节点；
存储电容，连接所述第一节点和第一电源电压端，并被配置为存储 所述第一节点和所述第一电源电压端之间的电压差；
驱动晶体管，连接所述第一节点、所述第一电源电压端和第二节点，所述垂直腔体表面发射激光器连接所述第二节点和第二电源电压端；
其中，所述第一节点连接至所述驱动晶体管的控制端，所述驱动晶体管被配置为在所述第一节点的控制下输出驱动电流至所述垂直腔体表面发射激光器。
在本公开的一种示例性实施例中，所述数据写入电路包括第二晶体管，所述第二晶体管的栅极与所述扫描信号端连接，所述第二晶体管的第一极与所述数据信号端连接，所述第二晶体管的第二极与所述第一节点连接。
在本公开的一种示例性实施例中，所述驱动电路层包括：
第一有源层，设于所述第一衬底基板的一侧，所述第一有源层包括多个半导体部组，所述半导体部组包括第一半导体部和第二半导体部，所述第一半导体部包括所述第二晶体管的有源层，所述第二半导体部包括所述驱动晶体管的有源层；
第一金属层，设于所述第一有源层远离所述第一衬底基板的一侧，所述第一金属层包括所述第二晶体管的栅极、所述驱动晶体管的栅极和所述存储电容的第一极板；
第二金属层，设于所述第一金属层远离所述第一衬底基板的一侧，所述第二金属层包括所述存储电容的第二极板。
在本公开的一种示例性实施例中，所述驱动电路层还包括多条扫描线和多条数据线，所述扫描线沿第一方向延伸，沿第二方向排列，所述数据线沿第二方向延伸，沿第一方向排列；
所述扫描线和所述数据线相互交叉界定出多个像素区，所述半导体部组一一对应地位于所述像素区；
所述第二晶体管的栅极与所述扫描线连接，所述第二晶体管的有源层的第一极区与所述数据线连接；
所述扫描线分布于所述第一金属层或所述第二金属层，所述数据线分布于所述第一金属层或所述第二金属层。
在本公开的一种示例性实施例中，所述驱动电路层还包括多条第一 电源电压线，所述第一电源电压线沿第二方向延伸，沿第一方向排列，所述驱动晶体管的有源层的第一极区与所述第一电源电压线连接；
所述第一电源电压线分布于所述第一金属层或所述第二金属层。
在本公开的一种示例性实施例中，所述垂直腔体表面发射激光器在所述第一衬底基板上的正投影与所述像素电路在所述第一衬底基板上的正投影不重叠。
根据本公开第二个方面，提供一种激光光源的制作方法，包括：
形成驱动背板，包括第一衬底基板和设于所述第一衬底基板一侧的驱动电路层，所述驱动电路层包括多个像素电路；
形成激光层，所述激光层包括多个垂直腔体表面发射激光器；
连接所述驱动背板和所述激光层，使所述垂直腔体表面发射激光器与所述像素电路一一对应连接，所述像素电路用于驱动所述垂直腔体表面发射激光器发光。
根据本公开第三个方面，提供一种激光光源模组，包括多个驱动芯片和多个如第一方面所述的激光光源，所述驱动芯片和所述激光光源连接，所述驱动芯片和所述激光光源交替排布。
根据本公开第四个方面，提供一种光学设备，包括如第一方面所述的激光光源。
本公开提供的激光光源，激光层设于驱动背板的一侧，驱动背板包含多个像素电路，激光层包括多个垂直腔体表面发射激光器，像素电路与垂直腔体表面发射激光器一一对应连接，像素电路可驱动垂直腔体表面发射激光器发光。本公开提供的激光光源，通过驱动背板的像素电路实现对激光光源的动态控制，为形成线光源、面光源和动态扫描等提供了结构基础。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是本公开示例性实施例中激光光源结构示意图；
图2是本公开另一示例性实施例中激光光源结构示意图；
图3是本公开示例性实施例中像素电路等效电路图；
图4是本公开示例性实施例中激光光源平面示意图；
图5是本公开另一示例性实施例中激光光源驱动背板的平面示意图；
图6是本公开示例性实施例中激光模组结构示意图。
图中主要元件附图标记说明如下：
1-第一衬底基板；20-缓冲层；2-驱动电路层；21-导热孔；211-第一导
热孔；2112-第二导热孔；22-导热件；23-散热元件；210-第一有源层；211-半导体部组；2111-第一半导体部；2112-第二半导体部；220-第一绝缘层；230-第一金属层；231-第一金属部；232-第二金属部；240-层间介质层；250-第二金属层；251-第一连接部；252-第二连接部；253-第三连接部；254-第四连接部；PVX1-第一钝化层；270-第二绝缘层；280-第三金属层；290-第一导电层；291-第一导电部；292-第二导电部；PVX2-第二钝化层；3-激光层；30-垂直腔体表面发射激光器；301-第一反射镜；302-氧化限制层；021-氧化区；022-未氧化区；303-第二有源层；304-第二反射镜；305-第二衬底基板；051-凹槽；306-第一电极；307-第二电极；308-绝缘膜；32-焊接件；4-导电柱；41-第一导电柱；42-第二导电柱；43-阻挡层；44-第一焊接层；5-散热层；61-数据写入电路；T2-第二晶体管；C-存储电容；T1-驱动晶体管；N1-第一节点；Gate-扫描信号端；Source-数据信号端；Vdd-第一电源电压端；Vss-第二电源电压端；C1-第一极板；C2-第二极板；GL-扫描线；DL-数据线；VDL-第一电源电压线；VSL-第二电源电压线；7-扇形区；01-激光光源；02-驱动芯片。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
垂直腔体表面发射激光器(Vertical-Cavity Surface-Emitting Laser，VCSEL)是出光方向垂直于谐振腔表面的激光器，可应用于3D扫描、激光投影、光通信等多个领域。例如，相关技术中，将VCSEL与衍射光学元件(Diffractive Optical Elements，DOE)结合作为3D扫描成像光源，然而，该方案无法实现动态扫描。
如图1和图2所示，本公开实施方式中提供一种激光光源，包括驱动背板和激光层3。驱动背板包括第一衬底基板1和设于第一衬底基板1一侧的驱动电路层2，驱动电路层2包括多个像素电路。激光层3设于驱动电路层2远离第一衬底基板1的一侧，激光层3包括多个垂直腔体表面发射激光器30，垂直腔体表面发射激光器30与像素电路一一对应连接，像素电路用于驱动垂直腔体表面发射激光器30发光。
本公开提供的激光光源，激光层3设于驱动背板的一侧，驱动背板包含多个像素电路，激光层3包括多个垂直腔体表面发射激光器30，像素电路与垂直腔体表面发射激光器30一一对应连接，像素电路可驱动垂直腔体表面发射激光器30发光。本公开提供的激光光源，通过驱动背板的像素电路实现对激光光源的动态控制，为形成线光源、面光源和动态扫描等提供了结构基础。
下面结合附图对本公开实施方式提供的激光光源的各部件进行详细说明：
如图1和图2所示，本公开提供一种激光光源，包括驱动背板和设于驱动背板一侧的激光层3。该激光光源可适用于光固化立体光刻光源、3D扫描光源、激光雷达、激光投影、光通信等，具体本公开不做限定。
驱动背板包括第一衬底基板1和设于第一衬底基板1一侧的驱动电路层2。激光层3设于驱动电路层2远离第一衬底基板1的一侧。驱动电路层2包含多个像素电路，激光层3包含多个垂直腔体表面发射激光器30。像素电路与垂直腔体表面发射激光器30一一对应连接，以驱动垂直腔体表面发射激光器30发光。本公开通过像素电路驱动垂直腔体表面发射激光器30，有助于实现高速、高功率、高像素密度的阵列激光发射，并且可以通过像素电路等进行时序、发射强度等控制。
第一衬底基板1可以为无机材料的衬底基板，也可以为有机材料的衬底基板。在本公开一些实施例中，第一衬底基板1的材料为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料。
驱动电路层2设于第一衬底基板1的一侧，驱动电路层2包括多个像素电路。多个像素电路可阵列排布，像素电路的数量和排布方式本公开不做限定。在一些实施例中，驱动电路层2可包含一行沿行方向排布的多个像素电路，以提供线光源，也可以包含多行多列矩阵阵列排布的多个像素电路，以提供面光源。像素电路可包含晶体管和电容，晶体管和电容的数量具体可根据实际的电路需求进行设定。
如图3所示，在本公开一些实施例中，像素电路包括数据写入电路61、驱动晶体管T1和存储电容C。数据写入电路61连接扫描信号端Gate、数据信号端Source和第一节点N1，并配置为在来自扫描信号端Gate的扫描信号的控制下将来自数据信号端Source的数据信号提供给第一节点N1。存储电容C，连接第一节点N1和第一电源电压端Vdd，并被配置为存储第一节点N1和第一电源电压端Vdd之间的电压差。驱动晶体管T1连接第一节点N1、第一电源电压端Vdd和第二节点N2，垂直腔体表面发射激光器30连接第二节点N2和第二电源电压端Vss。其中，第一节点N1连接至驱动晶体管T1的控制端，驱动晶体管T1被配置为在第一节点N1的 控制下输出驱动电流至垂直腔体表面发射激光器30。
在一些实施例中，数据写入电路61包括第二晶体管T2，第二晶体管T2的栅极与扫描信号端Gate连接，具体可连接至栅极驱动芯片。第二晶体管T2的第一极与数据信号端Source连接，具体可连接至数据驱动芯片，如CMOS芯片。第二晶体管T2的第二极与第一节点N1连接。在此需说明的是，第二晶体管T2的栅极和第一极也可连接至同一驱动芯片，该芯片集成栅极驱动芯片和数据驱动芯片，可为像素电路提供扫描信号和数据信号。
在一些实施例中，第二晶体管T2和驱动晶体管T1为P型晶体管。在该类实施例中，像素电路为2T1C像素电路，包含2个晶体管和1个电容。本公开，nTmC表示一个像素电路包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。当然，像素电路也可以为7T1C、7T2C、6T1C或6T2C等像素电路，具体本公开不做限定。
此外，在此需说明的是，在本公开的实施例中采用的晶体管也可以为N型晶体管，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。例如，对于N型晶体管，其输入端为漏极而输出端为源极，其控制端为栅极；对于P型晶体管，其输入端为源极而输出端为漏极，其控制端为栅极。对于不同类型的晶体管，其控制端的控制信号的电平也不相同。例如，对于N型晶体管，在控制信号为高电平时，该N型晶体管处于导通状态；而在控制信号为低电平时，N型晶体管处于截止状态。对于P型晶体管时，在控制信号为低电平时，该P型晶体管处于导通状态；而在控制信号为高电平时，P型晶体管处于截止状态。
如图1和图2所示，驱动电路层2为多层膜层层叠结构。下面将结合附图示例性说明本公开驱动电路层2的膜层层叠结构。
在本公开一些实施例中，驱动电路层2包括第一有源层210、第一绝缘层220、第一金属层230、层间介质层240和第二金属层250。
第一有源层210设于第一衬底基板1的一侧。第一有源层210的材料可采用多晶硅或IGZO(铟镓锌氧化物)等导电材料。第一绝缘层220设于第一有源层210远离第一衬底基板1的一侧，第一绝缘层220覆盖第一 有源层210。第一绝缘层220的材料可采用氮化硅、氧化硅、氧化铝等单膜层或由其组合形成的多膜层。第一金属层230设于第一绝缘层220远离第一衬底基板1的一侧，第一金属层230包括晶体管的栅极。第一金属层230可以为单层或多层结构，其可以是采用钼(Mo)、铜(Cu)等金属形成单层结构，也可以是采用钛(Ti)/铝/(Al)/钛(Ti)等金属形成多层结构，具体本公开不做限定。层间介质层240设于第一金属层230远离第一衬底基板1的一侧，层间介质层240覆盖第一金属层230。第二金属层250设于层间介质层240远离第一衬底基板1的一侧，第二金属层250包括晶体管的源极和漏极，晶体管的源极和漏极与第一有源层210连接。第二金属层250也可以是单层或多层结构，其可以采用钼、铜等金属形成单层结构，也可以是采用钛(Ti)/铝/(Al)/钛(Ti)、MoTiNi合金(MTD)/铜(Cu)、钛(Ti)/铜(Cu)或氧化铟锡(ITO)/银(Ag)等金属形成的多层结构，具体本公开不做限定。
本公开中，像素电路中的电容可由驱动电路层中不同的金属层形成。在本公开一些实施例中，第一金属层230还包括电容的第一极板C1，第二金属层250还包括电容的第二极板C2。或如图2所示，驱动电路层2还包括设于第一金属层230和层间介质层240之间的沿背离第一衬底基板1方向依次设置的第二绝缘层270和第三金属层280，第一金属层230还包括电容的第一极板C1，第三金属层280包括电容的第二极板C2。也即，本公开中，电容可由第一金属层230、层间介质层240和第二金属层250形成，也可以由第一金属层230、第二绝缘层270和第三金属层280形成。第三金属层280的材料可参照第一金属层230或第二金属层250，在此不详细赘述。
在本公开一些实施例中，第一有源层210、第一金属层230、第二金属层250和、第三金属层280的图案可根据像素电路的具体结构进行设计。
如图3、图4和图5所示，在一实施例中，第一有源层210包括多个半导体部组211，半导体部组211包括第一半导体部2111和第二半导体部2112，第一半导体部2111包括第二晶体管T2的有源层，第二半导体部2112包括驱动晶体管T1的有源层。
多个半导体部组211可沿第一方向X依次排列形成行，也可沿第二方 向Y依次排列形成列。第一半导体部2111和第二半导体部2112可沿多个方向排列，也可大致沿第二方向Y排列，具体本公开不做限定。如图4所示，在一具体实施例中，多个半导体部组211沿第一方向X依次排列形成行，且驱动电路层2只包含有一行半导体部组211，此时，单个半导体部组211内的第一半导体部2111和第二半导体部2112可沿第二方向Y排列。如图5所示，在另一具体实施例中，多个半导体部组211沿第一方向X和第二方向Y阵列排列，此时，单个半导体部组211内的第一半导体部2111和第二半导体部2112可沿第一方向X和第二方向Y的夹角方向排列。
第一金属层230设于第一有源层210远离第一衬底基板1的一侧，第一金属层230包括第二晶体管T2的栅极、驱动晶体管T1的栅极和存储电容C的第一极板C1。具体地，第一金属层230可包括第一金属部231和第二金属部232，第一金属部231在第一衬底基板1上的正投影与第一半导体部2111在第一衬底基板1上的正投影的重叠部分为第二晶体管T2的栅极，第二金属部232在第一衬底基板1上的正投影与第二半导体部2112在第一衬底基板1上的正投影的重叠部分为驱动晶体管T1的栅极。第二金属部232还包括电容的第一极板C1。第一金属部231和第二金属部232的排列方式可根据第一半导体部2111和第二半导体部2112的排列方式进行设定，电容的第一极板C1可位于第二晶体管T2的栅极和驱动晶体管T1的栅极之间或其他位置，具体本公开不做限定。
第二金属层250设于第一金属层230远离第一衬底基板1的一侧，第二金属层250包括存储电容C的第二极板C2。第二金属层250包括第一连接部251、第二连接部252、第三连接部253和第四连接部254。第一连接部251连接数据信号端Source并通过过孔与第二晶体管T2的有源层裸露于第一金属层230外的第一极区T2S连接。第二连接部252连接第二晶体管T2的有源层裸露于第一金属层230外的第二极区T2D和存储电容C的第一极板C1。第三连接部253包括存储电容C的第二极板C2，且第三连接部253连接第一电源电压端Vdd和驱动晶体管T1的有源层裸露于第一金属层230外的第一极区T1S。第四连接部254连接驱动晶体管T1的有源层裸露于第一金属层230外的第二极区T1D。第四连接部254可用于连接至垂直腔体表面发射激光器30。第一连接部251、第二连接部252、 第三连接部253和第四连接部254的排列方式可根据第一有源层210、第一金属层230等的图案及位置进行调整，具体本公开不做限定。例如，如图4所示，在一实施例中，第二金属部232和第二连接部252形成的存储电容C位于第二晶体管T2沿第一方向的一侧。在另一实施例中，如图5所示，第二金属部232和第二连接部252形成的存储电容C位于第二晶体管T2沿第二方向的一侧。
如图5所示，在本公开一些实施例中，驱动电路层2还包括多条扫描线GL和多条数据线DL，扫描线GL沿第一方向X延伸，沿第二方向Y排列，数据线DL沿第二方向Y延伸，沿第一方向X排列；扫描线GL和数据线DL相互交叉界定出多个像素区，半导体部组211一一对应地位于像素区；第二晶体管T2的栅极与扫描线GL连接，第二晶体管T2的有源层的第一极区T2S与数据线DL连接；扫描线GL分布于第一金属层230或第二金属层250，数据线DL分布于第一金属层230或第二金属层250。在一具体实施例中，扫描线GL分布于第一金属层230，数据线DL分布于第二金属层250。
在本公开一些实施例中，驱动电路层2还包括多条第一电源电压线VDL，第一电源电压线VDL沿第二方向Y延伸，沿第一方向X排列，驱动晶体管T1的有源层的第一极区T1S与第一电源电压线VDL连接；第一电源电压线VDL分布于第一金属层230或第二金属层250。在一具体实施例中，第一电源电压线VDL分布于第二金属层250。第一电源电压线VDL可位于靠近数据线DL的位置处。
在此需说明的是，如图5所示，当激光光源包含多行多列像素电路时，同一行像素电路可连接至同一条扫描线GL，各像素电路中的第二晶体管T2的栅极可通过扫描线GL连接至扫描信号端Gate。同一列的像素电路可连接至同一条数据线DL，各像素电路中的第二晶体管T2可通过数据线DL连接至数据信号端Source。而当激光光源只包含单行像素电路时，如图4所示，各像素电路的第二晶体管T2的栅极可直接引线至扇形区7进而连接至扫描信号端Gate，而不需要上述的扫描线GL；同理，各像素电路的第二晶体管T2也可直接引线至扇形区7进而连接至数据信号端Source，而不需要上述的数据线DL。
在本公开一些实施例中，垂直腔体表面发射激光器30在第一衬底基板1上的正投影与像素电路在第一衬底基板1上的正投影不重叠。具体地，垂直腔体表面发射激光器30在第一衬底基板1上的正投影与驱动晶体管T1、第二晶体管T2和存储电容C在第一衬底基板1上的正投影不重叠。该设置方式有助于激光光源散热。
如图1和图2所示，在本公开一些实施例中，驱动电路层2还包括第一钝化层PVX1和第一导电层290。其中，第一钝化层PVX1设于第二金属层250远离第一衬底基板1的一侧，第一钝化层PVX1覆盖第二金属层250。第一钝化层PVX1的材料可采用氮化硅等材料，其厚度可以为第一导电层290设于第一钝化层PVX1远离第一衬底基板1的一侧。第一导电层290可以是单层或多层结构，其可以采用钼、铜等金属形成单层结构，也可以是采用钛(Ti)/铝/(Al)/钛(Ti)、MoTiNi合金(MTD)/铜(Cu)、钛(Ti)/铜(Cu)或氧化铟锡(ITO)/银(Ag)等金属形成的多层结构，具体本公开不做限定。第一导电层290包括第一导电部291和第二导电部292，第一导电部291与晶体管的源极或漏极连接。具体地，第一导电部291可通过过孔与第二金属层250连接。第二导电部292可用于加载电源电压，如第二电源电压。
在本公开一些实施例中，驱动背板还包括多个导电柱4，设于驱动电路层2远离第一衬底基板1的一侧，导电柱4包括第一导电柱41和第二导电柱42，第一导电柱41与第一导电部291连接，第二导电柱42与第二导电部292连接。第一导电柱41和第二导电柱42用于连接垂直腔体表面发射激光器30。
在本公开一些实施例中，导电柱4可以为多层结构，例如，导电柱4包括阻挡层43和第一焊接层44，阻挡层43设于第一导电层290远离第一衬底基板1的一侧，阻挡层43与第一导电层290连接。第一焊接层44设于阻挡层43远离第一衬底基板1的一侧，第一焊接层44与阻挡层43相接触。阻挡层43可以为单层膜或多层膜结构，其具体可以是由镍(Ni)等金属材料形成的单层膜结构，也可以是由镍(Ni)/金(Au)、镍(Ni)/钯(Pd)等形成的多层膜结构。第一焊接层44的材料可采用铟(In)、金(Au)、锡(Sn)等金属材料。第一焊接层44用于完成垂直腔体表面 发射激光器30与驱动背板的连接。在该实施例中，导电柱4可采用电镀或剥离(lift-off)工艺制作形成，其具体制作过程可参照现有工艺步骤进行，在此不详细赘述。
如图1所示，在本公开一些实施例中，驱动电路层2还包括第二钝化层PVX2和缓冲层20，第二钝化层PVX2设于第一导电层290和多个导电柱4之间。第二钝化层PVX2的材料可采用氮化硅等材料，其厚度可以为多个导电柱4可通过过孔与第一导电层290连接。缓冲层20设于第一衬底基板1和驱动电路层2之间。
如图1和图2所示，在本公开一些实施例中，垂直腔体表面发射激光器30包括第一反射镜301、氧化限制层302、第二有源层303、第二反射镜304、第二衬底基板305、第一电极306和第二电极307。
第一反射镜301、氧化限制层302、第二有源层303、第二反射镜304和第二衬底基板305；沿远离第一衬底基板1方向依次设置。第一反射镜301和第二反射镜304可为分布式布拉格反射镜，由折射率不同的两种材料交替层叠而成。第一反射镜301和第二反射镜304可在某一波长产生强反射光，该光在第一反射镜301和第二反射镜304之间进行反射，以形成一个垂直腔体。第一反射镜301和第二反射镜304均具有较高的折射率，其中，第一反射镜301的折射率可以接近100％，以作为谐振腔的全反射镜。第二反射镜304的折射率可相对较低，以作为谐振腔的出射镜。
第二有源层303为垂直腔体表面发射激光器30的重要组成部分，其可以采用量子阱结构。氧化限制层302包括未氧化区022和位于未氧化区022外围的氧化区021。氧化限制层302可采用高铝组分的砷化铝镓(AlGaAs)层的侧面外周向该层中心部位氧化，形成具有氧化区021和未氧化区022的氧化限制层302。氧化限制层302的氧化区021的折射率较低，可将光限制在氧化区021围绕的未氧化区022内。
第二衬底基板305的可以为GaAs衬底。在一具体实施例中，第二衬底基板305具有一开口于远离第一衬底基板1方向的凹槽051，该凹槽051在第一衬底基板1上的正投影与氧化限制层302的非氧化区021在第一衬底基板1上的正投影至少部分重叠。该凹槽051可对应为激光出射口。
第一电极306与第一反射镜301连接，第二电极307与第二反射镜304 连接，且第一电极306和第二电极307与驱动电路层2连接。电流可经过第一电极306和第二电极307注入垂直腔体表面发射激光器30。
在本公开一些实施例中，垂直腔体表面发射激光器30还包括绝缘膜308.。第一电极306和氧化限制层302、第二有源层303以及第二反射镜304之间设有绝缘膜308。第二电极307和氧化限制层302、第二有源层303以及第一反射镜301之间设有绝缘膜308。
在本公开一些实施例中，激光层3还包括多个间隔分布的焊接件32，第一电极306和第二电极307通过焊接件32与驱动电路层2连接。具体地，焊接件32可位于第一电极306与第一焊接层44之间，或位于第二电极307与第一焊接层44之间。焊接件32的材料可采用铟(In)、金(Au)、锡(Sn)等金属材料。
本公开垂直腔体表面发射激光器30与驱动电路层2可通过共晶焊实现连接。本公开，共晶焊的焊接过程是指在一定的温度和一定的压力下，使焊接件32和第一焊接层44的接触表面之间熔化，由二个固相形成一个液相，随后，冷却，当温度低于两者共熔点时，由液相形成的晶粒形式互相结合成机械混合物，即焊接件32-第一焊接层44共熔晶体，如金-铟共熔晶体，从而使垂直腔体表面发射激光器30牢固的焊接在驱动背板上，并形成良好的低阻欧姆接触。
本公开中，将垂直腔体表面发射激光器30键合至驱动背板，可通过巨量转移技术，通过拾取、转移、绑定等步骤将垂直腔体表面发射激光器30分次键合至驱动背板，也可将含有垂直腔体表面发射激光器30的晶圆一次键合至驱动背板，具体键合方法本公开不做限定。当采用晶圆一次键合时，可采用金-金共晶焊方法，以提升键合的平整性。
如图1、图2、图4和图5所示，在本公开一些实施例中，驱动背板中设有导热孔21，垂直腔体表面发射激光器30在驱动背板上的正投影与导热孔21至少部分重叠；激光光源还包括散热层5，散热层5设于第一衬底基板1远离激光层3的一侧；导热孔21中填充有导热件22，导热件22与散热层5连接。在该实施例中，导热孔21和散热层5的设置可提升器件的散热能力，其中，导热孔21中的导热件22可将垂直腔体表面发射激光器30产生的热量传导至散热层5，并通过该散热层5将热量散发至外界 环境，提升器件的散热性能。散热层5的材料可采用散热性较好的金属材料，如铜等。同理，导热件22的材料也可采用金属材料，具体本公开不做限定。
在本公开一些实施例中，导热孔21可在垂直于第一衬底基板1方向上正对垂直腔体表面发射激光器30设置。导热孔21可贯穿驱动背板也可不贯穿驱动背板。在一实施例在，导热孔21开口于第一衬底基板1远离激光层3的一侧，以便导热件22与散热层5的连接。
如图1所示，在本公开一些实施例中，导热孔21形成于驱动背板的第二金属层250远离激光层3的膜层结构中。导热孔21在驱动背板中的设置方式可以有多种。举例而言，在一实施例中，导热孔21包括第一导热孔211和第二导热孔212，驱动电路层2的位于第二金属层250靠近第一衬底基板1一侧的膜层中设置有第一导热孔211，驱动背板的缓冲层20和第一衬底基板1中设置有第二导热孔212，第二导热孔212在第一衬底基板1上的正投影与第二导热孔212至少部分重叠。第二导热孔212开口于第一衬底基板1远离激光层3的一侧。在该实施例中，在形成第二金属层250之前，可采用同一道光刻工艺，于驱动电路层2的位于第二金属层250靠近第一衬底基板1一侧的膜层中形成连接有源层的通孔以及第一导热孔211，例如，采用同一道光刻工艺，刻蚀第一绝缘层220和层间介质层240，以在该两层膜层中形成暴露有源层表面的通孔，以及第一导热孔211。该实施例无需增加额外的光刻工艺，有助于降低工艺成本。
第一导热孔211和第二导热孔212中均填充有导热件22。其中，第一导热孔211中的导热件22可由第二金属层250形成，第二导热孔212中的导热件22可由散热层5形成。第一导热孔211和第二导热孔212连通，第一导热孔211中的导热件22可与第二导热孔212中的导热件22接触，以满足热传导需求，提升热传导速率，提高散热速率。
如图2所示，当然，第一导热孔211中的导热件22也可由其他膜层形成，如第一金属层230或第三金属层280，或由第一金属层230、第二金属层250或第三金属层280的结合形成，具体本公开不做限定。
此外，如图5所示，在本公开一些实施例中，激光光源还包括散热元件23，驱动电路层2包括金属层，散热元件23分布于驱动电路层2的金 属层，散热元件23与导热件22连接。分布于驱动电路层2的金属层中的散热元件23，可提供热量在水平方向的传导途径，提升散热效率。
散热元件23可分布于驱动电路层2的任一金属层中，如第一金属层230、第二金属层250或第三金属层280，具体本公开不做限定。散热元件23的形状可以为多种，如金属丝、金属片或金属网格等。散热元件23数量可以为多个，且散热元件23的排列方式也可以为多种，具体本公开不做限定。优选地，散热元件23分布于第二金属层250。
如图6所示，本公开还提供一种激光模组，包括多个驱动芯片02和多个如上述任一实施例中的激光光源01，驱动芯片02与激光光源01连接，用于向激光光源01提供驱动信号。驱动芯片02和激光光源01交替排布，以避免多个激光光源01集中导致激光模组某一区域温度过高，影响光源质量。多个激光光源01可共用一块第一衬底基板1。
本公开提供的激光光源，将垂直腔体表面发射激光器30键合至驱动背板上，为制作形成1维甚至2维的大规模激光阵列光源，其像素数量可大于10000，该激光阵列光源可应用于光固化立体光刻、无掩膜光刻、多通道光通信等。
如图1和图2所示，本公开还提供一种激光光源的制作方法，包括：
步骤S100，形成驱动背板，包括第一衬底基板1和设于第一衬底基板1一侧的驱动电路层2，驱动电路层2包括多个像素电路；
步骤S200，形成激光层3，激光层3包括多个垂直腔体表面发射激光器30；
步骤S300，连接驱动背板和激光层3，使垂直腔体表面发射激光器30与像素电路一一对应连接，像素电路用于驱动垂直腔体表面发射激光器30发光。
本公开还提供一种光学设备，包括本公开任一实施例的激光光源。该光学设备可以是投影仪、扫描仪等任何采用激光光源的产品或部件。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤 分解为多个步骤执行等，均应视为本公开的一部分。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (18)

  1. 一种激光光源，其中，包括：
    驱动背板，包括第一衬底基板和设于所述第一衬底基板一侧的驱动电路层，所述驱动电路层包括多个像素电路；
    激光层，设于所述驱动电路层远离所述第一衬底基板的一侧，所述激光层包括多个垂直腔体表面发射激光器，所述垂直腔体表面发射激光器与所述像素电路一一对应连接，所述像素电路用于驱动所述垂直腔体表面发射激光器发光。
  2. 根据权利要求1所述的激光光源，其中，所述驱动电路层包括：
    第一有源层，设于所述第一衬底基板的一侧；
    第一绝缘层，设于所述第一有源层远离所述第一衬底基板的一侧，所述第一绝缘层覆盖所述第一有源层；
    第一金属层，设于所述第一绝缘层远离所述第一衬底基板的一侧，所述第一金属层包括晶体管的栅极；
    层间介质层，设于所述第一金属层远离所述第一衬底基板的一侧，所述层间介质层覆盖所述第一金属层；
    第二金属层，设于所述层间介质层远离所述第一衬底基板的一侧，所述第二金属层包括晶体管的源极和漏极，所述晶体管的源极和漏极与所述第一有源层连接；
    第一钝化层，设于所述第二金属层远离所述第一衬底基板的一侧，所述第一钝化层覆盖所述第二金属层；
    第一导电层，设于所述第一钝化层远离所述第一衬底基板的一侧，所述第一导电层包括第一导电部和第二导电部，所述第一导电部与所述晶体管的源极或漏极连接，所述第二导电部用于加载电源电压。
  3. 根据权利要求2所述的激光光源，其中，所述驱动背板还包括：
    多个导电柱，设于所述驱动电路层远离所述第一衬底基板的一侧，所述导电柱包括第一导电柱和第二导电柱，所述第一导电柱与所述第一导电部连接，所述第二导电柱与所述第二导电部连接。
  4. 根据权利要求2所述的激光光源，其中，所述第一金属层还包括电容的第一极板，所述第二金属层还包括电容的第二极板；或
    所述驱动电路层还包括设于所述第一金属层和所述层间介质层之间的沿背离所述第一衬底基板方向依次设置的第二绝缘层和第三金属层，所述第一金属层还包括电容的第一极板，所述第三金属层包括电容的第二极板。
  5. 根据权利要求3所述的激光光源，其中，所述导电柱包括：
    阻挡层，设于所述第一导电层远离所述第一衬底基板的一侧，所述阻挡层与所述第一导电层连接；
    第一焊接层，设于所述阻挡层远离所述第一衬底基板的一侧，所述第一焊接层与所述阻挡层相接触。
  6. 根据权利要求1所述的激光光源，其中，所述垂直腔体表面发射激光器包括第一反射镜、氧化限制层、第二有源层、第二反射镜、第二衬底基板、第一电极和第二电极；
    所述第一反射镜、所述氧化限制层、所述第二有源层、所述第二反射镜和所述第二衬底基板；沿远离所述第一衬底基板方向依次设置，所述氧化限制层包括未氧化区和位于所述未氧化区外围的氧化区；
    所述第一电极与所述第一反射镜连接，所述第二电极与所述第二反射镜连接，且所述第一电极和所述第二电极与所述驱动电路层连接。
  7. 根据权利要求6所述的激光光源，其中，所述激光层还包括多个间隔分布的焊接件，所述第一电极和所述第二电极通过所述焊接件与所述驱动电路层连接。
  8. 根据权利要求1所述的激光光源，其中，所述驱动背板中设有导热孔，所述垂直腔体表面发射激光器在所述驱动背板上的正投影与所述导热孔至少部分重叠；
    所述激光光源还包括散热层，所述散热层设于所述第一衬底基板远离所述激光层的一侧；
    所述导热孔中填充有导热件，所述导热件与所述散热层连接。
  9. 根据权利要求8所述的激光光源，其中，所述驱动电路层包括金属层，所述激光光源还包括散热元件，所述散热元件分布于所述驱动电路层的金属层，所述散热元件与所述导热件连接。
  10. 根据权利要求1所述的激光光源，其中，所述像素电路包括：
    数据写入电路，连接扫描信号端、数据信号端和第一节点，并配置为在来自扫描信号端的扫描信号的控制下将来自所述数据信号端的数据信号提供给所述第一节点；
    存储电容，连接所述第一节点和第一电源电压端，并被配置为存储所述第一节点和所述第一电源电压端之间的电压差；
    驱动晶体管，连接所述第一节点、所述第一电源电压端和第二节点，所述垂直腔体表面发射激光器连接所述第二节点和第二电源电压端；
    其中，所述第一节点连接至所述驱动晶体管的控制端，所述驱动晶体管被配置为在所述第一节点的控制下输出驱动电流至所述垂直腔体表面发射激光器。
  11. 根据权利要求10所述的激光光源，其中，所述数据写入电路包括第二晶体管，所述第二晶体管的栅极与所述扫描信号端连接，所述第二晶体管的第一极与所述数据信号端连接，所述第二晶体管的第二极与所述第一节点连接。
  12. 根据权利要求11所述的激光光源，其中，所述驱动电路层包括：
    第一有源层，设于所述第一衬底基板的一侧，所述第一有源层包括多个半导体部组，所述半导体部组包括第一半导体部和第二半导体部，所述第一半导体部包括所述第二晶体管的有源层，所述第二半导体部包括所述驱动晶体管的有源层；
    第一金属层，设于所述第一有源层远离所述第一衬底基板的一侧，所述第一金属层包括所述第二晶体管的栅极、所述驱动晶体管的栅极和所述存储电容的第一极板；
    第二金属层，设于所述第一金属层远离所述第一衬底基板的一侧，所述第二金属层包括所述存储电容的第二极板。
  13. 根据权利要求12所述的激光光源，其中，所述驱动电路层还包括多条扫描线和多条数据线，所述扫描线沿第一方向延伸，沿第二方向排列，所述数据线沿第二方向延伸，沿第一方向排列；
    所述扫描线和所述数据线相互交叉界定出多个像素区，所述半导体部组一一对应地位于所述像素区；
    所述第二晶体管的栅极与所述扫描线连接，所述第二晶体管的有源 层的第一极区与所述数据线连接；
    所述扫描线分布于所述第一金属层或所述第二金属层，所述数据线分布于所述第一金属层或所述第二金属层。
  14. 根据权利要求13所述的激光光源，其中，所述驱动电路层还包括多条第一电源电压线，所述第一电源电压线沿第二方向延伸，沿第一方向排列，所述驱动晶体管的有源层的第一极区与所述第一电源电压线连接；
    所述第一电源电压线分布于所述第一金属层或所述第二金属层。
  15. 根据权利要求1所述的激光光源，其中，所述垂直腔体表面发射激光器在所述第一衬底基板上的正投影与所述像素电路在所述第一衬底基板上的正投影不重叠。
  16. 一种激光光源的制作方法，其中，包括：
    形成驱动背板，包括第一衬底基板和设于所述第一衬底基板一侧的驱动电路层，所述驱动电路层包括多个像素电路；
    形成激光层，所述激光层包括多个垂直腔体表面发射激光器；
    连接所述驱动背板和所述激光层，使所述垂直腔体表面发射激光器与所述像素电路一一对应连接，所述像素电路用于驱动所述垂直腔体表面发射激光器发光。
  17. 一种激光光源模组，其中，包括多个驱动芯片和多个如权利要求1-16任一项所述的激光光源，所述驱动芯片和所述激光光源连接，所述驱动芯片和所述激光光源交替排布。
  18. 一种光学设备，其中，包括如权利要求1-16任一项所述的激光光源。
PCT/CN2023/094301 2022-05-20 2023-05-15 光学设备、激光光源及制作方法 WO2023221943A1 (zh)

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