WO2023221901A1 - 转换电路及电子芯片 - Google Patents

转换电路及电子芯片 Download PDF

Info

Publication number
WO2023221901A1
WO2023221901A1 PCT/CN2023/094097 CN2023094097W WO2023221901A1 WO 2023221901 A1 WO2023221901 A1 WO 2023221901A1 CN 2023094097 W CN2023094097 W CN 2023094097W WO 2023221901 A1 WO2023221901 A1 WO 2023221901A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
module
analog
capacitor
conversion circuit
Prior art date
Application number
PCT/CN2023/094097
Other languages
English (en)
French (fr)
Inventor
叶乐
李和倚
黄如
Original Assignee
杭州未名信科科技有限公司
浙江省北大信息技术高等研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 杭州未名信科科技有限公司, 浙江省北大信息技术高等研究院 filed Critical 杭州未名信科科技有限公司
Publication of WO2023221901A1 publication Critical patent/WO2023221901A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H03M3/426—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one the quantiser being a successive approximation type analogue/digital converter

Definitions

  • the present invention relates to the technical field of integrated circuits, and in particular to a conversion circuit and an electronic chip.
  • ADCs or CDCs are usually divided into two categories, discrete domain and continuous domain. These two types of ADCs or CDCs have their own advantages and disadvantages. There are usually many high-efficiency operational amplifiers to choose from for discrete-domain analog-to-digital converters. However, when designing multi-bit (bit) quantization usually requires additional design to reduce the impact of nonlinearity, which increases system design complexity and power consumption. The continuous domain analog-to-digital converter has more advantages when designing multi-bit quantization, but it faces the problem of poor noise efficiency of the continuous domain op amp.
  • the invention provides a conversion circuit and an electronic chip, which are used to integrate discrete domains and continuous domains in realizing analog-to-digital conversion or capacitance-to-digital conversion circuits, so that the entire circuit not only has the advantages of high energy efficiency but also high precision.
  • the invention provides a conversion circuit, which includes: an input end coarse quantization module, a discrete domain amplification module, a continuous domain amplification module and an output end fine quantization module connected in sequence.
  • the discrete domain amplification module is used to convert the input coarse quantization module to The conversion result is pre-amplified to suppress the gain noise of the continuous domain amplification module, where the conversion circuit is a capacitor-to-digital conversion circuit or an analog-to-digital conversion circuit.
  • the invention also provides an electronic chip, including the above conversion circuit.
  • the present invention pre-amplifies the voltage difference for fine-quantization input by setting up a discrete domain amplification circuit, thereby increasing the input swing of the ⁇ modulator and easing its quantization pressure.
  • it because it pre-amplifies the fine-quantization input signal, it is quite It improves the pre-amplification capability of the gain transconductance and has high energy efficiency, which is equivalent to improving the energy efficiency of the gain transconductance stage, thus solving the problem of cross-conductance It solves the energy efficiency problem of conduction, thereby improving the energy efficiency of the system, ensuring the conversion accuracy in the fine quantization stage, and realizing a discrete domain and continuous domain fusion circuit architecture.
  • Figure 1 is a schematic structural diagram of a conversion circuit provided by an embodiment of the present invention.
  • Figure 2 is a schematic structural diagram of another conversion circuit provided by an embodiment of the present invention.
  • FIG. 3 is a specific circuit diagram of the circuit shown in Figure 2;
  • Figure 4 is a specific circuit diagram of a discrete domain amplification module provided by an embodiment of the present invention.
  • Figure 5 is a schematic structural diagram of the differential operational amplifier powered by the floating capacitor in Figure 4.
  • 6a-6b are schematic diagrams of a circuit for gain error compensation by adjusting the integrating capacitance provided by an embodiment of the present invention.
  • the first stage In existing conversion circuits based on a zoom (ZOOM) structure, the first stage generally uses a Successive Approximation Register (SAR) analog-to-digital conversion circuit to coarsely quantize the detection signal, and then sends the output signal to the second stage.
  • SAR Successive Approximation Register
  • a ⁇ modulator (delta-sigma modulator, DSM) performs analog-to-digital conversion for fine quantization. Multi-bit quantization can not only reduce the quantization error can also increase the stability of the system. Therefore, the current second-stage ⁇ modulator generally uses multi-bit quantization.
  • the second-stage continuous domain ⁇ modulator Since the second-stage continuous domain ⁇ modulator has advantages in multi-bit quantization, it is used before the second stage of fine quantization to convert the discrete output signal of the previous stage into a gain transconductance operational amplifier for fine quantization of the continuous signal. Noise cannot be ignored more and more, which greatly limits the energy efficiency improvement of the entire circuit. Therefore, before the second stage of refinement, the noise of the gain transconductance needs to be suppressed to improve the overall energy efficiency of the circuit.
  • Figure 1 is a schematic structural diagram of a conversion circuit provided by an embodiment of the present invention.
  • the circuit of this embodiment includes: an input end coarse quantization module 10, a discrete domain amplification module 20, and a continuous domain amplification module connected in sequence. 30 and the output end fine quantization module 40.
  • the discrete domain amplification module 20 is used to pre-amplify the conversion result of the input coarse quantization module 10 to suppress the gain noise of the continuous domain amplification module 30.
  • the input-side coarse quantization module 10 is used to perform preliminary quantization on the detection signal, which is generally an analog signal or a detection capacitance value, that is, the detection signal is coarsely quantized through analog-to-digital conversion; the output-side fine quantization module 40 is used to perform coarse quantization on the input signal.
  • the quantization result of the end coarse quantization module 10 is further converted into fine quantization through analog-to-digital conversion.
  • the output end fine quantization module 40 uses a continuous domain ⁇ modulator. Therefore, its input end is provided with a signal for outputting the input end coarse quantization module 10
  • the continuous domain amplification module 30 converts the quantization result in the discrete domain into a voltage or current in the continuous domain.
  • the continuous domain amplification module can be a gain transconductance, which is used to amplify and convert the signal amplified by the discrete domain amplification module into a voltage or current.
  • to control the oscillator in the output fine quantization module that is, the voltage or current converted into a continuous domain can directly drive the oscillator in the output fine quantization module 40 .
  • the final conversion accuracy of the ZOOM architecture conversion circuit also depends on the driving capability of the transconductance.
  • the thermal noise becomes increasingly difficult to ignore. Therefore, the thermal noise of the transconductance limits the performance of the circuit.
  • the conversion accuracy is not conducive to improving the energy efficiency of the entire circuit. In other words, in order to obtain both better energy efficiency and higher conversion accuracy, the improvement through gain transconductance is limited.
  • a discrete domain amplification module 20 is added before the continuous domain amplification module 30 to effectively improve the energy efficiency of the continuous domain amplification module and significantly suppress Noise in the continuous domain.
  • the discrete domain amplification module 20 can use a higher energy-efficiency operational amplifier, such as an inverter-type amplifier powered by a floating capacitor, it not only improves It improves the driving capability of the subsequent stage circuit and at the same time meets the demand for high energy efficiency, so the entire circuit can achieve high precision and low power consumption.
  • a higher energy-efficiency operational amplifier such as an inverter-type amplifier powered by a floating capacitor
  • it can also be achieved by compensating the gain error of an inverter-type amplifier powered by a floating capacitor, such as using the charge redistribution related level sliding technology in the later embodiments to compensate for the gain error.
  • Figure 2 is a schematic structural diagram of another conversion circuit provided by an embodiment of the present invention.
  • Figure 3 is a specific circuit diagram of the circuit shown in Figure 2.
  • the conversion circuit mainly includes a SAR digital-to-analog conversion loop. , discrete domain amplification and sampling module and continuous domain ⁇ digital-to-analog conversion loop.
  • the SAR digital-to-analog conversion loop is used to perform the first-level analog-to-digital conversion of the input detection signal. It mainly includes a dynamic comparator, SAR logic algorithm unit and SAR capacitor array.
  • the preliminary quantification of the input detection capacitance C CDC is completed, in which the difference between the input detection capacitance C CDC and the corresponding baseline capacitance in the SAR capacitor array is also input to the DP-CLS in the discrete domain amplification and sampling module (DT).
  • FIA performs operational amplification, and its amplification result is stored in the sampling capacitor (Sampling) to prepare for fine quantization by the back-end continuous domain ⁇ digital-to-analog conversion loop (continuous-time, CT).
  • the gain transconductance Gm in the back-end continuous domain ⁇ digital-to-analog conversion loop first amplifies the voltage input by the front-end sampling capacitor and converts it into a continuous domain voltage or current to drive the back-end refinement loop.
  • Figure 4 is a specific circuit diagram of a discrete domain amplification module provided by an embodiment of the present invention.
  • Figure 5 is a schematic structural diagram of a differential operational amplifier powered by a floating capacitor in Figure 4, that is, the suspension represented by Diff.FIA in the dotted box in Figure 4
  • the type of operational amplifier is selected based on power consumption and product performance requirements in specific applications.
  • the discrete domain amplification module 20 may include: a first operational amplifier (Diff.FIA), a first sampling capacitor, a first integrating capacitor (C INT ), and related level sampling connected to the output end of the first operational amplifier.
  • Diff.FIA first operational amplifier
  • C INT first integrating capacitor
  • the first sampling capacitor is connected to the input end of the operational amplifier, and the input signal of the first operational amplifier is sampled and held.
  • the An integrating capacitor or a relevant level sampling capacitor is adjusted to generate a compensation voltage with the same magnitude and opposite direction as the error level corresponding to the gain error. Gain error compensation in two ways will be described in detail later.
  • the discrete domain amplification module can also power the traditional inverter-type floating capacitor operational amplifier (Floating Inverter Amplifier, FIA), such as higher accuracy requirements.
  • FIA floating Inverter Amplifier
  • the circuit shown in Figure 4 can be used.
  • the discrete domain amplifier circuit 20 The working sequence of the module's access to the circuit is controlled through the control switch of each module. Generally, at the beginning of the circuit operation, the input sampling capacitor at the input end samples the input signal and saves its input information, and then the first operational amplifier samples the input signal. The operational amplifier processes and outputs.
  • the relevant level sampling capacitor set in the output terminal of the operational amplifier and the first integrating capacitor in the feedback loop are adjustable capacitors, and they can be adjusted separately.
  • the relevant level sampling capacitor and the first integrating capacitor are connected to the circuit according to the timing sequence by controlling the switch.
  • FIG. 4 and Figure 5 Take Figure 4 and Figure 5 as examples to illustrate the operation of the amplifier.
  • First by controlling the switch and closure, and Disconnect to charge the floating capacitors C RES1 and C RES2 .
  • the amplifier amplifies the input signal, disconnect first. to stop the DC power supply and close the After that, the circuit is powered by the floating capacitor C RES1 , and the switch is controlled by disconnect, and Closing causes the circuit to enter the gain error estimation stage, calculating the voltage that needs to be compensated through the capacitor voltage division relationship, and then through the control Disconnecting maintains the charge on capacitor CCLS , disconnecting and closure
  • the capacitor C CLS is connected to the integrating loop, so that the charge is transferred to the integrating capacitor, so that the error level is compensated.
  • the first operational amplifier is a highly energy-efficient inverter-type differential operational amplifier powered by a floating capacitor as shown in Figure 5.
  • the floating capacitor is used to power the floating capacitor.
  • the floating capacitor can be charged through timing control and the floating capacitor can be used to power the operational amplifier.
  • the floating capacitor is used to power the operational amplifier.
  • the relevant level sampling capacitor when the compensation voltage is generated by adjusting the relevant level sampling capacitor, is an adjustable capacitor, which includes a first capacitor array, and the first capacitor array is a combination of capacitors connected in series.
  • the first capacitor array may include C CLS , C TRIM in the dot-dash line frame connected to the output end of the amplifier in Figure 4.
  • the gain error can also be compensated by adjusting the first integrating capacitor.
  • Figures 6a-6b are schematic diagrams of a circuit that provides gain error compensation by adjusting the first integrating capacitor according to an embodiment of the present invention.
  • Figure 6a is Circuit schematic diagram of the estimation stage.
  • Figure 6b is a circuit schematic diagram of the shift stage.
  • the first integrating capacitor includes a second capacitor array, and the integrating capacitor includes a second capacitor array.
  • the gain error is first estimated. The generated error level is then adjusted by adjusting the capacitor array so that the relevant level sampling capacitor generates a compensation voltage, thereby increasing the gain of the circuit output.
  • the first integrating capacitor is adjusted according to the gain error of the first operational amplifier or the related level sampling capacitor is adjusted to generate a compensation voltage with the same error level and opposite direction corresponding to the gain error, so that The error level is fully compensated, and the output equivalent gain of the operational amplifier circuit is improved, thereby ensuring the conversion accuracy of the back-end analog-to-digital conversion circuit.
  • the gain improvement of the first operational amplifier includes three stages: the input sampling capacitor sampling input voltage stage; the error level stage caused by estimating the gain error of the first operational amplifier; and the compensation and offset error level through level sliding. stage.
  • the three working stages can be realized through timing switch control.
  • the first operational amplifier can be a large-swing operational amplifier.
  • the level sliding is used to compensate and offset the error level.
  • the first operational amplifier is a high-gain operational amplifier.
  • the operating mode of the operational amplifier in the estimation error level stage and the level sliding stage can be switched by controlling the switch, so that it can operate in a large swing mode or a high gain mode accordingly.
  • the embodiment of the present invention pre-amplifies the voltage difference for fine quantization input by setting up a discrete domain amplification circuit, which improves the input swing of the ⁇ modulator and relieves its quantization pressure. At the same time, it pre-amplifies the fine quantization input signal. , which equivalently improves the pre-amplification capability of the gain transconductance, and has high energy efficiency, which is equivalent to improving the energy efficiency of the gain transconductance stage, thus solving the energy efficiency problem of the transconductance, thereby improving the energy efficiency of the system and ensuring fine detail. Conversion precision in the quantification stage degree, realizing a discrete domain and continuous domain fusion circuit architecture.
  • an analog-to-digital converter based on a voltage-controlled oscillator (VCO) is used in the second-stage fine-quantized ⁇ modulator.
  • VCO voltage-controlled oscillator
  • Nonlinearity will be averaged out by natural shaping, and not only has the advantage of multi-bit quantization, but also can significantly reduce the oversampling rate of the ⁇ modulator, and also has the advantage of a smaller area.
  • a Phase Frequency Detector (PFD) is used as the quantizer.
  • the ⁇ analog-to-digital converter is also based on dual voltage-controlled oscillators, and the corresponding dual frequency and phase detectors are used for quantization, which can increase the quantization accuracy by two times.
  • a voltage-controlled oscillator can be implemented using a ring inverter chain, such as the CCO (Current Controlled Oscillator) shown in Figures 2 and 3.
  • the embodiment of the present invention adopts a VCO-based continuous-time analog-to-digital converter. Since it has the characteristic of innate loop traversal of the DAC unit, the nonlinearity of the DAC will be averaged out by natural shaping, thus having more advantages when designing multi-bit quantization. ; Through the VCO-based delta-sigma analog-to-digital converter designed based on the inverter chain, the system can have more advantages as the process node shrinks.
  • a system-level chopper (chopper) can also be connected to the input end.
  • the above-mentioned floating capacitors, input sampling capacitors, integrating capacitors and related level sampling capacitors can all be plate capacitors, interdigitated capacitors or MOS capacitors, depending on actual use.
  • An embodiment of the present invention also provides an electronic chip, which includes the above-mentioned conversion circuit.
  • the electronic chip has low power consumption and high precision.
  • the electronic chip can be a temperature, humidity, pressure, etc. sensing chip.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本发明公开一种转换电路及电子芯片，其中，转换电路，包括：依次连接的输入端粗量化模块、离散域放大模块、连续域放大模块和输出端细量化模块，离散域放大模块用于对输入粗量化模块的转换结果进行预放大以抑制连续域放大模块的增益噪声，其中，转换电路为电容数字转换电路或者模拟数字转换电路。本发明实现了模数转换或电容数字转换电路中将离散域与连续域进行融合，使得整个电路不仅具有高能效而且还具有高精度的优势。

Description

转换电路及电子芯片 技术领域
本发明涉及集成电路技术领域，尤其涉及一种转换电路及电子芯片。
背景技术
随着物联网技术的发展，越来越多的传感器芯片被部署在物联网节点端，这些节点端的芯片需要精确感知环境参数。通常通过高精度的模数转换器(Analog to Digital Converter，简称ADC)或者电容数字转换器(Capacitance to Digital Converter,简称CDC)实现。
ADC或者CDC通常分为两类，离散域和连续域，这两类ADC或者CDC有着各自的优势和不足，离散域的模数转换器通常可选择的高能效运放很多，然而在设计多位(bit)量化时，通常需要额外设计以减小非线性的影响，这会增加系统设计复杂度和功耗。而连续域模数转换器，在设计多位量化时具有更多的优势，但是面临着连续域运放噪声能效差的问题。
发明内容
本发明提供一种转换电路及电子芯片，用于在实现模数转换或电容数字转换电路中将离散域与连续域进行融合，使得整个电路不仅具有高能效而且还具有高精度的优势。
本发明提供的一种转换电路，包括：依次连接的输入端粗量化模块、离散域放大模块、连续域放大模块和输出端细量化模块，所述离散域放大模块用于对输入粗量化模块的转换结果进行预放大以抑制连续域放大模块的增益噪声，其中，所述转换电路为电容数字转换电路或者模拟数字转换电路。
本发明还提供一种电子芯片，包括如上述的转换电路。
本发明通过设置离散域放大电路对进行细量化输入的电压差值进行预放大，提升了ΔΣ调制器的输入摆幅，缓解其量化压力，同时由于其对细量化的输入信号进行预放大，相当于提升了增益跨导的预放大能力，而且其具有较高的能效，相当于提升了增益跨导阶段的能效，因此解决了跨 导的能效问题，从而改善了系统的能效，保证细量化阶段的转换精度，实现了一种离散域与连续域融合电路架构。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种转换电路的结构示意图；
图2为本发明实施例提供的另一种转换电路的结构示意图；
图3为图2所示电路的具体电路图；
图4为本发明实施例提供的一种离散域放大模块的具体电路图；
图5为图4中悬浮电容供电的差分运算放大器的结构示意图；
图6a-6b为本发明实施例提供的通过调整积分电容进行增益误差补偿的电路的示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为使本发明的技术方案更加清楚，以下结合附图对本发明的实施例进行详细说明。
现有的基于缩放(ZOOM)型结构的转换电路中，一般第一级采用逐次逼近(Successive Approximation Register,SAR)模数转换电路对检测信号进行粗量化，之后将输出信号送给第二级的ΔΣ调制器(delta-sigma modulator，DSM)进行模数转换以进行细量化，多位量化不仅可以减小量 化误差，还可以增加系统的稳定性，因此，目前第二级的ΔΣ调制器一般采用多位量化。由于第二级连续域的ΔΣ调制器在多位量化具有优势，但在第二级细量化前用于将前级的离散输出信号转换为用于细量化的连续信号的增益跨导的运放噪声越来越不可忽视，从而极大限制了整个电路的能效提升，因此，在第二级细量化前需要将增益跨导的噪声进行抑制以提升电路整体的能效。
图1为本发明实施例提供的一种转换电路的结构示意图，如图1所示，本实施例的电路包括：依次连接的输入端粗量化模块10、离散域放大模块20、连续域放大模块30和输出端细量化模块40，离散域放大模块20用于对输入粗量化模块10的转换结果进行预放大以抑制连续域放大模块30的增益噪声。
本实施例中，输入端粗量化模块10用于对检测信号，一般为模拟信号或者检测电容值进行初步量化，即对检测信号进行模数转换粗量化；输出端细量化模块40用于对输入端粗量化模块10的量化结果进一步模数转换细量化，
由于连续域模数转换电路具有多位量化的优势，本发明实施例中输出端细量化模块40采用连续域的ΔΣ调制器，因此，其输入端设置有用于将输入端粗量化模块10输出的离散域的量化结果进行转换为连续域的电压或电流的连续域放大模块30，该连续域放大模块可以为增益跨导，用于将离散域放大模块放大后的信号再放大转换成电压或电流，以控制输出端细量化模块中的振荡器，即其转化成的连续域的电压或电流可以直接驱动输出端细量化模块40中的振荡器。
在实际应用中，ZOOM架构的转换电路最终的转换精度还依赖于跨导的驱动能力，但增大跨导的增益，其热噪声越来越不能忽视，因此跨导的热噪声限制了电路的转换精度，从而不利于提升整个电路的能效，也就是说，要想获得既有较好能效，又有较高转换精度，通过增益跨导的改善是有限的。为使后级电路既具有较大的驱动能力，又不至于降低能效，本实施例中通过在连续域放大模块30之前增设离散域放大模块20以等效提升连续域放大模块的能效，显著压制连续域的噪声。同时，由于离散域放大模块20可以采用较高能效的运算放大器，如基于悬浮电容供电的反相器型放大器，不仅提升 了后级电路的驱动能力，同时又满足高能效的需求，因此可以使得整个电路能够实现高精度和低功耗。对精度要求更高的情况下，还可以通过补偿基于悬浮电容供电的反相器型放大器的增益误差的方法实现，如采用后面实施例中的电荷再分配的相关电平滑动技术以补偿增益误差。
图2为本发明实施例提供的另一种转换电路的结构示意图，图3为图2所示电路的具体电路图，如图2和图3所示，该转换电路主要包括SAR数模转换环路、离散域放大及采样模块和连续域ΔΣ数模转换环路，其中SAR数模转换环路用于对输入检测信号进行第一级模数转换，其主要包括动态比较器、SAR逻辑算法单元及SAR电容阵列。通过SAR环路，完成输入检测电容CCDC的初步量化，其中输入检测电容CCDC与SAR电容阵列中相应基线电容的差值还被输入到离散域放大及采样模块(DT)中的DP-CLS FIA进行运算放大，其放大结果保存在采样电容(Sampling)，以备后端连续域ΔΣ数模转换环路(continuous-time，CT)进行细量化。其中后端连续域ΔΣ数模转换环路中增益跨导Gm首先对前端采样电容输入的电压进行放大转换成连续域的电压或电流以驱动后端细量化环路。
图4为本发明实施例提供的一种离散域放大模块的具体电路图，图5为图4中悬浮电容供电的差分运算放大器的结构示意图，即图4中虚线框中的Diff.FIA表示的悬浮电容供电的差分运算放大器，在具体应用中根据对功耗及产品性能要求选择运算放大器类型。如图4所示，离散域放大模块20可以包括：第一运算放大器(Diff.FIA)、第一采样电容、第一积分电容(CINT)及连接在第一运算放大器输出端的相关电平采样电容(CCLS)，第一采样电容接入运算放大器的输入端，对第一运算放大器的输入信号进行采样并保持，第一运算放大器工作中，根据第一运算放大器的增益误差，通过调整第一积分电容的方式或者调整相关电平采样电容的方式以产生与所述增益误差对应的误差电平大小相同方向相反的补偿电压。通过两种方式进行增益误差补偿后面将详细说明。
在实际应用中，在对电路性能要求不是很高的情况下，离散域放大模块也可以为传统的反相器型悬浮电容供电的运算放大器(Floating Inverter Amplifier，FIA)，如对精度要求更高，可以采用图4所示的电路。
在实际的电路工作过程中，为降低电路功耗，该离散域放大电路20 会通过各个模块的控制开关来控制模块接入电路的工作时序，一般在电路工作开始，先是输入端的输入采样电容对输入信号进行采样并保存其输入信息，接着是第一运算放大器对输入信号进行运算放大处理并输出，本实施例中，为改善电路的增益性能，运放输出端中设置的相关电平采样电容及反馈回路中的第一积分电容为可调整电容，二者可分别调整，也可同时调整，主要能达到使该电路输出的增益误差消除即可，从而使该电路用于环境传感芯片中模数转换时，既不降低芯片中模数转换的能效，又能保证转换精度。在增益误差消除过程中，通过控制开关使得相关电平采样电容及第一积分电容依照时序接入电路。
以图4及图5示例说明放大器的工作，首先通过控制开关和闭合，和断开，对悬浮电容CRES1和CRES2进行充电，当放大器对输入信号进行放大时，先断开以停止直流供电，并闭合此后由悬浮电容CRES1对电路进行供电，通过控制开关断开，和闭合使电路进入增益误差估计阶段，通过电容分压关系计算需要补偿的电压，接着通过控制断开使电容CCLS上的电荷得以保持，断开和闭合使电容CCLS实现接入积分环路，使电荷向积分电容转移，从而使误差电平得到补偿。
其中，第一运算放大器如图5所示的高能效的悬浮电容供电的反相器型差分运算放大器，采用悬浮电容供电可以通过时序控制对悬浮电容充电及悬浮电容对运算放大器供电，采用悬浮电容给运放供电时，随着放大过程的进行，供电电容上的电压将逐渐减小，从而逐渐关断放大器，并且放大器在放大过程中对电流的需求也是逐渐减少的，从而能显著提升放大器的能效。
在一实施例中，当通过调整相关电平采样电容的方式产生补偿电压时，该相关电平采样电容为可调整电容，其包括第一电容阵列，该第一电容阵列为串联连接的电容组合，第一电容阵列可以包括图4中连接在放大器输出端的点划线框中的CCLS,CTRIM，通过调整电容CTRIM的分压可以使第一运算放大器的增益误差产生的误差电平得到补偿。具体来说，由于第一运算放大器的有限增益，其根据输入信号产生输出放大信号时会产生一定的增益误差，该增益误差会影响后续电路中模数转换精度，本实施例中为 解决这个问题，首先通过估计该增益误差产生的对应的误差电平，再通过调整相关电平采样电容中电容阵列的电容分压，使产生一个与估计得到的误差电平大小相同方向相反的补偿电压，对整个电路来说，其输出增益误差得到了补偿，即提升了电路的增益，从而有助于后端电路的模数转换精度。
在另一实施例中也可以通过调整第一积分电容来对增益误差进行补偿，图6a-图6b为本发明实施例提供通过调整第一积分电容进行增益误差补偿的电路的示意图，图6a为估计阶段的电路示意图，图6b为移位阶段的电路示意图，如图6a-图6b所示，第一积分电容包括第二电容阵列，积分电容包括第二电容阵列，工作中，首先估计增益误差产生的误差电平，然后通过调整电容阵列使得相关电平采样电容产生补偿电压，从而提升电路输出的增益。
上述实施例中通过根据第一运算放大器的增益误差，来调整第一积分电容的方式或者调整相关电平采样电容的方式以产生与增益误差对应的误差电平大小相同方向相反的补偿电压，使得误差电平得到完全补偿，运算放大电路的输出等效增益得到提升，从而使后端的模数转换电路的转换精度得到保证。
在时序上，第一运算放大器的增益提升包括三个阶段：输入采样电容采样输入电压阶段；估计第一运算放大器的增益误差产生的误差电平阶段；以及通过电平滑动以补偿抵消误差电平阶段。三个工作阶段通过时序开关控制即可实现，在估计第一运算放大器的增益误差产生的误差电平阶段，第一运算放大器可以为大摆幅运算放大器，在通过电平滑动以补偿抵消误差电平阶段，第一运算放大器为高增益运算放大器。在实际电路中，可以通过控制开关对估计误差电平阶段和电平滑动阶段的运算放大器的工作模式进行切换，使其相应工作在大摆幅模式或者高增益模式。
本发明实施例通过设置离散域放大电路对进行细量化输入的电压差值进行预放大，提升了ΔΣ调制器的输入摆幅，缓解其量化压力，同时由于其对细量化的输入信号进行预放大，等效提升了增益跨导的预放大能力，而且其具有较高的能效，相当于提升了增益跨导阶段的能效，因此解决了跨导的能效问题，从而改善了系统的能效，保证细量化阶段的转换精 度，实现了一种离散域与连续域融合电路架构。
在上述实施例的基础上，在具体应用中，为提升系统综合性能，第二级细量化的ΔΣ调制器中采用基于压控振荡器(Voltage Control Oscillator，简称：VCO)的模数转换器，非线性会被天然整形平均掉，而且不仅具有多位量化的优势，还能显著降低ΔΣ调制器的过采样率，且还具有面积较小的优势，在ΔΣ调制器的环路中，其量化采用鉴频鉴相器(Phase Frequency Detector，简称PFD)作为量化器。为进一步提升量化精度，ΔΣ模数转换器还采用基于双压控振荡器，对应采用双鉴频鉴相器进行量化，从而可以将量化精度提升两倍。压控振荡器可以采用环形反相器链实现，如图2和图3所示的CCO(电流控制振荡器，Current Controlled Oscillator)。
本发明实施例通过采用基于VCO的连续时间模数转换器，由于具有先天循环遍历DAC单元的特性，因此DAC的非线性会被天然整形平均掉，从而在设计多bit量化时具有更多的优势；通过基于反相器链设计的VCO-based delta-sigma模数转换器，可以使系统随着工艺节点的缩小会具有更多的优势。
在实际应用中，为减小偏移，在输入端粗量化模块10进行输入信号粗量化之前，还可以在输入端接入系统级斩波器(chopper)。
上述的悬浮电容、输入采样电容、积分电容及相关电平采样电容均可以采用平板电容、插指电容或MOS电容，具体根据实际采用。
本发明实施例还提供一种电子芯片，包括如上述的转换电路，该电子芯片具有低功耗高精度。该电子芯片可以为温度、湿度、压力等传感芯片。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

  1. 一种转换电路，其特征在于，包括：依次连接的输入端粗量化模块、离散域放大模块、连续域放大模块和输出端细量化模块，所述离散域放大模块用于对输入粗量化模块的转换结果进行预放大以抑制连续域放大模块的增益噪声，其中，所述转换电路为电容数字转换电路或者模拟数字转换电路。
  2. 根据权利要求1所述的电路，其特征在于，所述离散域放大模块为基于悬浮电容供电的反相器型放大器。
  3. 根据权利要求1或2所述的电路，其特征在于，所述离散域放大模块包括：第一运算放大器、第一采样电容、第一积分电容及连接在第一运算放大器输出端的相关电平采样电容，第一采样电容接入运算放大器的输入端，对第一运算放大器的输入信号进行采样并保持，第一运算放大器工作中，根据第一运算放大器的增益误差，通过调整第一积分电容的方式或者调整相关电平采样电容的方式以产生与所述增益误差对应的误差电平大小相同方向相反的补偿电压。
  4. 根据权利要求1所述的电路，其特征在于，所述输出端细量化模块为基于压控振荡器的ΔΣ模数转换器。
  5. 根据权利要求4所述的电路，其特征在于，所述ΔΣ模数转换器为基于双压控振荡器的ΔΣ模数转换器。
  6. 根据权利要求4或5所述的电路，其特征在于，所述压控振荡器为环形反相器链结构。
  7. 根据权利要求4所述的电路，其特征在于，所述连续域放大模块为增益跨导，用于将离散域放大模块放大后的信号再放大转换成电压或电流，以驱动输出端细量化模块中的振荡器。
  8. 根据权利要求1所述的电路，其特征在于，还包括输入端接入的系统级斩波器以减小偏移。
  9. 根据权利要求1所述的电路，其特征在于，所述输入端粗量化模块为基于逐次逼近模数转换电路，用于对输入检测信号进行第一级模数转换。
  10. 一种电子芯片，其特征在于，包括如权利要求1～9所述的转换电路。
PCT/CN2023/094097 2022-05-15 2023-05-14 转换电路及电子芯片 WO2023221901A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210518973.9A CN115514372A (zh) 2022-05-15 2022-05-15 转换电路及电子芯片
CN202210518973.9 2022-05-15

Publications (1)

Publication Number Publication Date
WO2023221901A1 true WO2023221901A1 (zh) 2023-11-23

Family

ID=84500832

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/094097 WO2023221901A1 (zh) 2022-05-15 2023-05-14 转换电路及电子芯片

Country Status (2)

Country Link
CN (1) CN115514372A (zh)
WO (1) WO2023221901A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115514372A (zh) * 2022-05-15 2022-12-23 杭州未名信科科技有限公司 转换电路及电子芯片

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100097256A1 (en) * 2008-10-21 2010-04-22 Analog Devices, Inc Apparatus for and Method of Performing an Analog to Digital Conversion
CN113225084A (zh) * 2021-04-16 2021-08-06 西安交通大学 自适应基准电压的Delta-Sigma ADC结构
US20210258014A1 (en) * 2020-02-16 2021-08-19 Board Of Regents, The University Of Texas System Time-domain incremental two-step capacitance-to-digital converter
CN113381711A (zh) * 2021-05-25 2021-09-10 杭州微纳核芯电子科技有限公司 基于功耗自感知动态电荷域放大器阵列电容传感芯片
CN115514372A (zh) * 2022-05-15 2022-12-23 杭州未名信科科技有限公司 转换电路及电子芯片

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100097256A1 (en) * 2008-10-21 2010-04-22 Analog Devices, Inc Apparatus for and Method of Performing an Analog to Digital Conversion
US20210258014A1 (en) * 2020-02-16 2021-08-19 Board Of Regents, The University Of Texas System Time-domain incremental two-step capacitance-to-digital converter
CN113225084A (zh) * 2021-04-16 2021-08-06 西安交通大学 自适应基准电压的Delta-Sigma ADC结构
CN113381711A (zh) * 2021-05-25 2021-09-10 杭州微纳核芯电子科技有限公司 基于功耗自感知动态电荷域放大器阵列电容传感芯片
CN115514372A (zh) * 2022-05-15 2022-12-23 杭州未名信科科技有限公司 转换电路及电子芯片

Also Published As

Publication number Publication date
CN115514372A (zh) 2022-12-23

Similar Documents

Publication Publication Date Title
US8907829B1 (en) Systems and methods for sampling in an input network of a delta-sigma modulator
US7528760B2 (en) Class D analog-to-digital converter
US6967611B2 (en) Optimized reference voltage generation using switched capacitor scaling for data converters
TWI751918B (zh) 類比數位轉換器及其操作方法
CN109787633B (zh) 带斩波稳定的适用于混合型adc结构的σδadc
US20060132341A1 (en) Systems and methods for mismatch cancellation in switched capacitor circuits
WO2023221901A1 (zh) 转换电路及电子芯片
US6909393B2 (en) Space efficient low power cyclic A/D converter
CN114900189B (zh) 低噪声泄露的mashδς调制器
KR101680081B1 (ko) 2차 노이즈 쉐이핑 기법을 적용한 sar adc
Brewer et al. A 100dB SNR 2.5 MS/s output data rate/spl Delta//spl Sigma/ADC
US9692444B1 (en) Neutralizing voltage kickback in a switched capacitor based data converter
CN110174834B (zh) 低功耗时间数字转换器
Hu et al. Ultra-Low OSR Calibration Free MASH Noise Shaping SAR ADC
Lin et al. Time-based all-digital sigma–delta modulators for nanometer low voltage CMOS data converters
Liao et al. A 1 V 175 μW 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques
CN114285414B (zh) 缩放式增量型模数转换方法及转换器
Leene et al. A 3rd order time domain delta sigma modulator with extended-phase detection
Ni et al. A 13-bit 312.5-MS/s pipelined SAR ADC with open-loop integrator-based residue amplifier and gain-stabilized integration time generation
US7423566B2 (en) Sigma-delta modulator using a passive filter
CN111711452A (zh) 一种有源-无源噪声整形逐次逼近adc
Sidun et al. Design of the ring amplifier for low-power ADC
Liu et al. A Second-Order Feedforward VCO-Based ADC with Continuous-Time Sigma-Delta Modulator for EEG Signal Recording Front Ends
Nam et al. A 11.4-ENOB First-Order Noise-Shaping SAR ADC With PVT-Insensitive Closed-Loop Dynamic Amplifier and Two CDACs
Kareppagoudr et al. Switched-Capacitor Integrator with Slew-Rate Enhancement and Low Distortion

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23806853

Country of ref document: EP

Kind code of ref document: A1