WO2023221481A1 - Substrate module, method for manufacturing substrate module, and display module - Google Patents

Abstract

The present application discloses a substrate module, a method for manufacturing a substrate module, and a display module. The substrate module comprises: a first substrate, pad groups and a test terminal being provided on the first substrate; a driving chip, provided on the side of the first substrate distant from the pad groups and the test terminal, the driving chip being separately connected to the pad groups and the test terminal; a second substrate, provided on the side of the driving chip distant from the first substrate, pins being provided on the side of the second substrate distant from the first substrate, and the driving chip being connected to the pins; and a filling layer, provided between the first substrate and the second substrate, and wrapping the driving chip.

Description

Substrate module, manufacturing method of substrate module, display module

This application claims priority to the Chinese patent application with application number 202210539300.1, which was submitted to the China Patent Office on May 17, 2022. The entire content of this application is incorporated into this application by reference.

Technical field

Embodiments of the present application relate to the field of display technology, for example, to a substrate module, a manufacturing method of a substrate module, and a display module.

Background technique

As a new display technology, light emitting diode (LED) display screens are widely favored by users for their advantages such as energy saving, environmental protection, and high efficiency. LED display screens in the related art generally include a circuit board and a display module. The display module includes light-emitting chips arranged in an array. In order to drive the light-emitting chips in the display module to emit light, multiple driver chips are usually provided on the circuit board. However, The setting of the driver chip will cause the circuit board to have many layers and a complex structure. In order to solve the problem of circuit boards with multiple layers and complex structures, in related technologies, the driver chip can be placed on the front of the display module. However, the placement of the driver chip will occupy a certain area of the display module, making the display module used to place light-emitting chips. The area is reduced, thereby reducing the pixel density of the display module.

Contents of the invention

This application provides a substrate module, a manufacturing method of the substrate module, and a display module to increase the pixel density of the display module and reduce the production cost of the display module.

In a first aspect, embodiments of the present application provide a substrate module, including: a first substrate, a pad group and a test terminal are provided on the first substrate; a driver chip is provided on the first substrate away from the On one side of the pad group and the test terminal, the driver chip is connected to the pad group and the test terminal respectively; a second substrate is provided on the side of the driver chip away from the first substrate, Pins are provided on the side of the second substrate away from the first substrate, and the driver chip is connected to the pins; a filling layer is provided between the first substrate and the second substrate, And cover the driver chip.

Optionally, the first substrate and the second substrate are provided with connection lines and conductive via holes, and the driver chip is connected to the pad group and the pad group through the connection lines and the conductive via holes respectively. Test the terminals and pin connections.

Optionally, a first conductive via hole and a first connection line are provided on the first substrate, a second conductive via hole and a second connection line are provided on the second substrate, and the pad group includes a first electrode pad and the second electrode pad; the driver chip is connected to the test terminal and the first electrode pad through the first conductive via hole and the first connection line; the driver chip is connected to the test terminal and the first electrode pad through the first conductive via hole and the first connection line; The first conductive via hole, the first connection line and the second connection line are connected to the second electrode pad; the driver chip passes through the first connection line and the first conductive via hole. at least one of the second connection line and the second conductive via hole is connected to the pin.

Optionally, the first connection line includes a first sub-connection line and a second sub-connection line, the first sub-connection line is provided on a side of the first substrate close to the driver chip, and the second sub-connection line The sub-connection line is provided on the side of the first substrate away from the driver chip; part of the first conductive via hole corresponds to the first electrode pad and the second electrode The vertical projections of the pads in the thickness direction of the first substrate at least partially overlap; the driver chip is connected to the first electrode pad through the first conductive via hole and the first sub-connection line, The driver chip is connected to the second electrode pad through the first conductive via hole, the first sub-connection line and the second connection line; the driver chip passes through the first conductive via hole, And at least one of the first sub-connection line and the second sub-connection line is connected to the test terminal.

Optionally, the second connection line is provided on a side of the second substrate close to the driver chip, and the second conductive via hole is perpendicular to the pin in the thickness direction of the second substrate. The projections at least partially overlap.

Optionally, the substrate module further includes a conductive structure, the conductive structure is disposed in the filling layer, and the driver chip passes through at least one of the connection line and the conductive via hole on the first substrate, the The conductive structure and at least one of the connection line and the conductive via hole on the second substrate are connected to the pin.

Optionally, the conductive structure is an alloy ball.

Optionally, the driver chip includes a first power input pin and a second power input pin. The pins include a first power input pin and a second power input pin. The first power input pin is connected to the first power input pin, and the second power input pin is connected to the second power input pin.

Optionally, the driver chip further includes two ground pins, the pins further include two ground pins, and the two ground pins are connected to the two ground pins in one-to-one correspondence.

Optionally, the two ground pins are connected in series.

Optionally, a copper-clad layer is provided on a side of the second substrate away from the first substrate, and the copper-clad layer is used to increase the heat dissipation performance of the second substrate.

Optionally, the material of the filling layer is a thermally conductive insulating material.

Embodiments of the present application also provide a method for manufacturing a substrate module, including: providing a first substrate with a pad group and a test terminal provided on the first substrate; A driver chip is provided on one side of the test terminal so that the pad group and the test terminal are connected to the driver chip respectively; a second substrate is provided on the side of the driver chip away from the first substrate, Pins are provided on a side of the second substrate away from the first substrate, and the pins are connected to the driver chip; a filling layer is formed between the first substrate and the second substrate. The filling layer covers the driving chip.

Optionally, connection lines and conductive vias are provided on the first substrate and the second substrate; the pins are connected to the driver chip, including: on the first substrate and the second substrate A conductive structure is arranged between the driver chip and the driver chip through at least one of the connection lines and conductive via holes on the first substrate, the conductive structure and the connection lines and conductive via holes on the second substrate. At least one of them is connected to the pins.

Optionally, a conductive structure is provided between the first substrate and the second substrate to allow the driver chip to pass through at least one of a connection line and a conductive via hole on the first substrate. The structure and at least one of the connection lines and the conductive vias on the second substrate are connected to the pins, including: applying coating on at least one of the connection lines and the conductive vias on the first substrate. Covering the first solder; soldering the conductive structure to the connecting wire or conductive via hole on the first substrate through the first solder; at least one of the connecting wire and the conductive via hole on the second substrate Coating one place with a second solder; attaching the first substrate with the conductive structure soldered to the second substrate, and soldering the conductive structure to the second substrate through the second solder on the connecting wires or conductive vias.

Optionally, a conductive structure is provided between the first substrate and the second substrate to allow the driver chip to pass through at least one of a connection line and a conductive via hole on the first substrate. The structure and at least one of the connection lines and conductive vias on the second substrate are connected to the pins, including:

disposing the conductive structure at the connection line or conductive via hole on the first substrate;

A temporary carrier plate is provided on the side of the conductive structure away from the first substrate to fix the conductive structure on the first substrate;

electroplating a conductive material at the connecting position of the conductive structure and the connection line or conductive via hole of the first substrate, so that the conductive structure is connected to the connection line or conductive via hole on the first substrate;

Remove the temporary carrier board and attach the first substrate connected to the conductive structure to the second substrate;

Conductive material is electroplated at the connection position between the conductive structure and the connection line or conductive via hole of the second substrate, so that the conductive structure is connected to at least one of the connection line and conductive via hole on the second substrate. connect.

An embodiment of the present application also provides a display module, including a light-emitting chip and the substrate module described in the first aspect. The light-emitting chip is disposed on the pad group of the first substrate, and the light-emitting chip is connected to the substrate module. The pad group of the first substrate is connected.

Optionally, the light-emitting chip includes a first light-emitting chip, a second light-emitting chip, and a third light-emitting chip of different light-emitting colors. The first light-emitting chip, the second light-emitting chip, and the third light-emitting chip all have first electrodes and second electrode;

The first electrodes of the first light-emitting chip and the second light-emitting chip are connected to the first power input pin of the driver chip through the correspondingly connected pad groups, and the first electrode of the third light-emitting chip The pad group is connected to the second power input pin of the driver chip through corresponding connections; the second electrodes of the first light-emitting chip, the second light-emitting chip and the third light-emitting chip are connected through corresponding connections. The pad group is connected to the ground pin of the driver chip.

Optionally, the light-emitting chip is a flip chip.

Description of the drawings

Figure 1 is a schematic cross-sectional structural diagram of a substrate module provided by an embodiment of the present application;

Figure 2 is a schematic top structural view of a first substrate provided by an embodiment of the present application;

Figure 3 is a schematic bottom view of the structure of a first substrate provided by an embodiment of the present application;

Figure 4 is a schematic top structural view of a second substrate provided by an embodiment of the present application;

Figure 5 is a schematic structural diagram from below of a second substrate provided by an embodiment of the present application;

Figure 6 is a flow chart of a method for manufacturing a substrate module provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a display module provided by an embodiment of the present application.

Detailed ways

The present application will be described below in conjunction with the drawings and embodiments. It can be understood that the embodiments described here are only used to explain the present application, but not to limit the present application. It should also be noted that, for convenience of description, only the structures related to the present application are shown in the drawings.

Figure 1 is a schematic cross-sectional structural diagram of a substrate module provided by an embodiment of the present application. As shown in Figure 1, the substrate module includes:

The first substrate 110 is provided with a pad group 120 and a test terminal 130 on the first substrate 110;

The driver chip 140 is disposed on the side of the first substrate 110 away from the pad group 120 and the test terminal 130. The driver chip 140 is connected to the pad group 120 and the test terminal 130 respectively;

The second substrate 150 is provided on the side of the driver chip 140 away from the first substrate 110. The second substrate 150 is provided with pins 160 on the side away from the first substrate 110. The driver chip 140 is connected to the pins 160;

The filling layer 170 is disposed between the first substrate 110 and the second substrate 150 and covers the driver chip 140 .

The first substrate 110 and the second substrate 150 may be a printed circuit board (PCB). The first substrate 110 may include a first surface 111 and a second surface 112 . The pad group 120 and the test terminal 130 may be disposed on the first surface. On one surface 111, the driver chip 140 can be disposed on the second surface 112. By disposing the driver chip 140 on the second surface 112, the driver chip 140 can be prevented from occupying the area of the first surface 111, thereby ensuring that the first substrate 110 can The area used for arranging the pad group 120 increases the density of arranging the pad group 120 on the first substrate 110 . When the substrate module is used to form a display module, the bonding pad group 120 is used to connect the light-emitting chips. When the density of the bonding pad group 120 is relatively large, the density of the light-emitting chips on the display module can be increased, thereby improving the efficiency of the display module. pixel density.

The driver chip 140 may include a plurality of pins. The pins of the driver chip 140 may be connected to external drive signals through the pins 160 on the second substrate 150 , or may be connected to the external driver through the test terminals 130 on the first substrate 110 . The driving signal is connected, and the external driving signal drives the light-emitting chip connected to the pad group 120 to emit light through the driving chip 140 . When the pins of the driving chip 140 are connected to external driving signals through the test terminals 130 on the first substrate 110, the external driving signals may be test signals. The test process can occur after the driver chip 140 is encapsulated in the filling layer 170, and an external test signal is input through the test terminal 130 to test the driver chip 140 and the circuit. When the test result is defective, the defect can be skipped in the subsequent die solidification process. The light-emitting chip corresponding to the position of the pad group 120 is solidified, thereby reducing the waste of light-emitting chips and conducive to reducing the production cost of the display module. The test process can also occur after the die is solidified on the substrate module, and the external drive signal is transmitted to the driver chip 140 through the test terminal 130. The driver chip 140 can drive the light-emitting chip connected to the pad group 120 to emit light according to the external drive signal. In this way, the display module can be detected after the driver chip 140 is integrated into the substrate module to detect defects in the display module, so that defective products can be eliminated based on the detection results and the product yield rate of the display module can be improved. Furthermore, when a fault occurs during use of the display module, the test terminal 130 can provide a detection signal for the display module for detection, which is helpful to determine the fault location and cause of the display module and facilitate repair of the display module.

When the pins of the driving chip 140 are connected to external driving signals through the pins 160 on the second substrate 150, the external driving signals can provide normal light-emitting driving signals for the light-emitting chips connected to the driving pad group 120. The driving chips The connection line between pin 140 and pin 160 is located in the display module, so that when the display module is connected to an external driving signal, the difficulty of connecting the display module can be reduced. Moreover, a filling layer 170 is provided around the driver chip 140 to cover the driver chip 140, so that the driver chip 140 can be built into the first substrate 110 and the second substrate 150 to achieve circuit integration and structural integration of the substrate module. It is helpful to reduce the size of the substrate module. Moreover, the substrate module only needs two layers of substrates to realize the integration of the substrate module, which reduces the cost of the substrate module. In addition, a constant current signal can be provided to the driver chip 140 through the pin 160, so that the light-emitting chip connected to the pad group 120 can be driven at a constant current, so that the display module can achieve static scanning, reduce the moiré phenomenon and back pressure phenomenon, and at the same time ensure The brightness and reliability of the display module are relatively high.

The technical solution of this embodiment is to provide test terminals on the first substrate, the test terminals are connected to the driver chip, and the driver chip is connected to the pad group, so that the driver chip can be provided with a driver signal through the test terminals, and the driver chip and the circuit can be Carry out the test, so that when the test results are bad, the die-bonding of the light-emitting chip corresponding to the pad group at the defective position can be skipped in the subsequent die-bonding process, thereby reducing the waste of light-emitting chips and helping to reduce the cost of the display module. Cost of production. Or after the die is solidified, the driver chip drives the light-emitting chip connected to the pad group to emit light according to the driving signal, so that the substrate module integrates the driver chip to detect the display module, which is used to detect defects in the display module, so that the detection results can be used Eliminate defective products and improve the product yield of display modules. Moreover, when a fault occurs during the use of the display module, the test terminal can provide a detection signal for the display module for detection, which is helpful to determine the fault location and cause of the display module and facilitate the repair of the display module. Moreover, the driver chip is packaged between the first substrate and the second substrate to realize circuit integration and structural integration of the display module, which is beneficial to reducing the size of the display module. At the same time, the driver chip can be avoided from occupying space on the first substrate, and the density of the pad groups provided on the first substrate can be increased. When the substrate module is used to form a display module, the pad group is used to connect the light-emitting chips. When the density of the pad group is relatively large, the density of the light-emitting chips on the display module can be increased, thereby increasing the pixel density of the display module. , thereby improving the display performance of the display module. Moreover, the substrate module only needs two layers of substrates to realize the integration of the substrate module, which reduces the cost of the substrate module.

Based on the above technical solution, the first substrate 110 and the second substrate 150 are provided with connecting wires and conductive vias. The driver chip 140 is connected to the pad group 120, the test terminal 130 and the pins through the connecting wires and conductive vias. 160 connections.

The pad group 120 and the test terminals 130 are disposed on one side of the first substrate 110 , and the driver chip 140 is disposed on the other side of the first substrate 110 . By arranging connection lines and conductive vias on the first substrate 110 , the driver chip 140 can be connected to the pad group 120 and the test terminal 130 at least through the conductive vias and connection lines on the first substrate 110 . Similarly, the driver chip 140 and the pins 160 are respectively provided on both sides of the second substrate 150. By providing connection lines and conductive vias on the second substrate 150, the driver chip 140 can at least pass through the conductive holes on the second substrate 150. The vias and wires connect to pin 160. When the pins of the driver chip 140 are connected to the first substrate 110 through the conductive vias and connecting wires on the first substrate 220, the pins of the driver chip 140 are disposed on a side of the driver chip 140 close to the first substrate 110. The driver chip When the pins of 140 and 160 are connected, the pins of the driver chip 140 can pass through the connecting lines and/or conductive vias on the first substrate 110, and then through the connecting lines and/or conductive vias on the second substrate 150. hole connects to pin 160. The connection between the connection lines or conductive vias of the first substrate 110 and the connection lines or conductive vias of the second substrate 150 can be achieved through a silicon conductive via process or a solder paste welding process.

FIG. 2 is a schematic structural diagram of a first substrate provided by an embodiment of the present application. FIG. 3 is a schematic structural diagram of a first substrate provided by an embodiment of the present application. FIG. 4 is a schematic structural diagram of a first substrate provided by an embodiment of the present application. A schematic top view of the structure of the two substrates. FIG. 5 is a schematic view of the structure of the second substrate provided in an embodiment of the present application. As shown in Figures 2 to 5, the first substrate 110 is provided with a first conductive via C1 and a first connection line L1, and the second substrate 150 is provided with a second conductive via C2 and a second connection line L2. The pad group 120 includes a first electrode pad 121 and a second electrode pad 122; the driver chip 140 is connected to the test terminal 130 and the first electrode pad 121 through the first conductive via C1 and the first connection line L1. The driver chip 140 The driver chip 140 is connected to the second electrode pad 122 through the first conductive via C1, the first connection line L1 and the second connection line L2, and the driver chip 140 passes through the first connection line L1 and/or the first conductive via C1, and the second The conductive via C2 and/or the second connection line L2 are connected to the pin 160 .

When the pad group 120 is connected to the light-emitting chip, the first electrode pad 121 and the second electrode pad 122 are respectively connected to the first electrode and the second electrode of the light-emitting chip. For example, when the first electrode is the anode of the light-emitting chip and the second electrode is the cathode of the light-emitting chip, the first electrode pad 121 is the anode pad and the second electrode pad 122 is the cathode pad. When the first electrode is the cathode of the light-emitting chip and the second electrode is the anode of the light-emitting chip, the first electrode pad 121 is the cathode pad and the second electrode pad 122 is the anode pad. Multiple sets of bonding pad groups 120 may be provided on the first substrate 110 . Each group of bonding pad groups 120 is used to connect a corresponding light-emitting chip. Multiple groups of bonding pad groups 120 are connected to a common pole of multiple light-emitting chips, thereby reducing the number of customers. The number of solder joints on the circuit board simplifies the structure of the customer's circuit board. For example, as shown in FIGS. 2 and 3 , when the first electrode pads 121 and the driver chip 140 in the multiple pad groups 120 are respectively disposed on both sides of the first substrate 110 , the driver chip 140 can pass through the first conductive The via hole C1 and the first connection line L1 are directly connected to the first electrode pad 121 . At the same time, the second electrode pads 122 in the plurality of pad groups 120 can be connected to the common pole through the first connection line L1 on the first substrate 110 and the second connection line L2 on the second substrate 150, and then through the first connection line L2. The conductive via C1 and the first connection line L1 are connected to the driving chip 140 . When the second electrode pad 122 realizes common pole connection through the first connection line L1 on the first substrate 110 and the second connection line L2 on the second substrate 150, the number of pins 160 on the second substrate 150 can be reduced. This reduces the number of solder joints for the display module to be mounted on the customer's circuit board and simplifies the structure of the customer's circuit board. In addition, the circuit design on the first substrate 110 can be reduced, and the probability of the circuit being close to the edge of the substrate can be reduced to meet the circuit design requirements of the substrate in the subsequent cutting process.

Similarly, the test terminal 130 and the driver chip 140 are respectively disposed on both sides of the first substrate 110, so that the driver chip 140 is connected to the test terminal 130 through the first connection line L1 and the first conductive via C1.

In addition, the driver chip 140 and the pins 160 are respectively provided on both sides of the second substrate 150. The pins of the driver chip 140 can be connected by setting connection points on the first connection line L1 and/or the first conductive via C1, and then The cross connection with the pin 160 is achieved through the second connection line L2 and/or the second conductive via C2.

It should be noted that the connection modes between the driver chip 140 and the pad 120, the test terminal 130 and the pin 160 provided in Figures 2 to 5 are only an example. In other embodiments, when the arrangement of the first connection line L1, the first conductive via C1, the second connection line L2 and the second conductive via C2 changes, the driver chip 140 is connected to the pad 120 and the test terminal 130 respectively. The connection method with the pin 160 can be changed according to the arrangement method of the first connection line L1, the first conductive via C1, the second connection line L2 and the second conductive via C2, which is not limited here.

Continuing to refer to FIGS. 2 to 5 , the first connection line L1 includes a first sub-connection line L11 and a second sub-connection line L12 . The first sub-connection line L11 is provided on the side of the first substrate 110 close to the driving chip 140 . The sub-connection line L12 is provided on the side of the first substrate 110 away from the driving chip 140; part of the first conductive via C1 and the corresponding first electrode pad 121 and the second electrode pad 122 are located in the thickness direction of the first substrate 110. The vertical projections at least partially overlap; the driver chip 140 is connected to the first electrode pad 121 through the first conductive via C1 and the first sub-connection line L11; the driver chip 140 passes through the first conductive via C1 and the first sub-connection line L11 The second connection line L2 is connected to the second electrode pad 122; the driver chip 140 is connected to the test terminal 130 through the first conductive via C1 and at least one of the first sub-connection line L11 and the second sub-connection line L12.

The driver chip 140 has multiple pins, and some of the pins are connected to the pad group 120 for providing driving signals to the pad group 120 . When the pad group 120 is connected to the light-emitting chip, the light-emitting chip can be driven to emit light. Another part of the pins of the driver chip 140 is connected to the test terminal 130 and the pin 160 to realize the connection between the driver chip 140 and the outside. In this embodiment, the connection between the first electrode pad 121 and the second electrode pad 122 is taken as an example for description. When the vertical projections of the first conductive via C1 and the first electrode pad 121 in the thickness direction of the first substrate 110 at least partially overlap, the first electrode pad 121 and one end of the first conductive via C1 can be directly realized Electrical connection. When the vertical projections of the first conductive via C1 and the pins of the driver chip 140 in the thickness direction of the first substrate 110 do not overlap, the other end of the first conductive via C1 may be in contact with the first sub-connection line L11, The connection with the pins of the driver chip 140 is realized, thereby realizing the pin connection between the first electrode pad 121 and the driver chip 140 . When the vertical projections of the first conductive via C1 and the second electrode pad 122 in the thickness direction of the first substrate 110 at least partially overlap, the second electrode pad 122 and one end of the first conductive via C1 can be directly realized Electrical connection. When the vertical projections of the first conductive via C1 and the pins of the driver chip 140 in the thickness direction of the first substrate 110 do not overlap, the other end of the first conductive via C1 may be in contact with the first sub-connection line L11, The connection with the pins of the driver chip 140 is realized, thereby realizing the pin connection between the second electrode pad 122 and the driver chip 140 . At the same time, when the second electrode pad 122 is connected to at least two first sub-connection lines L11 through the plurality of first conductive vias C1, the second electrode pad 122 can connect at least two first sub-connection lines L11 through the second connection line L2. The sub-connection lines L11 are connected to realize the common pole connection of the plurality of second electrode pads 122, thereby reducing the circuit arrangement on the side of the first substrate 110 close to the driver chip 140, which is beneficial to simplifying the manufacturing process of the substrate.

In addition, the pins of the driver chip 140 and the test terminals 130 are respectively disposed on both sides of the first substrate 110. When the vertical projections of the first conductive via C1 and the test terminal 130 on the first substrate 110 at least partially overlap, the third A conductive via C1 is directly connected to the test terminal 130 . When the vertical projections of the first conductive via C1 and the pins of the driver chip 140 on the first substrate 110 do not overlap, the first conductive via C1 can be connected to the driver chip 140 through the first sub-connection line L11. The connection of the pins realizes the connection between the test terminal 130 and the pins of the driver chip 140 . When the vertical projections of the first conductive via C1 and the test terminal 130 on the first substrate 110 do not overlap, the first conductive via C1 can be connected to the test terminal 130 through the second sub-connection line L12. When the vertical projections of the first conductive via C1 and the pins of the driver chip 140 on the first substrate 110 do not overlap, the first conductive via C1 and the pins of the driver chip 140 pass through the first sub-connection line L11 connection, the first conductive via C1 is connected to the test terminal 130 through the second sub-connection line L12, thereby realizing the connection between the test terminal 130 and the pin of the driver chip 140, so that the driver chip 140 can be provided with the test terminal 130. The driving signal is used to drive the light-emitting chip connected to the pad group 120 to emit light through the driving chip 140, thereby realizing the detection of the display module.

For example, referring to FIGS. 2 to 3 , when the first substrate 110 includes three sets of pad groups 120 , and each group of pad groups 120 is used to connect light-emitting chips with different light-emitting colors, the driving chip 140 includes three groups with light-emitting colors. The pins to which the electrodes of the chip are connected are used for signal input. One pin in each group of pins is connected to the first electrode pad 121 in a group of pad groups 120 , and another pin in each group of pins is connected to the first electrode pad 121 in the group of pad groups 120 . Diode pad 122 is connected. The number of groups of pins connected to the electrodes of the light-emitting chip is equal to the number of groups of pad groups 120 , so that the light-emitting chips connected to each group of pad groups 120 are all connected to the driving chip 140 . For example, FIG. 2 and FIG. 3 exemplarily show four light areas, namely the zeroth light area, the first light area, the second light area and the third light area, and each light area includes The three sets of pad groups 120 are connected to three light-emitting chips, for example, a red light-emitting chip, a green light-emitting chip and a blue light-emitting chip respectively. The driver chip 140 includes three groups of pins connected to the electrodes of the light-emitting chip in each lamp area, and are respectively connected to the three groups of pad groups 120 in each lamp area. For example, the first electrode of the red light-emitting chip R in the zeroth lamp area passes through one of the first electrode pads 121 in the three sets of pad groups 120 in the zeroth lamp area and one of the first electrodes in the zeroth lamp area on the driver chip 140. The pin OR0 is connected, and the first electrode of the green light-emitting chip G in the zeroth lamp area passes through the other first electrode pad 121 of the three sets of pad groups 120 in the zeroth lamp area and the zeroth lamp on the driver chip 140 A pin OG0 in the area is connected, and the first electrode of the blue light-emitting chip B in the zeroth lamp area is connected to the driver chip 140 through another first electrode pad 121 of the three sets of pad groups 120 in the zeroth lamp area. Connect a pin OB0 in the zeroth lamp area. By analogy, the first electrodes of the red light-emitting chip R, the green light-emitting chip G and the blue light-emitting chip B in the first lamp area respectively pass through the first electrode pads 121 of the three sets of pad groups 120 in the first lamp area. Connect to the pins OR1, OG1 and OB1 in the first lamp area on the driver chip 140. The first electrodes of the red light-emitting chip R, the green light-emitting chip G and the blue light-emitting chip B in the second lamp area respectively pass through the first electrode pad 121 of the three sets of pad groups 120 in the second lamp area and the driver chip 140 Connect the pins OR2, OG2 and OB2 in the second light area. The first electrodes of the red light-emitting chip R, the green light-emitting chip G and the blue light-emitting chip B in the third lamp area respectively pass through the first electrode pad 121 of the three sets of pad groups 120 in the third lamp area and the driver chip 140 Connect the pins OR3, OG3 and OB3 in the third lamp area.

At the same time, the pins of the driver chip 140 may also include a first power input pin VDDR, a second power input pin VDDGB, a data input pin SDI, a clock signal input pin CLKI, a data output pin SDO, and a clock signal output pin. pin CLKO and ground pin AVSS. The vertical projections of the first conductive via C1 corresponding to the second power input pin VDDGB, the data output pin SDO and the ground pin AVSS and the test terminal 130 on the first substrate 110 do not overlap, so that the second power input tube The pin VDDGB, the data output pin SDO and the ground pin AVSS are all connected to the test terminal 130 through the first conductive via C1, the first sub-connection line L11 and the second sub-connection line L12. At least part of the vertical projection of the first conductive via C1 and the test terminal 130 corresponding to the first power input pin VDDR, the data input pin SDI, the clock signal input pin CLKI and the clock signal output pin CLKO on the first substrate 110 Overlap, so that the first power input pin VDDR, data input pin SDI, clock signal input pin CLKI and clock signal output pin CLKO are all connected to the test terminal 130 through the first conductive via C1 and the first sub-connection line L11 connect. The ground pin AVSS realizes the grounding of the driver chip 140 .

Continuing to refer to FIGS. 2 to 5 , the second connection line L2 is disposed on the side of the second substrate 150 close to the driver chip 140 . The vertical projection of the second conductive via C2 and the pin 160 in the thickness direction of the second substrate 150 is at least Partially overlapped.

When the vertical projection of the second conductive via C2 and the pin 160 in the thickness direction of the second substrate 150 at least partially overlaps, the second conductive via C2 can be directly connected to the pin 160 to avoid being far away from the second substrate 150 Arranging circuits on one side of the driver chip 140 is helpful to simplify the connection difficulty between the substrate module and external circuits. When the pin of the driver chip 140 is connected to the pin 160, the pin of the driver chip 140 can be connected to the test terminal 130 through the first connection line L1 and the first conductive via C1, and then through the first connection line L1 and the first conductive via C1. A connection point is added to at least one of the conductive vias C1, and then the connection point is connected to the side of the second substrate 150 close to the driver chip 140, and then through at least one of the second connection line L2 and the second conductive via C2. One is connected to the pin 160, so that the driver chip 140 can be provided with a driving signal through the pin 160, and the driver chip 140 drives the light-emitting chip connected to the pad group 120 to emit light, thereby realizing the display of the display module.

For example, referring to Figures 2 to 5, when the pins of the driver chip 140 include the first input power pin VDDR, the second input power pin VDDGB, the data input pin SDI, the clock signal input pin CLKI, and the data output When the pin SDO, the clock signal output pin CLKO and the ground pin AVSS are connected, the pin 160 includes the first power input pin VDDR1, the second power input pin VDDGB1, the data input pin SDI1, the clock signal input pin CLKI1, Data output pin SDO1, clock signal output pin CLKO1 and ground pin AVSS1. The first input power supply pin VDDR, the second input power supply pin VDDGB, the clock signal output pin CLKO, the data input pin SDI and the ground pin AVSS are extended through the first connection line L1 and then connected to the second connection line L2 , the vertical projections of the second connection line L2, the second conductive via C2 and the pin 160 in the thickness direction of the second substrate 150 at least partially overlap, then the second connection line L2 passes through the second conductive via C2 and the corresponding pin 160 connections. The data output pin SDO also extends through the first connection line L1, and then is directly connected to the corresponding pin 160 through the second conductive via C2. The clock signal input pin CLKI extends through the first connection line L1 and the first conductive via C1, and one end of the first connection line L1 at least partially overlaps with the vertical projection of the first conductive via C1 in the thickness direction of the first substrate 110 , and then directly connected to the corresponding pin 160 through the second conductive via C2.

The substrate module also includes a conductive structure 180. The conductive structure 180 is disposed in the filling layer 170. The driver chip 140 passes through the connection lines and/or conductive vias on the first substrate 110, the conductive structure 180 and the connection lines on the second substrate 150. and/or conductive vias to connect to pin 160.

When the driver chip 140 is disposed between the first substrate 110 and the second substrate 150, the distance between the first substrate 110 and the second substrate 150 is relatively far along the thickness direction of the first substrate 110. When the pins of the driver chip 140 extend through the first connection line L1, the pins of the driver chip 140 may be connected to the second surface 112 of the first substrate 110. The conductive structure 180 has electrical conductivity. The conductive structure 180 is in contact with the side of the first substrate 110 close to the driving chip 140 and the side of the second substrate 150 close to the driving chip 140 in the thickness direction of the first substrate 110 respectively. When the driving chip 140 is connected to the pin 160, The pins of the driving chip 140 can be electrically connected to the side of the second substrate 150 close to the driving chip 140 through the conductive structure 180, and then connected to the pins 160 through at least one of the second conductive via C2 and the second connection line L2. connection, it is possible to avoid setting the second connection line L2 with an excessive thickness for connecting the circuits on the first substrate 110, thereby reducing the risk of short circuit. At the same time, the conductive structure 180 has a supporting role, which can prevent the driver chip 140 disposed between the first substrate 110 and the second substrate 150 from being crushed, thereby ensuring the reliability of the substrate module. In addition, the conductive structure 180 has thermal conductivity, which is beneficial to ensuring the heat dissipation performance when the first substrate 110 and the second substrate 150 are connected.

For example, referring to FIGS. 1-5 , when the first input power pin VDDR, the second input power pin VDDGB, the clock signal output pin CLKO, the data input pin SDI and the ground pin AVSS of the driver chip 140 pass The first connection line L1 extends, and one end of the first connection line L1 at least partially overlaps the vertical projection of the conductive structure 180 in the thickness direction of the first substrate 110 , so that the first connection line L1 is connected to the conductive structure 180 . At the same time, the vertical projections of the conductive structure 180 and the second connection line L2 in the thickness direction of the second substrate 150 at least partially overlap, so that the conductive structure 180 is connected to the second connection line L2, the second connection line L2, and the second conductive via C2 At least partially overlapping with the vertical projection of the pin 160 in the thickness direction of the second substrate 150, the second connection line L2 is connected to the corresponding pin 160 through the second conductive via C2. The data output pin SDO also extends through the first connection line L1, and one end of the first connection line L1 at least partially overlaps the vertical projection of the conductive structure 180 in the thickness direction of the first substrate 110, so that the first connection line L1 and the conductive structure 180 overlap. Structure 180 connections. At the same time, the conductive structure 180 and the second conductive via C2 and the vertical projection of the pin 160 in the thickness direction of the second substrate 150 at least partially overlap, so that the conductive structure 180 can be directly connected to the corresponding pin 160 through the second conductive via C2 . The clock signal input pin CLKI extends through the first connection line L1 and the first conductive via C1, and one end of the first connection line L1 at least partially overlaps with the vertical projection of the first conductive via C1 in the thickness direction of the first substrate 110 , so that the first connection line L1 is connected to the first conductive via C1, and at the same time, the vertical projection of the first conductive via C1 and the conductive structure 180 in the thickness direction of the first substrate 110 at least partially overlaps, so that the first conductive via C1 Connected to conductive structure 180. At the same time, the conductive structure 180 at least partially overlaps with the second conductive via C2 and the vertical projection of the pin 160 in the thickness direction of the second substrate 150 , so that the conductive structure 180 can be directly connected to the corresponding pin 160 through the second conductive via C2 .

The conductive structure 180 can be formed before the filling layer 170. After the conductive structure 180 realizes the electrical connection between the first substrate 110 and the second substrate 150, the filling layer 170 is then provided to cover the conductive structure 180 and the driver chip 140 to protect the conductive structure. 180 and the driver chip 140 simultaneously realize circuit integration and structural integration of the substrate module, which is beneficial to reducing the size of the substrate module.

Alternatively, the conductive structure 180 may be an alloy ball, and when the alloy ball contacts the first substrate 110 and the second substrate 150, it is a point contact. When the alloy ball is soldered to the first substrate 110 and the second substrate 150 , the solder can be prevented from accumulating at the point contact position between the alloy ball and the first substrate 110 and the second substrate 150 , thereby ensuring that the first substrate 110 and the second substrate 150 The thickness of the alloy ball is uniform, and the probability of false welding when the alloy ball is welded to the first substrate 110 and the second substrate 150 can be reduced.

Continuing to refer to FIGS. 1 to 5 , when the first substrate 110 includes multiple sets of pad groups 120 , the driver chip 140 includes at least two sets of pins connected to the electrodes of the light-emitting chip, and each group of tubes is connected to the electrodes of the light-emitting chip. The pins are connected to a set of pad groups 120 and provide driving signals to the light-emitting chips connected to the set of pad groups 120 to drive the light-emitting chips to emit light. This allows one driver chip 140 to drive at least two light-emitting chips to emit light, thereby reducing the demand for driver chips 140 based on a determined number of light-emitting chips, thereby reducing the production cost of the display module.

Based on the above technical solution, the driver chip 140 includes a first power input pin VDDR and a second power input pin VDDGB; the pin 160 includes a first power input pin VDDR1 and a second power input pin VDDGB1. The power input pin VDDR is connected to the first power input pin VDDR1, and the second power input pin VDDGB is connected to the second power input pin VDDGB1.

The first power input pin VDDR1 is used to provide the first power supply to the driver chip 140 , and the second power input pin VDDGB1 is used to provide the second power supply to the driver chip 140 . When multiple sets of pad groups 120 are provided on the first substrate 110, and the multiple sets of pad groups 120 can be connected to light-emitting chips of different luminous colors, the first power input pin VDDR1 and the second power input pin VDDGB1 are used for driving The chip 140 provides different power supplies, so that the driver chip 140 can provide corresponding power supplies for light-emitting chips with different light-emitting colors, thereby saving energy consumption of light-emitting chips with relatively low power requirements. Exemplarily, three sets of pad groups 120 are provided on the first substrate 110, and each set of pad groups 120 is respectively connected to a red light-emitting chip, a blue light-emitting chip and a green light-emitting chip; the power requirement of the red light-emitting chip is 2.8V, and the power requirement of the green light-emitting chip is 2.8V. The power requirement of the blue light-emitting chip and the blue light-emitting chip is 3.8V. At this time, the red light-emitting chip can be provided with a low power supply, such as 2.8V, through the first power input pin VDDR1, and the green and blue light-emitting chips can be provided through the second power input pin VDDGB1. The chip provides a high power supply such as 3.8V, which can save the energy consumption of the red light-emitting chip.

Based on the above technical solution, the driver chip 140 also includes two ground pins AVSS, and the pin 160 also includes two ground pins AVSS1. The two ground pins AVSS are respectively connected to the two ground pins AVSS1.

The two ground pins AVSS can simultaneously provide a ground terminal for the pad group 120, that is, provide a ground terminal for the connected light-emitting chips through the pad group 120, thereby increasing the number of light-emitting chips that the driver chip 140 can load, which is conducive to further reducing The demand for driver chip 140. In addition, the two ground pins AVSS1 corresponding to the two ground pins AVSS can be symmetrically arranged on the side of the second substrate 150 away from the driver chip 140, which can facilitate the connection process between the substrate module and other external structures and help save layout. space. For example, two ground pins AVSS1 are connected in series, which can further facilitate the connection process between the base module and external structures on different sides, and further save layout space.

Continuing to refer to FIGS. 2 to 5 , a first mark 191 is also provided on the first substrate 110 . For example, the first mark 191 on the first substrate 110 may be disposed on a side of the first substrate 110 away from the driving chip 140 . The placement direction of the light-emitting chip 140 can be identified through the first mark 191 . In the same way, the second identification 192 may also be provided on the second substrate 150. For example, the second identification 192 on the second substrate 150 may be provided on a side of the second substrate 150 away from the driving chip 140. The second identification 192 The pins 160 on the side of the second substrate 150 away from the driver chip 140 can be identified, thereby avoiding incorrect pin placement during chip placement. Optionally, both the first logo 191 on the first substrate 110 and the second logo 192 on the second substrate 150 may be made of metal. The first identification 191 on the first substrate 110 may be formed in the same process as the pad group 120 and the test terminal 130 , and the second identification 192 on the second substrate 150 may be formed in the same process as the pins 160 .

Based on the above technical solutions, a copper clad layer 190 is provided on the side of the second substrate 150 away from the first substrate 110 . The copper clad layer 190 is used to increase heat dissipation on the side of the second substrate 150 away from the first substrate 110 . sex.

The copper clad layer 190 is a copper layer formed by spreading copper on the side of the second substrate 150 away from the first substrate 110 . When the copper clad layer 190 is disposed on the side of the second substrate 150 away from the first substrate 110, the copper clad layer 190 may be connected to the ground pin AVSS1. By arranging the copper-clad layer 190 on the side of the second substrate 150 away from the first substrate 110, the copper-clad layer 190 has better heat dissipation, thereby improving the heat dissipation of the substrate module and at the same time providing signals inside the substrate module. It provides additional shielding protection and noise suppression, and can reduce the amount of corrosives used in the production process of the substrate module, and can reduce the warping deformation of the substrate module caused by uneven stress distribution during the welding process of the substrate module. In addition, the material of the copper-clad layer 190 is metal, and the copper-clad layer 190 can be covered with an insulating material, and the insulating material exposes the pins to avoid patch short circuit.

Based on the above technical solutions, the material of the filling layer 170 is a thermally conductive insulating material.

During the display process of the display module, the driver chip 140 easily generates heat. By setting the material of the filling layer 170 as a thermally conductive insulating material, the heat generated by the driver chip 140 is dissipated through the filling layer 170 , thereby ensuring the life of the driver chip 140 .

An embodiment of the present application also provides a method for manufacturing a substrate module. The manufacturing method of the substrate module can be used to manufacture the substrate module provided by any embodiment of the present application. FIG. 6 is a flow chart of a method for manufacturing a substrate module provided by an embodiment of the present application. As shown in Figure 6, the method includes:

S10. Provide a first substrate 110. The pad group 120 and the test terminal 130 are provided on the first substrate 110;

S20. Set the driver chip 140 on the side of the first substrate 110 away from the pad group 120 and the test terminal 130, so that the pad group 120 and the test terminal 130 are connected to the driver chip 140 respectively;

S30. The second substrate 150 is provided on the side of the driver chip 140 away from the first substrate 110. The second substrate 150 is provided with pins 160 on the side away from the first substrate 110. The pins 160 are connected to the driver chip 140;

S40. Form a filling layer 170 between the first substrate 110 and the second substrate 150, and the filling layer 170 covers the driving chip 140.

In the technical solution of the embodiment of the present application, test terminals are provided on the first substrate, the test terminals are connected to the drive chip, and the drive chip is connected to the pad group, so that the drive signal can be provided to the drive chip through the test terminals, and the drive chip and The circuit is tested, so that when the test results are defective, the die-bonding of the light-emitting chip corresponding to the pad group at the defective position can be skipped in the subsequent die-bonding process, thereby reducing the waste of light-emitting chips and conducive to reducing the cost of display modules. production costs. Or after the die is solidified, the driver chip drives the light-emitting chip connected to the pad group to emit light according to the driving signal. After the display module is integrated with the driver chip, the display module is detected to detect defects in the display module, so that the detection results can be used Eliminate defective products and improve the product yield of display modules. Moreover, when a fault occurs during the use of the display module, the test terminal can provide a detection signal for the display module for detection, which is helpful to determine the fault location and cause of the display module and facilitate the repair of the display module. Moreover, the driver chip is packaged between the first substrate and the second substrate to realize circuit integration and structural integration of the display module, which is beneficial to reducing the size of the display module. At the same time, the driver chip can be avoided from occupying space on the first substrate, and the density of the pad groups provided on the first substrate can be increased. When the substrate module is used to form a display module, the pad group is used to connect the light-emitting chips. When the density of the pad group is relatively large, the density of the light-emitting chips on the display module can be increased, thereby increasing the pixel density of the display module. , thereby improving the display performance of the display module. Moreover, the substrate module only needs two layers of substrates to realize the integration of the substrate module, which reduces the cost of the substrate module.

Based on the above technical solution, the first substrate 110 and the second substrate 150 are provided with connection lines and conductive vias, and the pins 160 are connected to the driver chip 140, including:

A conductive structure 180 is provided between the first substrate 110 and the second substrate 150 so that the driver chip 140 passes through the connection lines and/or conductive vias on the first substrate 110, the conductive structure 180 and the connection lines on the second substrate 150 and /or conductive vias to connect to pin 160.

When there is a driving chip 140 between the first substrate 110 and the second substrate 150, the distance between the first substrate 110 and the second substrate 150 is relatively long along the thickness direction of the first substrate 110. At this time, the conductive structure 180 is arranged between the first substrate 110 and the second substrate 150, so that the conductive structure 180 is in contact with the first substrate 110 and the second substrate 150 respectively, so that the connection between the first substrate 110 and the second substrate 150 can be realized. wires and/or conductive via connections. For example, there may be multiple conductive structures 180, and the conductive structures 180 may be alloy balls.

After the conductive structure 180 is provided, when the conductive structure 180 is connected to the connection line on the first substrate 110, the side of the conductive structure 180 close to the first substrate 110 can be brought into contact with the connection line on the first substrate 110, and then the electrical connection is made. connect. When the conductive structure 180 is connected to the conductive via hole on the first substrate 110, the side of the conductive structure 180 close to the first substrate 110 can be brought into contact with the conductive via hole on the first substrate 110, and then electrical connection is made.

The driver chip 140 may be connected to the connection lines and/or conductive vias on the first substrate 110. After the conductive structure 180 is electrically connected to the connection lines and/or conductive vias on the first substrate 110, the second substrate 150 may be disposed. It is attached to the first substrate 110 so that the side of the conductive structure 180 close to the second substrate 150 is in contact with the connection lines and/or conductive vias on the second substrate 150, and then is electrically connected. At the same time, the connection lines and/or conductive vias on the second substrate 150 are connected to the pins 160 , so that the driver chip 140 passes through the connection lines and/or conductive vias on the first substrate 110 , the conductive structure 180 , and the second substrate 150 The connection lines and/or conductive vias on the connector are connected to pin 160 .

Based on the above technical solution, a conductive structure 180 is provided between the first substrate 110 and the second substrate 150, so that the driver chip 140 passes through the connection lines and/or conductive vias on the first substrate 110, the conductive structure 180, and The connection lines and/or conductive vias on the second substrate 150 are connected to the pins 160, including:

Coating first solder at the connection lines and/or conductive vias on the first substrate 110;

Solder the conductive structure 180 to the connection wire or conductive via hole on the first substrate 110 through the first solder;

The conductive structure 180 and the connection lines and/or conductive vias on the first substrate 110 can be electrically connected through a welding process. The first solder is applied to the connection lines and/or conductive via holes on the first substrate 110, and the conductive structure 180 is soldered to the connection lines or conductive via holes on the first substrate 110 through the first solder.

The conductive structure 180 and the connection lines or conductive via holes on the first substrate 110 are welded using a welding process at the first solder, so that the conductive structure 180 is electrically connected to the connection lines or conductive via holes on the first substrate 100. For example, when the first solder is coated on the connection lines on the first substrate 110, the conductive structure 180 and the connection lines on the first substrate may be soldered during soldering. When the first solder is coated on the conductive via hole on the first substrate 110, the conductive structure 180 and the conductive via hole on the first substrate 110 can be soldered during soldering.

Coating the second solder at the connection lines or conductive vias on the second substrate 150;

When the connection lines on the second substrate 150 are connected to the conductive structure 180, the second solder may be coated at the connection lines on the second substrate 150. When the conductive via hole on the second substrate 150 is connected to the conductive structure 180, the second solder may be coated at the conductive via hole on the second substrate 150. The second solder may be the same as or different from the first solder.

The first substrate 110 and the second substrate 150 with the conductive structure 180 soldered are bonded together, and the conductive structure 180 is soldered to the connection line or conductive via hole on the second substrate 150 through the second solder.

When forming the substrate module, the positions of the structures on the first substrate 110 and the structures on the second substrate 150 have a corresponding relationship. After the conductive structure 180 is fixedly connected to the connection lines and/or conductive vias on the first substrate 110 , the first substrate 110 and the second substrate 150 are attached to each other, so that the structure on the second substrate 150 is aligned with the first substrate 110 The relative positional relationship of the structures meets the requirements of the substrate module. At this time, the connection lines and/or conductive vias on the second substrate 150 are in contact with the conductive structure 180 .

A welding process is used to weld the conductive structure 180 and the connection lines or conductive vias on the second substrate 150 at the second solder, so that the conductive structure 180 is electrically connected to the connection lines or conductive vias on the second substrate 150 . For example, when the second solder is coated on the connection lines on the second substrate 150, the conductive structure 180 and the connection lines on the second substrate 150 may be soldered during soldering. When the second solder is coated on the conductive via hole on the second substrate 150, the conductive structure 180 and the conductive via hole on the second substrate 150 can be soldered during soldering.

Based on the above technical solution, a conductive structure 180 is provided between the first substrate 110 and the second substrate 150, so that the driver chip 140 passes through the connection lines and/or conductive vias on the first substrate 110, the conductive structure 180, and The connection lines and/or conductive vias on the second substrate 150 are connected to the pins 160, including:

Arrange the conductive structure 180 at the connection line or conductive via hole on the first substrate 110;

When the connection lines on the first substrate 110 are connected to the conductive structure 180 , the conductive structure 180 can be disposed at the connection lines on the first substrate 110 so that the conductive structure 180 contacts the connection lines on the first substrate 110 . When the conductive via hole on the first substrate 110 is connected to the conductive structure 180 , the conductive structure 180 can be disposed at the conductive via hole on the first substrate 110 so that the conductive structure 180 is in contact with the conductive via hole on the first substrate 110 .

A temporary carrier is provided on the side of the conductive structure 180 away from the first substrate 110 to fix the conductive structure 180 on the first substrate 110;

The temporary carrier plate can be a temporary pressure plate. The conductive structure 180 can be fixed on the first substrate 110 by placing a temporary carrier on a side of the conductive structure 180 away from the first substrate 110 so that the temporary carrier exerts pressure on the conductive structure 180 .

Electroplating conductive material at the connection position of the connection line or conductive via hole between the conductive structure 180 and the first substrate 110 to connect the conductive structure 180 to the connection line or conductive via hole on the first substrate 110;

The conductive material can be metal. After the conductive structure 180 is fixed and in contact with the connection lines or conductive via holes on the first substrate 110, an electroplating process is used to perform electroplating on the contact area between the conductive structure 180 and the connection lines or conductive via holes on the first substrate 110, so that The conductive material connects the conductive structure 180 and the connection lines or conductive vias on the first substrate 110 to achieve electrical connection.

Remove the temporary carrier board, and attach the first substrate 110 and the second substrate 150 connected to the conductive structure 180;

After the conductive structure 180 is connected to the connection lines or conductive vias on the first substrate 110, the temporary carrier board is removed.

The first substrate 110 connected with the conductive structure 180 is attached to the second substrate 150 so that the relative positional relationship between the structure on the second substrate 150 and the structure on the first substrate 110 meets the needs of the substrate module. At this time, the second The connection lines and/or conductive vias on the substrate 150 are in contact with the conductive structure 180 .

Conductive material is electroplated at the connection position between the conductive structure 180 and the connection lines or conductive via holes on the second substrate 150 to connect the conductive structure 180 to the connection lines and/or conductive via holes on the second substrate 150 .

The conductive material can also be metal. An electroplating process is used to perform electroplating on the contact area between the conductive structure 180 and the connection lines or conductive via holes on the second substrate 150, so that the conductive material connects the conductive structure 180 and the connection lines or conductive via holes on the second substrate 150. For example, when the connection lines on the second substrate 150 are in contact with the conductive structure 180, plating is performed on the contact area between the connection lines on the second substrate 150 and the conductive structure 180, so that the conductive material connects the conductive structure 180 and the first conductive structure 180. The connection lines on the second substrate 150. When the conductive via hole on the second substrate 150 is in contact with the conductive structure 180, electroplating is performed on the contact area between the conductive via hole on the second substrate 150 and the conductive structure 180, so that the conductive material connects the conductive structure 180 and the second substrate. Conductive vias on 150. When a part of the conductive structure 180 is in contact with the connection line on the second substrate 150 and another part of the conductive structure 180 is in contact with the conductive via hole on the second substrate 150, an electroplating process is used to connect the part of the conductive structure 180 to the second substrate 150. The contact area of the line is electroplated, and an electroplating process is used to perform electroplating on the contact area of another part of the conductive structure 180 and the conductive via hole on the second substrate 150, so that the conductive material connects a part of the conductive structure 180 and the connection line on the second substrate 150 and connecting another part of the conductive structure 180 to the conductive via hole on the second substrate 150 .

An embodiment of the present application also provides a display module. Figure 7 is a schematic structural diagram of a display module provided by an embodiment of the present application. As shown in Figure 7, the display module includes a light-emitting chip 200 and a substrate module 100 provided by any embodiment of the present application; the light-emitting chip 200 is disposed on On the pad group 120 of the first substrate 110, the light emitting chip 200 is connected to the pad group 120 on the first substrate 110.

The light-emitting chip 200 may be an LED chip. By disposing the light-emitting chip 200 on the pad set 120 and connecting the light-emitting chip 200 to the driving chip 140 through the pad set 120, the light-emitting chip 200 can be driven to emit light through the driving chip 140 in the substrate module 100.

In addition, the display module may also include an encapsulation layer for plastic packaging of the light-emitting chip 200 and the substrate module 100 to protect the light-emitting chip 200 and the substrate module 100 and increase the life of the display module.

In the technical solution of this embodiment, the display module includes the substrate module provided by any embodiment of this application, which will not be described again here.

Based on the above technical solution, the light-emitting chip 200 includes a first light-emitting chip, a second light-emitting chip, and a third light-emitting chip of different light-emitting colors. The first light-emitting chip, the second light-emitting chip, and the third light-emitting chip all have first electrodes. and a second electrode; the first electrodes of the first light-emitting chip and the second light-emitting chip are connected to the first power input pin of the driver chip 140 through the correspondingly connected pad groups 120, and the first electrode of the third light-emitting chip is connected through the corresponding The pad group 120 is connected to the second power input pin of the driver chip 140; the second electrodes of the first light-emitting chip, the second light-emitting chip and the third light-emitting chip are connected to the ground of the driver chip 140 through the correspondingly connected pad group 120. Pin connections.

When the light-emitting chip 200 includes a first light-emitting chip, a second light-emitting chip and a third light-emitting chip with three different light-emitting colors, the first substrate 110 may be provided with three sets of pad groups 120, and the first one in each group of pad groups 120 The electrode pads 121 are respectively connected to the first electrodes of the first light-emitting chip, the second light-emitting chip and the third light-emitting chip. The second electrode pads 122 in each group of pad groups 120 are respectively connected to the first light-emitting chip, the second light-emitting chip and the first electrodes of the third light-emitting chip. The chip is connected to the second electrode of the third light-emitting chip. Light-emitting chips 200 with different light-emitting colors may have different power requirements. The first power input pin is connected to the pad 121 corresponding to the first electrode of the first light-emitting chip and the second light-emitting chip for passing through the corresponding pad 121 A first input power supply is provided to the first electrodes of the first light-emitting chip and the second light-emitting chip. The second power input pin is connected to the pad 121 corresponding to the first electrode of the third light-emitting chip, and is used to provide the second input power to the first electrode of the third light-emitting chip through the corresponding pad group. By allowing light-emitting chips with different light-emitting colors to input corresponding power supplies, the energy consumption of light-emitting chips with relatively low power requirements can be saved.

For example, the first light-emitting chip may be a blue light-emitting chip B, the second light-emitting chip may be a green light-emitting chip G, and the third light-emitting chip may be a red light-emitting chip R. The power requirement of the red light-emitting chip R is 2.8V. The power requirements of the green and blue light-emitting chips B and G are 3.8V. At this time, the second input power can be provided for the red light-emitting chip R through the second power input pin, and the green and blue light-emitting chips can be provided through the first power input pin. The light-emitting chips B and G provide the second input power supply, which can save the energy consumption of the red light-emitting chip R. At the same time, the second electrodes of the red light-emitting chip R, the green light-emitting chip G and the blue light-emitting chip B are connected to the ground pins of the driving chip 140 through the correspondingly connected pads 122, so that the ground pins of the red light-emitting chip R, the green light-emitting chip B The second electrodes of chip G and blue light-emitting chip B provide ground terminals. For example, the driver chip 140 may include two ground pins, and the two ground pins may provide ground terminals for the pad group at the same time, thereby increasing the number of light-emitting chips that the driver chip can load and further reducing the load of the driver chip. demand.

Based on the above multiple technical solutions, the light-emitting chip 200 is a flip chip.

When the light-emitting chip is a flip chip, the connection process between the light-emitting chip and the first substrate can be simplified, which is beneficial to simplifying the manufacturing process of the display module.

Claims (19)

1. A substrate module including:

   A first substrate, a pad group and a test terminal are provided on the first substrate;

   A driver chip, disposed on a side of the first substrate away from the pad group and the test terminal, and the driver chip is connected to the pad group and the test terminal respectively;

   The second substrate is disposed on the side of the driver chip away from the first substrate. The second substrate is provided with pins on the side away from the first substrate. The driver chip is connected to the pins. ;

   A filling layer is disposed between the first substrate and the second substrate and covers the driver chip.
2. The substrate module according to claim 1, wherein the first substrate and the second substrate are provided with connection lines and conductive via holes, and the driver chip passes through the connection lines and the conductive via holes respectively. Connect to the pad set, the test terminal and the pin.
3. The substrate module according to claim 2, wherein the first substrate is provided with a first conductive via hole and a first connection line, and the second substrate is provided with a second conductive via hole and a second connection line. , the pad group includes a first pole pad and a second pole pad;

   The driver chip is connected to the test terminal and the first electrode pad through the first conductive via hole and the first connection line;

   The driver chip is connected to the second electrode pad through the first conductive via, the first connection line and the second connection line;

   The driver chip communicates with the pin through at least one of the first connection line and the first conductive via hole, and at least one of the second connection line and the second conductive via hole. connect.
4. The substrate module according to claim 3, wherein the first connection line includes a first sub-connection line and a second sub-connection line, the first sub-connection line is disposed on the first substrate close to the driving On one side of the chip, the second sub-connection line is provided on the side of the first substrate away from the driver chip;

   The vertical projections of part of the first conductive via holes and the first electrode pads and the second electrode pads corresponding to the first conductive via holes in the thickness direction of the first substrate at least partially overlap. ;

   The driver chip is connected to the first electrode pad through the first conductive via hole and the first sub-connection line. The driver chip is connected to the first electrode pad through the first conductive via hole and the first sub-connection line. and the second connection line is connected to the second electrode pad;

   The driver chip is connected to the test terminal through the first conductive via hole and at least one of the first sub-connection line and the second sub-connection line.
5. The substrate module according to claim 3, wherein the second connection line is provided on a side of the second substrate close to the driver chip, and the second conductive via hole and the pin are on the Vertical projections in the thickness direction of the second substrate at least partially overlap.
6. The substrate module according to claim 2, further comprising a conductive structure disposed in the filling layer, and the driver chip passes through at least one of the connecting lines and conductive vias on the first substrate. 1. The conductive structure and at least one of the connection lines and conductive vias on the second substrate are connected to the pins.
7. The substrate module of claim 6, wherein the conductive structure is an alloy ball.
8. The substrate module according to claim 1, wherein the driver chip includes a first power input pin and a second power input pin, and the pins include a first power input pin and a second power input pin. , the first power input pin is connected to the first power input pin, and the second power input pin is connected to the second power input pin.
9. The substrate module according to claim 8, wherein the driver chip further includes two ground pins, and the two ground pins are connected to the two ground pins. The pins are connected in one-to-one correspondence.
10. The substrate module of claim 9, wherein the two ground pins are connected in series.
11. The substrate module according to claim 1, wherein a copper clad layer is provided on a side of the second substrate away from the first substrate, and the copper clad layer is used to increase the heat dissipation performance of the second substrate.
12. The substrate module according to claim 1, wherein the material of the filling layer is a thermally conductive insulating material.
13. A method for manufacturing a substrate module, including:

    Provide a first substrate on which a pad group and a test terminal are provided;

    A driver chip is provided on the side of the first substrate away from the pad group and the test terminal, and the pad group and the test terminal are respectively connected to the driver chip;

    A second substrate is provided on the side of the driving chip away from the first substrate, and pins are provided on the side of the second substrate away from the first substrate, and the pins are connected to the driving chip;

    A filling layer is formed between the first substrate and the second substrate, and the filling layer covers the driving chip.
14. The manufacturing method of a substrate module according to claim 13, wherein connecting lines and conductive vias are provided on the first substrate and the second substrate, and the pins are connected to the driver chip, including:

    A conductive structure is provided between the first substrate and the second substrate, allowing the driver chip to pass through at least one of the connection lines and conductive via holes on the first substrate, the conductive structure and the At least one of the connection line and the conductive via hole on the second substrate is connected to the pin.
15. The manufacturing method of a substrate module according to claim 14, wherein a conductive structure is provided between the first substrate and the second substrate, so that the driver chip passes through the connecting lines on the first substrate and At least one of the conductive vias, the conductive structure and at least one of the connection lines and the conductive vias on the second substrate are connected to the pins, including:

    Coating first solder on at least one of the connection lines and conductive vias on the first substrate;

    Solder the conductive structure to the connecting wire or conductive via hole on the first substrate through the first solder;

    Coating a second solder on at least one of the connection lines and conductive vias on the second substrate;

    The first substrate with the conductive structure soldered is bonded to the second substrate, and the conductive structure is soldered to the connecting wire or conductive via hole on the second substrate through the second solder.
16. The manufacturing method of a substrate module according to claim 14, wherein a conductive structure is provided between the first substrate and the second substrate, so that the driver chip passes through the connecting lines on the first substrate and At least one of the conductive vias, the conductive structure and at least one of the connection lines and the conductive vias on the second substrate are connected to the pins, including:

    disposing the conductive structure at the connection line or conductive via hole on the first substrate;

    A temporary carrier plate is provided on the side of the conductive structure away from the first substrate to fix the conductive structure on the first substrate;

    electroplating a conductive material at the connecting position of the conductive structure and the connection line or conductive via hole of the first substrate, so that the conductive structure is connected to the connection line or conductive via hole on the first substrate;

    Remove the temporary carrier board and attach the first substrate connected to the conductive structure to the second substrate;

    Conductive material is electroplated at the connection position between the conductive structure and the connection line or conductive via hole of the second substrate, so that the conductive structure is connected to at least one of the connection line and conductive via hole on the second substrate. connect.
17. A display module, comprising a light-emitting chip and the substrate module according to any one of claims 1-12, the light-emitting chip being disposed on the pad group of the first substrate, the light-emitting chip being in contact with the third A pad group connection on a substrate.
18. The display module according to claim 17, wherein the light-emitting chip includes a first light-emitting chip, a second light-emitting chip, and a third light-emitting chip of different light-emitting colors, and the first light-emitting chip, the second light-emitting chip, and the third light-emitting chip Each of the three-shot chips has a first electrode and a second electrode;

    The first electrodes of the first light-emitting chip and the second light-emitting chip are connected to the first power input pin of the driver chip through the correspondingly connected pad groups, and the first electrode of the third light-emitting chip The correspondingly connected pad group is connected to the second power input pin of the driver chip;

    The second electrodes of the first light-emitting chip, the second light-emitting chip and the third light-emitting chip are connected to the ground pin of the driver chip through the correspondingly connected pad groups.
19. The display module according to claim 17, wherein the light-emitting chip is a flip chip.

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