WO2023221276A1 - 一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器 - Google Patents

一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器 Download PDF

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Publication number
WO2023221276A1
WO2023221276A1 PCT/CN2022/105179 CN2022105179W WO2023221276A1 WO 2023221276 A1 WO2023221276 A1 WO 2023221276A1 CN 2022105179 W CN2022105179 W CN 2022105179W WO 2023221276 A1 WO2023221276 A1 WO 2023221276A1
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capacitor
terminal
inductor
tube
nmos tube
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PCT/CN2022/105179
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English (en)
French (fr)
Inventor
徐志伟
李泉涌
陈姜波
杜立康
王圣杰
宋春毅
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浙江大学
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Priority to US18/335,102 priority Critical patent/US20230378909A1/en
Publication of WO2023221276A1 publication Critical patent/WO2023221276A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details

Definitions

  • the present invention relates to the technical field of integrated circuits, and in particular to a flip complementary low-noise voltage-controlled oscillator that reduces flicker noise and upconverts the frequency.
  • VCO voltage-controlled oscillator
  • phase noise can be added to the classic Leeson noise model, which is defined as follows:
  • K VCO the latter term can be ignored, and the leeson noise of the former term dominates and determines the phase noise of the oscillator.
  • K VCO will be very large, which means that the VCO has high voltage/frequency gain, the latter term cannot be ignored, and low-frequency noise such as flicker noise will be larger The effect of oscillator phase noise.
  • the traditional complementary structure VCO circuit has poor upconversion ability to suppress low-frequency noise such as flicker noise, resulting in poor overall phase noise.
  • the purpose of the present invention is to achieve low-noise millimeter wave signal output in radar technology applications with large K VCO without increasing circuit complexity.
  • the present invention proposes a flip complementary low-noise voltage-controlled oscillator that reduces flicker noise and up-converts the frequency.
  • a circuit that can generate IQ quadrature differential signals is further proposed, as well as a flipping complementary low-noise voltage-controlled oscillator in the form of substrate injection and the corresponding IQ quadrature differential generation signal circuit.
  • the low-noise voltage controlled oscillator includes: inductor L1, inductor L2, inductor L3, capacitor array C1, variable capacitor C2, capacitor C3, capacitor C4, variable capacitor C5, capacitor array C6, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, as well as ports OUTP and port OUTN.
  • the inductor L1 is connected in parallel with the capacitor array C1 and the variable capacitor C2.
  • the NMOS tube M1 and the NMOS tube M2 form an NMOS mutually coupled pair.
  • the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M2 and then connected to the a terminal of the inductor L1.
  • NMOS tube M2 The drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then connected to the b terminal of inductor L1. Inductor L3, variable capacitor C5, and capacitor array C6 are connected in parallel. PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair.
  • the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the a terminal of inductor L3.
  • the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then connected to the b terminal of inductor L3.
  • the NMOS tube M1 is connected to the source level of NMOS tube M2 and then connected to the a terminal of inductor L2.
  • the source levels of PMOS tube M3 and PMOS tube M4 are connected to the b terminal of inductor L2.
  • the a terminal of capacitor C3 is connected to the terminal a of NMOS tube M1.
  • the drain is connected, the b terminal of capacitor C3 is connected to the drain of PMOS tube M3, the a terminal of capacitor C4 is connected to the drain of NMOS tube M2, the b terminal of capacitor C4 is connected to the drain of PMOS tube M4, the center of inductor L1
  • the tap is connected to the power supply, the center tap of the inductor L3 is connected to the ground, the port OUTP is connected to the drain of the NMOS tube M1, the port OUTN is connected to the drain of the NMOS tube M2, and the differential signal flows out from the port OUTP and the port OUTN.
  • NMOS tube M1 is the same as NMOS tube M2
  • capacitor array C1 is the same as capacitor array C6
  • variable capacitor C2 is the same as variable capacitor C5
  • capacitor C3 is the same as capacitor C4
  • PMOS tube M3 is the same as PMOS tube M4.
  • variable capacitor includes: transistor variable capacitors C1' and C2', capacitors C3' and C4', resistors R1 and R2, and four ports VOP, VON, VCTRL and VIBIAS.
  • the port VOP is connected to the a terminal of the capacitor C3'
  • the b terminal of the capacitor C3' is connected to the b terminal of the resistor R1 and the a terminal of the transistor variable capacitor C1'
  • the port VON is connected to the a terminal of the capacitor C4'
  • the b terminal is connected to the b terminal of the resistor R2 and the a terminal of the transistor variable capacitor C2'.
  • the port VCTRL is connected to the b terminal of the transistor variable capacitor C1' and the b terminal of the transistor variable capacitor C2', and the port VIBIAS is connected to the a terminal of the resistor R1 and the a terminal of the resistor R2.
  • Transistor variable capacitors C1’ and C2’ are the same, capacitors C3’ and C4’ are the same, and resistors R1 and R2 are the same.
  • the flip complementary low-noise voltage controlled oscillator circuit that generates IQ differential quadrature signals includes: inductor L1, inductor L2, inductor L3, inductor L4, inductor L5, inductor L6, capacitor array C1, variable Capacitor C2, capacitor C3, capacitor C4, variable capacitor C5, capacitor array C6, capacitor array C7, variable capacitor C8, capacitor C9, capacitor C10, variable capacitor C11, capacitor array C12, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, PMOS tube M7, PMOS tube M8, and ports OUTP_I, port OUTN_I, port OUTP_Q, and port OUTN_Q.
  • the inductor L1 is connected in parallel with the capacitor array C1 and the variable capacitor C2.
  • the NMOS tube M1 and the NMOS tube M2 form an NMOS mutually coupled pair.
  • the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M2 and then connected to the a terminal of the inductor L1.
  • the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then connected to the b terminal of inductor L1.
  • Inductor L3, variable capacitor C5, and capacitor array C6 are connected in parallel.
  • PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair.
  • the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the a terminal of inductor L3.
  • the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then connected to the b terminal of inductor L3.
  • the NMOS tube M1 is connected to the source level of NMOS tube M2 and then connected to the a terminal of inductor L2.
  • the source levels of PMOS tube M3 and PMOS tube M4 are connected to the b terminal of inductor L2.
  • the a terminal of capacitor C3 is connected to the terminal a of NMOS tube M1.
  • the drain is connected, the b terminal of capacitor C3 is connected to the drain of PMOS tube M3, the a terminal of capacitor C4 is connected to the drain of NMOS tube M2, the b terminal of capacitor C4 is connected to the drain of PMOS tube M4, the center of inductor L1
  • the tap is connected to the power supply, the center tap of the inductor L3 is connected to the ground, the port OUTP_I is connected to the drain of the NMOS tube M1, the port OUTN_I is connected to the drain of the NMOS tube M2, and the I differential signal flows out from the port OUTP_I and the port OUTN_I.
  • the inductor L4 is connected in parallel with the capacitor array C7 and the variable capacitor C8.
  • the NMOS tube M5 and the NMOS tube M6 form an NMOS mutually coupled pair.
  • the drain of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and then connected to the a terminal of the inductor L4.
  • the drain of NMOS tube M6 is connected to the gate of NMOS tube M5 and then connected to the b terminal of inductor L4.
  • Inductor L6 is connected in parallel with variable capacitor C11 and capacitor array C12.
  • PMOS tube M7 and PMOS tube M8 form a PMOS mutual coupling pair.
  • the drain of PMOS tube M7 is connected to the gate of PMOS tube M8 and then connected to the a terminal of inductor L6.
  • the drain of PMOS tube M8 is connected to the gate of PMOS tube M7 and then connected to the b terminal of inductor L6.
  • the NMOS tube The source levels of M5 and NMOS tube M6 are connected and then connected to the a-end of the inductor L5.
  • the source levels of PMOS tube M7 and PMOS tube M8 are connected and then connected to the b-end of the inductor L5.
  • the a-end of the capacitor C9 is connected to the a-end of the NMOS tube M5.
  • the drain is connected, the b terminal of capacitor C9 is connected to the drain of PMOS tube M7, the a terminal of capacitor C10 is connected to the drain of NMOS tube M6, the b terminal of capacitor C10 is connected to the drain of PMOS tube M8, the center of inductor L4
  • the tap is connected to the power supply, the center tap of the inductor L6 is connected to the ground, the port OUTP_Q is connected to the drain of the NMOS tube M5, the port OUTN_Q is connected to the drain of the NMOS tube M6, and the Q differential signal flows out from the port OUTP_Q and the port OUTN_Q.
  • Inductor L2 and inductor L5 are coupled to each other.
  • NMOS tube M1, NMOS tube M2, NMOS tube M5, and NMOS tube M6 are the same.
  • Capacitor array C1, capacitor array C6, capacitor array C7, and capacitor array C12 are the same.
  • Variable capacitor C2, variable capacitor C5, and variable capacitor C8 can be The variable capacitor C11 is the same, the capacitor C3, the capacitor C4, the capacitor C9, and the capacitor C10 are the same, and the PMOS tube M3, PMOS tube M4, PMOS tube M7, and PMOS tube M8 are the same.
  • the substrate injection type flipping complementary low-noise voltage-controlled oscillator that reduces flicker noise and up-converts the frequency, which includes: inductor L1, inductor L2, inductor L3, capacitor array C1, variable capacitor C2, capacitor C3, Capacitor C4, variable capacitor C5, capacitor array C6, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, and ports OUTP and OUTN.
  • Inductor L1, capacitor array C1, and variable capacitor C2 are connected in parallel.
  • NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair.
  • the substrate of NMOS tube M1 is connected to the gate of NMOS tube M1, and the substrate of NMOS tube M2 is connected to the NMOS tube.
  • the gate of M2 is connected, the drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then connected to the a terminal of inductor L1, the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then to the terminal a of inductor L1.
  • the b terminal is connected, the inductor L3 and the variable capacitor C5, the capacitor array C6 are connected in parallel, the PMOS tube M3 and the PMOS tube M4 form a PMOS mutual coupling pair, the substrate of the PMOS tube M3 is connected to the gate of the PMOS tube M3, and the lining of the PMOS tube M4
  • the bottom is connected to the gate of PMOS tube M4, the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the a terminal of inductor L3, the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then Connected to the b end of the inductor L3, the source levels of the NMOS transistors M1 and NMOS transistors M2 are connected and then connected to the a end of the inductor L2, the source levels of the PMOS transistors M3 and PMOS transistors M4 are connected and then connected to the b end of the inductor L2.
  • the a terminal of capacitor C3 is connected to the drain of NMOS tube M1, the b terminal of capacitor C3 is connected to the drain of PMOS tube M3, the a terminal of capacitor C4 is connected to the drain of NMOS tube M2, and the b terminal of capacitor C4 is connected to the drain of PMOS tube M2.
  • the drain of M4 is connected, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is connected to the ground, the port OUTP is connected to the drain of the NMOS tube M1, the port OUTN is connected to the drain of the NMOS tube M2, the differential signal is from the port OUTP, Port OUTN flows out.
  • NMOS tube M1 is the same as NMOS tube M2
  • capacitor array C1 is the same as capacitor array C6
  • variable capacitor C2 is the same as variable capacitor C5
  • capacitor C3 is the same as capacitor C4
  • PMOS tube M3 is the same as PMOS tube M4.
  • the flip complementary low-noise voltage controlled oscillator circuit that generates IQ differential quadrature signals in the form of substrate injection includes: inductor L1, inductor L2, inductor L3, inductor L4, inductor L5, inductor L6, capacitor Array C1, variable capacitor C2, capacitor C3, capacitor C4, variable capacitor C5, capacitor array C6, capacitor array C7, variable capacitor C8, capacitor C9, capacitor C10, variable capacitor C11, capacitor array C12, NMOS tube M1 , NMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, PMOS tube M7, PMOS tube M8, and port OUTP_I, port OUTN_I, port OUTP_Q, port OUTN_Q.
  • Inductor L1, capacitor array C1, and variable capacitor C2 are connected in parallel.
  • NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair.
  • the substrate of NMOS tube M1 is connected to the gate of NMOS tube M1, and the substrate of NMOS tube M2 is connected to the NMOS tube.
  • the gate of M2 is connected, the drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then connected to the a terminal of inductor L1, the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then to the terminal a of inductor L1.
  • the b terminal is connected, the inductor L3 and the variable capacitor C5, the capacitor array C6 are connected in parallel, the PMOS tube M3 and the PMOS tube M4 form a PMOS mutual coupling pair, the substrate of the PMOS tube M3 is connected to the gate of the PMOS tube M3, and the lining of the PMOS tube M4
  • the bottom is connected to the gate of PMOS tube M4, the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the a terminal of inductor L3, the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then Connected to the b end of the inductor L3, the source levels of the NMOS transistors M1 and NMOS transistors M2 are connected and then connected to the a end of the inductor L2, the source levels of the PMOS transistors M3 and PMOS transistors M4 are connected and then connected to the b end of the inductor L2.
  • the a terminal of capacitor C3 is connected to the drain of NMOS tube M1, the b terminal of capacitor C3 is connected to the drain of PMOS tube M3, the a terminal of capacitor C4 is connected to the drain of NMOS tube M2, and the b terminal of capacitor C4 is connected to the drain of PMOS tube M2.
  • the drain of M4 is connected, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is connected to the ground, the port OUTP_I is connected to the drain of the NMOS tube M1, the port OUTN_I is connected to the drain of the NMOS tube M2, and the I differential signal is connected from the port OUTP_I, port OUTN_I outflow.
  • Inductor L4 is connected in parallel with capacitor array C7 and variable capacitor C8.
  • NMOS tube M5 and NMOS tube M6 form an NMOS mutual coupling pair.
  • the substrate of NMOS tube M5 is connected to the gate of NMOS tube M5, and the substrate of NMOS tube M6 is connected to the NMOS tube.
  • the gate of M6 is connected, the drain of NMOS tube M5 is connected to the gate of NMOS tube M6 and then connected to the a terminal of inductor L4, the drain of NMOS tube M6 is connected to the gate of NMOS tube M5 and then to the terminal a of inductor L4.
  • the b terminal is connected, the inductor L6 and the variable capacitor C11, the capacitor array C12 are connected in parallel, the PMOS tube M7 and the PMOS tube M8 form a PMOS mutual coupling pair, the substrate of the PMOS tube M7 is connected to the gate of the PMOS tube M7, and the substrate of the PMOS tube M8
  • the bottom is connected to the gate of PMOS tube M8, the drain of PMOS tube M7 is connected to the gate of PMOS tube M8 and then connected to the a terminal of inductor L6, the drain of PMOS tube M8 is connected to the gate of PMOS tube M7 and then It is connected to the b end of the inductor L6, the source levels of the NMOS tube M5 and the NMOS tube M6 are connected and then connected to the a end of the inductor L5, the source levels of the PMOS tube M7 and PMOS tube M8 are connected and then connected to the b end of the inductor L5.
  • the a terminal of capacitor C9 is connected to the drain of NMOS tube M5, the b terminal of capacitor C9 is connected to the drain of PMOS tube M7, the a terminal of capacitor C10 is connected to the drain of NMOS tube M6, and the b terminal of capacitor C10 is connected to the drain of PMOS tube M6.
  • the drain of M8 is connected, the center tap of the inductor L4 is connected to the power supply, the center tap of the inductor L6 is connected to the ground, the port OUTP_Q is connected to the drain of the NMOS tube M5, the port OUTN_Q is connected to the drain of the NMOS tube M6, the Q differential signal is connected from the port OUTP_Q, port OUTN_Q flows out.
  • Inductor L2 and inductor L5 are coupled to each other.
  • NMOS tube M1, NMOS tube M2, NMOS tube M5, and NMOS tube M6 are the same.
  • Capacitor array C1, capacitor array C6, capacitor array C7, and capacitor array C12 are the same.
  • Variable capacitor C2, variable capacitor C5, and variable capacitor C8 can be The variable capacitor C11 is the same, the capacitor C3, the capacitor C4, the capacitor C9, and the capacitor C10 are the same, and the PMOS tube M3, PMOS tube M4, PMOS tube M7, and PMOS tube M8 are the same.
  • the present invention enables the voltage controlled oscillator to obtain greater transconductance.
  • K VCO is large, the noise is suppressed, the up-conversion function of reducing flicker noise is achieved, and the near-frequency phase is reduced. noise.
  • the flipped complementary structure proposed by the present invention multiplexes the current, improves performance while saving overall power consumption, and has a simple structure; compared with the traditional complementary structure, the flipped complementary structure proposed by the present invention Controlled oscillator reduces flicker noise and upconversion improves phase noise.
  • a circuit that can generate IQ quadrature differential signals is further proposed.
  • I and Q are formed.
  • the quadrature of the path outputs IQ quadrature differential signals.
  • Figure 1 is the circuit schematic diagram of the traditional NMOS VCO circuit
  • Figure 2 is the circuit schematic diagram of the traditional PMOS VCO circuit
  • FIG. 3 is the circuit schematic diagram of the traditional complementary structure VCO circuit
  • Figure 4 is a circuit schematic diagram of the flip complementary low-noise voltage-controlled oscillator proposed by the present invention.
  • Figure 5 is a schematic circuit diagram of the transistor variable capacitor in Figure 4 of the present invention.
  • Figure 6 is a schematic diagram of the IQ quadrature circuit of the flip complementary low-noise voltage-controlled oscillator proposed by the present invention.
  • Figure 7 is a circuit schematic diagram of a flip complementary low-noise voltage controlled oscillator in the form of substrate injection proposed by the present invention.
  • Figure 8 is a schematic diagram of an IQ quadrature circuit of a flip complementary low-noise voltage controlled oscillator in the form of substrate injection proposed by the present invention.
  • Figure 1-3 shows the traditional NMOS/PMOS VCO circuit and the complementary structure VCO circuit.
  • Figure 4 is a circuit schematic diagram of the flip complementary low-noise voltage controlled oscillator proposed by the present invention. It includes: inductor L1, inductor L2, inductor L3, capacitor array C1, variable capacitor C2, capacitor C3, capacitor C4, variable capacitor C5, capacitor array C6, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, as well as port OUTP and port OUTN.
  • the inductor L1 is connected in parallel with the capacitor array C1 and the variable capacitor C2.
  • the NMOS tube M1 and the NMOS tube M2 form an NMOS mutually coupled pair.
  • the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M2 and then connected to the a terminal of the inductor L1.
  • NMOS tube M2 The drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then connected to the b terminal of inductor L1. Inductor L3, variable capacitor C5, and capacitor array C6 are connected in parallel. PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair.
  • the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the a terminal of inductor L3.
  • the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then connected to the b terminal of inductor L3.
  • the NMOS tube M1 is connected to the source level of NMOS tube M2 and then connected to the a terminal of inductor L2.
  • the source levels of PMOS tube M3 and PMOS tube M4 are connected to the b terminal of inductor L2.
  • the a terminal of capacitor C3 is connected to the terminal a of NMOS tube M1.
  • the drain is connected, the b terminal of capacitor C3 is connected to the drain of PMOS tube M3, the a terminal of capacitor C4 is connected to the drain of NMOS tube M2, the b terminal of capacitor C4 is connected to the drain of PMOS tube M4, the center of inductor L1
  • the tap is connected to the power supply, the center tap of the inductor L3 is connected to the ground, the port OUTP is connected to the drain of the NMOS tube M1, the port OUTN is connected to the drain of the NMOS tube M2, and the differential signal flows out from the port OUTP and the port OUTN.
  • NMOS tube M1 is the same as NMOS tube M2
  • capacitor array C1 is the same as capacitor array C6
  • variable capacitor C2 is the same as variable capacitor C5
  • capacitor C3 is the same as capacitor C4
  • PMOS tube M3 is the same as PMOS tube M4.
  • the variable capacitor in Figure 4 includes: transistor variable capacitors C1’, C2’, capacitors C3’, C4’, resistors R1, R2, and four ports VOP, VON, VCTRL and VIBIAS.
  • the port VOP is connected to the a terminal of the capacitor C3', the b terminal of the capacitor C3' is connected to the b terminal of the resistor R1 and the a terminal of the transistor variable capacitor C1'; the port VON is connected to the a terminal of the capacitor C4', and the capacitor C4'
  • the b terminal is connected to the b terminal of the resistor R2 and the a terminal of the transistor variable capacitor C2'.
  • the port VCTRL is connected to the b terminal of the transistor variable capacitor C1' and the b terminal of the transistor variable capacitor C2', and the port VIBIAS is connected to the a terminal of the resistor R1 and the a terminal of the resistor R2.
  • Transistor variable capacitors C1’ and C2’ are the same, capacitors C3’ and C4’ are the same, and resistors R1 and R2 are the same.
  • NMOS tube M1 and NMOS tube M2 form an NMOS mutually coupled pair
  • PMOS tube M3 and PMOS tube M4 form a PMOS mutually coupled pair
  • the mutually coupled pair forms a negative resistance, which compensates during oscillation.
  • the energy loss of the LC resonant circuit maintains stable oscillation of the circuit.
  • the capacitance values of capacitor array C1 and capacitor array C6 can change the center frequency of the oscillator.
  • Variable capacitor C2 and variable capacitor C5 can change the capacitance size by changing the voltage of port VCTRL, thereby changing the center frequency of the oscillator.
  • the voltage controlled oscillator is analyzed according to the phase noise model.
  • K VCO is large, the latter term is mainly analyzed.
  • the V m of a pair of mutually coupled oscillators is the noise current multiplied by the equivalent impedance of the transistor and the equivalent impedance of the parallel inductor;
  • the V m of two pairs of mutually coupled pairs of traditional complementary voltage-controlled oscillators connected in parallel is The noise current is multiplied by the equivalent impedance of the transistor;
  • the flipped complementary low-noise voltage-controlled oscillator proposed by the present invention is approximately coupled with two resonant cavities, and its V m is twice that of a pair of mutually coupled oscillators.
  • the equivalent impedance of the inductor is generally much smaller than the equivalent impedance of the transistor, although the V m of the proposed voltage controlled oscillator is twice that of a pair of mutually coupled oscillators, it is still much smaller than the V m of the traditional complementary voltage controlled oscillator. , so the flip complementary low-noise voltage-controlled oscillator proposed by the present invention has smaller phase noise than the traditional complementary voltage-controlled oscillator.
  • a system in which N oscillators are coupled to each other will have reduced phase noise compared to a single oscillator, so that the flip complementary low-noise voltage-controlled oscillator proposed in the present invention has lower phase noise.
  • two resonant cavities perform current multiplexing, which improves transconductance while saving power consumption and optimizing the phase noise performance of the oscillator.
  • the tail inductor filters the second-order component of the oscillator noise, further optimizing the phase noise.
  • Figure 6 shows the flip complementary low-noise voltage-controlled oscillator proposed by the present invention applied to an IQ quadrature circuit. It includes: inductor L1, inductor L2, inductor L3, inductor L4, inductor L5, inductor L6, capacitor array C1, variable capacitor C2, capacitor C3, capacitor C4, variable capacitor C5, capacitor array C6, capacitor array C7, which can Variable capacitor C8, capacitor C9, capacitor C10, variable capacitor C11, capacitor array C12, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, PMOS tube M7, PMOS tube M8 , as well as port OUTP_I, port OUTN_I, port OUTP_Q, port OUTN_Q.
  • the inductor L1 is connected in parallel with the capacitor array C1 and the variable capacitor C2.
  • the NMOS tube M1 and the NMOS tube M2 form an NMOS mutually coupled pair.
  • the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M2 and then connected to the a terminal of the inductor L1.
  • the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then connected to the b terminal of inductor L1.
  • Inductor L3, variable capacitor C5, and capacitor array C6 are connected in parallel.
  • PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair.
  • the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the a terminal of inductor L3.
  • the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then connected to the b terminal of inductor L3.
  • the NMOS tube M1 is connected to the source level of NMOS tube M2 and then connected to the a terminal of inductor L2.
  • the source levels of PMOS tube M3 and PMOS tube M4 are connected to the b terminal of inductor L2.
  • the a terminal of capacitor C3 is connected to the a terminal of NMOS tube M1.
  • the drain is connected, the b terminal of capacitor C3 is connected to the drain of PMOS tube M3, the a terminal of capacitor C4 is connected to the drain of NMOS tube M2, the b terminal of capacitor C4 is connected to the drain of PMOS tube M4, the center of inductor L1
  • the tap is connected to the power supply, the center tap of the inductor L3 is connected to the ground, the port OUTP_I is connected to the drain of the NMOS tube M1, the port OUTN_I is connected to the drain of the NMOS tube M2, and the I differential signal flows out from the port OUTP_I and the port OUTN_I.
  • the inductor L4 is connected in parallel with the capacitor array C7 and the variable capacitor C8.
  • the NMOS tube M5 and the NMOS tube M6 form an NMOS mutually coupled pair.
  • the drain of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and then connected to the a terminal of the inductor L4.
  • the drain of NMOS tube M6 is connected to the gate of NMOS tube M5 and then connected to the b terminal of inductor L4.
  • Inductor L6 is connected in parallel with variable capacitor C11 and capacitor array C12.
  • PMOS tube M7 and PMOS tube M8 form a PMOS mutual coupling pair.
  • the drain of PMOS tube M7 is connected to the gate of PMOS tube M8 and then connected to the a terminal of inductor L6.
  • the drain of PMOS tube M8 is connected to the gate of PMOS tube M7 and then connected to the b terminal of inductor L6.
  • the NMOS tube The source levels of M5 and NMOS tube M6 are connected and then connected to the a-end of the inductor L5.
  • the source levels of PMOS tube M7 and PMOS tube M8 are connected and then connected to the b-end of the inductor L5.
  • the a-end of the capacitor C9 is connected to the a-end of the NMOS tube M5.
  • the drain is connected, the b terminal of capacitor C9 is connected to the drain of PMOS tube M7, the a terminal of capacitor C10 is connected to the drain of NMOS tube M6, the b terminal of capacitor C10 is connected to the drain of PMOS tube M8, the center of inductor L4
  • the tap is connected to the power supply, the center tap of the inductor L6 is connected to the ground, the port OUTP_Q is connected to the drain of the NMOS tube M5, the port OUTN_Q is connected to the drain of the NMOS tube M6, and the Q differential signal flows out from the port OUTP_Q and the port OUTN_Q.
  • Inductor L2 and inductor L5 are coupled to each other.
  • NMOS tube M1, NMOS tube M2, NMOS tube M5, and NMOS tube M6 are the same.
  • Capacitor array C1, capacitor array C6, capacitor array C7, and capacitor array C12 are the same.
  • Variable capacitor C2, variable capacitor C5, and variable capacitor C8 can be The variable capacitor C11 is the same, the capacitor C3, the capacitor C4, the capacitor C9, and the capacitor C10 are the same, and the PMOS tube M3, PMOS tube M4, PMOS tube M7, and PMOS tube M8 are the same.
  • the orthogonal I and Q paths are formed, and the IQ quadrature differential signal is output.
  • Figure 7 is a flip complementary low-noise voltage controlled oscillator that reduces flicker noise and upconverts in the form of substrate injection proposed by the present invention, which includes: inductor L1, inductor L2, inductor L3, capacitor array C1, variable capacitor C2, capacitor C3 , capacitor C4, variable capacitor C5, capacitor array C6, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, as well as port OUTP and port OUTN. Inductor L1, capacitor array C1, and variable capacitor C2 are connected in parallel. NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair.
  • NMOS tube M1 The substrate of NMOS tube M1 is connected to the gate of NMOS tube M1, and the substrate of NMOS tube M2 is connected to the NMOS tube.
  • the gate of M2 is connected, the drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then connected to the a terminal of inductor L1, the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then to the terminal a of inductor L1.
  • the b terminal is connected, the inductor L3 and the variable capacitor C5, the capacitor array C6 are connected in parallel, the PMOS tube M3 and the PMOS tube M4 form a PMOS mutual coupling pair, the substrate of the PMOS tube M3 is connected to the gate of the PMOS tube M3, and the lining of the PMOS tube M4
  • the bottom is connected to the gate of PMOS tube M4, the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the a terminal of inductor L3, the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then Connected to the b end of the inductor L3, the source levels of the NMOS transistors M1 and NMOS transistors M2 are connected and then connected to the a end of the inductor L2, the source levels of the PMOS transistors M3 and PMOS transistors M4 are connected and then connected to the b end of the inductor L2.
  • the a terminal of capacitor C3 is connected to the drain of NMOS tube M1, the b terminal of capacitor C3 is connected to the drain of PMOS tube M3, the a terminal of capacitor C4 is connected to the drain of NMOS tube M2, and the b terminal of capacitor C4 is connected to the drain of PMOS tube M2.
  • the drain of M4 is connected, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is connected to the ground, the port OUTP is connected to the drain of the NMOS tube M1, the port OUTN is connected to the drain of the NMOS tube M2, the differential signal is from the port OUTP, Port OUTN flows out.
  • NMOS tube M1 is the same as NMOS tube M2
  • capacitor array C1 is the same as capacitor array C6
  • variable capacitor C2 is the same as variable capacitor C5
  • capacitor C3 is the same as capacitor C4
  • PMOS tube M3 is the same as PMOS tube M4.
  • the substrates of NMOS transistor M1 and NMOS transistor M2 are connected to low level, and the substrates of PMOS transistor M3 and PMOS transistor M4 are connected to high level.
  • the substrates of the NMOS transistor M1 and the NMOS transistor M2 are connected to their respective gates, and the substrates of the PMOS transistor M3 and PMOS transistor M4 are connected to their respective gates, thereby forming substrate implantation.
  • Substrate implantation injects signals into the substrate, improving the g m of the transistor, so smaller size transistors can be used, reducing current and reducing flicker noise.
  • the transistor can switch the switching state more quickly, enhance the degree of turning on and off, improve the signal strength, and further reduce the phase noise.
  • Figure 8 is a flip complementary low-noise voltage controlled oscillator circuit that generates IQ differential quadrature signals in the form of substrate injection proposed by the present invention, which includes: inductor L1, inductor L2, inductor L3, inductor L4, inductor L5, inductor L6, Capacitor array C1, variable capacitor C2, capacitor C3, capacitor C4, variable capacitor C5, capacitor array C6, capacitor array C7, variable capacitor C8, capacitor C9, capacitor C10, variable capacitor C11, capacitor array C12, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, PMOS tube M7, PMOS tube M8, and port OUTP_I, port OUTN_I, port OUTP_Q, port OUTN_Q.
  • Inductor L1, capacitor array C1, and variable capacitor C2 are connected in parallel.
  • NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair.
  • the substrate of NMOS tube M1 is connected to the gate of NMOS tube M1, and the substrate of NMOS tube M2 is connected to the NMOS tube.
  • the gate of M2 is connected, the drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then connected to the a terminal of inductor L1, the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then to the terminal a of inductor L1.
  • the b terminal is connected, the inductor L3 and the variable capacitor C5, the capacitor array C6 are connected in parallel, the PMOS tube M3 and the PMOS tube M4 form a PMOS mutual coupling pair, the substrate of the PMOS tube M3 is connected to the gate of the PMOS tube M3, and the lining of the PMOS tube M4
  • the bottom is connected to the gate of PMOS tube M4, the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the a terminal of inductor L3, the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then It is connected to the b end of the inductor L3, the source levels of the NMOS transistor M1 and the NMOS transistor M2 are connected and then connected to the a end of the inductor L2, the source levels of the PMOS transistor M3 and PMOS transistor M4 are connected and then connected to the b end of the inductor L2.
  • the a terminal of capacitor C3 is connected to the drain of NMOS tube M1, the b terminal of capacitor C3 is connected to the drain of PMOS tube M3, the a terminal of capacitor C4 is connected to the drain of NMOS tube M2, and the b terminal of capacitor C4 is connected to the drain of PMOS tube M2.
  • the drain of M4 is connected, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is connected to the ground, the port OUTP_I is connected to the drain of the NMOS tube M1, the port OUTN_I is connected to the drain of the NMOS tube M2, and the I differential signal is connected from the port OUTP_I, port OUTN_I outflow.
  • Inductor L4 is connected in parallel with capacitor array C7 and variable capacitor C8.
  • NMOS tube M5 and NMOS tube M6 form an NMOS mutual coupling pair.
  • the substrate of NMOS tube M5 is connected to the gate of NMOS tube M5, and the substrate of NMOS tube M6 is connected to the NMOS tube.
  • the gate of M6 is connected, the drain of NMOS tube M5 is connected to the gate of NMOS tube M6 and then connected to the a terminal of inductor L4, the drain of NMOS tube M6 is connected to the gate of NMOS tube M5 and then to the terminal a of inductor L4.
  • the b terminal is connected, the inductor L6 and the variable capacitor C11, the capacitor array C12 are connected in parallel, the PMOS tube M7 and the PMOS tube M8 form a PMOS mutual coupling pair, the substrate of the PMOS tube M7 is connected to the gate of the PMOS tube M7, and the substrate of the PMOS tube M8
  • the bottom is connected to the gate of PMOS tube M8, the drain of PMOS tube M7 is connected to the gate of PMOS tube M8 and then connected to the a terminal of inductor L6, the drain of PMOS tube M8 is connected to the gate of PMOS tube M7 and then It is connected to the b end of the inductor L6, the source levels of the NMOS tube M5 and the NMOS tube M6 are connected and then connected to the a end of the inductor L5, the source levels of the PMOS tube M7 and PMOS tube M8 are connected and then connected to the b end of the inductor L5.
  • the a terminal of capacitor C9 is connected to the drain of NMOS tube M5, the b terminal of capacitor C9 is connected to the drain of PMOS tube M7, the a terminal of capacitor C10 is connected to the drain of NMOS tube M6, and the b terminal of capacitor C10 is connected to the drain of PMOS tube M6.
  • the drain of M8 is connected, the center tap of the inductor L4 is connected to the power supply, the center tap of the inductor L6 is connected to the ground, the port OUTP_Q is connected to the drain of the NMOS tube M5, the port OUTN_Q is connected to the drain of the NMOS tube M6, the Q differential signal is connected from the port OUTP_Q, port OUTN_Q flows out.
  • Inductor L2 and inductor L5 are coupled to each other.
  • NMOS tube M1, NMOS tube M2, NMOS tube M5, and NMOS tube M6 are the same.
  • Capacitor array C1, capacitor array C6, capacitor array C7, and capacitor array C12 are the same.
  • Variable capacitor C2, variable capacitor C5, and variable capacitor C8 can be The variable capacitor C11 is the same, the capacitor C3, the capacitor C4, the capacitor C9, and the capacitor C10 are the same, and the PMOS tube M3, PMOS tube M4, PMOS tube M7, and PMOS tube M8 are the same.

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Abstract

一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器。在雷达技术应用中，压控振荡器的电压/频率增益过大，使得低频噪声影响了相位噪声。通过提出的翻转互补结构以及尾电感，使得压控振荡器获得更大的跨导，抑制了噪声，实现减少闪烁噪声上变频的功能。与传统技术使用单个互耦对相比，翻转互补结构对电流进行复用，提升性能的同时节省整体功耗，且结构简单；与传统的互补结构相比，使得压控振荡器减少了闪烁噪声上变频，改善了相位噪声。在此基础上可进一步产生IQ正交差分信号的电路，以及衬底注入形式的翻转互补低噪声压控振荡器和对应的产生IQ正交差分信号的电路。

Description

一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器 技术领域
本发明涉及集成电路技术领域，具体地涉及一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器。
背景技术
随着雷达技术的更新发展，毫米波雷达技术逐渐成为研究热点。压控振荡器(Voltage Controlled Oscillator，VCO)作为毫米波雷达技术中的关键电路模块，其设计存在许多的挑战：(1)相位噪声性能的恶化，这主要是由于工作频率升高到毫米波频段之后，无源器件的品质因数(Q值)显著的下降导致；(2)互补金属氧化物半导体(CMOS)器件本身固有的闪烁噪声严重的影响毫米波VCO的近端相位噪声，即闪烁噪声性能差。
此外，由于晶体管可变电容器具有非线性的C-V曲线，导致相位噪声在调谐范围内不一致，压控振荡器产生的所有噪声都会通过压控振荡器的K VCO进行调制载波，并产生额外的相位噪声。这一部分相位噪声可以添加到经典的Leeson噪声模型中，其定义如下：
Figure PCTCN2022105179-appb-000001
其中f 0是振荡频率，f m是频率偏移，F是晶体管放大器的噪声系数，k是玻尔兹曼常量，T是温度，P s是闪烁噪声角频率，V m表示低频噪声的等效幅度，单位为
Figure PCTCN2022105179-appb-000002
在通信应用中，由于K VCO很小，所以后项可以忽略，前项的leeson噪声占主导地位，并决定了振荡器的相位噪声。但对于雷达应用，特别是需要大调谐范围的雷达，如FMCW雷达，K VCO将非常大，这意味着VCO具有高的电压/频率增益，后项无法忽略，低频噪声如闪烁噪声等将较大的影响振荡器的相位噪声。
在毫米波雷达技术中，传统的互补结构VCO电路抑制闪烁噪声等低频噪声上变频的能力较差，使得整体的相位噪声也较差。
发明内容
针对现有技术的不足，本发明目的在于不增加电路复杂度的情况下，在K VCO较大的雷达技术应用中，实现低噪声的毫米波信号输出。
本发明提出了一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器。同时，基于本发明提出的翻转互补低噪声压控振荡器，进一步提出可以产生IQ正交差分信号的电路，以及衬底注入形式的翻转互补低噪声压控振荡器和对应的产生IQ正交差分信号的电路。
进一步地，所述低噪声压控振荡器包括：电感L1，电感L2，电感L3，电容阵列C1， 可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，以及端口OUTP，端口OUTN。电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1的b端连接，电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS管M4组成PMOS互耦对，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接，NMOS管M1和NMOS管M2的源级相接再与电感L2的a端连接，PMOS管M3和PMOS管M4的源级相接再与电感L2的b端连接，电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP与NMOS管M1的漏极连接，端口OUTN与NMOS管M2的漏极连接，差分信号从端口OUTP，端口OUTN流出。
NMOS管M1和NMOS管M2相同，电容阵列C1和电容阵列C6相同，可变电容C2和可变电容C5相同，电容C3和电容C4相同，PMOS管M3和PMOS管M4相同。
进一步地，所述可变电容包括：晶体管可变电容器C1’、C2’，电容C3’、C4’，电阻R1、R2，四个端口VOP、VON、VCTRL和VIBIAS。端口VOP与电容C3’的a端连接，电容C3’的b端与电阻R1的b端和晶体管可变电容器C1’的a端连接；端口VON与电容C4’的a端连接，电容C4’的b端与电阻R2的b端和晶体管可变电容器C2’的a端连接。端口VCTRL与晶体管可变电容器C1’的b端和晶体管可变电容器C2’的b端连接，端口VIBIAS与电阻R1的a端和电阻R2的a端连接。
晶体管可变电容器C1’和C2’相同，电容C3’和C4’相同，电阻R1和R2相同。
进一步地，所述的产生IQ差分正交信号的翻转互补低噪声压控振荡器电路，其包括：电感L1，电感L2，电感L3，电感L4，电感L5，电感L6，电容阵列C1，可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，电容阵列C7，可变电容C8，电容C9，电容C10，可变电容C11，电容阵列C12，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，NMOS管M5，NMOS管M6，PMOS管M7，PMOS管M8，以及端口OUTP_I，端口OUTN_I，端口OUTP_Q，端口OUTN_Q。电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1的b端连接，电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS 管M4组成PMOS互耦对，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接，NMOS管M1和NMOS管M2的源级相接再与电感L2的a端连接，PMOS管M3和PMOS管M4的源级相接再与电感L2的b端连接，电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP_I与NMOS管M1的漏极连接，端口OUTN_I与NMOS管M2的漏极连接，I路差分信号从端口OUTP_I，端口OUTN_I流出。
电感L4和电容阵列C7，可变电容C8并联，NMOS管M5和NMOS管M6组成NMOS互耦对，NMOS管M5的漏极与NMOS管M6的栅极相接再与电感L4的a端连接，NMOS管M6的漏极与NMOS管M5的栅极相接再与电感L4的b端连接，电感L6和可变电容C11，电容阵列C12并联，PMOS管M7和PMOS管M8组成PMOS互耦对，PMOS管M7的漏极与PMOS管M8的栅极相接再与电感L6的a端连接，PMOS管M8的漏极与PMOS管M7的栅极相接再与电感L6的b端连接，NMOS管M5和NMOS管M6的源级相接再与电感L5的a端连接，PMOS管M7和PMOS管M8的源级相接再与电感L5的b端连接，电容C9的a端与NMOS管M5的漏极连接，电容C9的b端与PMOS管M7的漏极连接，电容C10的a端与NMOS管M6的漏极连接，电容C10的b端与PMOS管M8的漏极连接，电感L4的中心抽头接供电电源，电感L6的中心抽头接地，端口OUTP_Q与NMOS管M5的漏极连接，端口OUTN_Q与NMOS管M6的漏极连接，Q路差分信号从端口OUTP_Q，端口OUTN_Q流出。电感L2和电感L5相互耦合。
NMOS管M1、NMOS管M2、NMOS管M5、NMOS管M6相同，电容阵列C1、电容阵列C6、电容阵列C7、电容阵列C12相同，可变电容C2、可变电容C5、可变电容C8、可变电容C11相同，电容C3、电容C4、电容C9、电容C10相同，PMOS管M3、PMOS管M4、PMOS管M7、PMOS管M8相同。
进一步地，所述的衬底注入形式的减少闪烁噪声上变频的翻转互补低噪声压控振荡器，其包括：电感L1，电感L2，电感L3，电容阵列C1，可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，以及端口OUTP，端口OUTN。电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的衬底与NMOS管M1的栅极相连，NMOS管M2的衬底与NMOS管M2的栅极相连，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1 的b端连接，电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS管M4组成PMOS互耦对，PMOS管M3的衬底与PMOS管M3的栅极相连，PMOS管M4的衬底与PMOS管M4的栅极相连，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接，NMOS管M1和NMOS管M2的源级相接再与电感L2的a端连接，PMOS管M3和PMOS管M4的源级相接再与电感L2的b端连接，电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP与NMOS管M1的漏极连接，端口OUTN与NMOS管M2的漏极连接，差分信号从端口OUTP，端口OUTN流出。
NMOS管M1和NMOS管M2相同，电容阵列C1和电容阵列C6相同，可变电容C2和可变电容C5相同，电容C3和电容C4相同，PMOS管M3和PMOS管M4相同。
进一步地，所述的衬底注入形式的产生IQ差分正交信号的翻转互补低噪声压控振荡器电路，其包括：电感L1，电感L2，电感L3，电感L4，电感L5，电感L6，电容阵列C1，可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，电容阵列C7，可变电容C8，电容C9，电容C10，可变电容C11，电容阵列C12，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，NMOS管M5，NMOS管M6，PMOS管M7，PMOS管M8，以及端口OUTP_I，端口OUTN_I，端口OUTP_Q，端口OUTN_Q。电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的衬底与NMOS管M1的栅极相连，NMOS管M2的衬底与NMOS管M2的栅极相连，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1的b端连接，电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS管M4组成PMOS互耦对，PMOS管M3的衬底与PMOS管M3的栅极相连，PMOS管M4的衬底与PMOS管M4的栅极相连，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接，NMOS管M1和NMOS管M2的源级相接再与电感L2的a端连接，PMOS管M3和PMOS管M4的源级相接再与电感L2的b端连接，电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP_I与NMOS管M1的漏极连接，端口OUTN_I与NMOS管M2的漏极连接，I路差分信号从端口OUTP_I，端口OUTN_I 流出。
电感L4和电容阵列C7，可变电容C8并联，NMOS管M5和NMOS管M6组成NMOS互耦对，NMOS管M5的衬底与NMOS管M5的栅极相连，NMOS管M6的衬底与NMOS管M6的栅极相连，NMOS管M5的漏极与NMOS管M6的栅极相接再与电感L4的a端连接，NMOS管M6的漏极与NMOS管M5的栅极相接再与电感L4的b端连接，电感L6和可变电容C11，电容阵列C12并联，PMOS管M7和PMOS管M8组成PMOS互耦对，PMOS管M7的衬底与PMOS管M7的栅极相连，PMOS管M8的衬底与PMOS管M8的栅极相连，PMOS管M7的漏极与PMOS管M8的栅极相接再与电感L6的a端连接，PMOS管M8的漏极与PMOS管M7的栅极相接再与电感L6的b端连接，NMOS管M5和NMOS管M6的源级相接再与电感L5的a端连接，PMOS管M7和PMOS管M8的源级相接再与电感L5的b端连接，电容C9的a端与NMOS管M5的漏极连接，电容C9的b端与PMOS管M7的漏极连接，电容C10的a端与NMOS管M6的漏极连接，电容C10的b端与PMOS管M8的漏极连接，电感L4的中心抽头接供电电源，电感L6的中心抽头接地，端口OUTP_Q与NMOS管M5的漏极连接，端口OUTN_Q与NMOS管M6的漏极连接，Q路差分信号从端口OUTP_Q，端口OUTN_Q流出。电感L2和电感L5相互耦合。
NMOS管M1、NMOS管M2、NMOS管M5、NMOS管M6相同，电容阵列C1、电容阵列C6、电容阵列C7、电容阵列C12相同，可变电容C2、可变电容C5、可变电容C8、可变电容C11相同，电容C3、电容C4、电容C9、电容C10相同，PMOS管M3、PMOS管M4、PMOS管M7、PMOS管M8相同。
本发明通过提出的翻转互补结构以及尾电感，使得压控振荡器获得更大的跨导，在K VCO较大的情况下，抑制了噪声，实现减少闪烁噪声上变频的功能，减少近频相位噪声。与传统技术使用单个互耦对相比，本发明提出的翻转互补结构对电流进行复用，提升性能的同时节省整体功耗，且结构简单；与传统的互补结构相比，本发明提出的压控振荡器减少了闪烁噪声上变频，改善了相位噪声。同时，基于提出的翻转互补低噪声压控振荡器，进一步地提出可以产生IQ正交差分信号的电路，通过让两路相同的振荡器中间的电感L2和电感L5进行耦合，形成I路和Q路的正交，输出IQ正交差分信号。
附图说明
图1为传统NMOS VCO电路的电路原理图；
图2为传统PMOS VCO电路的电路原理图；
图3为传统互补结构VCO电路的电路原理图；
图4为本发明提出的翻转互补低噪声压控振荡器的电路原理图；
图5为本发明图4中的晶体管可变电容器的电路原理图；
图6为本发明提出的翻转互补低噪声压控振荡器的IQ正交电路的原理图；
图7为本发明提出的衬底注入形式翻转互补低噪声压控振荡器的电路原理图；
图8为本发明提出的衬底注入形式翻转互补低噪声压控振荡器的IQ正交电路的原理图。
具体实施方式
为了使本发明的目的和效果将变得更加明白，以下结合附图，对本发明进行进一步详细说明。应当理解，此处所描述的仅仅用以解释本发明，并不用于限定本发明。
图1-3为传统的NMOS/PMOS VCO电路和互补结构VCO电路。
图4为本发明提出的翻转互补低噪声压控振荡器的电路原理图。其包括：电感L1，电感L2，电感L3，电容阵列C1，可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，以及端口OUTP，端口OUTN。电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1的b端连接，电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS管M4组成PMOS互耦对，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接，NMOS管M1和NMOS管M2的源级相接再与电感L2的a端连接，PMOS管M3和PMOS管M4的源级相接再与电感L2的b端连接，电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP与NMOS管M1的漏极连接，端口OUTN与NMOS管M2的漏极连接，差分信号从端口OUTP，端口OUTN流出。
NMOS管M1和NMOS管M2相同，电容阵列C1和电容阵列C6相同，可变电容C2和可变电容C5相同，电容C3和电容C4相同，PMOS管M3和PMOS管M4相同。
如图5所示，图4中的可变电容包括：晶体管可变电容器C1’、C2’，电容C3’、C4’，电阻R1、R2，四个端口VOP、VON、VCTRL和VIBIAS。端口VOP与电容C3’的a端连接，电容C3’的b端与电阻R1的b端和晶体管可变电容器C1’的a端连接；端口VON与电容C4’的a端连接，电容C4’的b端与电阻R2的b端和晶体管可变电容器C2’的a端连接。端口VCTRL与晶体管可变电容器C1’的b端和晶体管可变电容器C2’的b端连接，端口 VIBIAS与电阻R1的a端和电阻R2的a端连接。
晶体管可变电容器C1’和C2’相同，电容C3’和C4’相同，电阻R1和R2相同。
如上所述压控振荡器，其工作原理为：NMOS管M1和NMOS管M2组成NMOS互耦对，PMOS管M3和PMOS管M4组成PMOS互耦对，互耦对形成负阻，在振荡时补偿LC谐振回路的能量损失，维持电路稳定振荡。电容阵列C1，电容阵列C6的容值可改变振荡器的中心频率。可变电容C2，可变电容C5，可通过改变端口VCTRL的电压改变电容大小，从而改变振荡器的中心频率。
根据所述的相位噪声模型对压控振荡器进行分析，在K VCO较大的情况下，主要对后项进行分析。根据电路的噪声模型，一对互耦对振荡器的V m为噪声电流与晶体管等效阻抗并联电感等效阻抗相乘；传统互补压控振荡器的两对互耦对并联，其V m为噪声电流与晶体管等效阻抗相乘；而本发明提出的翻转互补低噪声压控振荡器近似于两个谐振腔进行耦合，其V m为一对互耦对振荡器的两倍。由于一般情况下电感等效阻抗远小于晶体管等效阻抗，所以虽然提出的压控振荡器V m为一对互耦对振荡器的两倍，但还是远小于传统互补压控振荡器的V m，所以本发明提出的翻转互补低噪声压控振荡器相比传统互补压控振荡器具有更小的相位噪声。此外，N个振荡器互耦合的系统相比单振荡器在相位噪声上会有所减少，使得本发明提出的翻转互补低噪声压控振荡器具有更低的相位噪声。
本发明提出的翻转互补结构，两个谐振腔进行了电流复用，在提高跨导的同时节省了功耗，优化了振荡器的相位噪声性能。尾电感对振荡器噪声中的二阶分量起到滤波作用，进一步优化了相位噪声。
图6为本发明提出的翻转互补低噪声压控振荡器应用于IQ正交电路。其包括：电感L1，电感L2，电感L3，电感L4，电感L5，电感L6，电容阵列C1，可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，电容阵列C7，可变电容C8，电容C9，电容C10，可变电容C11，电容阵列C12，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，NMOS管M5，NMOS管M6，PMOS管M7，PMOS管M8，以及端口OUTP_I，端口OUTN_I，端口OUTP_Q，端口OUTN_Q。电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1的b端连接，电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS管M4组成PMOS互耦对，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接，NMOS管M1和NMOS管M2的源级相接再与电感L2的a端连接，PMOS管M3和PMOS管M4 的源级相接再与电感L2的b端连接，电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP_I与NMOS管M1的漏极连接，端口OUTN_I与NMOS管M2的漏极连接，I路差分信号从端口OUTP_I，端口OUTN_I流出。
电感L4和电容阵列C7，可变电容C8并联，NMOS管M5和NMOS管M6组成NMOS互耦对，NMOS管M5的漏极与NMOS管M6的栅极相接再与电感L4的a端连接，NMOS管M6的漏极与NMOS管M5的栅极相接再与电感L4的b端连接，电感L6和可变电容C11，电容阵列C12并联，PMOS管M7和PMOS管M8组成PMOS互耦对，PMOS管M7的漏极与PMOS管M8的栅极相接再与电感L6的a端连接，PMOS管M8的漏极与PMOS管M7的栅极相接再与电感L6的b端连接，NMOS管M5和NMOS管M6的源级相接再与电感L5的a端连接，PMOS管M7和PMOS管M8的源级相接再与电感L5的b端连接，电容C9的a端与NMOS管M5的漏极连接，电容C9的b端与PMOS管M7的漏极连接，电容C10的a端与NMOS管M6的漏极连接，电容C10的b端与PMOS管M8的漏极连接，电感L4的中心抽头接供电电源，电感L6的中心抽头接地，端口OUTP_Q与NMOS管M5的漏极连接，端口OUTN_Q与NMOS管M6的漏极连接，Q路差分信号从端口OUTP_Q，端口OUTN_Q流出。电感L2和电感L5相互耦合。
NMOS管M1、NMOS管M2、NMOS管M5、NMOS管M6相同，电容阵列C1、电容阵列C6、电容阵列C7、电容阵列C12相同，可变电容C2、可变电容C5、可变电容C8、可变电容C11相同，电容C3、电容C4、电容C9、电容C10相同，PMOS管M3、PMOS管M4、PMOS管M7、PMOS管M8相同。
通过让两路相同的振荡器中间的电感L2和电感L5进行耦合，形成I路和Q路的正交，输出IQ正交差分信号。
图7为本发明提出的衬底注入形式的减少闪烁噪声上变频的翻转互补低噪声压控振荡器，其包括：电感L1，电感L2，电感L3，电容阵列C1，可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，以及端口OUTP，端口OUTN。电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的衬底与NMOS管M1的栅极相连，NMOS管M2的衬底与NMOS管M2的栅极相连，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1的b端连接，电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS管 M4组成PMOS互耦对，PMOS管M3的衬底与PMOS管M3的栅极相连，PMOS管M4的衬底与PMOS管M4的栅极相连，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接，NMOS管M1和NMOS管M2的源级相接再与电感L2的a端连接，PMOS管M3和PMOS管M4的源级相接再与电感L2的b端连接，电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP与NMOS管M1的漏极连接，端口OUTN与NMOS管M2的漏极连接，差分信号从端口OUTP，端口OUTN流出。
NMOS管M1和NMOS管M2相同，电容阵列C1和电容阵列C6相同，可变电容C2和可变电容C5相同，电容C3和电容C4相同，PMOS管M3和PMOS管M4相同。
图4中NMOS管M1和NMOS管M2的衬底接低电平，PMOS管M3和PMOS管M4的衬底接高电平。图7中NMOS管M1和NMOS管M2的衬底接各自的栅极，PMOS管M3和PMOS管M4的衬底接各自的栅极，从而形成衬底注入。衬底注入将信号注入到衬底，提高了晶体管的g m，因此可以使用更小尺寸的晶体管，减少电流，降低了闪烁噪声。同时使得晶体管能够更加快速地切换开关状态，加强开启和关断程度，提高信号强度，进一步降低相位噪声。
图8为本发明提出的衬底注入形式的产生IQ差分正交信号的翻转互补低噪声压控振荡器电路，其包括：电感L1，电感L2，电感L3，电感L4，电感L5，电感L6，电容阵列C1，可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，电容阵列C7，可变电容C8，电容C9，电容C10，可变电容C11，电容阵列C12，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，NMOS管M5，NMOS管M6，PMOS管M7，PMOS管M8，以及端口OUTP_I，端口OUTN_I，端口OUTP_Q，端口OUTN_Q。电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的衬底与NMOS管M1的栅极相连，NMOS管M2的衬底与NMOS管M2的栅极相连，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1的b端连接，电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS管M4组成PMOS互耦对，PMOS管M3的衬底与PMOS管M3的栅极相连，PMOS管M4的衬底与PMOS管M4的栅极相连，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接，NMOS管M1和NMOS管M2的源级相接再与电感L2 的a端连接，PMOS管M3和PMOS管M4的源级相接再与电感L2的b端连接，电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP_I与NMOS管M1的漏极连接，端口OUTN_I与NMOS管M2的漏极连接，I路差分信号从端口OUTP_I，端口OUTN_I流出。
电感L4和电容阵列C7，可变电容C8并联，NMOS管M5和NMOS管M6组成NMOS互耦对，NMOS管M5的衬底与NMOS管M5的栅极相连，NMOS管M6的衬底与NMOS管M6的栅极相连，NMOS管M5的漏极与NMOS管M6的栅极相接再与电感L4的a端连接，NMOS管M6的漏极与NMOS管M5的栅极相接再与电感L4的b端连接，电感L6和可变电容C11，电容阵列C12并联，PMOS管M7和PMOS管M8组成PMOS互耦对，PMOS管M7的衬底与PMOS管M7的栅极相连，PMOS管M8的衬底与PMOS管M8的栅极相连，PMOS管M7的漏极与PMOS管M8的栅极相接再与电感L6的a端连接，PMOS管M8的漏极与PMOS管M7的栅极相接再与电感L6的b端连接，NMOS管M5和NMOS管M6的源级相接再与电感L5的a端连接，PMOS管M7和PMOS管M8的源级相接再与电感L5的b端连接，电容C9的a端与NMOS管M5的漏极连接，电容C9的b端与PMOS管M7的漏极连接，电容C10的a端与NMOS管M6的漏极连接，电容C10的b端与PMOS管M8的漏极连接，电感L4的中心抽头接供电电源，电感L6的中心抽头接地，端口OUTP_Q与NMOS管M5的漏极连接，端口OUTN_Q与NMOS管M6的漏极连接，Q路差分信号从端口OUTP_Q，端口OUTN_Q流出。电感L2和电感L5相互耦合。
NMOS管M1、NMOS管M2、NMOS管M5、NMOS管M6相同，电容阵列C1、电容阵列C6、电容阵列C7、电容阵列C12相同，可变电容C2、可变电容C5、可变电容C8、可变电容C11相同，电容C3、电容C4、电容C9、电容C10相同，PMOS管M3、PMOS管M4、PMOS管M7、PMOS管M8相同。

Claims (6)

  1. 一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器，其特征在于包括：电感L1，电感L2，电感L3，电容阵列C1，可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，以及端口OUTP，端口OUTN；
    电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1的b端连接；
    电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS管M4组成PMOS互耦对，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接；
    NMOS管M1和NMOS管M2的源级相接再与电感L2的a端连接，PMOS管M3和PMOS管M4的源级相接再与电感L2的b端连接，电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP与NMOS管M1的漏极连接，端口OUTN与NMOS管M2的漏极连接，差分信号从端口OUTP，端口OUTN流出；
    其中，NMOS管M1和NMOS管M2相同，电容阵列C1和电容阵列C6相同，可变电容C2和可变电容C5相同，电容C3和电容C4相同，PMOS管M3和PMOS管M4相同。
  2. 根据权利要求1所述的一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器，其特征在于，所述的可变电容包括：晶体管可变电容器C1’、C2’，电容C3’、C4’，电阻R1、R2，四个端口VOP、VON、VCTRL和VIBIAS；
    端口VOP与电容C3’的a端连接，电容C3’的b端与电阻R1的b端和晶体管可变电容器C1’的a端连接；端口VON与电容C4’的a端连接，电容C4’的b端与电阻R2的b端和晶体管可变电容器C2’的a端连接；端口VCTRL与晶体管可变电容器C1’的b端和晶体管可变电容器C2’的b端连接，端口VIBIAS与电阻R1的a端和电阻R2的a端连接；
    晶体管可变电容器C1’和C2’相同，电容C3’和C4’相同，电阻R1和R2相同。
  3. 产生IQ差分正交信号的翻转互补低噪声压控振荡器电路，其特征在于，包括一对权利要求1所述的翻转互补低噪声压控振荡器，其特征在于：该对翻转互补低噪声压控振荡器中与MOS管源级相接的电感之间产生耦合关系，进而形成I路和Q路的正交，输出IQ 正交差分信号。
  4. 一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器，其特征在于包括：电感L1，电感L2，电感L3，电容阵列C1，可变电容C2，电容C3，电容C4，可变电容C5，电容阵列C6，NMOS管M1，NMOS管M2，PMOS管M3，PMOS管M4，以及端口OUTP，端口OUTN；
    电感L1和电容阵列C1，可变电容C2并联，NMOS管M1和NMOS管M2组成NMOS互耦对，NMOS管M1的衬底与NMOS管M1的栅极相连，NMOS管M2的衬底与NMOS管M2的栅极相连，NMOS管M1的漏极与NMOS管M2的栅极相接再与电感L1的a端连接，NMOS管M2的漏极与NMOS管M1的栅极相接再与电感L1的b端连接；
    电感L3和可变电容C5，电容阵列C6并联，PMOS管M3和PMOS管M4组成PMOS互耦对，PMOS管M3的衬底与PMOS管M3的栅极相连，PMOS管M4的衬底与PMOS管M4的栅极相连，PMOS管M3的漏极与PMOS管M4的栅极相接再与电感L3的a端连接，PMOS管M4的漏极与PMOS管M3的栅极相接再与电感L3的b端连接，NMOS管M1和NMOS管M2的源级相接再与电感L2的a端连接，PMOS管M3和PMOS管M4的源级相接再与电感L2的b端连接；
    电容C3的a端与NMOS管M1的漏极连接，电容C3的b端与PMOS管M3的漏极连接，电容C4的a端与NMOS管M2的漏极连接，电容C4的b端与PMOS管M4的漏极连接，电感L1的中心抽头接供电电源，电感L3的中心抽头接地，端口OUTP与NMOS管M1的漏极连接，端口OUTN与NMOS管M2的漏极连接，差分信号从端口OUTP，端口OUTN流出；
    NMOS管M1和NMOS管M2相同，电容阵列C1和电容阵列C6相同，可变电容C2和可变电容C5相同，电容C3和电容C4相同，PMOS管M3和PMOS管M4相同。
  5. 根据权利要求4所述的一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器，其特征在于，所述的可变电容包括：晶体管可变电容器C1’、C2’，电容C3’、C4’，电阻R1、R2，四个端口VOP、VON、VCTRL和VIBIAS；
    端口VOP与电容C3’的a端连接，电容C3’的b端与电阻R1的b端和晶体管可变电容器C1’的a端连接；端口VON与电容C4’的a端连接，电容C4’的b端与电阻R2的b端和晶体管可变电容器C2’的a端连接；端口VCTRL与晶体管可变电容器C1’的b端和晶体管可变电容器C2’的b端连接，端口VIBIAS与电阻R1的a端和电阻R2的a端连接；
    晶体管可变电容器C1’和C2’相同，电容C3’和C4’相同，电阻R1和R2相同。
  6. 产生IQ差分正交信号的翻转互补低噪声压控振荡器电路，其特征在于，包括一对权 利要求4所述的翻转互补低噪声压控振荡器，其特征在于：该对翻转互补低噪声压控振荡器中与MOS管源级相接的电感之间产生耦合关系，进而形成I路和Q路的正交，输出IQ正交差分信号。
PCT/CN2022/105179 2022-05-17 2022-07-12 一种减少闪烁噪声上变频的翻转互补低噪声压控振荡器 WO2023221276A1 (zh)

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