WO2023220858A1 - 显示面板的驱动方法及显示装置 - Google Patents

显示面板的驱动方法及显示装置 Download PDF

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Publication number
WO2023220858A1
WO2023220858A1 PCT/CN2022/093024 CN2022093024W WO2023220858A1 WO 2023220858 A1 WO2023220858 A1 WO 2023220858A1 CN 2022093024 W CN2022093024 W CN 2022093024W WO 2023220858 A1 WO2023220858 A1 WO 2023220858A1
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WIPO (PCT)
Prior art keywords
display
data
display mode
sub
pixel
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PCT/CN2022/093024
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English (en)
French (fr)
Inventor
黄艳庭
戴珂
聂春扬
周留刚
陈韫璐
李清
汪俊
孟志
孙伟
修天洵
杨越
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/093024 priority Critical patent/WO2023220858A1/zh
Priority to CN202280001232.1A priority patent/CN117561567A/zh
Publication of WO2023220858A1 publication Critical patent/WO2023220858A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving method of a display panel and a display device.
  • Display panels such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED), they generally include multiple pixel units.
  • Each pixel unit may include: red sub-pixels, green sub-pixels, and blue sub-pixels. By controlling the brightness corresponding to each sub-pixel, the desired display color is mixed to display a color image.
  • the counting state after entering the counting state, it also includes:
  • the display panel is driven to display the corresponding screen based on the target display mode and the received display data.
  • the display panel after counting the first number of corresponding set targets in the display data, and after determining that the first number is the same as the set number corresponding to the target display mode, based on the The target display mode, before driving the display panel to display the corresponding picture according to the received display data, also includes:
  • the display panel is driven to display a second setting screen in at least one display frame based on the target display mode.
  • the following formula is used to determine the number of display frames for displaying the second setting screen
  • SM represents the number of display frames for displaying the second setting screen
  • TM represents the setting time
  • AM represents the reciprocal of the refresh frequency corresponding to the target display mode.
  • At least one of the first setting screen and the second setting screen includes at least one of a solid color screen and a grayscale screen.
  • the non-counting state includes one of a clear state, a disable state, and a power-off state.
  • the display panel includes a first display mode; wherein the first display mode includes: driving the display panel line by line in a first display frame of two adjacent display frames. gate line, and when the gate line connected to the previous odd-numbered row display sub-pixel is driven, and the gate line connected to the next odd-numbered row display sub-pixel is being driven, the data line corresponding to the next odd-numbered row display sub-pixel is input The data voltage corresponding to the display data; and, in the second display frame of the two adjacent display frames, drive the gate lines in the display panel row by row, and display the gate lines connected to the sub-pixels in the previous even row. After the driving is completed and the gate line connected to the next even-numbered row display sub-pixel is being driven, the data voltage corresponding to the display data is input to the data line corresponding to the next even-numbered row display sub-pixel.
  • the display panel includes a second display mode; wherein the second display mode includes: driving the gate lines row by row in each display frame, and driving the gate lines of the previous row is completed, and the gate lines of the next row are driven.
  • the data voltage corresponding to the display data is input to the data line corresponding to the sub-pixel connected to the next row of gate lines.
  • the display panel includes a third display mode; wherein the third display mode includes: in each display frame, using at least two adjacent rows of gate lines as a gate line group, receiving each of the gate lines
  • the display data corresponding to a row of sub-pixels in the line group drives the gate lines in the same gate line group at the same time according to the received display data, and drives the gate line groups one by one.
  • the gate line driving is completed and the gate line in the next gate line group is being driven, the data voltage corresponding to the display data is input to the data line corresponding to the sub-pixel connected to the gate line of the next gate line group.
  • the current display mode is one of the first display mode, the second display mode, and the third display mode
  • the target display mode is one of the first display mode, the second display mode and the third display mode, except the current display mode.
  • the set target includes a row of sub-pixels of the display panel
  • the display panel includes display sub-pixel rows and virtual sub-pixel rows;
  • the set number includes half of the total number of all virtual sub-pixel rows and the total number of the display sub-pixel rows;
  • the set number includes the total number of all virtual sub-pixel rows and the total number of all display sub-pixel rows.
  • the set target includes a gate line group of the display panel
  • the set number includes a total number of gate line groups.
  • Timing controller configured as:
  • the display device further includes:
  • System circuit configured as:
  • the data mode switching completion instruction is sent to the timing controller.
  • the display device further includes: a counting unit;
  • the counting unit is configured to count the first number of corresponding set targets in the display data, and output a counting pass instruction when it is determined that the first number is the same as the set number corresponding to the target display mode;
  • the timing controller is further configured to control the counting unit to enter the non-counting state when receiving the display mode switching start instruction; and to control the counting unit when receiving the data mode switching completion instruction. Enter counting state.
  • the counting unit is integrated within the timing controller.
  • Figure 1 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • Figure 3 is another structural schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 4 is some signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 5 is another signal timing diagram provided by an embodiment of the present disclosure.
  • Figure 6 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 7 is some flowcharts of driving methods provided by embodiments of the present disclosure.
  • Figure 8 is another structural schematic diagram of a display device provided by an embodiment of the present disclosure.
  • Figure 9 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • the display device may include a display panel 100 , a timing controller 200 and a system circuit 300 .
  • the display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (for example, GA1, GA2, GA3, GA4), a plurality of data lines DA (for example, DA1, DA2, DA3), a gate electrode
  • the driving circuit 110 and the source driving circuit 120 are coupled to the gate lines GA1, GA2, GA3, and GA4 respectively
  • the source driving circuit 120 is coupled to the data lines DA1, DA2, and DA3 respectively.
  • each pixel unit includes a plurality of sub-pixels SPX.
  • the pixel unit may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue colors can be mixed to achieve color display.
  • the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that the colors of red, green, blue and white can be mixed to achieve color display.
  • the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.
  • two source driving circuits 120 may be provided, one source driving circuit 120 is connected to half of the number of data lines, and the other source driving circuit 120 is connected to the other half of the number of data lines.
  • there can also be three, four, or more source driving circuits 120 which can be designed and determined according to actual application requirements, and are not limited here.
  • each sub-pixel SPX includes a transistor 01 and a pixel electrode 02 .
  • one row of sub-pixels SPX corresponds to one gate line
  • one column of sub-pixels SPX corresponds to one data line.
  • the gate of transistor 01 is electrically connected to the corresponding gate line
  • the source of transistor 01 is electrically connected to the corresponding data line
  • the drain of transistor 01 is electrically connected to pixel electrode 02.
  • the pixel array structure of the present disclosure can also be It is a double gate structure, that is, two gate lines are set between two adjacent rows of sub-pixels.
  • This arrangement can reduce the number of data lines by half, that is, some adjacent columns of sub-pixels include data lines, and some adjacent two columns of sub-pixels contain data lines. Data lines are not included between columns of sub-pixels.
  • the specific sub-pixel arrangement structure and data lines, and the arrangement of scan lines are not limited.
  • the display panel 100 in the embodiment of the present disclosure may be a liquid crystal display panel 100, an OLED display panel 100, etc., which is not limited here.
  • dummy sub-pixels can be set in the non-display area of the display panel 100 .
  • the virtual sub-pixel is located in a peripheral area of the display sub-pixel. That is, the area where the display sub-pixels are located is the display area, and the area on the substrate other than the display area can be the non-display area.
  • the gate driving circuit 110 and the source driving circuit 120 can be disposed in the non-display area, and the virtual sub-pixels can be disposed in the non-display area. Pixels can be in the virtual area of the non-display area. For example, as shown in FIG.
  • display sub-pixels R11 to B62 are illustrated, and dummy sub-pixels may be provided around the display sub-pixels R11 to B62.
  • dummy sub-pixels may be provided above the display sub-pixels R11 to B12.
  • dummy sub-pixels may also be provided below the display sub-pixels R61 to B62, which is not limited here.
  • the structure in the virtual sub-pixel may be substantially the same as the structure in the display sub-pixel.
  • only the pixel electrode may be provided in the virtual sub-pixel without providing the transistor.
  • the number of virtual sub-pixels can be set according to the needs of the actual application, which is not limited here.
  • the display panel 100 provided by the embodiment of the present disclosure can be applied in a variety of different display modes.
  • the system circuit 300 can obtain the original display data of the image to be displayed (the original display data includes each sub-pixel (including display sub-pixels and virtual sub-pixels) in the display panel 100 ) one by one.
  • the original display data is processed accordingly to obtain display data corresponding to the current display mode, and the obtained display data is sent to the timing controller 200 .
  • the timing controller 200 inputs corresponding control signals to the gate driving circuit 110 in the display panel 100 according to the obtained display data and the current display mode, and controls the gate driving circuit 110 to drive the gate line GA (for example, GA1 , GA2, GA3, GA4), control the transistors in the sub-pixels to turn on.
  • the timing controller 200 sends the received display data to the source driving circuit, and the source driving circuit loads data voltages to the data lines DA (eg, DA1, DA2, DA3) in the display panel 100 according to the received display data. , when the transistor in the sub-pixel is turned on, the sub-pixel is charged, so that each sub-pixel is charged with data voltage to realize the screen display function.
  • the following description takes the pixel unit including red sub-pixels, green sub-pixels and blue sub-pixels as an example.
  • the red sub-pixel R11, the green sub-pixel G11, and the blue sub-pixel B11 are one pixel unit
  • the red sub-pixel R12, the green sub-pixel G12, and the blue sub-pixel B12 are one pixel unit.
  • the red sub-pixel R21 and the green sub-pixel G21 take the blue sub-pixel B21 as one pixel unit
  • the red sub-pixel R22 and the green sub-pixel G22 take the blue sub-pixel B22 as one pixel unit.
  • the red sub-pixel R31 and the green sub-pixel G31 use the blue sub-pixel B31 as one pixel unit; the red sub-pixel R32 and the green sub-pixel G32 use the blue sub-pixel B32 as one pixel unit.
  • the red sub-pixel R41 and the green sub-pixel G41 take the blue sub-pixel B41 as one pixel unit, and the red sub-pixel R42 and the green sub-pixel G42 take the blue sub-pixel B42 as one pixel unit.
  • the red sub-pixel R51, the green sub-pixel G51, and the blue sub-pixel B51 serve as one pixel unit; the red sub-pixel R52, the green sub-pixel G52, and the blue sub-pixel B52 serve as one pixel unit.
  • the red sub-pixel R61, the green sub-pixel G61, and the blue sub-pixel B61 serve as one pixel unit; the red sub-pixel R62, the green sub-pixel G62, and the blue sub-pixel B62 serve as one pixel unit.
  • the display panel 100 in the embodiment of the present disclosure may include multiple different display modes. And can switch between any two display modes.
  • one of the plurality of display modes may be a second display mode.
  • the second display mode may include: in each display frame, the system circuit 300 executes a data sending mode corresponding to the second display mode: transmitting the received original display data (including each display sub-pixel and each virtual sub-pixel) A corresponding digital signal (in the form of a data voltage carrying a corresponding gray scale value) is sent to the timing controller 200 .
  • the timing controller 200 controls the gate driving circuit to drive the gate lines row by row according to the received display data, and sends the display data to the source driving circuit.
  • the source driving circuit drives the gate lines in the previous row according to the received display data. When the gate line of the next row is driven, the data voltage corresponding to the display data is input to the data line corresponding to the sub-pixel connected to the gate line of the next row.
  • ga1 represents the signal loaded on the gate line GA1
  • ga2 represents the signal loaded on the gate line GA2
  • ga3 represents the signal loaded on the gate line GA3,
  • ga4 represents the signal loaded on the gate line GA4.
  • ga5 represents the signal loaded on the gate line GA5
  • ga6 represents the signal loaded on the gate line GA6.
  • Vda1 represents the data voltage loaded on data line DA1.
  • the high level in the signals ga1 to ga6 can be used as a gate turn-on signal to control the conduction of the transistor in the sub-pixel.
  • the gate turn-on signals may be sequentially applied to the gate lines GA1 to GA6.
  • the data line DA1 connected to the red sub-pixel R21 is loaded with the data voltage Vr21 corresponding to the display data, so that the red sub-pixel R21 is charged with the data voltage Vr21.
  • the signal ga3 on the gate line GA3 outputs a high-level gate turn-on signal, and the transistor in the red sub-pixel R31 is turned on.
  • the data voltage Vr21 is simultaneously input into the red sub-pixel R31 to precharge the red sub-pixel R31.
  • the data line DA1 connected to the red sub-pixel R31 is loaded with the data voltage Vr31 corresponding to the display data, so that the red sub-pixel R31 is charged with the data voltage Vr31.
  • the signal ga4 on the gate line GA4 outputs a high-level gate turn-on signal, and the transistor in the red sub-pixel R41 is turned on.
  • the data voltage Vr31 is simultaneously input into the red sub-pixel R41 to precharge the red sub-pixel R41.
  • the data line DA1 connected to the red sub-pixel R41 is loaded with the data voltage Vr41 corresponding to the display data, so that the red sub-pixel R41 is charged with the data voltage Vr41.
  • the signal ga5 on the gate line GA5 outputs a high-level gate turn-on signal, and the transistor in the red sub-pixel R51 is turned on.
  • the data voltage Vr41 is simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51.
  • the data line DA1 connected to the red sub-pixel R51 is loaded with the data voltage Vr51 corresponding to the display data, so that the red sub-pixel R51 is charged with the data voltage Vr51.
  • the signal ga6 on the gate line GA6 outputs a high-level gate turn-on signal, and the transistor in the red sub-pixel R61 is turned on.
  • the data voltage Vr51 is simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51.
  • the data line DA1 connected to the red sub-pixel R61 is loaded with the data voltage Vr61 corresponding to the display data, so that the red sub-pixel R61 is charged with the data voltage Vr61. And precharge the next red sub-pixel.
  • each display frame can be basically the same as the working process of the above-mentioned display frame F03, and will not be described in detail here.
  • one of the plurality of display modes may be the first display mode.
  • the first display mode includes: in the first display frame of two adjacent display frames, the system circuit 300 executes the data sending mode corresponding to the first display mode: the corresponding display sub-pixel in the received original display data is After deleting the original display data, the display data corresponding to the odd-numbered rows of display sub-pixels is obtained, and the obtained display data including the corresponding odd-numbered rows of display sub-pixels and the display data corresponding to each virtual sub-pixel are sent to the timing controller 200 , It should be noted that in the embodiment of the present disclosure, optionally, the display panel includes virtual sub-pixels, and data voltages are sent to the virtual sub-pixels.
  • the display panel may only include display sub-pixels, which is not limited here.
  • the timing controller 200 sends a control signal corresponding to the first display mode to the gate driving circuit according to the received display data to control the gate driving circuit to drive the gate lines in the display panel 100 row by row, and sends a control signal to the source driving circuit.
  • the source driver circuit connects the previous virtual sub-pixel row according to the received display data (for example, the display data of odd-numbered row display sub-pixels).
  • the system circuit 300 executes the data sending mode corresponding to the first display mode: deleting the original display data corresponding to the display sub-pixel in the received original display data.
  • the display data corresponding to the even-numbered row display sub-pixels is obtained, and the obtained display data corresponding to the even-numbered rows of display sub-pixels and the display data corresponding to each virtual sub-pixel are sent to the timing controller 200 .
  • the timing controller 200 sends a control signal corresponding to the first display mode to the gate driving circuit according to the received display data to control the gate driving circuit to drive the gate lines in the display panel 100 row by row, and sends a control signal to the source driving circuit.
  • the source driver circuit controls the display data of the previous virtual sub-pixel row according to the received display data (for example, the display data of the even-numbered rows of display sub-pixels).
  • the data voltage corresponding to the display data is input to the data line corresponding to the sub-pixel connected to the gate line connected to the next virtual sub-pixel row, and
  • the gate line connected to the display sub-pixel in the previous even-numbered row is driven and the gate line connected to the display sub-pixel in the next even-numbered row is being driven, the data voltage corresponding to the display data is input to the data line corresponding to the display sub-pixel in the next even-numbered row.
  • ga1 represents the signal loaded on the gate line GA1
  • ga2 represents the signal loaded on the gate line GA2
  • ga3 represents the signal loaded on the gate line GA3
  • ga4 represents the signal loaded on the gate line GA4
  • ga5 represents the signal loaded on the gate line GA5.
  • G6 represents the signal loaded on gate line GA6.
  • Vda1 represents the data voltage loaded on data line DA1.
  • the high level in the signals ga1 to ga6 can be used as a gate turn-on signal to control the conduction of the transistor in the sub-pixel.
  • gate turn-on signals can be loaded on the gate lines GA1 to GA6 in sequence. Take two adjacent display frames F01 and F02, the data line DA1, and the red sub-pixel connected to the data line DA1 as an example.
  • the transistor in the red sub-pixel R11 is turned on.
  • the data line DA1 connected to the red sub-pixel R11 is loaded with the data voltage Vr11 corresponding to the display data of the red sub-pixel R11, so that the red sub-pixel R11 inputs the data voltage Vr11.
  • the signal ga2 on the gate line GA2 outputs a high-level gate-on signal, and the transistor in the red sub-pixel R21 is turned on.
  • the data voltage Vr11 is simultaneously input into the red sub-pixel R21 to precharge the red sub-pixel R21.
  • the signal ga3 on the gate line GA3 outputs a high-level gate-on signal, and the transistor in the red sub-pixel R31 is turned on.
  • the data voltage Vr11 is simultaneously input into the red sub-pixel R31 to precharge the red sub-pixel R31.
  • the signal ga4 on the gate line GA4 outputs a high-level gate turn-on signal, and the transistor in the red sub-pixel R41 is turned on.
  • the data voltage Vr11 is simultaneously input into the red sub-pixel R41 to precharge the red sub-pixel R41.
  • the signal ga5 on the gate line GA5 outputs a high-level gate-on signal, and the transistor in the red sub-pixel R51 is turned on.
  • the data voltage Vr11 is simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51. And, in the T11 period, the signal ga6 on the gate line GA6 outputs a high-level gate turn-on signal, and the transistor in the red sub-pixel R61 is turned on. The data voltage Vr11 is simultaneously input into the red sub-pixel R61 to precharge the red sub-pixel R61.
  • the signal ga1 becomes low level, and the signal ga3 is high level.
  • the data line DA1 connected to the red sub-pixel R31 is loaded with the data voltage Vr31 corresponding to the display data of the red sub-pixel R31, so that the red sub-pixel R31 is charged with the data voltage Vr31.
  • the high level of the signal ga2 and the data voltage Vr31 are simultaneously input into the red sub-pixel R21 to charge the red sub-pixel R21.
  • the high level of the signal ga4 and the data voltage Vr31 are simultaneously input into the red sub-pixel R41 to precharge the red sub-pixel R41.
  • the high level of the signal ga5 and the data voltage Vr31 are simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51.
  • the high level of the signal ga6 and the data voltage Vr31 are simultaneously input into the red sub-pixel R61 to precharge the red sub-pixel R61.
  • the signal ga3 becomes low level, and the signal ga5 is high level.
  • the data line DA1 connected to the red sub-pixel R51 is loaded with the data voltage Vr51 corresponding to the display data of the red sub-pixel R51, so that the red sub-pixel R51 is charged with the data voltage Vr51.
  • the high level of the signal ga4 and the data voltage Vr51 are simultaneously input into the red sub-pixel R41 to charge the red sub-pixel R41.
  • the high level of the signal ga6 and the data voltage Vr51 are simultaneously input into the red sub-pixel R61 to precharge the red sub-pixel R61.
  • the transistor in the red sub-pixel R21 is turned on.
  • the data line DA1 connected to the red sub-pixel R21 is loaded with the data voltage Vr21 corresponding to the display data of the red sub-pixel R21, so that the red sub-pixel R21 inputs the data voltage Vr21.
  • the signal ga1 on the gate line GA1 outputs a high-level gate-on signal, and the transistor in the red sub-pixel R11 is turned on.
  • the data voltage Vr21 is simultaneously input into the red sub-pixel R11 to charge the red sub-pixel R11.
  • the signal ga3 on the gate line GA3 outputs a high-level gate-on signal, and the transistor in the red sub-pixel R31 is turned on.
  • the data voltage Vr21 is simultaneously input into the red sub-pixel R31 to precharge the red sub-pixel R31.
  • the signal ga4 on the gate line GA4 outputs a high-level gate turn-on signal, and the transistor in the red sub-pixel R41 is turned on.
  • the data voltage Vr21 is simultaneously input into the red sub-pixel R41 to precharge the red sub-pixel R41.
  • the signal ga5 on the gate line GA5 outputs a high-level gate turn-on signal, and the transistor in the red sub-pixel R51 is turned on.
  • the data voltage Vr21 is simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51.
  • the signal ga6 on the gate line GA6 outputs a high-level gate-on signal, and the transistor in the red sub-pixel R61 is turned on.
  • the data voltage Vr21 is simultaneously input into the red sub-pixel R61 to precharge the red sub-pixel R61.
  • the signal ga2 becomes low level, and the signal ga4 is high level.
  • the data line DA1 connected to the red sub-pixel R41 is loaded with the data voltage Vr41 corresponding to the display data of the red sub-pixel R41, so that the red sub-pixel R41 is charged with the data voltage Vr41.
  • the high level of the signal ga3 and the data voltage Vr41 are simultaneously input into the red sub-pixel R31 to charge the red sub-pixel R31.
  • the high level of the signal ga5 and the data voltage Vr41 are simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51.
  • the high level of the signal ga6 and the data voltage Vr41 are simultaneously input into the red sub-pixel R61 to precharge the red sub-pixel R61.
  • the signal ga4 becomes low level, and the signal ga6 is high level.
  • the data line DA1 connected to the red sub-pixel R61 is loaded with the data voltage Vr61 corresponding to the display data of the red sub-pixel R61, so that the red sub-pixel R61 is charged with the data voltage Vr61.
  • the high level of the signal ga5 and the data voltage Vr61 are simultaneously input into the red sub-pixel R51 to charge the red sub-pixel R51. and, precharging other red sub-pixels.
  • the working process of the remaining display frames can be basically the same as the working process of the above-mentioned display frame F01 and display frame F02, that is, the display panel 100 can work in the HSR display mode. , which can achieve high refresh frequency while increasing the charging rate of sub-pixels.
  • the even row sub-pixels can be charged by the data voltage of the adjacent odd-numbered row sub-pixels, thereby realizing the even-numbered row sub-pixels.
  • Pixel display function when the display panel 100 is driven in the first display mode, in the display frame F01, the even row sub-pixels can be charged by the data voltage of the adjacent odd-numbered row sub-pixels, thereby realizing the even-numbered row sub-pixels. Pixel display function.
  • the voltage charged by the red sub-pixel R21 may be related to the data voltage corresponding to the red sub-pixel R11 and the data voltage corresponding to the red sub-pixel R31 (which may be roughly the data voltage corresponding to the red sub-pixel R11 and the data corresponding to the red sub-pixel R31 The average value of the voltage), the voltage charged by the red sub-pixel R41 can be related to the data voltage corresponding to the red sub-pixel R31 and the data voltage corresponding to the red sub-pixel R51 (can be roughly the data voltage corresponding to the red sub-pixel R31 and the red sub-pixel The average value of the data voltage corresponding to R51).
  • the odd-numbered row sub-pixels can be charged by the data voltage of the adjacent even-numbered row sub-pixels, thereby realizing the display function of the odd-numbered row sub-pixels.
  • the voltage charged in the red sub-pixel R11 may be related to the data voltage corresponding to the red sub-pixel R21 (which may be roughly the data voltage corresponding to the red sub-pixel R21), and the voltage charged in the red sub-pixel R31 may correspond to the data voltage corresponding to the red sub-pixel R21.
  • the data voltage of is related to the data voltage corresponding to the red sub-pixel R41 (which can be roughly the average of the data voltage corresponding to the red sub-pixel R21 and the data voltage corresponding to the red sub-pixel R41).
  • the voltage charged by the red sub-pixel R51 can be related to the data voltage corresponding to the red sub-pixel R41 and the data voltage corresponding to the red sub-pixel R61 (which can be roughly the data voltage corresponding to the red sub-pixel R41 and the data voltage corresponding to the red sub-pixel R61). average value).
  • one of the plurality of display modes may be a third display mode.
  • the third display mode includes: in each display frame, at least two adjacent rows of gate lines are used as a gate line group, and the system circuit 300 executes the data sending mode corresponding to the third display mode: the received original display data is After the deletion process, display data corresponding to sub-pixels electrically connected to one gate line in each gate line group is obtained, and the obtained display data is sent to the timing controller 200 .
  • the timing controller 200 sends a control signal corresponding to the third display mode to the gate driving circuit according to the received display data, so as to control the gate driving circuit to simultaneously drive the gate lines in the same gate line group and drive the gate line groups one by one.
  • the source drive circuit completes driving the gate lines in the previous gate line group based on the received display data, and the next
  • the data voltage corresponding to the display data is input to the data line corresponding to the sub-pixel connected to the gate line of the next gate line group.
  • two adjacent rows of gate lines can be used as a gate line group; or, three adjacent rows of gate lines can be used as a gate line group; or, adjacent rows of gate lines can also be used as a gate line group. ; Alternatively, more adjacent rows of gate lines can also be combined into a gate line group, which is not limited here.
  • the gate lines GA1 and GA2 are a gate line group
  • the gate lines GA3 and GA4 are a gate line group
  • the gate lines GA5 and GA6 are a gate line group.
  • the display data corresponding to each sub-pixel connected to the gate line GA2 the display data corresponding to each sub-pixel connected to the gate line GA4, and the display data corresponding to each sub-pixel connected to the gate line GA4 can also be obtained. Display data and send these display data to the timing controller 200, which is not limited here.
  • ga1 represents the signal loaded on the gate line GA1
  • ga2 represents the signal loaded on the gate line GA2
  • ga3 represents the signal loaded on the gate line GA3
  • ga4 represents the signal loaded on the gate line GA4
  • ga5 represents the signal loaded on the gate line GA5.
  • G6 represents the signal loaded on gate line GA6.
  • Vda1 represents the data voltage loaded on data line DA1.
  • the high level in the signals ga1 to ga6 can be used as a gate turn-on signal to control the conduction of the transistor in the sub-pixel.
  • the display panel 100 When the display panel 100 is controlled to be driven in the first display mode, taking a display frame F04, data line DA1 and a red sub-pixel connected to the data line DA1 as an example, the signal ga1 on the gate line GA1 and the signal ga2 on the gate line GA2 are simultaneously A high-level gate turn-on signal is output, and the transistors in the red sub-pixels R11 and R21 are turned on at the same time. And in the T41 period corresponding to the high level of the signals ga1 and ga2, the data voltage Vr11 corresponding to the display data is input to the data line DA1 connected to the red sub-pixels R11 and R21, so that the red sub-pixels R11 and R21 are charged with the data voltage. Vr11.
  • the signal ga3 on the gate line GA3 and the signal ga4 on the gate line GA4 output a high-level gate-on signal at the same time, and the transistors in the red sub-pixels R31 and R41 are turned on at the same time.
  • the data voltage Vr11 is simultaneously input into the red sub-pixels R31 and R41 to precharge the red sub-pixels R31 and R41.
  • the data line DA1 connected to the red sub-pixels R31 and R41 is loaded with the data voltage Vr31 corresponding to the display data, so that the red sub-pixels R31 and R41 are charged with data.
  • Voltage Vr31 the signal ga5 on the gate line GA5 and the signal ga6 on the gate line GA6 simultaneously output a high-level gate-on signal, and the transistors in the red sub-pixels R51 and R61 are turned on.
  • the data voltage Vr31 is simultaneously input into the red sub-pixels R51 and R61 to precharge the red sub-pixels R51 and R61.
  • the data line DA1 connected to the red sub-pixels R51 and R61 is loaded with the data voltage Vr51 corresponding to the display data, so that the red sub-pixels R51 and R61 are charged with data. Voltage Vr51. And precharge the next red sub-pixel.
  • each display frame can be basically the same as the working process of the above-mentioned display frame F04, that is, the display panel 100 can work in the DLG display mode, which will not be described again here.
  • the refresh frequency of the second display mode may be made smaller than the refresh frequency of the first display mode and the refresh frequency of the third display mode.
  • the refresh frequency of the display panel 100 may include 30Hz, 48Hz, 60Hz, 90Hz, 96Hz, 120Hz, 144Hz, 240Hz, etc.
  • the refresh frequency of the first display mode, the refresh frequency of the second display mode, and the refresh frequency of the third display mode can be selected from the refresh frequencies supported by the display panel 100 .
  • the refresh frequency of the second display mode includes 60 Hz
  • the refresh frequency of the first display mode includes 120 Hz
  • the refresh frequency of the third display mode includes 120 Hz.
  • the refresh frequency of the first display mode, the refresh frequency of the second display mode, and the refresh frequency of the third display mode can be determined according to the needs of the actual application, and are not limited here.
  • the display mode can be switched in different application scenarios.
  • the system circuit since the data transmission mode switching speed of the system circuit is slower than the display mode switching speed of the timing controller, after the timing controller completes switching from the second display mode to the first display mode, the system circuit usually has not completed the switching. At this time, the system The circuit still uses the data sending mode corresponding to the second display mode to send the original display data Vdata1 corresponding to all sub-pixels to the timing controller. After the timing controller receives the original display data Vdata1, the counting unit will count the total number of corresponding sub-pixel rows in the original display data Vdata1 to obtain the statistical number of the corresponding sub-pixel rows.
  • the timing controller since the timing controller has switched to the first display mode, the set number corresponding to the counting unit in the first display mode is different from the statistical number obtained by counting the original display data Vdata1, causing the counting unit to be unable to be automatically cleared, causing the counting unit to If it gets stuck, the counting unit returns an abnormal command to the timing controller, and the timing controller will enter the warning mode where the control display panel displays the warning screen, resulting in abnormal display.
  • embodiments of the present disclosure provide a driving method for a display panel.
  • the display panel When receiving a display mode switching enable command, the display panel is driven to display the first setting screen and switches the current display mode to the target display mode to achieve The process of mode switching. Moreover, when receiving the display mode switching enable command, it enters the non-counting state and puts the counting unit in the non-counting working state. In this way, even after the timing controller receives the display data sent by the system circuit, it will not process any received data. Display data for statistics.
  • the non-counting state is released and the counting state is entered, so that the counting unit is in the counting working state, so that any received display data can be counted. In this way, after the system circuit completes the mode switch and then starts the counting work, it can avoid the problem of the counting unit being stuck due to the inability of the counting unit to automatically clear.
  • the display panel driving method provided by the embodiment of the present disclosure may include the following steps:
  • the driving method provided by the embodiment of the present disclosure can realize switching between different display modes according to the actual application scenario of the display panel. For example, game display screens require a high refresh frequency. However, a high refresh frequency will compress the charging time of the sub-pixels of the display panel, resulting in insufficient charging of the sub-pixels. In the embodiments of the present disclosure, when switching from a display mode with a low refresh frequency to a display mode with a high refresh frequency, a high refresh frequency can be achieved while improving the charging rate of the sub-pixels.
  • the system circuit 300 determines to switch between different display modes according to the application scenario.
  • the current application scenario of the display panel 100 can be a common video playback interface, and the second display mode is used to drive the display panel 100 to display images.
  • the system circuit 300 recognizes that the next application scenario is a game interface, and the game interface requires a higher refresh frequency.
  • the system circuit 300 can determine that different display modes need to be switched, and then sends the display mode to the timing controller 200 Switching on command, when the timing controller 200 receives the display mode switching on command, executes the process of step S10.
  • the system circuit 300 also switches its own data sending mode corresponding to the current display mode to the data sending mode corresponding to the target display mode.
  • the display device may further include a connector 400 .
  • the first end 410 of the connector 400 is connected to the system circuit 300
  • the second end 420 of the connector 400 is connected to the timing controller 200 .
  • the first end 410 of the connector 400 may include a first IIC pin 411 and a first switching command transmission pin 412
  • the second end 420 of the connector 400 may include a second IIC pin 421 and a second switching command transmission pin. 422.
  • the system circuit 300 outputs a handshake signal through the first IIC pin corner 410
  • the timing controller 200 receives the handshake signal through the second IIC pin corner 421, and performs handshake with the system circuit 300 after receiving the handshake signal.
  • the system circuit 300 and the timing controller 200 are connected, and signal transmission can be carried out.
  • the system circuit 300 can output the display mode switching enable instruction through the first switching instruction transmission pin 412 (for example, raising the level of the first switching instruction transmission pin 412), and the timing controller 200 can output the display mode switching enable instruction through the second switching instruction transmission pin 412.
  • the command transmission pin 422 receives the display mode switching enable command output by the system circuit 300 (for example, because the level of the first switching command transmission pin 412 is pulled high, the second switching command transmission pin 422 is also pulled high).
  • the system circuit 300 can output a display mode switching enable command in the form of a digital signal through the first IIC pin 411 (for example, the display mode switch enable command has Byte0 ⁇ Byte1.
  • the timing controller 200 receives the display mode switching enable command through the second IIC pin 421, and performs the display mode switching process according to the display mode switch enable command. And, when the system circuit 300 determines that there is no need to switch the display mode, the system circuit 300 can output a display mode switching stop command in the form of a digital signal through the first IIC pin 411 (for example, the display mode switching stop command has Byte0 ⁇ Byte1.
  • the timing controller 200 receives the display mode switching stop command through the second IIC pin 421, and the timing controller 200 does not perform display mode switching.
  • the first end 410 of the connector 400 may also include a first data transmission pin corner 413 ; the second end 420 of the connector 400 may also include a second data transmission pin corner 423 .
  • the system circuit 300 may output display data through the first data transmission pin 413 .
  • the timing controller 200 receives the display data through the second data transmission pin 423 .
  • the display device further includes: a counting unit 500 .
  • the counting unit 500 is configured to count the first number of corresponding set targets in the display data, and output a counting pass instruction when it is determined that the first number is the same as the set number corresponding to the target display mode.
  • the timing controller 200 is configured to control the counting unit 500 to enter a non-counting state when receiving a display mode switching start instruction; and to control the counting unit 500 to enter a counting state when receiving a data mode switching completion instruction.
  • the counting unit 500 can be integrated in the timing controller 200 to improve the integration level and shorten the length of the data transmission line between the timing controller 200 and the counting unit 500 .
  • counting unit 500 may include, but is not limited to, a counter circuit.
  • the timing controller 200 when the timing controller 200 receives the display mode switching enable command, the timing controller 200 controls the counting unit 500 to be in a clearing state, so that the counting unit 500 does not perform the counting operation and maintains the clearing operation to enter the non-zero state. Count status.
  • the timing controller 200 receives the display mode switching enable command, the counting unit 500 is controlled to be in a disable state, that is, the counting unit 500 is not enabled, and the counting unit 500 does not perform a counting operation to enter a non-counting state.
  • the timing controller 200 when the timing controller 200 receives the display mode switching enable command, it does not supply power to the counting unit 500 and controls the counting unit 500 to be in a power-off state, so that the counting unit 500 does not perform a counting operation and enters a non-counting state. This is because the counting unit 500 does not perform a counting operation. Even if the system circuit 300 sends display data, it will not count the set targets in the display data, thereby avoiding the problem of stuck.
  • the circuit board on which the timing controller 200 is located will be equipped with a flash memory (Flash), and the display data corresponding to the first setting screen is stored in the flash memory (the display data includes one-to-one corresponding data voltage for each sub-pixel). digital voltage form).
  • flash flash memory
  • the timing controller 200 switches from the second display mode to the first display mode, since the timing controller 200 begins to enter the switching process of different display modes when receiving the display mode switching enable command, during the display mode switching Before completion, the timing controller 200 still drives the display panel 100 to display images in the second display mode.
  • the timing controller 200 when receiving the display mode switching enable command, obtains the pre-stored display data corresponding to the first setting screen from the flash memory, and outputs the obtained display data corresponding to the first setting screen to Source driver circuit 120.
  • the source driving circuit 120 can receive the display data corresponding to the first setting screen, and load the corresponding data voltage to the data line according to the display data corresponding to the first setting screen.
  • the timing controller 200 inputs a control signal to the gate driving circuit, and the gate driving circuit drives the gate lines row by row.
  • the specific process refer to the above-mentioned driving process when the display panel 100 adopts the second display mode, thereby driving the display panel 100 to display the first display mode. Setting screen.
  • the timing controller 200 may drive the display panel 100 to display a picture according to the first display mode. Specifically, the timing controller 200 obtains the pre-stored display data corresponding to the first setting screen from the flash memory, and performs deletion processing on the display data corresponding to the display sub-pixels in the obtained display data corresponding to the first setting screen. Finally, the display data corresponding to the virtual sub-pixels and the remaining display data corresponding to the display sub-pixels are output to the source driving circuit 120 .
  • the source driving circuit 120 can receive the display data and load corresponding data voltages to the data lines according to the display data.
  • the timing controller 200 inputs a control signal to the gate driving circuit, and the gate driving circuit drives the gate lines row by row. For the specific process, refer to the above-mentioned driving process when the display panel 100 adopts the second display mode, thereby driving the display panel 100 to display the first display mode. Setting screen.
  • the current display mode may be the second display mode
  • the target display mode may be the first display mode.
  • the display panel 100 can be switched from the second display mode to the first display mode which is the HSR display mode.
  • a game-type display screen requires a high refresh frequency. Therefore, when the display panel 100 is to display a game-type display screen, the first display mode as the HSR display mode can be used. In this way, a high refresh frequency can be achieved while improving the sub-pixel efficiency. charging rate.
  • the second display mode corresponding to 120Hz 4K 2K can be switched to the first display mode corresponding to 240Hz 4K 1K.
  • the current display mode may be the second display mode
  • the target display mode may be the third display mode.
  • the display panel 100 can be switched from the second display mode to the third display mode which is the DLG display mode.
  • a game-type display screen requires a high refresh frequency. Therefore, when the display panel 100 is to display a game-type display screen, the third display mode as the DLG display mode can be used. In this way, a high refresh frequency can be achieved while improving the sub-pixel efficiency. charging rate.
  • the current display mode may be the third display mode
  • the target display mode may be the first display mode.
  • the display panel 100 can be switched from the third display mode as the DLG display mode to the first display mode as the HSR display mode. Since the screen resolution displayed by the display panel 100 in the third display mode as the DLG display mode will be reduced, although the screen resolution displayed by the display panel 100 in the first display mode as the HSR display mode will also be reduced, the display When the panel 100 is in the first display mode as the HSR display mode, the input voltages of the sub-pixels in two adjacent rows in the same column are not exactly the same. Therefore, the display panel 100 displays in the first display mode as the HSR display mode. The picture will be more detailed. Therefore, when the display panel 100 wants to display a game display picture, the first display mode as the HSR display mode can be used to further improve the display quality of the picture.
  • the current display mode may be the first display mode
  • the target display mode may be the third display mode.
  • the display panel 100 can be switched from the first display mode as the HSR display mode to the third display mode as the DLG display mode.
  • the third display mode as the DLG display mode can be used to further improve the charging rate of the sub-pixels.
  • the current display mode may be the third display mode
  • the target display mode may be the second display mode.
  • the third display mode which is the DLG display mode
  • a static display does not require a high refresh frequency, but requires lower power consumption. Therefore, when the display panel 100 displays a static display, the second display mode as a normal display mode can be used, which can reduce power consumption. Consumption.
  • the current display mode may be the first display mode
  • the target display mode may be the second display mode.
  • the first display mode which is the HSR display mode
  • the second display mode as a normal display mode can be used, which can reduce power consumption. Consumption.
  • the first display mode corresponding to 240Hz 4K 1K can be switched to the second display mode corresponding to 120Hz 4K 2K.
  • Gray scale generally divides the brightness change between the darkest and the brightest into several parts to facilitate screen brightness control.
  • the displayed image consists of three colors: red, green, and blue. Each color can show different brightness levels, and the combination of red, green, and blue with different brightness levels can form different colors.
  • the number of grayscale bits of the liquid crystal display panel 100 is 6 bits, so the three colors of red, green, and blue respectively have 64 (ie, 2 6 ) grayscales, and these 64 grayscale values are 0 to 63 respectively.
  • the number of grayscale bits of the liquid crystal display panel 100 is 8 bits, so the three colors of red, green, and blue respectively have 256 (that is, 2 8 ) grayscales, and these 256 grayscale values are 0 to 255 respectively.
  • the number of gray scale bits of the liquid crystal display panel 100 is 10 bits, so the three colors of red, green, and blue respectively have 1024 (ie, 2 10 ) gray scales, and these 1024 gray scale values are 0 to 1023 respectively.
  • the gray scale number of the liquid crystal display panel 100 is 12 bits, so the three colors of red, green and blue respectively have 4096 (ie 2 12 ) gray scales, and these 4096 gray scale values are 0 to 4093 respectively.
  • the first setting screen may include a solid color screen.
  • the first setting screen may include a red solid color screen, a green solid color screen, and a blue solid color screen.
  • the red sub-pixel input in the display panel 100 corresponds to the same grayscale value (for example, 127 grayscale value, 255 grayscale value). value, etc.), and the green sub-pixel and blue sub-pixel inputs correspond to the data voltage of the display data with a grayscale value of 0.
  • the green sub-pixel in the display panel 100 inputs the data voltage corresponding to the display data of the same gray scale value (for example, 127 gray scale value, 255 gray scale value, etc.), and the red sub-pixel and blue The sub-pixel inputs a data voltage corresponding to display data with a grayscale value of 0.
  • the blue sub-pixel in the display panel 100 inputs the data voltage corresponding to the display data of the same gray-scale value (for example, 127 gray-scale value, 255 gray-scale value, etc.), and the green sub-pixel and The red sub-pixel inputs a data voltage corresponding to display data with a grayscale value of 0.
  • the first setting screen may also include a grayscale screen.
  • the grayscale picture may be a picture in which sub-pixels of various colors have the same grayscale value. For example, assuming that the display panel 100 has a grayscale value of 0 to 255, the sub-pixels of various colors have a grayscale value of 0 (ie, a black screen).
  • the sub-pixels of each color are images with 127 grayscale values. Or, a picture in which the sub-pixels of each color are all 100 grayscale values. Or, the sub-pixels of each color are all 200 grayscale values. Or, the sub-pixels of each color are all 255 grayscale values.
  • the system circuit 300 may send a data mode switching completion instruction to the timing controller 200 after completing switching the data transmission mode corresponding to the current display mode to the data transmission mode corresponding to the target display mode. Since the switching speed of the system circuit 300 is smaller than the switching speed of the timing controller 200, after the switching of the system circuit 300 is completed, the timing controller 200 has completed the switching. Therefore, when the system circuit 300 sends the data mode switching completion command to the timing controller 200, the timing The controller 200 may determine that the system circuit 300 has completed switching, and upon receiving the data mode switching completion instruction, control the counting unit 500 to enter the counting state. For example, the timing controller 200 can enable the counter circuit in the counting unit 500 so that the counter circuit can perform a counting operation.
  • the system circuit 300 can also output a data mode switching completion instruction in the form of a digital signal through the first IIC pin 411 (for example, the display mode switching start instruction has Byte0 ⁇ Byte1.
  • the display mode switching start instruction has Byte0 ⁇ Byte1.
  • Byte0 is 0xC2
  • Byte1 is 0xF26F
  • Byte2 is 0x01
  • Byte3 is 0x66
  • the timing controller 200 receives the data mode switching completion instruction through the second IIC pin 421, and controls the counter circuit to start the function of performing the counting operation according to the data mode switching completion instruction.
  • the counting state after entering the counting state, it may also include: receiving display data; counting the first number of corresponding set targets in the display data; and determining that the first number is the same as the set number corresponding to the target display mode.
  • the display panel 100 is driven to display the corresponding screen.
  • the system circuit 300 may use a data sending mode corresponding to the target display mode to process the received original display data into display data corresponding to the target display mode.
  • the processed display data is output to the timing controller 200 .
  • the timing controller 200 controls the counting unit 500 to count the corresponding set targets in the display data to obtain the first number.
  • the counting unit 500 determines that the first number of statistics is the same as the set number corresponding to the target display mode, it can automatically clear it and feed back a pass instruction to the timing controller 200.
  • the timing controller 200 receives the pass instruction.
  • the timing controller 200 can drive the display panel 100 to display based on the target display mode and the received display data. corresponding screen.
  • the display panel 100 includes a plurality of sub-pixel rows, wherein the sub-pixel rows may have display sub-pixel rows (the first to sixth rows of sub-pixels as shown in FIG. 3 ) and virtual sub-pixels. OK. Setting the target may include sub-pixel rows of the display panel 100 .
  • the set number may include the total number of all virtual sub-pixel rows and half of the total number of display sub-pixel rows.
  • the counting unit 500 can count the number of corresponding sub-pixel rows in the display data received by the timing controller 200 to calculate the total number of these sub-pixel rows as the first number.
  • the set number may be half of the total number of all virtual sub-pixel rows and the total number of display sub-pixel rows.
  • the display panel 100 includes a plurality of sub-pixel rows, wherein the sub-pixel rows may have display sub-pixel rows (the first to sixth rows of sub-pixels as shown in FIG. 3 ) and virtual sub-pixels. OK. Setting the target may include sub-pixel rows of the display panel 100 .
  • the target display mode is the second display mode
  • the set number may include the total number of all virtual sub-pixel rows and the total number of all display sub-pixel rows.
  • the counting unit 500 can count the number of corresponding sub-pixel rows in the display data received by the timing controller 200 to calculate the total number of these sub-pixel rows as the first number.
  • the set number may be the total number of all virtual sub-pixel rows and the total number of all display sub-pixel rows. For example, when switching from the second display mode to the first display mode, if the display data of the second display mode is 4K2K display data, the number of settings corresponding to the second display mode may be 2177 (including 2160 display sub-pixel rows). and 17 virtual sub-pixel rows), the set number corresponding to the first display mode may be 1097 (including 1080 display sub-pixel rows (ie, half of the total number of display sub-pixel rows) and 17 virtual sub-pixel rows).
  • the display panel 100 includes a plurality of sub-pixel rows, wherein the sub-pixel rows may have display sub-pixel rows (the first to sixth rows of sub-pixels as shown in FIG. 3 ) and virtual sub-pixels. OK.
  • the plurality of sub-pixel rows are divided into a plurality of gate line groups, and the setting target may include the gate line groups of the display panel 100 .
  • the set number includes the total number of gate line groups.
  • the counting unit 500 can count the number of corresponding gate line groups in the display data received by the timing controller 200 to calculate the total number of these gate line groups as the first number. After the timing controller 200 switches to the third display mode, the set number may be the total number of all gate line groups.
  • the timing controller 200 may directly drive the display panel 100 to display the corresponding screen based on the target display mode and the received display data.
  • the function may be unstable.
  • the first number and the setting target are determined.
  • the display panel 100 is driven to display the second setting screen in at least one display frame based on the target display mode, and then the display panel 100 is driven to display the corresponding screen based on the target display mode and the received display data. .
  • the system circuit 300 may use a data sending mode corresponding to the target display mode to process the received original display data into display data corresponding to the target display mode.
  • the processed display data is output to the timing controller 200 .
  • the timing controller 200 controls the counting unit 500 to count the corresponding set targets in the display data to obtain the first number.
  • the counting unit 500 may feedback a pass instruction to the timing controller 200 .
  • the timing controller 200 may drive the display panel 100 to display the second setting screen in one or more display frames based on the target display mode. Afterwards, based on the target display mode and the received display data, the display panel 100 is driven to display the corresponding screen.
  • the setting time may be determined according to the time it takes for the system circuit 300 to switch to improve stability. Alternatively, the setting time may also be determined based on the interval between the timing controller 200 receiving the display mode switching start instruction and the data mode switching completion instruction to further improve stability.
  • the refresh frequency corresponding to the target display mode is 240 Hz
  • one display frame The time is approximately 4.16ms
  • the number of display frames SM for displaying the second setting screen can be 20.
  • the refresh frequency corresponding to the target display mode is 120Hz
  • the time of one display frame at 120Hz is approximately 8.33ms
  • the number of display frames SM for displaying the second setting screen can be 10 .
  • the second setting screen may include a solid color screen.
  • the second setting screen may include a red solid color screen, a green solid color screen, and a blue solid color screen.
  • the red sub-pixel input in the display panel 100 corresponds to the same grayscale value (for example, 127 grayscale value, 255 grayscale value). value, etc.)
  • the green sub-pixel and blue sub-pixel inputs correspond to the data voltage of the display data with a grayscale value of 0.
  • the green sub-pixel in the display panel 100 inputs the data voltage corresponding to the display data of the same gray scale value (for example, 127 gray scale value, 255 gray scale value, etc.), and the red sub-pixel and blue The sub-pixel inputs a data voltage corresponding to display data with a grayscale value of 0.
  • the blue sub-pixel in the display panel 100 inputs the data voltage corresponding to the display data of the same gray-scale value (for example, 127 gray-scale value, 255 gray-scale value, etc.), and the green sub-pixel and The red sub-pixel inputs a data voltage corresponding to display data with a grayscale value of 0.
  • the second setting screen may also include a grayscale screen.
  • the grayscale picture may be a picture in which sub-pixels of various colors have the same grayscale value. For example, assuming that the display panel 100 has a grayscale value of 0 to 255, the sub-pixels of various colors have a grayscale value of 0 (ie, a black screen).
  • the sub-pixels of each color are images with 127 grayscale values. Or, a picture in which the sub-pixels of each color are all 100 grayscale values. Or, the sub-pixels of each color are all 200 grayscale values. Or, the sub-pixels of each color are all 255 grayscale values.
  • the display data of the second setting screen may also be stored in the flash memory.
  • the first setting screen and the second setting screen can be made the same, so that only the display data of the first setting screen or the second setting screen can be stored in the flash memory, thereby reducing the storage space required for storage.
  • the first setting screen and the second setting screen may also be different, which is not limited here.
  • the system circuit 300 may include a system on a chip (SOC).
  • SOC system on a chip
  • the system circuit 300 can be implemented in other ways, which are not limited here.
  • the system circuit 300 When the display device is turned on, the system circuit 300 is powered on, and the system circuit 300 provides the supply voltage VIN1 to the timing controller 200 through the first power supply pin of the connector 400, such as 3.3V, and then pulls the first power supply pin high from 0V. is 3.3V.
  • the system circuit 300 provides the supply voltage VIN2 to the timing controller 200 through the second power supply pin of the connector 400, such as 1.1V, and then pulls the second power supply pin from 0V to 1.1V.
  • the system circuit 300 provides the supply voltage VIN3, such as 1.8V, to the timing controller 200 through the third power supply pin of the connector 400, and then pulls the third power supply pin from 0V to 1.8V.
  • the system circuit 300 provides the initialization voltage RES to the timing controller 200 through the initialization pin angle of the connector 400, such as 1.15V, and then raises the initialization pin angle from 0V to 1.15V.
  • t1 represents the delay time from when the first power supply pin angle is pulled up from 0V to 2.8V to when the second power supply pin angle is pulled up from 0V to 0.8V
  • t2 represents when the second power supply pin angle is pulled up from 0V to 0.8V.
  • t2 represents the delay time from when the third power supply pin angle is pulled up from 0V to 1.5V to when the initialization pin angle is pulled up from 0V to 0.8V.
  • the timing controller 200 can start the function to be performed after the supply voltages VIN1 ⁇ VIN3 are stable. After the initialization voltage is raised to 1.15V, phase t4 is entered, and the timing controller 200 performs an initialization operation to determine the current display mode as the second display mode. That is to say, when the timing controller 200 is powered on again, it will perform the operation of the second display mode by default. After entering the t5 stage, the system circuit has not determined that the display mode needs to be switched, so it continues to use the second display mode to drive the display panel 100 to display 4K2K data.
  • the system circuit After entering the t6 stage, the system circuit determines that it is necessary to perform a switching process of switching the second display mode (for example, 4K2K display data) to the first display mode (for example, 4K1K display data).
  • the system circuit 300 raises the level of the first switching command transmission pin 412 to output the display mode switching enable command through the first switching command transmission pin 412 . And start the switching process of switching the data sending mode corresponding to the second display mode to the data sending mode corresponding to the first display mode.
  • the timing controller 200 Since the level of the first switching command transmission pin 412 is pulled high, the second switching command transmission pin 422 is also pulled high, and the timing controller 200 receives the display output from the system circuit 300 through the second switching command transmission pin 422
  • the mode switching enable command controls the counter circuit in the counting unit 500 to be in a clearing state, so that the counter circuit in the counting unit 500 does not perform a counting operation and maintains a clearing operation to enter a non-counting state.
  • the timing controller 200 obtains the pre-stored display data corresponding to the black screen from the flash memory. Since it also takes time for the timing controller 200 to switch its second display mode to the first display mode, before the display mode switching is completed, the timing controller 200 still inputs a control signal to the gate drive circuit in the second display mode.
  • the gate driving circuit is controlled to drive the gate lines row by row.
  • the timing controller 200 outputs the acquired display data (eg, 4K2K data) corresponding to the black screen to the source driving circuit 120 in the second display mode.
  • the source driving circuit 120 can receive the display data corresponding to the black screen, and load the corresponding data voltage to the data line according to the display data corresponding to the black screen, and drive the display panel 100 to display the black screen.
  • the system circuit 300 can send display data to the timing controller 200 while switching.
  • the display data sent by the system circuit 300 can be received, and the received display data can be cached or not stored.
  • the counter circuit in the counting unit 500 since the counter circuit in the counting unit 500 is controlled to be in a clear state, the counter circuit in the counting unit 500 will not make statistics on any received display data.
  • the timing controller 200 inputs a control signal to the gate driving circuit in the first display mode, and controls the gate driving circuit to drive the gate lines row by row. And the timing controller 200 outputs the obtained display data corresponding to the black screen (for example, 4K1K display data) to the source driving circuit 120 in the first display mode.
  • the source driving circuit 120 can receive the display data corresponding to the black screen, and load the corresponding data voltage to the data line according to the display data corresponding to the black screen, and drive the display panel 100 to display the black screen.
  • the system circuit 300 can send display data to the timing controller 200 while switching. After the switching of the timing controller 200 is completed, the display data sent by the system circuit 300 can be received, and the received display data can be cached or not stored. Moreover, since the control counting unit 500 is in a clearing state, the counting unit 500 will not make statistics on any received display data.
  • the system circuit 300 After the system circuit 300 completes switching the data transmission mode corresponding to the second display mode to the data transmission mode corresponding to the first display mode, it outputs a data mode switching completion instruction in the form of a digital signal through the first IIC pin 411.
  • the timing controller 200 receives the data mode switching completion instruction through the second IIC pin 421, and controls the counter circuit in the counting unit 500 to release the non-counting state and start the function of performing counting operations according to the data mode switching completion instruction.
  • the system circuit 300 uses the data transmission mode corresponding to the second display mode to send the display data.
  • the timing controller 200 receives the display data and controls the counter circuit in the counting unit 500 to count the corresponding sub-pixel rows in the display data to obtain the third statistics. A number.
  • the timing controller 200 When the counter circuit in the counting unit 500 determines that the first number of statistics is the same as the set number (such as 1097) corresponding to the first display mode, it can be automatically cleared and feedback a pass instruction to the timing controller 200.
  • the timing When the controller 200 receives the pass instruction, it can determine that the display data output by the system circuit 300 corresponds to the display data required by the first display mode. Therefore, the timing controller 200 can, based on the first display mode, according to The received display data (for example, 4K1K display data) drives the display panel 100 to display the corresponding screen.
  • the timing controller 200 When the counter circuit in the counting unit 500 determines that the first number of statistics is different from the set number (such as 1097) corresponding to the first display mode, it cannot be automatically cleared and feeds back an abnormal readback instruction (such as 32448) to the timing controller 200 ), when the timing controller 200 receives the abnormal readback command, it can determine that the display data output by the system circuit 300 does not correspond to the display data required for the first display mode. Therefore, the timing controller 200 reads the display data from the flash memory. The display data of the warning screen is obtained, and based on the first display mode, the display panel 100 is driven to display the warning screen (for example, a red village color screen, a green solid color screen, and a blue solid color screen are played in a loop). It should be noted that the warning screen is different from the first setting screen and the second setting screen, so that the corresponding prompt information can be obtained through the difference in the display screen.
  • an abnormal readback instruction such as 32448
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • the driving method and display device can realize switching between different display modes according to the actual application scenario of the display panel 100 .
  • game display screens require a high refresh rate.
  • a high refresh rate will compress the charging time of 100 sub-pixels on the display panel, resulting in insufficient charging of the sub-pixels.
  • a high refresh frequency can be achieved while improving the charging rate of the sub-pixels.
  • embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

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Abstract

显示面板（100）的驱动方法及显示装置，驱动方法包括：在接收到显示模式切换开启指令时，进入非计数状态，并驱动显示面板（100）显示第一设定画面，并将当前显示模式切换至目标显示模式（S10）；在接收到数据模式切换完成指令时，进入计数状态（S20）。

Description

显示面板的驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及显示面板的驱动方法及显示装置。
背景技术
在诸如液晶显示面板(Liquid Crystal Display，LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板中，一般包括多个像素单元。每个像素单元可以包括：红色子像素、绿色子像素以及蓝色子像素。通过控制每个子像素对应的亮度，从而混合出所需显示的色彩来显示彩色图像。
发明内容
本公开实施例提供的显示面板的驱动方法，包括：
在接收到显示模式切换开启指令时，进入非计数状态，并驱动所述显示面板显示第一设定画面，并将当前显示模式切换至目标显示模式；
在接收到数据模式切换完成指令时，进入计数状态。
在一些示例中，在所述进入计数状态之后，还包括：
接收显示数据；
统计所述显示数据中对应的设定目标的第一数目；
在确定所述第一数目与所述目标显示模式对应的设定数目相同后，基于所述目标显示模式，根据接收到的所述显示数据，驱动所述显示面板显示对应的画面。
在一些示例中，在所述统计所述显示数据中对应的设定目标的第一数目之后，且在确定所述第一数目与所述目标显示模式对应的设定数目相同后，基于所述目标显示模式，根据接收到的所述显示数据，驱动所述显示面板显示对应的画面之前，还包括：
在确定所述第一数目与所述设定数目相同时，基于所述目标显示模式， 驱动所述显示面板在至少一个显示帧中显示第二设定画面。
在一些示例中，采用如下公式确定显示所述第二设定画面的显示帧的数量；
SM＝TM/AM；
其中，SM代表显示所述第二设定画面的显示帧的数量，TM代表设定时间，AM代表所述目标显示模式对应的刷新频率的倒数。
在一些示例中，所述第一设定画面和所述第二设定画面中的至少一个包括纯色画面和灰阶画面中的至少一个。
在一些示例中，所述非计数状态包括清零状态、未使能状态以及断电状态中的一种。
在一些示例中，所述显示面板包括第一显示模式；其中，所述第一显示模式包括：在相邻的两个显示帧的第一个显示帧中，逐行驱动所述显示面板中的栅线，并在上一个奇数行显示子像素连接的栅线驱动完，且下一个奇数行显示子像素连接的栅线驱动中时，对所述下一个奇数行显示子像素对应的数据线输入对应显示数据的数据电压；以及，在相邻的两个显示帧的第二个显示帧中，逐行驱动所述显示面板中的栅线，并在上一个偶数行显示子像素连接的栅线驱动完，且下一个偶数行显示子像素连接的栅线驱动中时，对所述下一个偶数行显示子像素对应的数据线输入对应显示数据的数据电压。
在一些示例中，所述显示面板包括第二显示模式；其中，所述第二显示模式包括：在各显示帧中，逐行驱动栅线，并在上一行栅线驱动完，且下一行栅线驱动中时，对下一行栅线连接的子像素对应的数据线输入对应显示数据的数据电压。
在一些示例中，所述显示面板包括第三显示模式；其中，所述第三显示模式包括：在各显示帧中，以至少相邻两行栅线为一个栅线组，接收各所述栅线组中一行子像素对应的显示数据，根据接收到的显示数据，同时驱动同一所述栅线组中的栅线，并逐个驱动所述栅线组，在上一个所述栅线组中的栅线驱动完，且下一个所述栅线组中的栅线驱动中时，对下一个所述栅线组 的栅线连接的子像素对应的数据线输入对应显示数据的数据电压。
在一些示例中，所述当前显示模式为所述第一显示模式、所述第二显示模式以及所述第三显示模式中的一个；
所述目标显示模式为所述第一显示模式、所述第二显示模式以及所述第三显示模式中，除所述当前显示模式之外的一个。
在一些示例中，所述设定目标包括所述显示面板的子像素行；
所述显示面板包括显示子像素行和虚拟子像素行；
在所述目标显示模式为所述第一显示模式时，所述设定数目包括所有的虚拟子像素行的总数和所述显示子像素行的总数的一半；
在所述目标显示模式为所述第二显示模式时，所述设定数目包括所有的虚拟子像素行的总数和所有显示子像素行的总数。
在一些示例中，所述设定目标包括所述显示面板的栅线组；
在所述目标显示模式为所述第三显示模式时，所述设定数目包括栅线组的总数。
本公开实施例提供的显示装置，包括：
显示面板；
时序控制器，被配置为：
在接收到显示模式切换开启指令时，进入非计数状态，并驱动所述显示面板显示第一设定画面，并将当前显示模式切换至目标显示模式；
在接收到数据模式切换完成指令时，进入计数状态。
在一些示例中，所述显示装置，还包括：
系统电路，被配置为：
在确定进行不同显示模式切换时，向所述时序控制器发送所述显示模式切换开启指令，并将对应所述当前显示模式的数据发送模式切换至对应所述目标显示模式的数据发送模式；
在将对应所述当前显示模式的数据发送模式切换至对应所述目标显示模式的数据发送模式完成后，向所述时序控制器发送所述数据模式切换完成指 令。
在一些示例中，所述显示装置还包括：计数单元；
所述计数单元被配置为统计所述显示数据中对应的设定目标的第一数目，并在确定所述第一数目与所述目标显示模式对应的设定数目相同时输出计数通过指令；
所述时序控制器进一步被配置为在接收到所述显示模式切换开启指令时，控制所述计数单元进入所述非计数状态；在接收到所述数据模式切换完成指令时，控制所述计数单元进入计数状态。
在一些示例中，所述计数单元集成在所述时序控制器内。
附图说明
图1为本公开实施例提供的显示装置的一些结构示意图；
图2为本公开实施例提供的显示面板的一些结构示意图；
图3为本公开实施例提供的显示面板的另一些结构示意图；
图4为本公开实施例提供的一些信号时序图；
图5为本公开实施例提供的另一些信号时序图；
图6为本公开实施例提供的又一些信号时序图；
图7为本公开实施例提供的驱动方法的一些流程图；
图8为本公开实施例提供的显示装置的另一些结构示意图；
图9为本公开实施例提供的又一些信号时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所 获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
参见图1与图2，显示装置可以包括显示面板100、时序控制器200以及系统电路300。其中，显示面板100可以包括多个阵列排布的像素单元，多条栅线GA(例如，GA1、GA2、GA3、GA4)、多条数据线DA(例如，DA1、DA2、DA3)、栅极驱动电路110以及源极驱动电路120。栅极驱动电路110分别与栅线GA1、GA2、GA3、GA4耦接，源极驱动电路120分别与数据线DA1、DA2、DA3耦接。示例性地，每个像素单元包括多个子像素SPX。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
示例性地，源极驱动电路120可以设置为2个，其中一个源极驱动电路120连接一半数量的数据线，另一个源极驱动电路120连接另一半数量的数据线。当然，源极驱动电路120也可以设置3个、4个、或更多个，其可以根据实际应用的需求进行设计确定，在此不作限定。
参见图2所示，每个子像素SPX中包括晶体管01和像素电极02。其中， 一行子像素SPX对应一条栅线，一列子像素SPX对应一条数据线。晶体管01的栅极与对应的栅线电连接，晶体管01的源极与对应的数据线电连接，晶体管01的漏极与像素电极02电连接，需要说明的是，本公开像素阵列结构还可以是双栅结构，即相邻两行子像素之间设置两条栅线，此排布方式可以减少一半的数据线，即有的相邻两列子像素之间包含数据线，有的相邻两列子像素之间不包括数据线，具体子像素排布结构和数据线，扫描线的排布方式不限定。
需要说明的是，本公开实施例中的显示面板100可以为液晶显示面板100、OLED显示面板100等，在此不作限定。
为了提高画面的显示质量，可以在显示面板100中的非显示区设置虚拟(Dummy)子像素。示例性地，在本公开实施例中，虚拟子像素位于显示子像素的外围区。即显示子像素所在的区为显示区，衬底基板上除显示区之外的区可以为非显示区，栅极驱动电路110和源极驱动电路120可以设置在非显示区中，并且虚拟子像素可以在非显示区的虚拟区。例如，如图3所示，示意出了显示子像素R11～B62，可以在显示子像素R11～B62的外围设置虚拟子像素。例如，可以在显示子像素R11～B12上方设置虚拟子像素。或者，也可以在显示子像素R61～B62下方设置虚拟子像素，在此不作限定。可选的，虚拟子像素中的结构可以与显示子像素中的结构大致相同。或者，也可以仅在虚拟子像素中设置像素电极，而不设置晶体管。当然，在实际应用中，可以根据实际应用的需求设置虚拟子像素的数量，在此不作限定。
不同的显示应用场景所需求的显示效果也不同。例如，静态画面时，需求降低功耗而不追求较高的刷新频率。在游戏模式时为显示更加流畅，追求较高的刷新频率。本公开实施例提供的显示面板100可以应用于多种不同的显示模式下。示例性地，结合图1与图2，系统电路300可以获取待显示画面的原始显示数据(该原始显示数据包括显示面板100中的每一个子像素(包括显示子像素和虚拟子像素)一一对应的携带有相应灰阶值的数据电压的数字信号形式)，将该原始显示数据进行相应处理，得到对应当前显示模式的显 示数据，并将得到的显示数据发送给时序控制器200。时序控制器200根据得到的显示数据和当前显示模式，向显示面板100中的栅极驱动电路110输入对应的控制信号，控制栅极驱动电路110驱动显示面板100中的栅线GA(例如，GA1、GA2、GA3、GA4)，控制子像素中的晶体管打开。并且，时序控制器200将接收到的显示数据发送给源极驱动电路，源极驱动电路根据接收到的显示数据向显示面板100中的数据线DA(例如，DA1、DA2、DA3)加载数据电压，在子像素中的晶体管打开时，对子像素充电，使各子像素充入数据电压，实现画面显示功能。
下面以像素单元包括红色子像素，绿色子像素以及蓝色子像素为例进行说明。如图3所示，红色子像素R11、绿色子像素G11、以蓝色子像素B11为一个像素单元，红色子像素R12、绿色子像素G12、以蓝色子像素B12为一个像素单元。红色子像素R21、绿色子像素G21、以蓝色子像素B21为一个像素单元，红色子像素R22、绿色子像素G22、以蓝色子像素B22为一个像素单元。红色子像素R31、绿色子像素G31、以蓝色子像素B31为一个像素单元，红色子像素R32、绿色子像素G32、以蓝色子像素B32为一个像素单元。红色子像素R41、绿色子像素G41、以蓝色子像素B41为一个像素单元，红色子像素R42、绿色子像素G42、以蓝色子像素B42为一个像素单元。红色子像素R51、绿色子像素G51、以蓝色子像素B51为一个像素单元，红色子像素R52、绿色子像素G52、以蓝色子像素B52为一个像素单元。红色子像素R61、绿色子像素G61、以蓝色子像素B61为一个像素单元，红色子像素R62、绿色子像素G62、以蓝色子像素B62为一个像素单元。
本公开实施例中的显示面板100可以包括多个不同的显示模式。并且可以在任意两个显示模式下进行切换。在一些示例中，该多个显示模式中的一个可以为第二显示模式。其中，第二显示模式可以包括：在各显示帧中，系统电路300执行对应第二显示模式的数据发送模式：将接收到的原始显示数据(包括每一个显示子像素和每一个虚拟子像素一一对应的携带有相应灰阶值的数据电压的数字信号形式)发送给时序控制器200。时序控制器200根据 接收到的显示数据，控制栅极驱动电路逐行驱动栅线，并向源极驱动电路发送该显示数据，源极驱动电路根据接收到的显示数据，在上一行栅线驱动完，且下一行栅线驱动中时，对下一行栅线连接的子像素对应的数据线输入对应显示数据的数据电压。
例如，结合图3与图4所示，ga1代表栅线GA1上加载的信号，ga2代表栅线GA2上加载的信号，ga3代表栅线GA3上加载的信号，ga4代表栅线GA4上加载的信号，ga5代表栅线GA5上加载的信号，ga6代表栅线GA6上加载的信号。Vda1代表数据线DA1上加载的数据电压。并且，信号ga1～ga6中的高电平可以作为栅极开启信号，以控制子像素中的晶体管导通。在控制显示面板100采用第二显示模式驱动时，可以依次对栅线GA1～GA6加载栅极开启信号。以一个显示帧F03、数据线DA1以及数据线DA1连接的红色子像素为例，栅线GA1上的信号ga1输出高电平的栅极开启信号时，红色子像素R11中的晶体管导通。且在信号ga1的高电平对应的T31时间段中，对红色子像素R11连接的数据线DA1加载对应显示数据的数据电压Vr11，以使红色子像素R11输入数据电压Vr11。以及，在T31时间段中，栅线GA2上的信号ga2输出高电平的栅极开启信号，红色子像素R21中的晶体管导通。数据电压Vr11同时输入到红色子像素R21中，以对红色子像素R21进行预充电。
以及，在信号ga2的高电平对应的T32时间段中，对红色子像素R21连接的数据线DA1加载对应显示数据的数据电压Vr21，以使红色子像素R21充入数据电压Vr21。以及，在T32时间段中，栅线GA3上的信号ga3输出高电平的栅极开启信号，红色子像素R31中的晶体管导通。数据电压Vr21同时输入到红色子像素R31中，以对红色子像素R31进行预充电。
以及，在信号ga3的高电平对应的T33时间段中，对红色子像素R31连接的数据线DA1加载对应显示数据的数据电压Vr31，以使红色子像素R31充入数据电压Vr31。以及，在T33时间段中，栅线GA4上的信号ga4输出高电平的栅极开启信号，红色子像素R41中的晶体管导通。数据电压Vr31同时输入到红色子像素R41中，以对红色子像素R41进行预充电。
以及，在信号ga4的高电平对应的T34时间段中，对红色子像素R41连接的数据线DA1加载对应显示数据的数据电压Vr41，以使红色子像素R41充入数据电压Vr41。以及，在T34时间段中，栅线GA5上的信号ga5输出高电平的栅极开启信号，红色子像素R51中的晶体管导通。数据电压Vr41同时输入到红色子像素R51中，以对红色子像素R51进行预充电。
以及，在信号ga5的高电平对应的T35时间段中，对红色子像素R51连接的数据线DA1加载对应显示数据的数据电压Vr51，以使红色子像素R51充入数据电压Vr51。以及，在T35时间段中，栅线GA6上的信号ga6输出高电平的栅极开启信号，红色子像素R61中的晶体管导通。数据电压Vr51同时输入到红色子像素R51中，以对红色子像素R51进行预充电。
以及，在信号ga6的高电平对应的T36时间段中，对红色子像素R61连接的数据线DA1加载对应显示数据的数据电压Vr61，以使红色子像素R61充入数据电压Vr61。并对下一个红色子像素进行预充电。
其余子像素的实施方式依次类推，直至整个显示面板100中的子像素完成充入数据电压，在此不作赘述。
需要说明的是，在显示面板100采用第二显示模式驱动时。每一个显示帧的工作过程可以与上述显示帧F03的工作过程基本相同，在此不作赘述。
在另一些示例中，该多个显示模式中的一个可以为第一显示模式。其中，第一显示模式包括：在相邻的两个显示帧的第一个显示帧中，系统电路300执行对应第一显示模式的数据发送模式：将接收到的原始显示数据中对应显示子像素的原始显示数据进行删减处理后，得到对应奇数行显示子像素的显示数据，将得到的包括对应奇数行显示子像素的显示数据和对应每一个虚拟子像素的显示数据发送给时序控制器200，需要说明的是，在本公开实施例中，可选的，显示面板包括虚拟子像素，且给虚拟子像素发送数据电压。可选的，显示面板也可以仅仅包括显示子像素，在此不做限定。时序控制器200根据接收到的显示数据，向栅极驱动电路发送对应第一显示模式的控制信号，以控制栅极驱动电路逐行驱动显示面板100中的栅线，并向源极驱动电路发送 对应奇数行显示子像素的显示数据和对应每一个虚拟子像素的显示数据，源极驱动电路根据接收到的显示数据(例如奇数行显示子像素的显示数据)，在上一个虚拟子像素行连接的栅线驱动完，且下一个虚拟子像素行连接的栅线驱动中时，对下一个虚拟子像素行连接的栅线连接的子像素对应的数据线输入对应显示数据的数据电压，以及在上一个奇数行显示子像素连接的栅线驱动完，且下一个奇数行显示子像素连接的栅线驱动中时，对下一个奇数行显示子像素对应的数据线输入对应显示数据的数据电压。以及，在相邻的两个显示帧的第二个显示帧中，系统电路300执行对应第一显示模式的数据发送模式：将接收到的原始显示数据中对应显示子像素的原始显示数据进行删减处理后，得到对应偶数行显示子像素的显示数据，将得到的对应包括偶数行显示子像素的显示数据和对应每一个虚拟子像素的显示数据发送给时序控制器200。时序控制器200根据接收到的显示数据，向栅极驱动电路发送对应第一显示模式的控制信号，以控制栅极驱动电路逐行驱动显示面板100中的栅线，并向源极驱动电路发送对应偶数行显示子像素的显示数据和对应每一个虚拟子像素的显示数据，源极驱动电路根据接收到的显示数据(例如，偶数行显示子像素的显示数据)，在上一个虚拟子像素行连接的栅线驱动完，且下一个虚拟子像素行连接的栅线驱动中时，对下一个虚拟子像素行连接的栅线连接的子像素对应的数据线输入对应显示数据的数据电压，以及在上一个偶数行显示子像素连接的栅线驱动完，且下一个偶数行显示子像素连接的栅线驱动中时，对下一个偶数行显示子像素对应的数据线输入对应显示数据的数据电压。
例如，结合图3与图5所示，对显示面板100采用第一显示模式驱动时的工作过程进行说明。其中，ga1代表栅线GA1上加载的信号，ga2代表栅线GA2上加载的信号，ga3代表栅线GA3上加载的信号，ga4代表栅线GA4上加载的信号，ga5代表栅线GA5上加载的信号，ga6代表栅线GA6上加载的信号。Vda1代表数据线DA1上加载的数据电压。并且，信号ga1～ga6中的高电平可以作为栅极开启信号，以控制子像素中的晶体管导通。在控制显示 面板采用第三显示模式驱动时，可以依次对栅线GA1～GA6加载栅极开启信号。以相邻的两个显示帧F01和F02、数据线DA1以及数据线DA1连接的红色子像素为例。
在显示帧F01中，栅线GA1上的信号ga1输出高电平的栅极开启信号时，红色子像素R11中的晶体管导通。且在信号ga1的高电平对应的T11时间段中，对红色子像素R11连接的数据线DA1加载对应红色子像素R11的显示数据的数据电压Vr11，以使红色子像素R11输入数据电压Vr11。以及，在T11时间段中，栅线GA2上的信号ga2输出高电平的栅极开启信号，红色子像素R21中的晶体管导通。数据电压Vr11同时输入到红色子像素R21中，以对红色子像素R21进行预充电。以及，在T11时间段中，栅线GA3上的信号ga3输出高电平的栅极开启信号，红色子像素R31中的晶体管导通。数据电压Vr11同时输入到红色子像素R31中，以对红色子像素R31进行预充电。以及，在T11时间段中，栅线GA4上的信号ga4输出高电平的栅极开启信号，红色子像素R41中的晶体管导通。数据电压Vr11同时输入到红色子像素R41中，以对红色子像素R41进行预充电。以及，在T11时间段中，栅线GA5上的信号ga5输出高电平的栅极开启信号，红色子像素R51中的晶体管导通。数据电压Vr11同时输入到红色子像素R51中，以对红色子像素R51进行预充电。以及，在T11时间段中，栅线GA6上的信号ga6输出高电平的栅极开启信号，红色子像素R61中的晶体管导通。数据电压Vr11同时输入到红色子像素R61中，以对红色子像素R61进行预充电。
以及，在T12时间段中，信号ga1变为低电平，且信号ga3为高电平。对红色子像素R31连接的数据线DA1加载对应红色子像素R31的显示数据的数据电压Vr31，以使红色子像素R31充入数据电压Vr31。以及，信号ga2的高电平，数据电压Vr31同时输入到红色子像素R21中，以对红色子像素R21进行充电。以及，信号ga4的高电平，数据电压Vr31同时输入到红色子像素R41中，以对红色子像素R41进行预充电。以及，信号ga5的高电平，数据电压Vr31同时输入到红色子像素R51中，以对红色子像素R51进行预充电。 以及，信号ga6的高电平，数据电压Vr31同时输入到红色子像素R61中，以对红色子像素R61进行预充电。
以及，在T13时间段中，信号ga3变为低电平，且信号ga5为高电平。对红色子像素R51连接的数据线DA1加载对应红色子像素R51的显示数据的数据电压Vr51，以使红色子像素R51充入数据电压Vr51。以及，信号ga4的高电平，数据电压Vr51同时输入到红色子像素R41中，以对红色子像素R41进行充电。以及，信号ga6的高电平，数据电压Vr51同时输入到红色子像素R61中，以对红色子像素R61进行预充电。
其余子像素的实施方式依次类推，直至整个显示面板中的子像素完成充入数据电压，在此不作赘述。
在显示帧F02中，栅线GA2上的信号ga2输出高电平的栅极开启信号时，红色子像素R21中的晶体管导通。且在信号ga2的高电平对应的T21时间段中，对红色子像素R21连接的数据线DA1加载对应红色子像素R21的显示数据的数据电压Vr21，以使红色子像素R21输入数据电压Vr21。以及，在T21时间段中，栅线GA1上的信号ga1输出高电平的栅极开启信号，红色子像素R11中的晶体管导通。数据电压Vr21同时输入到红色子像素R11中，以对红色子像素R11进行充电。以及，在T21时间段中，栅线GA3上的信号ga3输出高电平的栅极开启信号，红色子像素R31中的晶体管导通。数据电压Vr21同时输入到红色子像素R31中，以对红色子像素R31进行预充电。以及，在T21时间段中，栅线GA4上的信号ga4输出高电平的栅极开启信号，红色子像素R41中的晶体管导通。数据电压Vr21同时输入到红色子像素R41中，以对红色子像素R41进行预充电。以及，在T21时间段中，栅线GA5上的信号ga5输出高电平的栅极开启信号，红色子像素R51中的晶体管导通。数据电压Vr21同时输入到红色子像素R51中，以对红色子像素R51进行预充电。以及，在T21时间段中，栅线GA6上的信号ga6输出高电平的栅极开启信号，红色子像素R61中的晶体管导通。数据电压Vr21同时输入到红色子像素R61中，以对红色子像素R61进行预充电。
以及，在T22时间段中，信号ga2变为低电平，且信号ga4为高电平。对红色子像素R41连接的数据线DA1加载对应红色子像素R41的显示数据的数据电压Vr41，以使红色子像素R41充入数据电压Vr41。以及，信号ga3的高电平，数据电压Vr41同时输入到红色子像素R31中，以对红色子像素R31进行充电。以及，信号ga5的高电平，数据电压Vr41同时输入到红色子像素R51中，以对红色子像素R51进行预充电。以及，信号ga6的高电平，数据电压Vr41同时输入到红色子像素R61中，以对红色子像素R61进行预充电。
以及，在T23时间段中，信号ga4变为低电平，且信号ga6为高电平。对红色子像素R61连接的数据线DA1加载对应红色子像素R61的显示数据的数据电压Vr61，以使红色子像素R61充入数据电压Vr61。以及，信号ga5的高电平，数据电压Vr61同时输入到红色子像素R51中，以对红色子像素R51进行充电。以及，对其他红色子像素进行预充电。
其余子像素的实施方式依次类推，直至整个显示面板中的子像素完成充入数据电压，在此不作赘述。
需要说明的是，在显示面板100采用第一显示模式驱动时，其余显示帧的工作过程可以与上述显示帧F01和显示帧F02的工作过程基本相同，即显示面板100可以采用HSR显示模式进行工作，可以实现高刷新频率的同时，提高子像素的充电率。
并且，需要说明的是，在显示面板100采用第一显示模式驱动时，在显示帧F01中，偶数行子像素中可以通过相邻的奇数行子像素的数据电压进行充电，从而实现偶数行子像素的显示功能。例如，红色子像素R21充入的电压可以与红色子像素R11对应的数据电压和红色子像素R31对应的数据电压相关(可以大致为红色子像素R11对应的数据电压和红色子像素R31对应的数据电压的平均值)，红色子像素R41充入的电压可以与红色子像素R31对应的数据电压和红色子像素R51对应的数据电压相关(可以大致为红色子像素R31对应的数据电压和红色子像素R51对应的数据电压的平均值)。
以及，在显示帧F02中，奇数行子像素中可以通过相邻的偶数行子像素 的数据电压进行充电，从而实现奇数行子像素的显示功能。例如，红色子像素R11充入的电压可以与红色子像素R21对应的数据电压相关(可以大致为红色子像素R21对应的数据电压)，红色子像素R31充入的电压可以与红色子像素R21对应的数据电压和红色子像素R41对应的数据电压相关(可以大致为红色子像素R21对应的数据电压和红色子像素R41对应的数据电压的平均值)。红色子像素R51充入的电压可以与红色子像素R41对应的数据电压和红色子像素R61对应的数据电压相关(可以大致为红色子像素R41对应的数据电压和红色子像素R61对应的数据电压的平均值)。
在另一些示例中，该多个显示模式中的一个可以为第三显示模式。其中，第三显示模式包括：在各显示帧中，以至少相邻两行栅线为一个栅线组，系统电路300执行对应第三显示模式的数据发送模式：将接收到的原始显示数据进行删减处理后，得到对应每一个栅线组中一条栅线电连接的子像素对应的显示数据，将得到的显示数据发送给时序控制器200。时序控制器200根据接收到的显示数据，向栅极驱动电路发送对应第三显示模式的控制信号，以控制栅极驱动电路同时驱动同一栅线组中的栅线，并逐个驱动栅线组。并向源极驱动电路发送该显示数据，以使源极驱动电路根据接收到的显示数据，源极驱动电路根据接收到的显示数据，在上一个栅线组中的栅线驱动完，且下一个栅线组中的栅线驱动中时，对下一个栅线组的栅线连接的子像素对应的数据线输入对应显示数据的数据电压。示例性地，可以将相邻两行栅线作为一个栅线组；或者，也可以将相邻三行栅线为一个栅线组；或者，也可以将相邻行栅线为一个栅线组；或者，也可以将相邻更多行栅线为一个栅线组，在此不作限定。
例如，结合图3与图6所示，对显示面板100采用第三显示模式驱动时的工作过程进行说明。其中，以相邻两行栅线为一个栅线组。例如，栅线GA1和GA2为一个栅线组，栅线GA3和GA4为一个栅线组，栅线GA5和GA6为一个栅线组。系统电路300进行删减处理后，得到栅线GA1连接的各子像素对应的显示数据，栅线GA3连接的各子像素对应的显示数据，栅线GA5 连接的各子像素对应的显示数据，并将这些显示数据发送给时序控制器200。当然，系统电路300进行删减处理后，也可以得到栅线GA2连接的各子像素对应的显示数据，栅线GA4连接的各子像素对应的显示数据，栅线GA4连接的各子像素对应的显示数据，并将这些显示数据发送给时序控制器200，在此不作限定。
其中，ga1代表栅线GA1上加载的信号，ga2代表栅线GA2上加载的信号，ga3代表栅线GA3上加载的信号，ga4代表栅线GA4上加载的信号，ga5代表栅线GA5上加载的信号，ga6代表栅线GA6上加载的信号。Vda1代表数据线DA1上加载的数据电压。并且，信号ga1～ga6中的高电平可以作为栅极开启信号，以控制子像素中的晶体管导通。在控制显示面板100采用第一显示模式驱动时，以一个显示帧F04、数据线DA1以及数据线DA1连接的红色子像素为例，栅线GA1上的信号ga1和栅线GA2上的信号ga2同时输出高电平的栅极开启信号，红色子像素R11和R21中的晶体管同时导通。且在信号ga1和ga2的高电平对应的T41时间段中，对红色子像素R11和R21连接的数据线DA1输入对应显示数据的数据电压Vr11，以使红色子像素R11和R21充入数据电压Vr11。以及，在T41时间段中，栅线GA3上的信号ga3和栅线GA4上的信号ga4同时输出高电平的栅极开启信号，红色子像素R31和R41中的晶体管同时导通。数据电压Vr11同时输入到红色子像素R31和R41中，以对红色子像素R31和R41进行预充电。
以及，在信号ga3和ga4的高电平对应的T42时间段中，对红色子像素R31和R41连接的数据线DA1加载对应显示数据的数据电压Vr31，以使红色子像素R31和R41充入数据电压Vr31。以及，在T42时间段中，栅线GA5上的信号ga5和栅线GA6上的信号ga6同时输出高电平的栅极开启信号，红色子像素R51和R61中的晶体管导通。数据电压Vr31同时输入到红色子像素R51和R61中，以对红色子像素R51和R61进行预充电。
以及，在信号ga5和ga6的高电平对应的T43时间段中，对红色子像素R51和R61连接的数据线DA1加载对应显示数据的数据电压Vr51，以使红色 子像素R51和R61充入数据电压Vr51。并对下一个红色子像素进行预充电。
其余子像素的实施方式依次类推，直至整个显示面板100中的子像素完成充入数据电压，在此不作赘述。
需要说明的是，在显示面板100采用第三显示模式驱动时。每一个显示帧的工作过程可以与上述显示帧F04的工作过程基本相同，即显示面板100可以采用DLG显示模式进行工作，在此不作赘述。
在本公开实施例中，可以使第二显示模式的刷新频率小于第一显示模式的刷新频率和第三显示模式的刷新频率。示例性地，显示面板100的刷新频率可以包括30Hz，48Hz，60Hz，90Hz，96Hz，120Hz，144Hz，240Hz等。第一显示模式的刷新频率，第二显示模式的刷新频率以及第三显示模式的刷新频率可以从上述显示面板100支持的刷新频率中进行选取。例如，第二显示模式的刷新频率包括60Hz，第一显示模式的刷新频率包括120Hz，第三显示模式的刷新频率包括120Hz。当然，在实际应用，第一显示模式的刷新频率，第二显示模式的刷新频率以及第三显示模式的刷新频率可以根据实际应用的需求进行确定，在此不作限定。
在本公开实施例中，由于显示面板包括多个显示模式，因此可以在不同的应用场景下进行显示模式的切换。然而，公开人发现：系统电路在确定进行不同显示模式切换时，自身也开始进行数据发送模式的切换过程，例如，系统电路在确定由第二显示模式切换为第一显示模式时，自身也开始进行由对应第二显示模式的数据发送模式切换为对应第一显示模式的数据发送模式的过程。并同时给时序控制器发送模式切换信号，时序控制器接收到模式切换信号后，将第二显示模式切换为第一显示模式。然而，由于系统电路在数据发送模式切换的过程中，可以边切换，边向时序控制器发显示数据。然而，由于系统电路的数据发送模式切换速度小于时序控制器的显示模式切换速度，在时序控制器由第二显示模式切换为第一显示模式完成后，系统电路通常还没切换完成，这时系统电路还是采用对应第二显示模式的数据发送模式向时序控制器发送对应全部子像素的原始显示数据Vdata1。时序控制器在接收原 始显示数据Vdata1后，计数单元会对原始显示数据Vdata1中对应的子像素行的总数进行统计，得到对应子像素行的统计数目。然而，由于时序控制器已经切换为第一显示模式，计数单元在第一显示模式对应的设定数目与对原始显示数据Vdata1统计得到的统计数目不同，导致计数单元无法自动清零，造成计数单元卡死，计数单元向时序控制器返回异常指令，时序控制器则会进入控制显示面板显示预警画面的预警模式，导致显示异常。
为了解决上述问题，本公开实施例提供了显示面板的驱动方法，在接收到显示模式切换开启指令时，驱动显示面板显示第一设定画面，并将当前显示模式切换至目标显示模式，以实现模式切换的过程。并且，在接收到显示模式切换开启指令时，进入非计数状态，使计数单元处于非计数工作状态中，这样即使时序控制器接收到系统电路发送的显示数据后，也不会对接收到的任何显示数据进行统计。在接收到数据模式切换完成指令时，非计数状态解除，进入计数状态，使计数单元处于计数工作状态中，从而可以对接收到的任何显示数据进行统计。这样在系统电路完成模式切换后，再开启计数工作，可以避免由于计数单元无法自动清零而造成的计数单元卡死的问题。
结合图7所示，本公开实施例提供的显示面板的驱动方法，可以包括如下步骤：
S10、在接收到显示模式切换开启指令时，进入非计数状态，以及驱动显示面板显示第一设定画面，并将当前显示模式切换至目标显示模式。
本公开实施例提供的驱动方法，可以根据显示面板的实际应用场景，实现不同显示模式之间的切换。例如对于游戏类显示画面需要高刷新频率，然而，高刷新频率会压缩显示面板子像素的充电时间，导致子像素的充电不足。本公开实施例中，在由低刷新频率的显示模式切换到高刷新频率的显示模式时，可以实现高刷新频率的同时，提高子像素的充电率。
示例性地，系统电路300根据应用场景，确定进行不同显示模式的切换。例如，显示面板100当前的应用场景可以为普通的视频播放界面，并采用第二显示模式驱动显示面板100显示画面。在用户要打开游戏时，系统电路300 识别到下一个应用场景为游戏界面，游戏界面需要较高的刷新频率，系统电路300可以确定需要进行不同显示模式切换，则向时序控制器200发送显示模式切换开启指令，时序控制器200在接收到显示模式切换开启指令时，执行步骤S10的过程。系统电路300在发送显示模式切换开启指令时，还将自身对应当前显示模式的数据发送模式切换至对应目标显示模式的数据发送模式。
示例性地，如图8所示，显示装置还可以包括连接器400。其中，连接器400的第一端410与系统电路300连接，连接器400的第二端420与时序控制器200连接。连接器400的第一端410可以包括第一IIC pin角411以及第一切换指令传输pin角412，连接器400的第二端420可以包括第二IIC pin角421以及第二切换指令传输pin角422。示例性地，系统电路300通过第一IIC pin角410输出握手信号，时序控制器200通过第二IIC pin角421接收握手信号，并在接收到握手信号后与系统电路300进行握手，在握手完成后，说明系统电路300和时序控制器200连接上了，可以进行信号传输了。示例性地，系统电路300可以通过第一切换指令传输pin角412输出显示模式切换开启指令(例如将第一切换指令传输pin角412的电平拉高)，时序控制器200可以通过第二切换指令传输pin角422接收系统电路300输出的显示模式切换开启指令(例如，由于第一切换指令传输pin角412的电平拉高，则第二切换指令传输pin角422也被拉高)。在不需要进行显示模式切换时，以及，系统电路300确定不需要进行显示模式切换时，将第一切换指令传输pin角412的电平拉低，以输出显示模式切换停止指令，则第二切换指令传输pin角422也被拉低，以接收显示模式切换停止指令，时序控制器200不进行显示模式切换。或者，系统电路300可以通过第一IIC pin角411输出采用数字信号形式的显示模式切换开启指令(例如，显示模式切换开启指令具有Byte0～Byte1。示例性地，Byte0为0xC2，Byte1为0xF26F，Byte2为0x01，Byte3为0xAA)，时序控制器200通过第二IIC pin角421接收显示模式切换开启指令，并根据显示模式切换开启指令进行显示模式切换的过程。以及，系统电路300确定不 需要进行显示模式切换时，系统电路300可以通过第一IIC pin角411输出采用数字信号形式的显示模式切换停止指令(例如，显示模式切换停止指令具有Byte0～Byte1。示例性地，Byte0为0xC2，Byte1为0xF26F，Byte2为0x01，Byte3为0x55)，时序控制器200通过第二IIC pin角421接收显示模式切换停止指令，时序控制器200不进行显示模式切换。
在本公开实施例中，如图8所示，连接器400的第一端410还可以包括第一数据传输pin角413；连接器400的第二端420还可以包括第二数据传输pin角423。其中，系统电路300可以通过第一数据传输pin角413输出显示数据。以及，时序控制器200通过第二数据传输pin角423接收显示数据。
在本公开实施例中，如图8所示，显示装置还包括：计数单元500。计数单元500被配置为统计显示数据中对应的设定目标的第一数目，并在确定第一数目与目标显示模式对应的设定数目相同时输出计数通过指令。以及，时序控制器200被配置为在接收到显示模式切换开启指令时，控制计数单元500进入非计数状态；在接收到数据模式切换完成指令时，控制计数单元500进入计数状态。示例性地，计数单元500可以集成在时序控制器200中，以提高集成度，以及缩短时序控制器200和计数单元500之间数据传输线的长度。在一些示例中，计数单元500可以包括但不限于计数器电路。
示例性地，如图8所示，时序控制器200在接收到显示模式切换开启指令时，控制计数单元500处于清零状态，使计数单元500不执行计数操作，保持清零操作，以进入非计数状态。或者，时序控制器200在接收到显示模式切换开启指令时，控制计数单元500处于未使能状态，即未使能计数单元500，则计数单元500不执行计数操作，以进入非计数状态。或者，时序控制器200在接收到显示模式切换开启指令时，不对计数单元500供电，控制计数单元500处于断电状态，则计数单元500不执行计数操作，以进入非计数状态。这由于计数单元500不执行计数操作，即使系统电路300发送来显示数据，也不会对显示数据中的设定目标进行计数统计，从而可以避免卡死的问题出现。
示例性地，时序控制器200所在的电路板上会设置有闪存(Flash)，在闪存中存储有第一设定画面对应的显示数据(该显示数据包括每一个子像素一一对应的数据电压的数字电压形式)。示例性地，在时序控制器200由第二显示模式切换为第一显示模式时，由于时序控制器200在接收到显示模式切换开启指令时，开始进入不同显示模式的切换过程，在显示模式切换完成之前，时序控制器200还是以第二显示模式驱动显示面板100显示画面。具体地，时序控制器200在接收到显示模式切换开启指令时，从闪存中获取预先存储的第一设定画面对应的显示数据，并将获取到的第一设定画面对应的显示数据输出给源极驱动电路120。源极驱动电路120可以接收第一设定画面对应的显示数据，以及根据第一设定画面对应的显示数据，向数据线加载对应的数据电压。并且，时序控制器200向栅极驱动电路输入控制信号，栅极驱动电路逐行驱动栅线，具体过程参照上述显示面板100采用第二显示模式时的驱动过程，从而驱动显示面板100显示第一设定画面。在显示模式切换完成之后，时序控制器200可以根据第一显示模式驱动显示面板100显示画面。具体地，时序控制器200从闪存中获取预先存储的第一设定画面对应的显示数据，并将获取到的第一设定画面对应的显示数据中对应显示子像素的显示数据进行删减处理后，将对应虚拟子像素的显示数据以及剩余的对应显示子像素的显示数据输出给源极驱动电路120。源极驱动电路120可以接收这些显示数据，以及根据这些显示数据，向数据线加载对应的数据电压。并且，时序控制器200向栅极驱动电路输入控制信号，栅极驱动电路逐行驱动栅线，具体过程参照上述显示面板100采用第二显示模式时的驱动过程，从而驱动显示面板100显示第一设定画面。
在一些示例中，当前显示模式可以为第二显示模式，目标显示模式可以为第一显示模式。这样可以使显示面板100由第二显示模式切换为作为HSR显示模式的第一显示模式。例如对于游戏类显示画面需要高刷新频率，因此，可以在显示面板100要显示游戏类显示画面时，采用作为HSR显示模式的第一显示模式，这样可以实现高刷新频率的同时，提高子像素的充电率。例如， 可以将对应120Hz 4K 2K的第二显示模式切换为对应240Hz 4K 1K的第一显示模式。
在又一些示例中，当前显示模式可以为第二显示模式，目标显示模式可以为第三显示模式。这样可以使显示面板100由第二显示模式切换为作为DLG显示模式的第三显示模式。例如对于游戏类显示画面需要高刷新频率，因此，可以在显示面板100要显示游戏类显示画面时，采用作为DLG显示模式的第三显示模式，这样可以实现高刷新频率的同时，提高子像素的充电率。
在又一些示例中，当前显示模式可以为第三显示模式，目标显示模式可以为第一显示模式。这样可以使显示面板100由作为DLG显示模式的第三显示模式切换为作为HSR显示模式的第一显示模式。由于显示面板100在作为DLG显示模式的第三显示模式下显示的画面分辨率会降低，虽然显示面板100在作为HSR显示模式的第一显示模式下显示的画面分辨率也会降低，但是，显示面板100在作为HSR显示模式的第一显示模式下时，同一列中相邻两行子像素输入的电压并不会完全相同，因此，显示面板100在作为HSR显示模式的第一显示模式下显示的画面会更加细致，因此，可以在显示面板100要显示游戏类显示画面时，采用作为HSR显示模式的第一显示模式，进一步提高画面的显示质量。
在又一些示例中，当前显示模式可以为第一显示模式，目标显示模式可以为第三显示模式。这样可以使显示面板100由作为HSR显示模式的第一显示模式切换为作为DLG显示模式的第三显示模式。这样可以在显示面板100要显示游戏类显示画面时，采用作为DLG显示模式的第三显示模式，进一步提高子像素的充电率。
在又一些示例中，当前显示模式可以为第三显示模式，目标显示模式可以为第二显示模式。这样可以使显示面板100由作为DLG显示模式的第三显示模式切换为第二显示模式。例如对于静态类显示画面不需要高刷新频率，而是需要较低功耗，因此，可以在显示面板100要显示静态类显示画面时，采用作为普通显示模式的第二显示模式，这样可以降低功耗。
在又一些示例中，当前显示模式可以为第一显示模式，目标显示模式可以为第二显示模式。这样可以使显示面板100由作为HSR显示模式的第一显示模式切换为第二显示模式。例如对于静态类显示画面不需要高刷新频率，而是需要较低功耗，因此，可以在显示面板100要显示静态类显示画面时，采用作为普通显示模式的第二显示模式，这样可以降低功耗。例如，可以将对应240Hz 4K 1K的第一显示模式切换为对应120Hz 4K 2K的第二显示模式。
灰阶，一般是将最暗与最亮之间的亮度变化区分为若干份，以便于进行屏幕亮度管控。例如，以显示的图像由红、绿、蓝三种颜色组成，其中每一个颜色都可以显现出不同的亮度级别，并且不同亮度层次的红、绿、蓝组合起来，可以形成不同的色彩。例如，液晶显示面板100的灰阶位数为6bit，则红、绿、蓝这三种颜色分别具有64(即2 6)个灰阶，这64个灰阶值分别为0～63。液晶显示面板100的灰阶位数为8bit，则红、绿、蓝这三种颜色分别具有256(即2 8)个灰阶，这256个灰阶值分别为0～255。液晶显示面板100的灰阶位数为10bit，则红、绿、蓝这三种颜色分别具有1024(即2 10)个灰阶，这1024个灰阶值分别为0～1023。液晶显示面板100的灰阶位数为12bit，则红、绿、蓝这三种颜色分别具有4096(即2 12)个灰阶，这4096个灰阶值分别为0～4093。
在本公开实施例中，第一设定画面可以包括纯色画面。例如，第一设定画面可以包括红色纯色画面、绿色纯色画面、蓝色纯色画面。例如，以显示面板100具有0～255灰阶值为例，在显示面板100显示红色纯色画面时，显示面板100中的红色子像素输入对应同一灰阶值(例如127灰阶值、255灰阶值等)的显示数据的数据电压，绿色子像素和蓝色子像素输入对应0灰阶值的显示数据的数据电压。在显示面板100显示绿色纯色画面时，显示面板100中的绿色子像素输入对应同一灰阶值(例如127灰阶值、255灰阶值等)的显示数据的数据电压，红色子像素和蓝色子像素输入对应0灰阶值的显示数据的数据电压。在显示面板100显示蓝色纯色画面时，显示面板100中的蓝色子像素输入对应同一灰阶值(例如127灰阶值、255灰阶值等)的显示数据的 数据电压，绿色子像素和红色子像素输入对应0灰阶值的显示数据的数据电压。
在本公开实施例中，第一设定画面也可以包括灰阶画面。该灰阶画面可以为各种颜色的子像素均为同一灰阶值的画面。例如，以显示面板100具有0～255灰阶值为例，各种颜色的子像素均为0灰阶值的画面(即黑画面)。各种颜色的子像素均为127灰阶值的画面。或者，各种颜色的子像素均为100灰阶值的画面。或者，各种颜色的子像素均为200灰阶值的画面。或者，各种颜色的子像素均为255灰阶值的画面。
S20、在接收到数据模式切换完成指令时，进入计数状态。
在本公开实施例中，系统电路300可以在将对应当前显示模式的数据发送模式切换至对应目标显示模式的数据发送模式完成后，向时序控制器200发送数据模式切换完成指令。由于系统电路300的切换速度小于时序控制器200的切换速度，在系统电路300切换完成后，时序控制器200已经切换完成，因此系统电路300向时序控制器200发送数据模式切换完成指令时，时序控制器200可以确定系统电路300已经切换完成，并在接收到数据模式切换完成指令时，控制计数单元500进入计数状态。示例性地，时序控制器200可以使能计数单元500中的计数器电路，使计数器电路可以执行计数操作。示例性地，系统电路300也可以通过第一IIC pin角411输出采用数字信号形式的数据模式切换完成指令(例如，显示模式切换开启指令具有Byte0～Byte1。示例性地，Byte0为0xC2，Byte1为0xF26F，Byte2为0x01，Byte3为0x66)，时序控制器200通过第二IIC pin角421接收数据模式切换完成指令，并根据数据模式切换完成指令控制计数器电路开启执行计数操作的功能。
在本公开实施例中，在进入计数状态之后，还可以包括：接收显示数据；统计显示数据中对应的设定目标的第一数目；在确定第一数目与目标显示模式对应的设定数目相同后，基于目标显示模式，根据接收到的显示数据，驱动显示面板100显示对应的画面。示例性地，系统电路300可以采用对应目标显示模式的数据发送模式，将接收到的原始显示数据进行处理，以处理成 对应目标显示模式的显示数据。并将处理后的显示数据输出给时序控制器200。时序控制器200接收到该显示数据后，控制计数单元500对显示数据中对应的设定目标进行计数，以统计得到第一数目。计数单元500在确定统计的第一数目和目标显示模式对应的设定数目相同时，可以自动清零，并向时序控制器200反馈通过(Pass)指令，时序控制器200在接收到该通过指令时，可以确定出系统电路300输出的显示数据与目标显示模式所需要的显示数据是相对应的，因此，时序控制器200可以基于目标显示模式，根据接收到的显示数据，驱动显示面板100显示对应的画面。
在本公开实施例中，显示面板100包括多个子像素行，其中这些子像素行可以具有显示子像素行(如图3所示的第一行子像素至第六行子像素)和虚拟子像素行。设定目标可以包括显示面板100的子像素行。在目标显示模式为第一显示模式时，设定数目可以包括所有的虚拟子像素行的总数和显示子像素行的总数的一半。示例性地，计数单元500可以对时序控制器200接收到的显示数据中对应的子像素行的数量进行统计，以统计出这些子像素行的总数，作为第一数目。在时序控制器200切换为第一显示模式后，设定数目可以为所有的虚拟子像素行的总数和显示子像素行的总数的一半。
在本公开实施例中，显示面板100包括多个子像素行，其中这些子像素行可以具有显示子像素行(如图3所示的第一行子像素至第六行子像素)和虚拟子像素行。设定目标可以包括显示面板100的子像素行。在目标显示模式为第二显示模式时，设定数目可以包括所有的虚拟子像素行的总数和所有显示子像素行的总数。示例性地，计数单元500可以对时序控制器200接收到的显示数据中对应的子像素行的数量进行统计，以统计出这些子像素行的总数，作为第一数目。在时序控制器200切换为第二显示模式后，设定数目可以为所有的虚拟子像素行的总数和所有显示子像素行的总数。例如，由第二显示模式切换为第一显示模式时，若第二显示模式的显示数据为4K2K的显示数据，则第二显示模式对应的设定数目可以为2177(包括2160个显示子像素行和17个虚拟子像素行)，第一显示模式对应的设定数目可以为1097(包 括1080个显示子像素行(即显示子像素行总数的一半)和17个虚拟子像素行)。
在本公开实施例中，显示面板100包括多个子像素行，其中这些子像素行可以具有显示子像素行(如图3所示的第一行子像素至第六行子像素)和虚拟子像素行。在第三显示模式时，该多个子像素行分为了多个栅线组，则设定目标可以包括显示面板100的栅线组。并且，在目标显示模式为第三显示模式时，设定数目包括栅线组的总数。示例性地，计数单元500可以对时序控制器200接收到的显示数据中对应的栅线组的数量进行统计，以统计出这些栅线组的总数，作为第一数目。在时序控制器200切换为第三显示模式后，设定数目可以为所有栅线组的总数。
在具体实施时，时序控制器200可以在接收到该通过指令时，可以直接基于目标显示模式，根据接收到的显示数据，驱动显示面板100显示对应的画面。当然，由于系统电路300在切换后，可能会出现功能不稳定的情况，为了进一步提高显示的稳定性，在统计显示数据中对应的设定目标的第一数目之后，在确定第一数目与设定数目相同时，基于目标显示模式，驱动显示面板100在至少一个显示帧中显示第二设定画面，之后，再基于目标显示模式，根据接收到的显示数据，驱动显示面板100显示对应的画面。例如，系统电路300可以采用对应目标显示模式的数据发送模式，将接收到的原始显示数据进行处理，以处理成对应目标显示模式的显示数据。并将处理后的显示数据输出给时序控制器200。时序控制器200接收到该显示数据后，控制计数单元500对显示数据中对应的设定目标进行计数，以统计得到第一数目。计数单元500在确定统计的第一数目和目标显示模式对应的设定数目相同时，可以向时序控制器200反馈通过(Pass)指令。时序控制器200可以在接收到该通过指令时，基于目标显示模式，驱动显示面板100在一个或多个显示帧中显示第二设定画面。之后，再基于目标显示模式，根据接收到的显示数据，驱动显示面板100显示对应的画面。
在本公开实施例中，采用公式SM＝TM/AM，确定显示第二设定画面的显 示帧的数量；其中，SM代表显示第二设定画面的显示帧的数量，TM代表设定时间，AM代表目标显示模式对应的刷新频率的倒数。示例性地，可以根据系统电路300切换所耗费的时间来确定设定时间，以提高稳定性。或者，也可以根据时序控制器200接收显示模式切换开启指令和数据模式切换完成指令之间的间隔时间来确定设定时间，以进一步提高稳定性。
示例性地，在根据系统电路300切换所耗费的时间来确定设定时间时，若系统电路300切换所耗费的时间大致为83ms，目标显示模式对应的刷新频率为240Hz，240Hz时一个显示帧的时间大致为4.16ms，则显示第二设定画面的显示帧的数量SM可以为20。若系统电路300切换所耗费的时间为83ms，目标显示模式对应的刷新频率为120Hz，120Hz时一个显示帧的时间大致为8.33ms，则显示第二设定画面的显示帧的数量SM可以为10。
在本公开实施例中，第二设定画面可以包括纯色画面。例如，第二设定画面可以包括红色纯色画面、绿色纯色画面、蓝色纯色画面。例如，以显示面板100具有0～255灰阶值为例，在显示面板100显示红色纯色画面时，显示面板100中的红色子像素输入对应同一灰阶值(例如127灰阶值、255灰阶值等)的显示数据的数据电压，绿色子像素和蓝色子像素输入对应0灰阶值的显示数据的数据电压。在显示面板100显示绿色纯色画面时，显示面板100中的绿色子像素输入对应同一灰阶值(例如127灰阶值、255灰阶值等)的显示数据的数据电压，红色子像素和蓝色子像素输入对应0灰阶值的显示数据的数据电压。在显示面板100显示蓝色纯色画面时，显示面板100中的蓝色子像素输入对应同一灰阶值(例如127灰阶值、255灰阶值等)的显示数据的数据电压，绿色子像素和红色子像素输入对应0灰阶值的显示数据的数据电压。
在本公开实施例中，第二设定画面也可以包括灰阶画面。该灰阶画面可以为各种颜色的子像素均为同一灰阶值的画面。例如，以显示面板100具有0～255灰阶值为例，各种颜色的子像素均为0灰阶值的画面(即黑画面)。各种颜色的子像素均为127灰阶值的画面。或者，各种颜色的子像素均为100 灰阶值的画面。或者，各种颜色的子像素均为200灰阶值的画面。或者，各种颜色的子像素均为255灰阶值的画面。
在本公开实施例中，闪存中也可以存储第二设定画面的显示数据。示例性地，可以使第一设定画面和第二设定画面相同，这样可以仅需在闪存中存储第一设定画面或第二设定画面的显示数据，降低存储所需的存储空间。当然，在实际应用中，第一设定画面和第二设定画面也可以不相同，在此不作限定。
在本公开实施例中，系统电路300可以包括系统级芯片(System on a Chip，SOC)。当然，系统电路300可以采用其他可以实现的方式，在此不作限定。
下面结合图8与图9对本公开实施例提供的上述驱动方法进行说明书。
在显示装置开机时，系统电路300上电，系统电路300通过连接器400的第一供电pin角给时序控制器200提供供电电压VIN1，如3.3V，则将第一供电pin角由0V拉高为3.3V。系统电路300通过连接器400的第二供电pin角给时序控制器200提供供电电压VIN2，如1.1V，则将第二供电pin角由0V拉高为1.1V。系统电路300通过连接器400的第三供电pin角给时序控制器200提供供电电压VIN3，如1.8V，则将第三供电pin角由0V拉高为1.8V。以及系统电路300通过连接器400的初始化pin角给时序控制器200提供初始化电压RES，如1.15V，则将初始化pin角由0V拉高为1.15V。其中，t1代表第一供电pin角由0V拉高为2.8V时至第二供电pin角由0V拉高为0.8V时的延迟时间，t2代表第二供电pin角由0V拉高为0.8V时至第三供电pin角由0V拉高为1.5V时的延迟时间，t2代表第三供电pin角由0V拉高为1.5V时至初始化pin角由0V拉高为0.8V的延迟时间。时序控制器200在供电电压VIN1～VIN3稳定后可以开启所要执行的功能。在初始化电压拉高为1.15V后，进入t4阶段，时序控制器200会执行初始化操作，以将当前显示模式确定为第二显示模式。也就是说，时序控制器200在重新上电时，会默认执行第二显示模式的操作。之后进入t5阶段，系统电路并未确定需要进行显示模式切换，因此继续采用第二显示模式驱动显示面板100显示4K2K数据的画 面。之后进入t6阶段，系统电路确定需要进行将第二显示模式(例如4K2K的显示数据)切换为第一显示模式(例如4K1K的显示数据)的切换过程。系统电路300将第一切换指令传输pin角412的电平拉高，以通过第一切换指令传输pin角412输出显示模式切换开启指令。并开启自身对应第二显示模式的数据发送模式切换至对应第一显示模式的数据发送模式的切换过程。
由于第一切换指令传输pin角412的电平拉高，则第二切换指令传输pin角422也被拉高，时序控制器200通过第二切换指令传输pin角422接收到系统电路300输出的显示模式切换开启指令，控制计数单元500中的计数器电路处于清零状态，使计数单元500中的计数器电路不执行计数操作，保持清零操作，以进入非计数状态。并且，时序控制器200从闪存中获取预先存储的黑画面对应的显示数据。由于时序控制器200将自身的第二显示模式切换为第一显示模式也是需要时间的，因此在显示模式切换完成之前，时序控制器200还是以第二显示模式向栅极驱动电路输入控制信号，控制栅极驱动电路逐行驱动栅线。以及时序控制器200以第二显示模式将获取到的黑画面对应的显示数据(例如4K2K数据)输出给源极驱动电路120。源极驱动电路120可以接收黑画面对应的显示数据，以及根据黑画面对应的显示数据，向数据线加载对应的数据电压，驱动显示面板100显示黑画面。由于系统电路300在数据发送模式切换的过程中，可以边切换，边向时序控制器200发显示数据。在时序控制器200进行显示模式切换的过程中，可以接收系统电路300发送的显示数据，可以将接收的显示数据进行缓存或不存储。并且，由于控制计数单元500中的计数器电路处于清零状态，因此，计数单元500中的计数器电路不会对接收到的任何显示数据进行统计。
由于系统电路300的数据发送模式切换速度小于时序控制器200的显示模式切换速度，在时序控制器200由第二显示模式切换为第一显示模式完成后，系统电路300通常还没切换完成。时序控制器200则以第一显示模式向栅极驱动电路输入控制信号，控制栅极驱动电路逐行驱动栅线。以及时序控制器200以第一显示模式将获取到的黑画面对应的显示数据(例如4K1K的 显示数据)输出给源极驱动电路120。源极驱动电路120可以接收黑画面对应的显示数据，以及根据黑画面对应的显示数据，向数据线加载对应的数据电压，驱动显示面板100显示黑画面。由于系统电路300在数据发送模式切换的过程中，可以边切换，边向时序控制器200发显示数据。在时序控制器200切换完成后，可以接收系统电路300发送的显示数据，可以将接收的显示数据进行缓存或不存储。并且，由于控制计数单元500处于清零状态，因此，计数单元500不会对接收到的任何显示数据进行统计。
系统电路300在将对应第二显示模式的数据发送模式切换至对应第一显示模式的数据发送模式完成后，通过第一IIC pin角411输出采用数字信号形式的数据模式切换完成指令。时序控制器200通过第二IIC pin角421接收数据模式切换完成指令，并根据数据模式切换完成指令控制计数单元500中的计数器电路解除非计数状态，开启执行计数操作的功能。系统电路300采用对应第二显示模式的数据发送模式发送显示数据，时序控制器200接收该显示数据，控制计数单元500中的计数器电路对显示数据中对应的子像素行进行计数，以统计得到第一数目。计数单元500中的计数器电路在确定统计的第一数目和第一显示模式对应的设定数目(如1097)相同时，可以自动清零，并向时序控制器200反馈通过(Pass)指令，时序控制器200在接收到该通过指令时，可以确定出系统电路300输出的显示数据与第一显示模式所需要的显示数据是相对应的，因此，时序控制器200可以基于第一显示模式，根据接收到的显示数据(例如4K1K的显示数据)，驱动显示面板100显示对应的画面。
计数单元500中的计数器电路在确定统计的第一数目和第一显示模式对应的设定数目(如1097)不相同时，无法自动清零，向时序控制器200反馈异常回读指令(例如32448)，时序控制器200在接收到该异常回读指令时，可以确定出系统电路300输出的显示数据与第一显示模式所需要的显示数据是不对应的，因此，时序控制器200从闪存中获取预警画面的显示数据，并基于第一显示模式，驱动显示面板100显示预警画面(例如循环播放红色村 色画面、绿色纯色画面以及蓝色纯色画面)。需要说明的是，预警画面与第一设定画面和第二设定画面不同，从而可以通过显示画面的区别，得到相应的提示信息。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
并且，本公开实施例提供的驱动方法及显示装置，可以根据显示面板100的实际应用场景，实现不同显示模式之间的切换。例如对于游戏类显示画面需要高刷新频率，然而，高刷新频率会压缩显示面板100子像素的充电时间，导致子像素的充电不足。本公开实施例中，在由低刷新频率的显示模式切换到高刷新频率的显示模式时，可以实现高刷新频率的同时，提高子像素的充电率。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设 备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种显示面板的驱动方法，包括：
    在接收到显示模式切换开启指令时，进入非计数状态，并驱动所述显示面板显示第一设定画面，并将当前显示模式切换至目标显示模式；
    在接收到数据模式切换完成指令时，进入计数状态。
  2. 如权利要求1所述的显示面板的驱动方法，其中，在所述进入计数状态之后，还包括：
    接收显示数据；
    统计所述显示数据中对应的设定目标的第一数目；
    在确定所述第一数目与所述目标显示模式对应的设定数目相同后，基于所述目标显示模式，根据接收到的所述显示数据，驱动所述显示面板显示对应的画面。
  3. 如权利要求2所述的显示面板的驱动方法，其中，在所述统计所述显示数据中对应的设定目标的第一数目之后，且在确定所述第一数目与所述目标显示模式对应的设定数目相同后，基于所述目标显示模式，根据接收到的所述显示数据，驱动所述显示面板显示对应的画面之前，还包括：
    在确定所述第一数目与所述设定数目相同时，基于所述目标显示模式，驱动所述显示面板在至少一个显示帧中显示第二设定画面。
  4. 如权利要求3所述的显示面板的驱动方法，其中，采用如下公式确定显示所述第二设定画面的显示帧的数量；
    SM＝TM/AM；
    其中，SM代表显示所述第二设定画面的显示帧的数量，TM代表设定时间，AM代表所述目标显示模式对应的刷新频率的倒数。
  5. 如权利要求3或4所述的显示面板的驱动方法，其中，所述第一设定画面和所述第二设定画面中的至少一个包括纯色画面和灰阶画面中的至少一个。
  6. 如权利要求1-5任一项所述的显示面板的驱动方法，其中，所述非计数状态包括清零状态、未使能状态以及断电状态中的一种。
  7. 如权利要求1-6任一项所述的显示面板的驱动方法，其中，所述显示面板包括第一显示模式；其中，所述第一显示模式包括：在相邻的两个显示帧的第一个显示帧中，逐行驱动所述显示面板中的栅线，并在上一个奇数行显示子像素连接的栅线驱动完，且下一个奇数行显示子像素连接的栅线驱动中时，对所述下一个奇数行显示子像素对应的数据线输入对应显示数据的数据电压；以及，在相邻的两个显示帧的第二个显示帧中，逐行驱动所述显示面板中的栅线，并在上一个偶数行显示子像素连接的栅线驱动完，且下一个偶数行显示子像素连接的栅线驱动中时，对所述下一个偶数行显示子像素对应的数据线输入对应显示数据的数据电压。
  8. 如权利要求7所述的显示面板的驱动方法，其中，所述显示面板包括第二显示模式；其中，所述第二显示模式包括：在各显示帧中，逐行驱动栅线，并在上一行栅线驱动完，且下一行栅线驱动中时，对下一行栅线连接的子像素对应的数据线输入对应显示数据的数据电压。
  9. 如权利要求8所述的显示面板的驱动方法，其中，所述显示面板包括第三显示模式；其中，所述第三显示模式包括：在各显示帧中，以至少相邻两行栅线为一个栅线组，接收各所述栅线组中一行子像素对应的显示数据，根据接收到的显示数据，同时驱动同一所述栅线组中的栅线，并逐个驱动所述栅线组，在上一个所述栅线组中的栅线驱动完，且下一个所述栅线组中的栅线驱动中时，对下一个所述栅线组的栅线连接的子像素对应的数据线输入对应显示数据的数据电压。
  10. 如权利要求9所述的显示面板的驱动方法，其中，所述当前显示模式为所述第一显示模式、所述第二显示模式以及所述第三显示模式中的一个；
    所述目标显示模式为所述第一显示模式、所述第二显示模式以及所述第三显示模式中，除所述当前显示模式之外的一个。
  11. 如权利要求10所述的显示面板的驱动方法，其中，所述设定目标包 括所述显示面板的子像素行；
    所述显示面板包括显示子像素行和虚拟子像素行；
    在所述目标显示模式为所述第一显示模式时，所述设定数目包括所有的虚拟子像素行的总数和所述显示子像素行的总数的一半；
    在所述目标显示模式为所述第二显示模式时，所述设定数目包括所有的虚拟子像素行的总数和所有显示子像素行的总数。
  12. 如权利要求11所述的显示面板的驱动方法，其中，所述设定目标包括所述显示面板的栅线组；
    在所述目标显示模式为所述第三显示模式时，所述设定数目包括栅线组的总数。
  13. 一种显示装置，包括：
    显示面板；
    时序控制器，被配置为：
    在接收到显示模式切换开启指令时，进入非计数状态，并驱动所述显示面板显示第一设定画面，并将当前显示模式切换至目标显示模式；
    在接收到数据模式切换完成指令时，进入计数状态。
  14. 如权利要求13所述的显示装置，其中，所述显示装置，还包括：
    系统电路，被配置为：
    在确定进行不同显示模式切换时，向所述时序控制器发送所述显示模式切换开启指令，并将对应所述当前显示模式的数据发送模式切换至对应所述目标显示模式的数据发送模式；
    在将对应所述当前显示模式的数据发送模式切换至对应所述目标显示模式的数据发送模式完成后，向所述时序控制器发送所述数据模式切换完成指令。
  15. 如权利要求13所述的显示装置，其中，所述显示装置还包括：计数单元；
    所述计数单元被配置为统计所述显示数据中对应的设定目标的第一数目， 并在确定所述第一数目与所述目标显示模式对应的设定数目相同时输出计数通过指令；
    所述时序控制器进一步被配置为在接收到所述显示模式切换开启指令时，控制所述计数单元进入所述非计数状态；在接收到所述数据模式切换完成指令时，控制所述计数单元进入计数状态。
  16. 如权利要求15所述的显示装置，其中，所述计数单元集成在所述时序控制器内。
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06202602A (ja) * 1992-12-25 1994-07-22 Oki Electric Ind Co Ltd 表示モード切り換え制御装置
CN1825404A (zh) * 2005-02-24 2006-08-30 富士通日立等离子显示器股份有限公司 显示面板的显示控制装置和具有该显示控制装置的显示装置
CN101496089A (zh) * 2006-07-31 2009-07-29 夏普株式会社 显示控制器、显示装置、显示系统以及显示装置的控制方法
CN102982759A (zh) * 2011-09-02 2013-03-20 三星电子株式会社 显示驱动器及其操作方法、控制显示驱动器的主机及系统
CN104123907A (zh) * 2014-06-05 2014-10-29 友达光电股份有限公司 显示装置及切换显示模式的方法
CN107507552A (zh) * 2017-09-05 2017-12-22 京东方科技集团股份有限公司 一种信号处理方法和时序控制电路
CN108831370A (zh) * 2018-08-28 2018-11-16 京东方科技集团股份有限公司 显示驱动方法及其装置、显示装置和可穿戴设备
CN113593463A (zh) * 2021-07-30 2021-11-02 福州京东方光电科技有限公司 一种显示模式切换系统、方法及显示装置
CN114267293A (zh) * 2021-12-29 2022-04-01 Tcl华星光电技术有限公司 显示装置及其显示方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06202602A (ja) * 1992-12-25 1994-07-22 Oki Electric Ind Co Ltd 表示モード切り換え制御装置
CN1825404A (zh) * 2005-02-24 2006-08-30 富士通日立等离子显示器股份有限公司 显示面板的显示控制装置和具有该显示控制装置的显示装置
CN101496089A (zh) * 2006-07-31 2009-07-29 夏普株式会社 显示控制器、显示装置、显示系统以及显示装置的控制方法
CN102982759A (zh) * 2011-09-02 2013-03-20 三星电子株式会社 显示驱动器及其操作方法、控制显示驱动器的主机及系统
CN104123907A (zh) * 2014-06-05 2014-10-29 友达光电股份有限公司 显示装置及切换显示模式的方法
CN107507552A (zh) * 2017-09-05 2017-12-22 京东方科技集团股份有限公司 一种信号处理方法和时序控制电路
CN108831370A (zh) * 2018-08-28 2018-11-16 京东方科技集团股份有限公司 显示驱动方法及其装置、显示装置和可穿戴设备
CN113593463A (zh) * 2021-07-30 2021-11-02 福州京东方光电科技有限公司 一种显示模式切换系统、方法及显示装置
CN114267293A (zh) * 2021-12-29 2022-04-01 Tcl华星光电技术有限公司 显示装置及其显示方法

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