WO2023050127A1 - 显示面板的驱动方法、显示驱动电路及显示装置 - Google Patents

显示面板的驱动方法、显示驱动电路及显示装置 Download PDF

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Publication number
WO2023050127A1
WO2023050127A1 PCT/CN2021/121618 CN2021121618W WO2023050127A1 WO 2023050127 A1 WO2023050127 A1 WO 2023050127A1 CN 2021121618 W CN2021121618 W CN 2021121618W WO 2023050127 A1 WO2023050127 A1 WO 2023050127A1
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WIPO (PCT)
Prior art keywords
voltage
sub
display
data
data line
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PCT/CN2021/121618
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English (en)
French (fr)
Inventor
田宇航
廖燕平
陈东川
姚树林
缪应蒙
张银龙
胡鹏飞
马文鹏
张正
刘建涛
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180002738.XA priority Critical patent/CN116802723A/zh
Priority to PCT/CN2021/121618 priority patent/WO2023050127A1/zh
Publication of WO2023050127A1 publication Critical patent/WO2023050127A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving method of a display panel, a display driving circuit and a display device.
  • Displays such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED) generally include a plurality of pixels. Each pixel may include: a red sub-pixel, a green sub-pixel and a blue sub-pixel. By controlling the display data corresponding to each sub-pixel, the display brightness of each sub-pixel is controlled, so as to display the color image by mixing the required displayed colors.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the display panel works in a plurality of continuous display frames, and each display frame includes a data refresh phase and a blank time phase;
  • the driving method of the display panel includes:
  • a gate-on voltage is applied to the gate lines in the display panel, and a data voltage of an image to be displayed is applied to each data line, so that Each sub-pixel inputs a corresponding data voltage;
  • the compensation voltage applied on the data line is lower than the data voltage in the sub-pixel connected to the data line
  • the compensation voltage loaded on the data line is greater than the data voltage in the sub-pixels connected to the data line.
  • the compensation voltage is fully loaded during at least one blank time period of the display frame.
  • the display panel adopts a column inversion method or a frame inversion method;
  • the compensation voltage includes a first sub-compensation voltage;
  • the polarity corresponding to the first sub-compensation voltage loaded on the data line is opposite to the polarity corresponding to the sub-pixel connected to the data line.
  • the display frames in which the compensation voltage is applied to each of the data lines during the blank time period there are a first display frame and a second display frame;
  • the first display frame corresponds to a first refresh rate
  • the second display frame corresponds to a second refresh rate
  • the first refresh rate is greater than the second refresh rate
  • the duration of the blank time period in the first display frame is shorter than the duration of the blank time period in the second display frame.
  • the display frame in which the compensation voltage is applied to each of the data lines in the blank time period is defined as a set display frame; in two adjacent set display frames, for the same data line, the There is a first difference between the first sub-compensation voltage applied to the data line in the previous setting display frame and the voltage of the common electrode, and the first sub-compensation voltage applied to the data line in the next setting display frame There is a second difference between the compensation voltage and the common electrode voltage;
  • the absolute value of the first difference is equal to the absolute value of the second difference.
  • the compensation voltage further includes a transition compensation voltage occurring before the first sub-compensation voltage
  • the polarity corresponding to the transition compensation voltage loaded on the data line is the same as the polarity corresponding to the sub-pixel connected to the data line.
  • the display panel adopts a column inversion method or a frame inversion method;
  • the compensation voltage includes a second sub-compensation voltage;
  • the polarity corresponding to the second sub-compensation voltage loaded on the data line is the same as the polarity corresponding to the data voltage in the sub-pixel connected to the data line.
  • a display frame in which the compensation voltage is applied to each of the data lines during a blank time period is defined as a set display frame
  • Part of the display frames in the plurality of consecutive display frames are the set display frames
  • the display frames other than the set display frame are non-set display frames
  • the non-set display frame includes:
  • the gate-on voltage is applied to the gate lines in the display panel, and the data voltage of the image to be displayed is applied to the data lines, so that each sub-pixel inputs a corresponding data voltage;
  • the gate-off voltage is applied to the gate lines in the display panel, and each of the data lines is floated.
  • the number of the non-set display frames between every two adjacent set display frames is the same.
  • the gray scales corresponding to the compensation voltages loaded by the data lines are the same.
  • the gray scale corresponding to the compensation voltage loaded on the data line is the same as the gray scale corresponding to a data voltage in the sub-pixel connected to the data line.
  • the gray scale corresponding to the compensation voltage is determined by using the following formula
  • VS11 represents the gray scale corresponding to the compensation voltage
  • VA11 represents the maximum gray scale in a display frame selected from the multiple consecutive display frames
  • VA12 represents the gray scale selected from the multiple consecutive display frames.
  • the minimum gray scale in the display frame, and VA11+VA12 is an even number.
  • the gray scale corresponding to the compensation voltage is determined by using the following formula
  • VS21 represents the gray scale corresponding to the compensation voltage
  • VA21 represents the maximum gray scale in a display frame selected from the multiple continuous display frames
  • VA22 represents the maximum gray scale selected from the multiple continuous display frames.
  • the minimum gray scale in the display frame, and VA21+VA22 is an odd number.
  • the applying a compensation voltage to each of the data lines includes:
  • the applying a compensation voltage to each of the data lines includes:
  • the applying a compensation voltage to each of the data lines includes:
  • the display frame selected from the plurality of display frames is one of the previous display frame adjacent to the set display frame and the set display frame.
  • the display panel works in a plurality of consecutive display frames, and each display frame includes a data refresh phase and a blank time phase;
  • the display driver circuit is configured as:
  • a gate-on voltage is applied to the gate lines in the display panel, and a data voltage of an image to be displayed is applied to each data line, so that Each sub-pixel inputs a corresponding data voltage;
  • the compensation voltage applied on the data line is lower than the data voltage in the sub-pixel connected to the data line
  • the compensation voltage loaded on the data line is greater than the data voltage in the sub-pixels connected to the data line.
  • the display device includes a display panel and a timing controller; the display panel includes a plurality of gate lines, a plurality of data lines, a source driving circuit and a gate driving circuit; wherein the source driving circuit coupled with the plurality of data lines; the gate drive circuit coupled with the plurality of gate lines;
  • the timing controller is coupled to the source drive circuit and the gate drive circuit;
  • the timing controller is configured to input a first gate driving signal to the gate driving circuit, and to input a first gate driving signal to the source driving inputting a first source driving signal to the circuit; and inputting a second gate driving signal to the gate driving circuit, and inputting a second source to the source driving circuit during at least one blank time period of the display frame drive signal;
  • the gate drive circuit is configured to apply a gate turn-on voltage to the gate lines in the display panel according to receiving the first gate drive signal; and according to the received second gate drive signal, applying a gate-off voltage to the gate lines in the display panel;
  • the source driving circuit is configured to load each data line with a data voltage of an image to be displayed according to receiving the first source driving signal, so that each sub-pixel inputs a corresponding data voltage;
  • the second source driving signal applies a compensation voltage to each of the data lines.
  • FIG. 1a is a schematic structural diagram of a display panel in an embodiment of the present disclosure
  • FIG. 1b is a schematic diagram of a common electrode voltage and a data voltage in an embodiment of the present disclosure
  • FIG. 2 is a signal timing diagram in a related disclosed embodiment
  • FIG. 3 is a flowchart of a method for driving a display panel in an embodiment of the present disclosure
  • Fig. 4a is some schematic diagrams of the polarity of each sub-pixel in the display panel corresponding to the previous display frame in two adjacent display frames in an embodiment of the present disclosure
  • Fig. 4b is some schematic diagrams of the polarity of each sub-pixel in the display panel corresponding to the next display frame in two adjacent display frames in the embodiment of the present disclosure
  • 4c is another schematic diagram of the polarity of each sub-pixel in the display panel corresponding to the previous display frame in two adjacent display frames in the embodiment of the present disclosure
  • Figure 4d is another schematic diagram of the polarity of each sub-pixel in the display panel corresponding to the next display frame in two adjacent display frames in the embodiment of the present disclosure
  • FIG. 5 is a timing diagram of some signals in an embodiment of the present disclosure.
  • FIG. 6 is another timing diagram of signals in an embodiment of the present disclosure.
  • FIG. 7 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 8 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 9 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 10 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 11 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 12 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 13 is some structural schematic diagrams of a display device in an embodiment of the present disclosure.
  • the current display frequency is generally 60HZ, that is, the screen of the display is refreshed 60 times per second, so that the screen seen by the human eye is dynamic and smooth.
  • it is necessary to reduce the display frequency of the display for example: from 60HZ to 30HZ.
  • it is necessary to increase the frequency of the display for example: from 60HZ to 90HZ or 120HZ, so as to make the picture smoother. Therefore, in order to be suitable for different scenes, the display needs to change the display frequency, that is, the dynamic frame rate display.
  • a display may include a plurality of pixels arranged in an array, a plurality of gate lines (eg, GA1, GA2, GA3, GA4) and a plurality of data lines (eg, DA1, DA2, DA3).
  • Each pixel includes a plurality of sub-pixels.
  • a pixel may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue can be mixed to achieve color display.
  • the pixels may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that color mixing of red, green, blue and white can be performed to realize color display.
  • the luminous color of the sub-pixels in the pixel can be designed and determined according to the practical application environment, which is not limited here.
  • each sub-pixel includes a transistor 01 and a pixel electrode 02 .
  • one row of sub-pixels corresponds to one gate line
  • one column of sub-pixels corresponds to one data line.
  • the gate of the transistor 01 is electrically connected to the corresponding gate line
  • the source of the transistor 01 is electrically connected to the corresponding data line
  • the drain of the transistor 01 is electrically connected to the pixel electrode 02.
  • the pixel array structure of the present invention can also be It is a double-gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce half of the data lines, that is, there are data lines between two adjacent columns of pixels, and some adjacent two rows of pixels.
  • a display frame F0 of the display may include a data refreshing period TS and a blanking time period TB.
  • the signal ga1 is applied to the gate line GA1
  • the signal ga2 is applied to the gate line GA2
  • the signal ga3 is applied to the gate line GA3
  • the signal ga4 is applied to the gate line GA4, and the gate turn-on voltage ( For example, when the voltage corresponds to a high level), the corresponding transistor 010 can be controlled to be turned on.
  • all the transistors 01 in the first row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, and the corresponding data voltage da2 is applied to the data line DA2.
  • the data line DA3 is loaded with a corresponding data voltage da3, so that the pixel electrode 02 in the first row of sub-pixels inputs the corresponding data voltage.
  • the signal ga2 When the signal ga2 has a gate-on voltage, it can control the transistors 01 in the second row of sub-pixels to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, the corresponding data voltage da2 is applied to the data line DA2, and the corresponding data voltage da2 is applied to the data line DA2.
  • DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the second row of sub-pixels inputs the corresponding data voltage.
  • the signal ga3 When the signal ga3 has a gate-on voltage, it can control the transistors 01 in the third row of sub-pixels to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, and the corresponding data voltage da2 is applied to the data line DA2, and the corresponding data voltage da2 is applied to the data line DA2.
  • DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the third row of sub-pixels inputs the corresponding data voltage.
  • the transistors 01 in the fourth row of sub-pixels can be controlled to be turned on, the corresponding data voltage da1 is applied to the data line DA1, the corresponding data voltage da2 is applied to the data line DA2, and the corresponding data voltage da2 is applied to the data line DA2.
  • DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the fourth row of sub-pixels inputs the corresponding data voltage. The rest of the lines are deduced in the same way, and will not be repeated here.
  • the signals ga1-ga4 are all at low level, and the transistor 01 in each sub-pixel is in an off state. Moreover, the data lines DA1 - DA3 may not be loaded with voltage, and are all in a floating state.
  • Embodiments of the present disclosure provide a driving method for a display panel, which can solve the problem of increased brightness of a display screen when the display frequency of the display changes from high frequency to low frequency, maintain stable brightness, and improve display quality and viewing experience.
  • the display panel works in a plurality of continuous display frames, and each display frame may include a data refresh period and a blank time period.
  • the gate-on voltage is applied to the gate lines in the display panel, and the data voltage of the image to be displayed is applied to each data line, so that each sub-pixel Corresponding data voltages are input, so as to realize the picture display of one display frame.
  • a gate-off voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each data line.
  • the display frame in which the compensation voltage is applied to the data line in the blank time period is defined as the set display frame.
  • the driving method of the display panel provided by the embodiment of the present disclosure, as shown in FIG. 3 may include the following steps:
  • the display panel in the embodiments of the present disclosure may be a liquid crystal display panel.
  • a set display frame is designed, and in the set display frame, there is a data refresh phase and a blank time phase.
  • the gate-on voltage is applied to the gate lines in the display panel, and the data voltage of the image to be displayed is applied to each data line, so that each sub-pixel inputs a corresponding data voltage, thereby realizing a display Frames are displayed on the screen.
  • a gate-off voltage is applied to the gate lines in the display panel, so as to control the transistors in each sub-pixel to be in an off state.
  • Vda1-1 ⁇ Vda1-4 respectively represent the data voltages input to the sub-pixels in the first row to the fourth row in the first column of sub-pixels.
  • Vdc1 represents the compensation voltage loaded on the data line DA1 connected to the sub-pixels in the first column.
  • Vda1-1 ⁇ Vda1-4 are all greater than the common electrode voltage Vcom, and Vdc1 is less than Vda1-1 ⁇ Vda1-4, due to the leakage of the transistor in the sub-pixel, the leakage current direction is from the sub-pixel to the data line DA1, so that Vda1-1 ⁇ Vda1-4 voltage drops.
  • Vda1-1 is reduced to Vda1-1'. This allows the voltage difference ⁇ V1 between Vda1-1 and Vcom to be reduced to ⁇ V1'.
  • the reduction of the voltage difference can reduce the brightness of the sub-pixel, therefore, the brightness of the sub-pixels in the first row can be reduced.
  • Vda2-1 ⁇ Vda2-4 respectively represent the data voltages input to the sub-pixels in the first row to the fourth row in the second column of sub-pixels.
  • Vdc2 represents the compensation voltage loaded on the data line DA2 connected to the sub-pixels in the second column.
  • Vda2-1 ⁇ Vda2-4 are all less than the common electrode voltage Vcom, and Vdc2 is greater than Vda1-1 ⁇ Vda1-4, due to the leakage of the transistor in the sub-pixel, the leakage current direction is from the data line DA2 to the sub-pixel, so that Vda1- 1 ⁇ Vda1-4 voltage rises.
  • Vda2-1 is elevated to Vda2-1'. This allows the voltage difference ⁇ V2 between Vda2-1 and Vcom to be reduced to ⁇ V2'.
  • the reduction of the voltage difference can reduce the brightness of the sub-pixel, therefore, the brightness of the sub-pixels in the second row can be reduced.
  • the rest are the same, so that the brightness of the sub-pixel can be reduced.
  • the brightness of the display screen at low frequency can be reduced, so that the brightness of the display screen at high frequency and the brightness of the display screen at low frequency can be as much as possible Stay stable, improve display quality and viewing experience.
  • the display panel in the embodiments of the present disclosure may be a liquid crystal display panel.
  • the polarity of the sub-pixel when the data voltage in the pixel electrode of the sub-pixel is greater than the voltage of the common electrode, the polarity of the sub-pixel can be positive.
  • the common electrode voltage on the common electrode can be 8V. Taking a sub-pixel as an example, if a voltage of 8V-12V is applied to the pixel electrode of the sub-pixel, the liquid crystal molecules at the sub-pixel can be for positive polarity.
  • the sub-pixel corresponds to a brightness of +255 gray scales when a voltage of 12V is applied to the pixel electrode. If a voltage of 4V-8V is applied to the pixel electrode of the sub-pixel, the liquid crystal molecules at the sub-pixel can be made to have a negative polarity. Taking gray scales 0 to 255 as an example, the sub-pixel corresponds to a brightness of -255 gray scale when a voltage of 4V is applied to the pixel electrode.
  • FIG. 4 a and FIG. 4 b schematically illustrate the polarities of sub-pixels in two adjacent display frames when the display panel adopts the column inversion mode.
  • FIG. 4a schematically shows the polarity of each sub-pixel in the display panel corresponding to the previous display frame in two adjacent display frames.
  • 4b schematically shows the polarity of each sub-pixel in the display panel corresponding to the next display frame in two adjacent display frames.
  • "+" represents that the polarity of the sub-pixel is positive
  • "-" represents that the polarity of the sub-pixel is negative.
  • sub-pixel columns of positive polarity and sub-pixel columns of negative polarity are arranged alternately.
  • the sub-pixel column has a positive polarity.
  • the sub-pixel row is negative.
  • the sub-pixel column is negative polarity.
  • the sub-pixel row is positive.
  • the display panel in order to improve the performance of the liquid crystal and reduce the power consumption, the display panel may adopt the frame inversion mode.
  • FIG. 4c and FIG. 4d schematically show the polarities of sub-pixels in two adjacent display frames when the display panel adopts the frame inversion mode.
  • FIG. 4c schematically shows the polarity of each sub-pixel in the display panel corresponding to the previous display frame in two adjacent display frames.
  • Fig. 4d schematically shows the polarity of each sub-pixel in the display panel corresponding to the next display frame in two adjacent display frames.
  • "+" represents that the polarity of the sub-pixel is positive
  • "-" represents that the polarity of the sub-pixel is negative.
  • each sub-pixel column has positive polarity.
  • each sub-pixel column is negative.
  • the compensation voltage may include a first sub-compensation voltage, and, for each data line, the polarity corresponding to the first sub-compensation voltage applied on the data line is the same as the polarity corresponding to the sub-pixel connected to the data line. Sex is the opposite.
  • the first sub-pixel column corresponds to positive polarity
  • the polarity corresponding to the first sub-compensation voltage that can be applied to the data line corresponding to the first sub-pixel column in the blank time period is negative polarity , for example, a voltage selected from 4V-8V can be applied to the data line.
  • the second sub-pixel column corresponds to negative polarity, then the polarity corresponding to the first sub-compensation voltage that can be applied to the data line corresponding to the second sub-pixel column during the blank time period is positive polarity, for example, the voltage can be selected from 8V to 12V applied to the data line.
  • the third sub-pixel column corresponds to positive polarity, then the polarity corresponding to the first sub-compensation voltage that can be applied to the data line corresponding to the third sub-pixel column during the blank time period is negative polarity, for example, the voltage can be selected from 4V to 8V applied to the data line.
  • the fourth sub-pixel column corresponds to negative polarity
  • the polarity corresponding to the first sub-compensation voltage that can be applied to the data line corresponding to the fourth sub-pixel column in the blank time period is positive polarity, for example, the voltage can be selected from 8V to 12V applied to the data line.
  • the first sub-pixel column corresponds to negative polarity
  • the polarity corresponding to the first sub-compensation voltage that can be applied to the data line corresponding to the first sub-pixel column in the blank time period is positive polarity
  • a voltage selected from 8V-12V can be applied to the data line.
  • the second sub-pixel column corresponds to positive polarity
  • the polarity corresponding to the first sub-compensation voltage that can be loaded to the data line corresponding to the second sub-pixel column in the blank time period is negative polarity, for example, the voltage can be selected from 4V to 8V applied to the data line.
  • the third sub-pixel column corresponds to negative polarity, then the polarity corresponding to the first sub-compensation voltage that can be loaded to the data line corresponding to the third sub-pixel column during the blank time period is positive polarity, for example, the voltage can be selected from 8V to 12V applied to the data line.
  • the fourth sub-pixel column corresponds to positive polarity, then the polarity corresponding to the first sub-compensation voltage that can be applied to the data line corresponding to the fourth sub-pixel column in the blank time period is negative polarity, for example, the voltage can be selected from 4V to 8V applied to the data line.
  • the first voltage between the first sub-compensation voltage and the common electrode voltage applied to the data line in the previous setting display frame.
  • There is a second difference between the first sub-compensation voltage applied to the data line and the common electrode voltage in the next set display frame.
  • the absolute value of the first difference may be made equal to the absolute value of the second difference.
  • ⁇ Vdc1 between the first sub-compensation voltage Vdc11-1 applied to the data line and the common electrode voltage Vcom.
  • the compensation voltage may be fully loaded during the blank time period of at least one display frame.
  • the first sub-compensation voltage may be applied to each data line during the entire blank time period TB in the F1 display frame.
  • the first sub-compensation voltage is applied to each data line.
  • each display frame in a plurality of continuous display frames may be set as a set display frame. That is, in the data refresh period included in each display frame in a plurality of consecutive display frames, the gate-on voltage is applied to the grid lines in the display panel, and the data voltage of the image to be displayed is applied to each data line, so that each sub- The pixels input corresponding data voltages. And, in the blank time period included in each display frame of the multiple consecutive display frames, the gate-off voltage is applied to the gate lines in the display panel, and the first sub-compensation voltage is applied to each data line. This can compensate for each display frame, so that the brightness can be kept stable.
  • the gray scales corresponding to the compensation voltages applied to the data lines can be made the same. In this way, the gray scale of each compensation voltage can be determined without excessive calculation, and power consumption can be reduced.
  • the gray scales corresponding to the first sub-compensation voltages applied to each data line may be the same. In this way, the amount of calculation for determining the first sub-compensation voltage in different set display frames can be reduced, and the power consumption can be reduced.
  • the gray scale corresponding to the first sub-compensation voltage loaded by each data line is 127 gray scales.
  • the first sub-pixel column corresponds to positive polarity
  • the polarity corresponding to the first sub-compensation voltage that can be loaded to the data line corresponding to the first sub-pixel column is negative polarity
  • the polarity is from 4V to 8V
  • a voltage corresponding to gray scale 127 is selected and applied to the data line.
  • the second sub-pixel column corresponds to negative polarity
  • the polarity corresponding to the first sub-compensation voltage that can be loaded to the data line corresponding to the second sub-pixel column is positive polarity
  • the voltage corresponding to 127 gray scales is selected from 8V to 12V and applied to the data line.
  • the third sub-pixel column corresponds to positive polarity, then the polarity corresponding to the first sub-compensation voltage that can be applied to the data line corresponding to the third sub-pixel column is negative polarity, and the voltage corresponding to 127 gray scales is selected from 4V ⁇ 8V to apply on the data line.
  • the fourth sub-pixel column corresponds to negative polarity, then the polarity corresponding to the compensation voltage that can be applied to the data line corresponding to the fourth sub-pixel column is positive polarity, and a voltage corresponding to 127 gray scales is selected from 8V to 12V to apply to the data line superior.
  • the first sub-pixel column corresponds to negative polarity
  • the polarity corresponding to the first sub-compensation voltage that can be loaded to the data line corresponding to the first sub-pixel column is positive polarity
  • a voltage corresponding to 127 gray scales is applied to the data line.
  • the second sub-pixel column corresponds to positive polarity
  • the polarity corresponding to the first sub-compensation voltage that can be loaded to the data line corresponding to the second sub-pixel column is negative polarity
  • the voltage corresponding to 127 gray scales is selected from 4V ⁇ 8V to apply on the data line.
  • the third sub-pixel column corresponds to negative polarity, then the polarity corresponding to the first sub-compensation voltage that can be loaded to the data line corresponding to the third sub-pixel column is positive polarity, and the voltage corresponding to 127 gray scales is selected from 8V to 12V and applied to the data line.
  • the fourth sub-pixel column corresponds to positive polarity, then the polarity corresponding to the first sub-compensation voltage that can be applied to the data line corresponding to the fourth sub-pixel column is negative polarity, and the voltage corresponding to 127 gray scales is selected from 4V ⁇ 8V to apply on the data line.
  • the voltage value of the compensation voltage may be a voltage value of any gray scale.
  • the voltage value of the first sub-compensation voltage may be a voltage value of any gray scale.
  • the gray scale corresponding to the first sub-compensation voltage loaded by each data line may be selected from one of 0 to 255 gray scales, for example, may be 127 gray scales.
  • 200 gray scales may also be used.
  • Any gray scale here means that the same voltage of any gray scale can be added to the sub-pixels of the display panel that need to be compensated.
  • the compensation method is simple, no additional compensation modules or operations are required, and power consumption is saved.
  • the gray scale can be selected according to the needs of practical applications, which is not limited here.
  • the gray scale corresponding to the compensation voltage loaded on the data line is the same as the gray scale corresponding to a data voltage in the sub-pixel connected to the data line.
  • the gray scale corresponding to the first sub-compensation voltage loaded on the data line is the same as the gray scale corresponding to one data voltage in the sub-pixels connected to the data line.
  • the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column may be the same as the gray scale corresponding to the data voltage in the first row of sub-pixels in the first sub-pixel column.
  • the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column may be the same as the gray scale corresponding to the data voltage in the first row of sub-pixels in the second sub-pixel column.
  • the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column may be the same as the gray scale corresponding to the data voltage in the last row of sub-pixels in the first sub-pixel column.
  • the blank time period of the display frame may also be partially loaded with the first compensation voltage, for example, the blank time period may have at least one compensation phase, and the first sub-compensation voltage is applied to the data line in the compensation phase .
  • the blank time period for setting the display frame may have a compensation period BC.
  • the blank time period for setting the display frame may have multiple compensation stages, for example, including 3 compensation stages.
  • the number of compensation stages that can be included in the blank time period of the set display frame can be set and determined according to the needs of practical applications, and is not limited here.
  • the interval between every two adjacent compensation stages is the same. In this way, the compensation voltage can be evenly applied to the data line during the blank time period.
  • the duration of the compensation phase satisfies the relationship: 0 ⁇ tc ⁇ 1/2tb; wherein, tc represents the duration of the compensation phase, and tb represents the duration of the blank time phase.
  • tc represents the duration of the compensation phase
  • tb represents the duration of the blank time phase.
  • the boundary of the compensation phase may coincide with the boundary of the data refresh phase.
  • a certain period of time may be set between the boundary of the compensation phase and the boundary of the data refresh phase.
  • each of the multiple consecutive display frames is a set display frame.
  • Fig. 4a corresponds to the display frame F1
  • Fig. 4b corresponds to the display frame F2.
  • the display frames F1 and F2 are two adjacent display frames in a plurality of continuous display frames.
  • the transistors 01 in the first row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, and the data voltage da1 is applied to the data line DA1.
  • the line DA2 is loaded with the corresponding data voltage da2
  • the data line DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the first row of sub-pixels inputs the corresponding data voltage.
  • the signal ga2 When the signal ga2 has a gate-on voltage, it can control the transistors 01 in the second row of sub-pixels to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, the corresponding data voltage da2 is applied to the data line DA2, and the corresponding data voltage da2 is applied to the data line DA2.
  • DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the second row of sub-pixels inputs the corresponding data voltage.
  • the signal ga3 When the signal ga3 has a gate-on voltage, it can control the transistors 01 in the third row of sub-pixels to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, and the corresponding data voltage da2 is applied to the data line DA2, and the corresponding data voltage da2 is applied to the data line DA2.
  • DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the third row of sub-pixels inputs the corresponding data voltage.
  • the transistors 01 in the fourth row of sub-pixels can be controlled to be turned on, the corresponding data voltage da1 is applied to the data line DA1, the corresponding data voltage da2 is applied to the data line DA2, and the corresponding data voltage da2 is applied to the data line DA2.
  • DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the fourth row of sub-pixels inputs the corresponding data voltage. The rest of the lines are deduced in the same way, and will not be repeated here.
  • the gate-off voltage is simultaneously applied to the gate lines in the display panel, so as to control the transistor 01 in each sub-pixel to be in an off state.
  • a voltage corresponding to 127 gray scales is selected from 4V-8V as the first sub-compensation voltage corresponding to the negative polarity, and applied to the data line corresponding to the first sub-pixel column.
  • a voltage corresponding to 127 gray scales is selected from 8V-12V as the first sub-compensation voltage corresponding to positive polarity, and applied to the data line corresponding to the second sub-pixel column.
  • a voltage corresponding to 127 gray scales is selected from 4V-8V as the first sub-compensation voltage corresponding to the negative polarity, and applied to the data line corresponding to the third sub-pixel column.
  • a voltage corresponding to 127 gray scales is selected from 8V-12V as the first sub-compensation voltage corresponding to positive polarity, and applied to the data line corresponding to the fourth sub-pixel column.
  • the transistors 01 in the first row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, and the data voltage da1 is applied to the data line DA1.
  • the line DA2 is loaded with the corresponding data voltage da2
  • the data line DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the first row of sub-pixels inputs the corresponding data voltage.
  • the signal ga2 When the signal ga2 has a gate-on voltage, it can control the transistors 01 in the second row of sub-pixels to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, the corresponding data voltage da2 is applied to the data line DA2, and the corresponding data voltage da2 is applied to the data line DA2.
  • DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the second row of sub-pixels inputs the corresponding data voltage.
  • the signal ga3 When the signal ga3 has a gate-on voltage, it can control the transistors 01 in the third row of sub-pixels to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, and the corresponding data voltage da2 is applied to the data line DA2, and the corresponding data voltage da2 is applied to the data line DA2.
  • DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the third row of sub-pixels inputs the corresponding data voltage.
  • the transistors 01 in the fourth row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is applied to the data line DA1, and the corresponding data voltage da2 is applied to the data line DA2, and the corresponding data voltage da2 is applied to the data line DA2.
  • DA3 is loaded with the corresponding data voltage da3, so that the pixel electrode 02 in the fourth row of sub-pixels inputs the corresponding data voltage. The rest of the lines are deduced in the same way, and will not be repeated here.
  • the gate-off voltage is simultaneously applied to the gate lines in the display panel, so as to control the transistor 01 in each sub-pixel to be in an off state.
  • a voltage corresponding to 127 gray scales is selected from 8V-12V as the first sub-compensation voltage corresponding to positive polarity, and applied to the data line corresponding to the first sub-pixel column.
  • a voltage corresponding to 127 gray scales is selected from 4V-8V as the first sub-compensation voltage corresponding to the negative polarity, and applied to the data line corresponding to the second sub-pixel column.
  • a voltage corresponding to 127 gray scales is selected from 8V-12V as the first sub-compensation voltage corresponding to positive polarity, and applied to the data line corresponding to the third sub-pixel column.
  • a voltage corresponding to 127 gray scales is selected from 4V-8V as the first sub-compensation voltage corresponding to the negative polarity, and applied to the data line corresponding to the fourth sub-pixel column.
  • the embodiments of the present disclosure provide some other driving methods of the display panel, which are modified with respect to the implementation manners in the above-mentioned embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the compensation voltage may further include a transition compensation voltage that appears before the first sub-compensation voltage. Moreover, when the data voltage in the sub-pixels connected to the data line is higher than the common electrode voltage, the transition compensation voltage applied on the data line is lower than the data voltage in the sub-pixels connected to the data line. And, when the data voltage in the sub-pixels connected with the data line is lower than the voltage of the common electrode, the transition compensation voltage loaded on the data line is greater than the data voltage in the sub-pixels connected with the data line.
  • the polarity corresponding to the transition compensation voltage loaded on the data line is the same as the polarity corresponding to the sub-pixels connected to the data line.
  • the first sub-pixel column in the data refresh phase TS corresponds to positive polarity
  • the data corresponding to the first sub-pixel column can be first Load the transition compensation voltage Vdc21-1 corresponding to the positive polarity on the line, for example, select a voltage from 8V to 12V as the transition compensation voltage Vdc21-1 and apply it to the data line, and then load the corresponding data line to the first sub-pixel column.
  • the negative first sub-compensation voltage Vdc11-1 for example, a voltage selected from 4V ⁇ 8V is applied to the data line as the first sub-compensation voltage Vdc11-1.
  • the second sub-pixel column corresponds to the negative polarity
  • in the blank time period TB can first load the transition compensation voltage corresponding to the negative polarity to the data line corresponding to the second sub-pixel column, for example, select a voltage from 4V to 8V as the A transition compensation voltage is applied to the data line, and then a first sub-compensation voltage corresponding to positive polarity is applied to the data line corresponding to the second sub-pixel column, for example, a voltage selected from 8V-12V is applied to the data line as the first sub-compensation voltage.
  • transition compensation voltage and the first sub-compensation voltage loaded on the data line corresponding to the third sub-pixel column are in the same manner as the transition compensation voltage and the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column, and will not be repeated here.
  • the transition compensation voltage and the first sub-compensation voltage applied to the data line corresponding to the fourth sub-pixel column are in the same manner as the transition compensation voltage and the first sub-compensation voltage applied to the data line corresponding to the second sub-pixel column, which will not be repeated here.
  • the first sub-pixel column in the data refresh phase TS corresponds to negative polarity
  • the data corresponding to the first sub-pixel column can be first Load the transition compensation voltage Vdc21-2 corresponding to the negative polarity on the line, for example, select a voltage from 4V to 8V as the transition compensation voltage Vdc21-2 and apply it to the data line, and then load the corresponding data line to the first sub-pixel column.
  • the positive first sub-compensation voltage Vdc11-2 for example, a voltage selected from 8V ⁇ 12V is applied to the data line as the first sub-compensation voltage Vdc11-2.
  • the second sub-pixel column corresponds to the positive polarity
  • the blank time period TB can first load the transition compensation voltage corresponding to the positive polarity to the data line corresponding to the second sub-pixel column, for example, select a voltage from 8V to 12V as the A transition compensation voltage is applied to the data line, and then a first sub-compensation voltage of negative polarity is applied to the data line corresponding to the second sub-pixel column, for example, a voltage selected from 4V-8V is applied to the data line as the first sub-compensation voltage. on-line.
  • transition compensation voltage and the first sub-compensation voltage loaded on the data line corresponding to the third sub-pixel column are in the same manner as the transition compensation voltage and the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column, and will not be repeated here.
  • the transition compensation voltage and the first sub-compensation voltage applied to the data line corresponding to the fourth sub-pixel column are in the same manner as the transition compensation voltage and the first sub-compensation voltage applied to the data line corresponding to the second sub-pixel column, which will not be repeated here.
  • Embodiments of the present disclosure provide some methods for driving display panels, which are modified for the implementation manners in the above embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the following formula may also be used to determine the gray scale corresponding to the compensation voltage
  • VS11 represents the gray scale corresponding to the compensation voltage
  • VA11 represents the maximum gray scale in a display frame selected from multiple consecutive display frames
  • VA12 represents the minimum gray scale in a display frame selected from multiple consecutive display frames
  • VA11+VA12 is an even number.
  • the display frame selected from the plurality of display frames may be a previous display frame adjacent to the set display frame.
  • VS11 may represent the gray scale corresponding to the first sub-compensation voltage in the display frame F2
  • VA11 may represent the maximum value corresponding to the data voltage in the input sub-pixel in the display frame F1.
  • Gray scale VA12 may represent the minimum gray scale corresponding to the data voltage input to the sub-pixel in the display frame F1.
  • the display frame selected from the plurality of display frames may be the set display frame.
  • VS11 may represent the gray scale corresponding to the first sub-compensation voltage in the display frame F1
  • VA11 may represent the maximum value corresponding to the data voltage in the input sub-pixel in the display frame F1.
  • Gray scale VA12 may represent the minimum gray scale corresponding to the data voltage input to the sub-pixel in the display frame F1.
  • the rest of the working process of the display panel driving method corresponding to this embodiment may be basically the same as the rest of the working process of the display panel driving method in the above-mentioned embodiment, and will not be repeated here.
  • Embodiments of the present disclosure provide still some driving methods of the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the following formula may also be used to determine the gray scale corresponding to the compensation voltage
  • VS21 represents the gray scale corresponding to the compensation voltage
  • VA21 represents the maximum gray scale in a display frame selected from multiple consecutive display frames
  • VA22 represents the minimum gray scale in a display frame selected from multiple consecutive display frames
  • VA21+VA22 is an odd number.
  • the display frame selected from the plurality of display frames may be a previous display frame adjacent to the set display frame.
  • VS21 may represent the gray scale corresponding to the first sub-compensation voltage in the display frame F2
  • VA21 may represent the maximum value corresponding to the data voltage in the input sub-pixel in the display frame F1.
  • Gray scale VA22 may represent the minimum gray scale corresponding to the data voltage input to the sub-pixel in the display frame F1.
  • the display frame selected from the plurality of display frames may be the set display frame.
  • VS21 can represent the gray scale corresponding to the first sub-compensation voltage in the display frame F1
  • VA21 can represent the maximum value corresponding to the data voltage input to the sub-pixel in the display frame F1.
  • Gray scale VA12 may represent the minimum gray scale corresponding to the data voltage input to the sub-pixel in the display frame F1.
  • the rest of the working process of the display panel driving method corresponding to this embodiment may be basically the same as the rest of the working process of the display panel driving method in the above-mentioned embodiment, and will not be repeated here.
  • Embodiments of the present disclosure provide still some driving methods of the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • applying the compensation voltage to each data line may include: selecting a display frame from a plurality of display frames in the blank time period of setting the display frame, and for each data line, the data The data voltage of the selected display frame is input into the display panel by the line loading, and the data voltage corresponding to the grayscale voltage of a row of sub-pixels in the display panel.
  • the display frame selected from the plurality of display frames may be a previous display frame adjacent to the set display frame.
  • the display frame selected from the plurality of display frames may be the set display frame.
  • applying the compensation voltage to each data line may include: selecting a display frame from a plurality of display frames in the blank time period of setting the display frame, and for each data line, Loading the selected display frame and inputting the data voltage of the first row of sub-pixels in the display panel corresponding to the grayscale voltage as the first sub-compensation voltage.
  • selecting a display frame from a plurality of display frames in the blank time period of setting the display frame and for each data line, Loading the selected display frame and inputting the data voltage of the first row of sub-pixels in the display panel corresponding to the grayscale voltage as the first sub-compensation voltage.
  • the data voltage input by the subpixels in the first row of the first subpixel column in the display frame F1 corresponds to 120 gray scales
  • the data voltage electrically connected to the first subpixel column A voltage corresponding to gray scale 120 is applied to the line as the first sub-compensation voltage, and the polarity corresponding to the voltage of gray scale 120 is opposite to that corresponding to the first sub-pixel column in the display frame F2.
  • the data voltage input by the sub-pixels in the first row of the second sub-pixel column in the display frame F1 corresponds to a gray scale of 220, then in the blank time period of the display frame F2, the data line electrically connected to the second sub-pixel column is loaded corresponding to 220
  • the grayscale voltage is used as the first sub-compensation voltage, and the polarity corresponding to the 220 grayscale voltage is opposite to the polarity corresponding to the second subpixel column in the display frame F2.
  • the data line corresponding to the third sub-pixel column is loaded with the first sub-compensation voltage in the same manner as the data line corresponding to the first sub-pixel column is loaded with the first sub-compensation voltage.
  • the manner in which the data line corresponding to the fourth sub-pixel column is loaded with the first sub-compensation voltage is the same as the manner in which the data line corresponding to the second sub-pixel column is loaded with the first sub-compensation voltage, which will not be repeated here.
  • applying the compensation voltage to each data line may include: selecting a display frame from a plurality of display frames in the blank time period of setting the display frame, and for each data line, Loading the selected display frame and inputting the data voltage of the middle row of sub-pixels in the display panel corresponds to the gray scale voltage as the first sub-compensation voltage.
  • selecting a display frame from a plurality of display frames in the blank time period of setting the display frame and for each data line, Loading the selected display frame and inputting the data voltage of the middle row of sub-pixels in the display panel corresponds to the gray scale voltage as the first sub-compensation voltage.
  • the gray scale corresponding to the data voltage input by the sub-pixel in the third row in the display frame F1 is selected as the gray scale corresponding to the first sub-compensation voltage input by the data line electrically connected to the sub-pixel.
  • the data voltage input by the sub-pixels in the third row and the first column in the display frame F1 corresponds to 120 gray scales, then in the blank time period in the display frame F2, the data voltage corresponding to the 120 gray scales is applied to the data lines electrically connected to the sub-pixels in the first column.
  • the voltage is used as the first sub-compensation voltage, and the polarity corresponding to the 120-gray-scale voltage is opposite to the polarity corresponding to the sub-pixels in the third row and first column in the display frame F2.
  • the data voltage input by the sub-pixels in the third row and the second column in the display frame F1 corresponds to 220 gray scales, then in the blank time period in the display frame F2, the voltage corresponding to the 220 gray scales is applied to the data lines electrically connected to the sub-pixels in the second column as The first sub-compensation voltage, and the polarity corresponding to the 220-gray-scale voltage is opposite to the polarity corresponding to the sub-pixels in the third row and second column in the display frame F2.
  • the data voltage input by the sub-pixels in the third row and third column in the display frame F1 corresponds to 150 gray scales, then in the blank time period in the display frame F2, a voltage corresponding to 150 gray scales is applied to the data lines electrically connected to the sub-pixels in the third column as The first sub-compensation voltage, and the polarity corresponding to the 150-gray-scale voltage is the same as the polarity corresponding to the sub-pixel in the third row and third column in the display frame F2.
  • the data voltage input by the sub-pixels in the third row and the fourth column in the display frame F1 corresponds to 60 gray scales, then in the blank time period in the display frame F2, the voltage corresponding to the 60 gray scales is applied to the data line electrically connected to the sub-pixels in the fourth column as The first sub-compensation voltage, and the polarity corresponding to the 60-gray-scale voltage is opposite to the polarity corresponding to the sub-pixels in the third row and fourth column in the display frame F2.
  • applying the compensation voltage to each data line may include: selecting a display frame from a plurality of display frames in the blank time period of setting the display frame, and for each data line, Loading the selected display frame and inputting the data voltage of the last row of sub-pixels in the display panel corresponds to the gray scale voltage as the first sub-compensation voltage.
  • selecting a display frame from a plurality of display frames in the blank time period of setting the display frame and for each data line, Loading the selected display frame and inputting the data voltage of the last row of sub-pixels in the display panel corresponds to the gray scale voltage as the first sub-compensation voltage.
  • the gray scale corresponding to the data voltage input by the sub-pixel in the fourth row in the display frame F1 is selected as the gray scale corresponding to the compensation voltage input by the data line electrically connected to the sub-pixel.
  • the data voltage input by the sub-pixels in the fourth row and the first column in the display frame F1 corresponds to 120 gray scales, then in the blank time period in the display frame F2, the data voltage corresponding to the 120 gray scales is applied to the data lines electrically connected to the sub-pixels in the first column.
  • the voltage is used as the first sub-compensation voltage, and the polarity corresponding to the 120-gray-scale voltage is the same as the polarity corresponding to the sub-pixel in the fourth row and the first column in the display frame F2.
  • the data voltage input by the sub-pixels in the fourth row and the second column in the display frame F1 corresponds to 220 gray scales, then in the blank time period in the display frame F2, the voltage corresponding to the 220 gray scales is applied to the data lines electrically connected to the sub-pixels in the second column as The first sub-compensation voltage, and the polarity corresponding to the 220-gray-scale voltage is the same as the polarity corresponding to the sub-pixel in the fourth row and second column in the display frame F2.
  • the data voltage input by the sub-pixels in the fourth row and third column in the display frame F1 corresponds to 150 gray scales, then in the blank time period in the display frame F2, a voltage corresponding to 150 gray scales is applied to the data lines electrically connected to the sub-pixels in the third column as The first sub-compensation voltage, and the polarity corresponding to the voltage of 150 gray scales is the same as the polarity corresponding to the sub-pixels in the fourth row and third column in the display frame F2.
  • the data voltage input by the sub-pixels in the fourth row and the fourth column in the display frame F1 corresponds to 60 gray scales, then in the blank time period in the display frame F2, the voltage corresponding to the 60 gray scales is applied to the data lines electrically connected to the sub-pixels in the fourth column as The first sub-compensation voltage, and the polarity corresponding to the 60-gray-scale voltage is the same as the polarity corresponding to the sub-pixels in the fourth row and fourth column in the display frame F2.
  • the rest of the working process of the display panel driving method corresponding to this embodiment may be basically the same as the rest of the working process of the display panel driving method in the above-mentioned embodiment, and will not be repeated here.
  • Embodiments of the present disclosure provide still some driving methods of the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • applying the compensation voltage to each data line may include: selecting a display frame from a plurality of display frames in the blank time period of setting the display frame, and for each data line, The data voltage corresponding to the gray scale voltage on the input data line of the selected display frame is sequentially loaded. In this way, the selection of the compensation voltage can be more diversified, and the compensation can be made more detailed.
  • the display frame selected from the plurality of display frames may be a previous display frame adjacent to the set display frame.
  • the display frame F2 select the gray scale corresponding to the data voltage input by the sub-pixels in the first row to the fourth row in the display frame F1, as the gray scale corresponding to the compensation voltage input by the data line electrically connected to the sub-pixel .
  • the data voltage input to the sub-pixels in the first row and the first column corresponds to gray scale 120
  • the data voltage input to the sub-pixels in the second row and the first column corresponds to gray scale 150
  • the data voltage input to the sub-pixels in the third row and the first column corresponds to gray scale 120.
  • 60 gray scale the data voltage input by the sub-pixels in the fourth row and the first column corresponds to the 220 gray scale
  • the compensation stage in the display frame F2 the data lines electrically connected to the sub-pixels in the first column sequentially input the first data voltage corresponding to the 120 gray scale.
  • the sub-compensation voltage corresponds to the first sub-compensation voltage of grayscale 150, the first sub-compensation voltage corresponding to grayscale 60, and the first sub-compensation voltage of grayscale 220, and displays the sub-pixels electrically connected to the first column in frame F2
  • the polarity corresponding to the first sub-compensation voltage input by the data line is opposite to the polarity corresponding to the data voltage input to the first column of sub-pixels in the display frame F2, for example, both are positive polarity.
  • the data voltage input by the sub-pixels in the first row and the second column corresponds to 127 gray levels
  • the data voltage input by the sub-pixels in the second row and the second column corresponds to 159 gray levels
  • the data voltage input by the sub-pixels in the third row and the second column corresponds to 160 gray levels
  • the data voltage input by the sub-pixels in the fourth row and the second column corresponds to 68 gray scales
  • the data lines electrically connected to the sub-pixels in the second column are sequentially input with the first sub-compensation voltage corresponding to 127 gray scales voltage, corresponding to the first sub-compensation voltage of gray scale 159, the first sub-compensation voltage corresponding to gray scale 160, and the first sub-compensation voltage of gray scale 68, and displaying the data lines electrically connected to the sub-pixels in the second column in frame F2
  • the polarity corresponding to the input first sub-compensation voltage is opposite to the polarity corresponding
  • the data voltage input by the sub-pixels in the first row and the third column corresponds to 140 gray levels
  • the data voltage input by the sub-pixels in the second row and the third column corresponds to 130 gray levels
  • the data voltage input by the sub-pixels in the third row and the third column corresponds to 40 gray levels
  • the data voltage input by the sub-pixels in the fourth row and the third column corresponds to gray scale 175, then in the compensation stage in the display frame F2, the data lines electrically connected to the sub-pixels in the third column sequentially input the first sub-compensation voltage corresponding to gray scale 140 voltage, corresponding to the first sub-compensation voltage of gray scale 130, the first sub-compensation voltage corresponding to gray scale 40, and the first sub-compensation voltage of gray scale 175, and displaying the data line electrically connected to the third column of sub-pixels in frame F2
  • the polarity corresponding to the input first sub-compensation voltage is opposite to the polarity corresponding to the data voltage input to the sub-pixels
  • the data voltage input by the sub-pixels in the first row and fourth column corresponds to 177 gray levels
  • the data voltage input by the sub-pixels in the second row and fourth column corresponds to 129 gray levels
  • the data voltage input by the sub-pixels in the third row and fourth column corresponds to 80 gray levels.
  • the data voltage input by the sub-pixels in the fourth row and the fourth column corresponds to 198 gray scales, then in the compensation stage in the display frame F2, the data lines electrically connected to the sub-pixels in the fourth column are sequentially input with the first sub-compensation voltage corresponding to the 177 gray scales
  • the voltage corresponds to the first sub-compensation voltage of gray scale 129, the first sub-compensation voltage corresponding to gray scale 80, and the first sub-compensation voltage of gray scale 198, and displays the data line electrically connected to the fourth column of sub-pixels in frame F2
  • the polarity corresponding to the input first sub-compensation voltage is opposite to the polarity corresponding to the data voltage input to the sub-pixels in the fourth column in the display frame F2, for example, both are negative polarity.
  • the display frame selected from the plurality of display frames may be the set display frame.
  • the display frame F2 taking a display panel with a total of four rows of sub-pixels as an example (of course, in practical applications, the number of sub-pixel rows of a display panel is not only four, which can be determined according to actual conditions, and is not limited here), in combination with FIG. 4a to In Fig. 8, in the display frame F2, the gray scale corresponding to the data voltage input by the sub-pixels in the first row to the fourth row in the display frame F2 is selected, as the first sub-compensation voltage input by the data line electrically connected to the sub-pixel corresponding to gray scale.
  • the data voltage input by the sub-pixels in the first row and the first column corresponds to gray scale 120
  • the data voltage input by the sub-pixels in the second row and the first column corresponds to gray scale 150
  • the data voltage input by the sub-pixels in the third row and the first column corresponds to gray scale 120.
  • 60 gray scale the data voltage input by the sub-pixels in the fourth row and the first column corresponds to the 220 gray scale
  • the compensation stage in the display frame F2 the data lines electrically connected to the sub-pixels in the first column sequentially input the first data voltage corresponding to the 120 gray scale.
  • the sub-compensation voltage corresponds to the first sub-compensation voltage of grayscale 150, the first sub-compensation voltage corresponding to grayscale 60, and the first sub-compensation voltage of grayscale 220, and displays the sub-pixels electrically connected to the first column in frame F2
  • the polarity corresponding to the first sub-compensation voltage input by the data line is opposite to the polarity corresponding to the data voltage input to the first column of sub-pixels in the display frame F2, for example, both are positive polarity.
  • the data voltage input by the sub-pixels in the first row and the second column corresponds to 127 gray levels
  • the data voltage input by the sub-pixels in the second row and the second column corresponds to 159 gray levels
  • the data voltage input by the sub-pixels in the third row and the second column corresponds to 160 gray levels
  • the data voltage input by the sub-pixels in the fourth row and the second column corresponds to 68 gray scales
  • the data lines electrically connected to the sub-pixels in the second column are sequentially input with the first sub-compensation voltage corresponding to 127 gray scales voltage, corresponding to the first sub-compensation voltage of gray scale 159, the first sub-compensation voltage corresponding to gray scale 160, and the first sub-compensation voltage of gray scale 68, and displaying the data lines electrically connected to the sub-pixels in the second column in frame F2
  • the polarity corresponding to the input first sub-compensation voltage is opposite to the polarity corresponding
  • the data voltage input by the sub-pixels in the first row and the third column corresponds to 140 gray levels
  • the data voltage input by the sub-pixels in the second row and the third column corresponds to 130 gray levels
  • the data voltage input by the sub-pixels in the third row and the third column corresponds to 40 gray levels
  • the data voltage input by the sub-pixels in the fourth row and the third column corresponds to gray scale 175, then in the compensation stage in the display frame F2, the data lines electrically connected to the sub-pixels in the third column sequentially input the first sub-compensation voltage corresponding to gray scale 140 voltage, corresponding to the first sub-compensation voltage of gray scale 130, the first sub-compensation voltage corresponding to gray scale 40, and the first sub-compensation voltage of gray scale 175, and displaying the data line electrically connected to the third column of sub-pixels in frame F2
  • the polarity corresponding to the input first sub-compensation voltage is opposite to the polarity corresponding to the data voltage input to the sub-pixels
  • the data voltage input by the sub-pixels in the first row and fourth column corresponds to 177 gray levels
  • the data voltage input by the sub-pixels in the second row and fourth column corresponds to 129 gray levels
  • the data voltage input by the sub-pixels in the third row and fourth column corresponds to 80 gray levels
  • the data voltage input by the sub-pixels in the fourth row and the fourth column corresponds to 198 gray scales
  • the data lines electrically connected to the sub-pixels in the fourth column are sequentially input with the first sub-compensation voltage corresponding to the 177 gray scales
  • the voltage corresponds to the first sub-compensation voltage of gray scale 129, the first sub-compensation voltage corresponding to gray scale 80, and the first sub-compensation voltage of gray scale 198, and displays the data line electrically connected to the fourth column of sub-pixels in frame F2
  • the polarity corresponding to the input first sub-compensation voltage is opposite to the polarity corresponding to the data voltage
  • Embodiments of the present disclosure provide still some driving methods of the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • part of the display frames in the multiple consecutive display frames are set display frames. Furthermore, among the plurality of consecutive display frames, the display frames other than the set display frame are non-set display frames. That is to say, part of the display frames in the plurality of consecutive display frames are set display frames, and the rest of the display frames are non-set display frames.
  • non-set display frames include:
  • the gate-on voltage is applied to the gate lines in the display panel in time division, and the data voltage of the image to be displayed is applied to each data line when the gate-on voltage is applied to each gate line, so that each sub-pixel inputs a corresponding the data voltage;
  • the gate-off voltage is simultaneously applied to the gate lines in the display panel, and each data line is floated.
  • each data line in the blank time period may mean that no voltage is applied to each data line.
  • the working process of the data refreshing stage in the non-set display frame is basically the same as the working process of the data refreshing stage in the set display frame.
  • no compensation phase is set in the blank time phase in the non-set display frame.
  • two non-setting display frames between two adjacent setting display frames It is also possible to have three non-setting display frames between two adjacent setting display frames.
  • display frame F1 , display frame F3 , and display frame F5 are set display frames
  • display frame F2 and display frame F4 are non-set display frames.
  • the number of non-set display frames between every two adjacent set display frames may be the same.
  • two non-set display frames between every two adjacent set display frames It is also possible to have three non-setting display frames between every two adjacent setting display frames.
  • display frame F1 , display frame F3 , and display frame F5 are set display frames
  • display frame F2 and display frame F4 are non-set display frames.
  • Embodiments of the present disclosure provide still some driving methods of the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the compensation voltage may include a second sub-compensation voltage; for each data line, the polarity corresponding to the second sub-compensation voltage applied on the data line is the same as the polarity corresponding to the sub-pixel connected to the data line. Sex is the same.
  • the first sub-pixel column corresponds to positive polarity
  • the polarity corresponding to the second sub-compensation voltage Vdc31-1 that can be applied to the data line corresponding to the first sub-pixel column is positive
  • a voltage from 8V to 12V can be selected and applied to the data line.
  • the second sub-pixel column corresponds to negative polarity, then the polarity corresponding to the second sub-compensation voltage that can be applied to the data line corresponding to the second sub-pixel column is negative polarity, for example, a voltage can be selected from 4V to 8V to apply to the data line superior.
  • the third sub-pixel column corresponds to positive polarity, then the polarity corresponding to the second sub-compensation voltage that can be applied to the data line corresponding to the third sub-pixel column is positive polarity, for example, a voltage can be selected from 8V to 12V to apply to the data line superior.
  • the fourth sub-pixel column corresponds to negative polarity
  • the polarity corresponding to the second sub-compensation voltage that can be applied to the data line corresponding to the fourth sub-pixel column is negative polarity, for example, a voltage can be selected from 4V to 8V to apply to the data line superior.
  • the first sub-pixel column corresponds to negative polarity
  • the polarity corresponding to the second sub-compensation voltage Vdc31-2 that can be applied to the data line corresponding to the first sub-pixel column is negative polarity
  • a voltage selected from 4V-8V can be applied to the data line.
  • the second sub-pixel column corresponds to positive polarity
  • the polarity corresponding to the second sub-compensation voltage that can be applied to the data line corresponding to the second sub-pixel column is positive polarity, for example, a voltage can be selected from 8V to 12V to apply to the data line superior.
  • the third sub-pixel column corresponds to negative polarity, then the polarity corresponding to the second sub-compensation voltage that can be applied to the data line corresponding to the third sub-pixel column is negative polarity, for example, a voltage can be selected from 4V to 8V to apply to the data line superior.
  • the fourth sub-pixel column corresponds to positive polarity, then the polarity corresponding to the second sub-compensation voltage that can be applied to the data line corresponding to the fourth sub-pixel column is positive polarity, for example, a voltage can be selected from 8V to 12V to apply to the data line superior.
  • Embodiments of the present disclosure provide still some driving methods of the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the display frequency when the display frequency is switched from a higher frequency H1 (for example, 120 Hz) to a lower frequency H2 (for example, 60 Hz, 30 Hz, 48 Hz), only the lower frequency H2 can be used on the display , use the driving method in the embodiment of the present disclosure to drive the display panel to display.
  • H1 for example, 120 Hz
  • H2 for example, 60 Hz, 30 Hz, 48 Hz
  • the maintenance duration of the blank time period TB of the display frames F1-F5 is shorter than the maintenance duration of the blank time period TB of the display frames F6-F10
  • the display frames F1-F5 can be used as the first frame
  • the display frames F6-F10 can be used as the second frame. frame.
  • the data lines are floating in the blank time period TB.
  • the display is switched from 120 Hz to 48 Hz, and the display frequency is refreshed at 48 Hz, in the blank time period TB in each display frame (for example, display frames F6-F10), a gate-off voltage is applied to the grid lines in the display panel, And a compensation voltage is applied to each data line. In this way, the brightness of the picture displayed at low frequency is increased compared with the picture displayed at high frequency, the brightness is kept stable, and the display quality and viewing experience are improved.
  • the driving method in the embodiment of the present disclosure is used to drive the display panel to display at both the higher frequency H1 and the lower frequency H2.
  • the maintenance duration of the blank time period TB of the display frames F1-F5 is shorter than the maintenance duration of the blank time period TB of the display frames F6-F10
  • the display frames F1-F5 can be used as the first frame
  • the display frames F6-F10 can be used as the second frame. frame.
  • each display frame for example, display frames F1 to F5
  • apply a gate-off voltage to the gate lines in the display panel and apply a compensation voltage to each data line , that is, display frames F1 to F5 are all refreshed at a display frequency of 120 Hz, and a compensation voltage is applied to each data line.
  • each display frame for example, display frames F6-F10
  • apply a gate-off voltage to the grid lines in the display panel and A compensation voltage is applied to each data line, that is, display frames F6 to F10 are refreshed at a display frequency of 48 Hz, and a compensation voltage is applied to each data line.
  • the compensation voltage can be applied to the data line in the blank time period, so that compensation is not performed by additionally distinguishing display frequencies. That is, different display frequencies can be uniformly compensated.
  • the TCON timing is easier to adjust, the TCON timing design is simplified, and the power consumption is reduced.
  • the reason for the abnormal display is the leakage of electricity in the blank time period and the insufficient charging of the high refresh rate.
  • the display tends to have a high refresh rate, such as 144HZ, 240Hz, etc.
  • the higher the refresh rate the lower the charging rate, resulting in a decrease in the brightness of the display panel.
  • Insufficient charging rate at the refresh rate dominates, resulting in lower display brightness at high refresh rate than at low refresh rate. In this way, when the refresh rate is switched, the display will have a difference in brightness and darkness, and the display will be abnormal.
  • a compensation voltage with opposite polarity to that of the data signal can be loaded at both high and low frequencies.
  • the blank time period at high refresh rates is shorter than that at low refresh rates.
  • the compensation voltage can only be applied to the display frame at a low refresh rate, and the blank time period is maintained at a high refresh rate. For example, only 0 grayscale voltage is given at this stage, and the brightness at the refresh rate is reduced to match. Brightness with high refresh rate achieves good display uniformity.
  • Embodiments of the present disclosure provide still some driving methods of the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the compensation voltage loaded on the data line may also be higher than the data voltage in the sub-pixels connected to the data line.
  • the compensation voltage loaded on the data line may also be lower than the data voltage in the sub-pixels connected to the data line. In this way, the voltage difference between the source and the drain of the transistor in the sub-pixel can be reduced during the blanking time, and the leakage of the transistor can be reduced.
  • the input data voltage in the sub-pixel can be kept stable, thereby avoiding the problem that the brightness of the display screen decreases when the display is continuously at a low display frequency.
  • An embodiment of the present disclosure also provides a display driving circuit, wherein the display panel works in a plurality of consecutive display frames, and each display frame includes a data refresh phase and a blank time phase; and the display driving circuit is configured to:
  • a gate-on voltage is applied to the gate lines in the display panel, and the data voltage of the image to be displayed is applied to each data line, so that each sub-pixel input corresponding data voltage;
  • a gate-off voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each data line; wherein, the data voltage in the sub-pixel connected to the data line is greater than the common electrode voltage
  • the compensation voltage loaded on the data line is lower than the data voltage in the sub-pixel connected to the data line; when the data voltage in the sub-pixel connected to the data line is lower than the common electrode voltage, the compensation voltage loaded on the data line is greater than the Data voltage in the subpixel.
  • the working principle and specific implementation of the display driving circuit are the same as those of the driving method of the display panel in the above-mentioned embodiment. Therefore, the working method of the display driving circuit can refer to the description of the display panel in the above-mentioned embodiment The specific implementation manner of the driving method is implemented, and details are not repeated here.
  • An embodiment of the present disclosure also provides a display device, as shown in FIG. 13 , including a display panel 100 and a timing controller (Timing Control-ller, TCON) 200; the display panel 100 includes a plurality of gate lines GA1-GA5, a plurality of Data lines DA1-DA6, source drive circuit 110 and gate drive circuit 120; wherein, source drive circuit 110 is coupled to multiple data lines DA1-DA6; gate drive circuit 120 is coupled to multiple gate lines GA1-GA5 catch.
  • TCON Timing Control-ller
  • the timing controller 200 is coupled to the source driving circuit 110 and the gate driving circuit 120 respectively.
  • the timing controller 200 is configured to input the first gate driving signal to the gate driving circuit 120 and the first source pole drive signal.
  • the gate driving circuit 120 is configured to apply a gate turn-on voltage to the gate lines GA1 - GA5 in the display panel 100 according to receiving the first gate driving signal.
  • the source driving circuit 110 is configured to load the data lines DA1 - DA6 with the data voltage of the image to be displayed according to receiving the first source driving signal, so as to realize the screen display of one display frame.
  • the timing controller 200 is configured to input a second gate driving signal to the gate driving circuit 120 and a second source driving signal to the source driving circuit 110 during at least one blank time period of a display frame.
  • the gate driving circuit 120 is configured to apply a gate-off voltage to the gate lines GA1 - GA5 in the display panel according to the received second gate driving signal.
  • the source driving circuit 110 is configured to apply a compensation voltage to each of the data lines DA1 - DA6 according to receiving the second source driving signal.
  • the compensation voltage loaded on the data line when the data voltage in the sub-pixel connected with the data line is greater than the common electrode voltage, the compensation voltage loaded on the data line is lower than the data voltage in the sub-pixel connected with the data line; the data voltage in the sub-pixel connected with the data line is less than When the voltage of the common electrode is lower than the common electrode voltage, the compensation voltage loaded on the data line is greater than the data voltage in the sub-pixels connected to the data line.
  • the working principle and specific implementation of the display device are the same as those of the driving method of the display panel in the above-mentioned embodiment. Therefore, the working method of the display device can refer to the driving method of the display panel in the above-mentioned embodiment.
  • the specific implementation manners are implemented, and details are not repeated here.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.
  • the gate lines in the display panel are time-divisionally loaded with gates in the data refresh phase of the set display frame in a plurality of consecutive display frames.
  • the gate-on voltage is applied to each gate line
  • the data voltage of the image to be displayed is applied to each data line, so that each sub-pixel inputs the corresponding data voltage, so as to realize the screen display of one display frame.
  • the gate-off voltage is simultaneously applied to the gate lines in the display panel, and the compensation voltage is applied to each data line. This can reduce the voltage difference between the source and the drain of the transistor in the blank time period, thereby reducing the leakage of the sub-pixel and improving the display quality and viewing experience.
  • the embodiments of the present invention may be provided as methods, systems, or computer program products. Accordingly, the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

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Abstract

一种显示面板的驱动方法、显示驱动电路及显示装置。显示面板的驱动方法，包括：在连续的多个显示帧中的至少一个显示帧的数据刷新阶段内，对显示面板中的栅线加载栅极开启电压，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压（S100）；在至少一个显示帧的空白时间阶段内，对显示面板中的栅线加载栅极关闭电压，并对各数据线加载补偿电压（S200）。在数据线连接的子像素中的数据电压大于公共电极电压时，数据线上加载的补偿电压小于数据线连接的子像素中的数据电压；和/或在数据线连接的子像素中的数据电压小于公共电极电压时，数据线上加载的补偿电压大于数据线连接的子像素中的数据电压。

Description

显示面板的驱动方法、显示驱动电路及显示装置 技术领域
本公开涉及显示技术领域，特别涉及显示面板的驱动方法、显示驱动电路及显示装置。
背景技术
在诸如液晶显示器(Liquid Crystal Display，LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器中，一般包括多个像素。每个像素可以包括：红色子像素、绿色子像素以及蓝色子像素。通过控制每个子像素对应的显示数据，以控制每个子像素的显示亮度，从而混合出所需显示的色彩来显示彩色图像。
发明内容
本公开实施例提供的显示面板的驱动方法，所述显示面板工作于连续的多个显示帧，每个显示帧包括数据刷新阶段和空白时间阶段；
所述显示面板的驱动方法，包括：
在连续的多个显示帧中的至少一个所述显示帧的数据刷新阶段内，对所述显示面板中的栅线加载栅极开启电压，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；
在至少一个所述显示帧的空白时间阶段内，对所述显示面板中的栅线加载栅极关闭电压，并对各所述数据线加载补偿电压；
其中，在所述数据线连接的子像素中的数据电压大于公共电极电压时，所述数据线上加载的补偿电压小于所述数据线连接的子像素中的数据电压；
和/或，在所述数据线连接的子像素中的数据电压小于公共电极电压时，所述数据线上加载的补偿电压大于所述数据线连接的子像素中的数据电压。
在一些示例中，在至少一个所述显示帧的空白时间阶段内，全部加载所 述补偿电压。
在一些示例中，所述显示面板采用列反转方式或帧反转方式；所述补偿电压包括第一子补偿电压；
针对每一条所述数据线，在所述数据线上加载的第一子补偿电压对应的极性与所述数据线连接的子像素对应的极性相反。
在一些示例中，在空白时间阶段内对各所述数据线加载所述补偿电压的显示帧中，具有第一显示帧和第二显示帧；
所述第一显示帧对应第一刷新频率，所述第二显示帧对应第二刷新频率；并且所述第一刷新频率大于所述第二刷新频率；
所述第一显示帧中空白时间阶段的维持时长小于所述第二显示帧中空白时间阶段的维持时长。
在一些示例中，将在空白时间阶段内对各所述数据线加载所述补偿电压的显示帧定义为设定显示帧；相邻的两个设定显示帧中，针对同一条数据线，在上一个设定显示帧中加载于所述数据线的第一子补偿电压与所述公共电极电压之间具有第一差值，在下一个设定显示帧中加载于所述数据线的第一子补偿电压与所述公共电极电压之间具有第二差值；
所述第一差值的绝对值等于所述第二差值的绝对值。
在一些示例中，所述补偿电压还包括在所述第一子补偿电压之前出现的过渡补偿电压；
针对每一条所述数据线，在所述数据线上加载的过渡补偿电压对应的极性与所述数据线连接的子像素对应的极性相同。
在一些示例中，所述显示面板采用列反转方式或帧反转方式；所述补偿电压包括第二子补偿电压；
针对每一条所述数据线，在所述数据线上加载的第二子补偿电压对应的极性与所述数据线连接的子像素中的数据电压对应的极性相同。
在一些示例中，将在空白时间阶段内对各所述数据线加载所述补偿电压的显示帧定义为设定显示帧；
所述连续多个显示帧中的部分显示帧为所述设定显示帧；
所述连续多个显示帧中，除所述设定显示帧之外的显示帧为非设定显示帧；
所述非设定显示帧包括：
数据刷新阶段，对所述显示面板中的栅线加载栅极开启电压，对数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；
空白时间阶段，对所述显示面板中的栅线加载栅极关闭电压，并使各所述数据线浮接。
在一些示例中，相邻的两个所述设定显示帧之间具有至少一个所述非设定显示帧。
在一些示例中，每相邻的两个所述设定显示帧之间具有的所述非设定显示帧的数量相同。
在一些示例中，各所述数据线加载的所述补偿电压对应的灰阶相同。
在一些示例中，针对每一条所述数据线，所述数据线上加载的所述补偿电压对应的灰阶与所述数据线连接的子像素中的一个数据电压对应的灰阶相同。
在一些示例中，采用如下公式，确定所述补偿电压对应的灰阶；
VS11＝(VA12+VA12)/2；
其中，VS11代表所述补偿电压对应的灰阶，VA11代表从所述连续的多个显示帧中选取的一个显示帧中的最大灰阶，VA12代表从所述连续的多个显示帧中选取的所述显示帧中最小灰阶，且VA11+VA12为偶数。
在一些示例中，采用如下公式，确定所述补偿电压对应的灰阶；
VS21＝(VA21+VA22+1)/2；
其中，VS21代表所述补偿电压对应的灰阶，VA21代表从所述连续的多个显示帧中选取的一个显示帧中的最大灰阶，VA22代表从所述连续的多个显示帧中选取的所述显示帧中最小灰阶，且VA21+VA22为奇数。
在一些示例中，所述对各所述数据线加载补偿电压，包括：
在所述设定显示帧的空白时间阶段中，从所述多个显示帧中选取一个显示帧，并针对每一条所述数据线，对所述数据线加载选取的所述显示帧输入所述显示面板内一行子像素的数据电压对应灰阶的电压。
在一些示例中，所述对各所述数据线加载补偿电压，包括：
在所述设定显示帧的空白时间阶段中，从所述多个显示帧中选取一个显示帧，并针对每一条所述数据线，对所述数据线加载选取的所述显示帧输入所述显示面板内最后一行子像素的数据电压对应灰阶的电压。
在一些示例中，所述对各所述数据线加载补偿电压，包括：
在所述设定显示帧的空白时间阶段中，从所述多个显示帧中选取一个显示帧，并针对每一条所述数据线，对所述数据线依次加载选取的所述显示帧输入所述数据线上的数据电压对应灰阶的电压。
在一些示例中，从所述多个显示帧中选取的所述显示帧为所述设定显示帧相邻的上一个显示帧和所述设定显示帧中的一个。
本公开实施例提供的显示驱动电路，所述显示面板工作于连续的多个显示帧，每个显示帧包括数据刷新阶段和空白时间阶段；
所述显示驱动电路被配置为：
在连续的多个显示帧中的至少一个所述显示帧的数据刷新阶段内，对所述显示面板中的栅线加载栅极开启电压，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；
在至少一个所述显示帧的空白时间阶段内，对所述显示面板中的栅线加载栅极关闭电压，并对各所述数据线加载补偿电压；
其中，在所述数据线连接的子像素中的数据电压大于公共电极电压时，所述数据线上加载的补偿电压小于所述数据线连接的子像素中的数据电压；
在所述数据线连接的子像素中的数据电压小于公共电极电压时，所述数据线上加载的补偿电压大于所述数据线连接的子像素中的数据电压。
本公开实施例提供的显示装置，包括显示面板以及时序控制器；所述显示面板包括多条栅线、多条数据线、源极驱动电路以及栅极驱动电路；其中， 所述源极驱动电路与所述多条数据线耦接；所述栅极驱动电路与所述多条栅线耦接；
所述时序控制器与所述源极驱动电路以及所述栅极驱动电路耦接；
所述时序控制器被配置为在连续的多个显示帧中的至少一个所述显示帧的数据刷新阶段内，对所述栅极驱动电路输入第一栅极驱动信号，对所述源极驱动电路输入第一源极驱动信号；以及在至少一个所述显示帧的空白时间阶段内，对所述栅极驱动电路输入第二栅极驱动信号，对所述源极驱动电路输入第二源极驱动信号；
所述栅极驱动电路被配置为根据接收到所述第一栅极驱动信号，对所述显示面板中的栅线加载栅极开启电压；以及根据接收到的所述第二栅极驱动信号，对所述显示面板中的栅线加载栅极关闭电压；
所述源极驱动电路被配置为根据接收到所述第一源极驱动信号，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；以及根据接收到所述第二源极驱动信号，对各所述数据线加载补偿电压。
附图说明
图1a为本公开实施例中的显示面板的结构示意图；
图1b为本公开实施例中的公共电极电压和数据电压的示意图；
图2为相关公开实施例中的信号时序图；
图3为本公开实施例中的显示面板的驱动方法的流程图；
图4a为本公开实施例中的相邻两个显示帧中上一个显示帧对应的显示面板中各子像素的极性的一些示意图；
图4b为本公开实施例中的相邻两个显示帧中下一个显示帧对应的显示面板中各子像素的极性的一些示意图；
图4c为本公开实施例中的相邻两个显示帧中上一个显示帧对应的显示面板中各子像素的极性的另一些示意图；
图4d为本公开实施例中的相邻两个显示帧中下一个显示帧对应的显示面 板中各子像素的极性的另一些示意图；
图5为本公开实施例中的一些信号时序图；
图6为本公开实施例中的另一些信号时序图；
图7为本公开实施例中的又一些信号时序图；
图8为本公开实施例中的又一些信号时序图；
图9为本公开实施例中的又一些信号时序图；
图10为本公开实施例中的又一些信号时序图；
图11为本公开实施例中的又一些信号时序图；
图12为本公开实施例中的又一些信号时序图；
图13为本公开实施例中的显示装置的一些结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元 件或具有相同或类似功能的元件。
目前的显示器频率一般为60HZ，即每秒内显示器的画面刷新60次，使人眼看到的画面是动态流畅的。而在某些应用场景下，为了节省显示器的功耗，需要显示器降频显示，例如：从60HZ降为30HZ。在另外一些场景下，例如：执行高频游戏时，需要提高显示器的频率，例如：从60HZ上升为90HZ或120HZ，从而使画面更为流畅。因此，为了适用于不同的场景，显示器需要变换显示频率，即动态帧频显示。
参见图1a，显示器可以包括多个阵列排布的像素，多条栅线(例如，GA1、GA2、GA3、GA4)以及多条数据线(例如，DA1、DA2、DA3)。每个像素包括多个子像素。示例性地，像素可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
参见图1a和图2，每个子像素中包括晶体管01和像素电极02。其中，一行子像素对应一条栅线，一列子像素对应一条数据线。晶体管01的栅极与对应的栅线电连接，晶体管01的源极与对应的数据线电连接，晶体管01的漏极与像素电极02电连接，需要说明的是，本发明像素阵列结构还可以是双栅结构，即相邻两行像素之间设置两条栅极线，此排布方式可以减少一半的数据线，即包含相邻两列像素之间有的数据线，有的相邻两列像素之间不包括数据线，具体像素排布结构和数据线，扫描线的排布方式不限定。并且，显示器的一个显示帧F0可以包括数据刷新阶段TS和空白时间(Blanking Time)阶段TB。在数据刷新阶段TS，对栅线GA1加载信号ga1，对栅线GA2加载信号ga2，对栅线GA3加载信号ga3，对栅线GA4加载信号ga4，在信号ga1～ga4中出现栅极开启电压(例如高电平对应的电压)时，可以控制对应的晶体管010导通。并且，在信号ga1出现栅极开启电压时，可以控制第一行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2 加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第一行子像素中的像素电极02输入对应的数据电压。在信号ga2出现栅极开启电压时，可以控制第二行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第二行子像素中的像素电极02输入对应的数据电压。在信号ga3出现栅极开启电压时，可以控制第三行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第三行子像素中的像素电极02输入对应的数据电压。在信号ga4出现栅极开启电压时，可以控制第四行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第四行子像素中的像素电极02输入对应的数据电压。其余行以此类推，在此不作赘述。
参见图1a和图2，在空白时间(Blanking Time)阶段TB中，信号ga1～ga4均为低电平，每个子像素中的晶体管01均处于截止状态。并且，数据线DA1～DA3可以不加载电压，均处于浮接状态。
在显示器的显示频率从高频变换到低频时，若显示器显示同一画面，低频时显示的画面的亮度会高于高频时显示的画面的亮度。这样由于低频时数据刷新阶段的充电率高于高频时数据刷新阶段的充电率导致的。虽然在空白时间阶段中，子像素中的晶体管具有漏电现象，但是在该情况下，晶体管的漏电现象先比充电率来说，占比重较小。为了使显示器从不同频率切换时，保持亮度稳定，避免出现切换频率时导致的显示画面异常，提高显示器的显示品质，提高观看体验。本公开实施例提供了显示面板的驱动方法，可以改善显示器的显示频率从高频变换到低频时，显示画面亮度增加的问题，保持亮度稳定，提高显示品质和观看体验。
本公开实施例提供的显示面板的驱动方法中，显示面板工作于连续的多个显示帧，每个显示帧可以包括数据刷新阶段和空白时间阶段。通过在连续 的多个显示帧中的至少一个显示帧的数据刷新阶段内，对显示面板中的栅线加载栅极开启电压，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压，从而实现一个显示帧的画面显示。并且，在至少一个显示帧的空白时间阶段内，对显示面板中的栅线加载栅极关闭电压，并对各数据线加载补偿电压。这样可以改善显示器的显示频率从高频切换到低频时，低频时显示的画面相比高频时显示的画面的亮度增加的问题，保持亮度稳定，提高显示品质和观看体验。
在本公开实施例中，将在空白时间阶段内对数据线加载补偿电压的显示帧定义为设定显示帧。本公开实施例提供的显示面板的驱动方法，如图3所示，可以包括如下步骤：
S100、在设定显示帧的数据刷新阶段内，对显示面板中的栅线加载栅极开启电压，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；
S200、在设定显示帧的空白时间阶段内，对显示面板中的栅线加载栅极关闭电压，并对各数据线加载补偿电压。
需要说明的是，本公开实施例中的显示面板可以为液晶显示面板。本公开实施例中，在连续的多个显示帧中，设计了设定显示帧，在该设定显示帧中，具有数据刷新阶段和空白时间阶段。其中，在该数据刷新阶段内，对显示面板中的栅线加载栅极开启电压，并对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压，从而实现一个显示帧的画面显示。在该空白时间阶段内，对显示面板中的栅线加载栅极关闭电压，以控制每个子像素中的晶体管均处于截止状态。并且，对各数据线加载补偿电压，在数据线连接的子像素中的数据电压大于公共电极电压时，数据线上加载的补偿电压小于数据线连接的子像素中的数据电压。结合图1a与图1b所示，Vda1-1～Vda1-4分别代表输入第一列子像素中的第一行至第四行子像素中的数据电压。Vdc1代表第一列子像素连接的数据线DA1上加载的补偿电压。若Vda1-1～Vda1-4均大于公共电极电压Vcom，Vdc1小于Vda1-1～Vda1-4，由于 子像素中晶体管的漏电，漏电流方向为由子像素流向数据线DA1，从而可以使Vda1-1～Vda1-4电压降低。例如，Vda1-1降低为Vda1-1’。这样使得Vda1-1和Vcom之间的压差ΔV1可降低为ΔV1’。由于子像素的亮度与子像素中的数据电压和公共电极电压之间的压差相关，压差降低，可以使子像素的亮度降低，因此，第一列子像素的亮度可以降低。
以及，在数据线连接的子像素中的数据电压小于公共电极电压时，数据线上加载的补偿电压大于数据线连接的子像素中的数据电压。结合图1a与图1b所示，Vda2-1～Vda2-4分别代表输入第二列子像素中的第一行至第四行子像素中的数据电压。Vdc2代表第二列子像素连接的数据线DA2上加载的补偿电压。若Vda2-1～Vda2-4均小于公共电极电压Vcom，Vdc2大于Vda1-1～Vda1-4，由于子像素中晶体管的漏电，漏电流方向为由数据线DA2流向子像素，从而可以使Vda1-1～Vda1-4电压升高。例如，Vda2-1升高为Vda2-1’。这样使得Vda2-1和Vcom之间的压差ΔV2可降低为ΔV2’。由于子像素的亮度与子像素中的数据电压和公共电极电压之间的压差相关，压差降低，可以使子像素的亮度降低，因此，第二列子像素的亮度可以降低。
其余同理，从而可以使子像素的亮度降低。这样在将显示频率从高频变换到低频时，通过对数据线加载补偿电压，可以将低频时显示画面的亮度降低，从而可以使高频时显示画面的亮度和低频时显示画面的亮度尽可能保持稳定，提高显示品质和观看体验。
需要说明的是，本公开实施例中的显示面板可以为液晶显示面板。示例性地在子像素的像素电极中的数据电压大于公共电极电压时，可以使子像素的极性为正极性。在子像素的像素电极中的数据电压小于公共电极电压时，可以使子像素的极性为负极性。例如，在实际应用中，公共电极上的公共电极电压可以为8V，以一个子像素为例，若在该子像素的像素电极中施加8V～12V的电压，可以使该子像素处的液晶分子为正极性。以0～255灰阶来说，该子像素在像素电极施加12V电压时，对应+255灰阶的亮度。若在该子像素的像素电极中施加4V～8V的电压，可以使该子像素处的液晶分子为负极性。 以0～255灰阶来说，该子像素在像素电极施加4V电压时，对应-255灰阶的亮度。
为追求更好的显示效果，对于液晶分子的控制，往往采用列反转或帧反转的方式，提高液晶分子的显示效果，在实际使用过程中，对液晶分子的反转采用电场驱动，使其极性发生反转。本公开实施例中，为了提高液晶的性能，可以使显示面板采用列反转方式。示例性地，图4a与图4b示意出了显示面板采用列反转方式时，相邻两个显示帧中子像素的极性。其中，图4a示意出了相邻两个显示帧中上一个显示帧对应的显示面板中各子像素的极性。图4b示意出了相邻两个显示帧中下一个显示帧对应的显示面板中各子像素的极性。其中，“+”代表子像素的极性为正极性，“-”代表子像素的极性为负极性。例如，正极性的子像素列和负极性的子像素列交替排列。并且，针对同一个子像素列，在上一个显示帧，该子像素列为正极性。在下一个显示帧，该子像素列则为负极性。以及在上一个显示帧，该子像素列为负极性。在下一个显示帧，该子像素列则为正极性。
本公开实施例中，为了提高液晶的性能，同时降低功耗，可以使显示面板采用帧反转方式。示例性地，图4c与图4d示意出了显示面板采用帧反转方式时，相邻两个显示帧中子像素的极性。其中，图4c示意出了相邻两个显示帧中上一个显示帧对应的显示面板中各子像素的极性。图4d示意出了相邻两个显示帧中下一个显示帧对应的显示面板中各子像素的极性。其中，“+”代表子像素的极性为正极性，“-”代表子像素的极性为负极性。例如，在上一个显示帧，各子像素列均为正极性。在下一个显示帧，各子像素列均为负极性。
下面以显示面板采用列反转方式为例进行说明。
在本公开实施例中，补偿电压可以包括第一子补偿电压，并且，针对每一条数据线，在数据线上加载的第一子补偿电压对应的极性与数据线连接的子像素对应的极性相反。例如，如图4a所示，第一个子像素列对应正极性，那么在空白时间阶段内可以向第一个子像素列对应的数据线加载的第一子补 偿电压对应的极性为负极性，例如可以从4V～8V中选取电压施加于该数据线上。第二个子像素列对应负极性，那么在空白时间阶段内可以向第二个子像素列对应的数据线加载的第一子补偿电压对应的极性为正极性，例如可以从8V～12V中选取电压施加于该数据线上。第三个子像素列对应正极性，那么在空白时间阶段内可以向第三个子像素列对应的数据线加载的第一子补偿电压对应的极性为负极性，例如可以从4V～8V中选取电压施加于该数据线上。第四个子像素列对应负极性，那么在空白时间阶段内可以向第四个子像素列对应的数据线加载的第一子补偿电压对应的极性为正极性，例如可以从8V～12V中选取电压施加于该数据线上。
例如，如图4b所示，第一个子像素列对应负极性，那么在空白时间阶段内可以向第一个子像素列对应的数据线加载的第一子补偿电压对应的极性为正极性，例如可以从8V～12V中选取电压施加于该数据线上。第二个子像素列对应正极性，那么在空白时间阶段内可以向第二个子像素列对应的数据线加载的第一子补偿电压对应的极性为负极性，例如可以从4V～8V中选取电压施加于该数据线上。第三个子像素列对应负极性，那么在空白时间阶段内可以向第三个子像素列对应的数据线加载的第一子补偿电压对应的极性为正极性，例如可以从8V～12V中选取电压施加于该数据线上。第四个子像素列对应正极性，那么在空白时间阶段内可以向第四个子像素列对应的数据线加载的第一子补偿电压对应的极性为负极性，例如可以从4V～8V中选取电压施加于该数据线上。
在本公开实施例中，相邻的两个设定显示帧中，针对同一条数据线，在上一个设定显示帧中加载于数据线的第一子补偿电压与公共电极电压之间具有第一差值，在下一个设定显示帧中加载于数据线的第一子补偿电压与公共电极电压之间具有第二差值。可以使第一差值的绝对值等于第二差值的绝对值。例如，如图5所示，在F1显示帧中，在加载于数据线的第一子补偿电压Vdc11-1与公共电极电压Vcom之间的具有第一差值ΔVdc1。在F2显示帧中，在加载于数据线的第一子补偿电压Vdc11-2与公共电极电压Vcom之间的具有 第二差值ΔVdc2。|ΔVdc1|＝|ΔVdc2|，这样可以降低确定第一子补偿电压的计算量，降低功耗。
在本公开实施例中，在至少一个显示帧的空白时间阶段内，可以全部加载补偿电压。例如，如图5所示，可以在F1显示帧中的整个空白时间阶段TB内，对各数据线均加载第一子补偿电压。在F2显示帧中的整个空白时间阶段TB内，对各数据线均加载第一子补偿电压。
在本公开实施例中，可以将连续多个显示帧中的每一个显示帧设置为设定显示帧。即，在连续多个显示帧中的每一个显示帧包括的数据刷新阶段内，对显示面板中的栅线加载栅极开启电压，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压。以及，在连续多个显示帧中的每一个显示帧包括的空白时间阶段内，对显示面板中的栅线加载栅极关闭电压，并对各数据线加载第一子补偿电压。这样可以对每一个显示帧进行补偿，从而可以使亮度保持稳定。
在本公开实施例中，可以使各数据线加载的补偿电压对应的灰阶相同。这样可以不用过多的计算量即可确定每个补偿电压的灰阶，可以降低功耗。示例性地，可以使各数据线加载的第一子补偿电压对应的灰阶相同。这样可以降低确定不同设定显示帧中第一子补偿电压的计算量，降低功耗。例如，各数据线加载的第一子补偿电压对应的灰阶为127灰阶。如图4a所示，第一个子像素列对应正极性，那么可以向第一个子像素列对应的数据线加载的第一子补偿电压对应的极性为负极性，并从4V～8V中选取对应127灰阶的电压施加于该数据线上。第二个子像素列对应负极性，那么可以向第二个子像素列对应的数据线加载的第一子补偿电压对应的极性为正极性，并8V～12V中选取对应127灰阶的电压施加于该数据线上。第三个子像素列对应正极性，那么可以向第三个子像素列对应的数据线加载的第一子补偿电压对应的极性为负极性，并从4V～8V中选取对应127灰阶的电压施加于该数据线上。第四个子像素列对应负极性，那么可以向第四个子像素列对应的数据线加载的补偿电压对应的极性为正极性，并8V～12V中选取对应127灰阶的电压施加于 该数据线上。
如图4b所示，第一个子像素列对应负极性，那么可以向第一个子像素列对应的数据线加载的第一子补偿电压对应的极性为正极性，并8V～12V中选取对应127灰阶的电压施加于该数据线上。第二个子像素列对应正极性，那么可以向第二个子像素列对应的数据线加载的第一子补偿电压对应的极性为负极性，并从4V～8V中选取对应127灰阶的电压施加于该数据线上。第三个子像素列对应负极性，那么可以向第三个子像素列对应的数据线加载的第一子补偿电压对应的极性为正极性，并8V～12V中选取对应127灰阶的电压施加于该数据线上。第四个子像素列对应正极性，那么可以向第四个子像素列对应的数据线加载的第一子补偿电压对应的极性为负极性，并从4V～8V中选取对应127灰阶的电压施加于该数据线上。
在本公开实施例中，补偿电压的电压值可以为任一灰阶的电压值。示例性地，第一子补偿电压的电压值可以为任一灰阶的电压值。例如，可以使各数据线加载的第一子补偿电压对应的灰阶从0～255灰阶中选取一个，例如，可以为127灰阶。例如，也可以为200灰阶。这里的任一灰阶指的是可以给显示面板需要补偿的子像素补充同一个任一灰阶的电压，补偿方式简单，不需要额外的补偿模块或者操作，节省功耗。在实际应用中，可以根据实际应用的需要对该灰阶进行选取，在此不作限定。
在本公开实施例中，针对每一条数据线，该数据线上加载的补偿电压对应的灰阶与数据线连接的子像素中的一个数据电压对应的灰阶相同。例如，针对每一条数据线，数据线上加载的第一子补偿电压对应的灰阶与数据线连接的子像素中的一个数据电压对应的灰阶相同。例如，第一个子像素列对应的数据线上加载的第一子补偿电压可以与第一个子像素列中的第一行子像素中的数据电压对应的灰阶相同。或第一个子像素列对应的数据线上加载的第一子补偿电压可以与第二个子像素列中的第一行子像素中的数据电压对应的灰阶相同。或第一个子像素列对应的数据线上加载的第一子补偿电压可以与第一个子像素列中的最后一行子像素中的数据电压对应的灰阶相同。
在本公开实施例中，设定显示帧的空白时间阶段也可以部分加载第一补偿电压，例如可以使空白时间阶段具有至少一个补偿阶段，并在补偿阶段中对数据线加载第一子补偿电压。示例性地，如图6所示，设定显示帧的空白时间阶段可以具有一个补偿阶段BC。或者，设定显示帧的空白时间阶段可以具有多个补偿阶段，例如包括3个补偿阶段。当然，在实际应用中，设定显示帧的空白时间阶段可以具有的补偿阶段的数量可以根据实际应用的需要进行设定确定，在此不作限定。
在本公开实施例中，设定显示帧的空白时间阶段具有多个补偿阶段时，每相邻两个补偿阶段间隔的时间相同。这样可以在空白时间阶段内，对数据线均匀的加载的补偿电压。
在本公开实施例中，补偿阶段的持续时间满足关系：0<tc<1/2tb；其中，tc代表补偿阶段的持续时间，tb代表空白时间阶段的持续时间。这样可以仅使空白时间阶段中的部分时间作为补偿阶段，从而可以避免应用晶体管漏电，导致数据线上加载的电压倒流入子像素中而影响子像素的亮度。
在本公开实施例中，可以使补偿阶段的边界与数据刷新阶段的边界重合。或者，也可以使补偿阶段的边界与数据刷新阶段的边界之间间隔一定的时间。
下面结合图1a、以及图4a至图5，对本公开实施例提供的显示面板的驱动方法进行说明。其中，连续的多个显示帧中的每一个显示帧为设定显示帧。其中，图4a对应显示帧F1，图4b对应显示帧F2。并且，显示帧F1和F2为连续的多个显示帧中的相邻两个显示帧。
在显示帧F1内，在数据刷新阶段TS，在信号ga1出现栅极开启电压时，可以控制第一行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第一行子像素中的像素电极02输入对应的数据电压。在信号ga2出现栅极开启电压时，可以控制第二行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第二行子像素中的像 素电极02输入对应的数据电压。在信号ga3出现栅极开启电压时，可以控制第三行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第三行子像素中的像素电极02输入对应的数据电压。在信号ga4出现栅极开启电压时，可以控制第四行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第四行子像素中的像素电极02输入对应的数据电压。其余行以此类推，在此不作赘述。
在空白时间阶段TB内，对显示面板中的栅线同时加载栅极关闭电压，以控制每个子像素中的晶体管01处于截止状态。从4V～8V中选取对应127灰阶的电压作为对应负极性的第一子补偿电压，施加于第一个子像素列对应的数据线上。从8V～12V中选取对应127灰阶的电压作为对应正极性的第一子补偿电压，施加于第二个子像素列对应的数据线上。从4V～8V中选取对应127灰阶的电压作为对应负极性的第一子补偿电压，施加于第三个子像素列对应的数据线上。从8V～12V中选取对应127灰阶的电压作为对应正极性的第一子补偿电压，施加于第四个子像素列对应的数据线上。
在显示帧F2内，在数据刷新阶段TS，在信号ga1出现栅极开启电压时，可以控制第一行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第一行子像素中的像素电极02输入对应的数据电压。在信号ga2出现栅极开启电压时，可以控制第二行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第二行子像素中的像素电极02输入对应的数据电压。在信号ga3出现栅极开启电压时，可以控制第三行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第三行子像素中的像素电极02输入对应的数据电压。在信号ga4 出现栅极开启电压时，可以控制第四行子像素中的晶体管01均导通，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第四行子像素中的像素电极02输入对应的数据电压。其余行以此类推，在此不作赘述。
在空白时间阶段TB内，对显示面板中的栅线同时加载栅极关闭电压，以控制每个子像素中的晶体管01处于截止状态。从8V～12V中选取对应127灰阶的电压作为对应正极性的第一子补偿电压，施加于第一个子像素列对应的数据线上。从4V～8V中选取对应127灰阶的电压作为对应负极性的第一子补偿电压，施加于第二个子像素列对应的数据线上。从8V～12V中选取对应127灰阶的电压作为对应正极性的第一子补偿电压，施加于第三个子像素列对应的数据线上。从4V～8V中选取对应127灰阶的电压作为对应负极性的第一子补偿电压，施加于第四个子像素列对应的数据线上。
其余显示帧，以此类推，在此不作赘述。
本公开实施例提供了另一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，补偿电压还可以包括在第一子补偿电压之前出现的过渡补偿电压。并且，在数据线连接的子像素中的数据电压大于公共电极电压时，数据线上加载的过渡补偿电压小于数据线连接的子像素中的数据电压。以及，在数据线连接的子像素中的数据电压小于公共电极电压时，数据线上加载的过渡补偿电压大于数据线连接的子像素中的数据电压。
在本公开实施例中，针对每一条数据线，在数据线上加载的过渡补偿电压对应的极性与数据线连接的子像素对应的极性相同。例如，结合图4a与图7所示，在显示帧F1中，数据刷新阶段TS中第一个子像素列对应正极性，那么在空白时间阶段TB可以先向第一个子像素列对应的数据线加载对应正极性的过渡补偿电压Vdc21-1，例如从8V～12V中选取电压作为过渡补偿电压Vdc21-1施加于该数据线上，之后，向第一个子像素列对应的数据线加载对应 负极性的第一子补偿电压Vdc11-1，例如从4V～8V中选取电压作为第一子补偿电压Vdc11-1施加于该数据线上。数据刷新阶段TS中第二个子像素列对应负极性，那么在空白时间阶段TB可以先向第二个子像素列对应的数据线加载对应负极性的过渡补偿电压，例如从4V～8V中选取电压作为过渡补偿电压施加于该数据线上，之后，向第二个子像素列对应的数据线加载对应正极性的第一子补偿电压，例如从8V～12V中选取电压作为第一子补偿电压施加于该数据线上。第三个子像素列对应的数据线加载的过渡补偿电压和第一子补偿电压与第一个子像素列对应的数据线加载的过渡补偿电压和第一子补偿电压的方式相同，在此不作赘述。第四个子像素列对应的数据线加载的过渡补偿电压和第一子补偿电压与第二个子像素列对应的数据线加载的过渡补偿电压和第一子补偿电压的方式相同，在此不作赘述。
例如，结合图4a与图7所示，在显示帧F2中，数据刷新阶段TS中第一个子像素列对应负极性，那么在空白时间阶段TB可以先向第一个子像素列对应的数据线加载对应负极性的过渡补偿电压Vdc21-2，例如从4V～8V中选取电压作为过渡补偿电压Vdc21-2施加于该数据线上，之后，向第一个子像素列对应的数据线加载对应正极性的第一子补偿电压Vdc11-2，例如从8V～12V中选取电压作为第一子补偿电压Vdc11-2施加于该数据线上。数据刷新阶段TS中第二个子像素列对应正极性，那么在空白时间阶段TB可以先向第二个子像素列对应的数据线加载对应正极性的过渡补偿电压，例如从8V～12V中选取电压作为过渡补偿电压施加于该数据线上，之后，向第二个子像素列对应的数据线加载负极性的第一子补偿电压，例如从4V～8V中选取电压作为第一子补偿电压施加于该数据线上。第三个子像素列对应的数据线加载的过渡补偿电压和第一子补偿电压与第一个子像素列对应的数据线加载的过渡补偿电压和第一子补偿电压的方式相同，在此不作赘述。第四个子像素列对应的数据线加载的过渡补偿电压和第一子补偿电压与第二个子像素列对应的数据线加载的过渡补偿电压和第一子补偿电压的方式相同，在此不作赘述。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中 的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，也可以采用如下公式，确定补偿电压对应的灰阶；
VS11＝(VA12+VA12)/2；
其中，VS11代表补偿电压对应的灰阶，VA11代表从连续的多个显示帧中选取的一个显示帧中的最大灰阶，VA12代表从连续的多个显示帧中选取的显示帧中最小灰阶，且VA11+VA12为偶数。
示例性地，例如，VS11可以代表补偿电压中的第一子电压对应的灰阶，这样可以通过VS11＝(VA12+VA12)/2，确定第一子补偿电压的灰阶。
在本公开实施例中，从多个显示帧中选取的显示帧可以为设定显示帧相邻的上一个显示帧。例如，如图5所示，在VA11+VA12为偶数时，VS11可以代表显示帧F2中第一子补偿电压对应的灰阶，VA11可以代表显示帧F1中输入子像素中的数据电压对应的最大灰阶，VA12可以代表显示帧F1中输入子像素中的数据电压对应的最小灰阶。
在本公开实施例中，从多个显示帧中选取的显示帧可以为设定显示帧。例如，如图5所示，在VA11+VA12为偶数时，VS11可以代表显示帧F1中第一子补偿电压对应的灰阶，VA11可以代表显示帧F1中输入子像素中的数据电压对应的最大灰阶，VA12可以代表显示帧F1中输入子像素中的数据电压对应的最小灰阶。
需要说明的是，本实施例对应的显示面板的驱动方法其余的工作过程，可以与上述实施例中显示面板的驱动方法的其余工作过程基本相同，在此不作赘述。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，也可以采用如下公式，确定补偿电压对应的灰阶；
VS21＝(VA21+VA22+1)/2；
其中，VS21代表补偿电压对应的灰阶，VA21代表从连续的多个显示帧中选取的一个显示帧中的最大灰阶，VA22代表从连续的多个显示帧中选取的显示帧中最小灰阶，且VA21+VA22为奇数。
示例性地，例如，VS21可以代表补偿电压中的第一子电压对应的灰阶，这样可以通过VS21＝(VA21+VA22+1)/2，确定第一子补偿电压的灰阶。
在本公开实施例中，从多个显示帧中选取的显示帧可以为设定显示帧相邻的上一个显示帧。例如，如图5所示，在VA21+VA22为奇数时，VS21可以代表显示帧F2中第一子补偿电压对应的灰阶，VA21可以代表显示帧F1中输入子像素中的数据电压对应的最大灰阶，VA22可以代表显示帧F1中输入子像素中的数据电压对应的最小灰阶。
在本公开实施例中，从多个显示帧中选取的显示帧可以为设定显示帧。例如，如图5所示，在VA21+VA22为奇数时，VS21可以代表显示帧F1中第一子补偿电压对应的灰阶，VA21可以代表显示帧F1中输入子像素中的数据电压对应的最大灰阶，VA12可以代表显示帧F1中输入子像素中的数据电压对应的最小灰阶。
需要说明的是，本实施例对应的显示面板的驱动方法其余的工作过程，可以与上述实施例中显示面板的驱动方法的其余工作过程基本相同，在此不作赘述。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，对各数据线加载补偿电压，可以包括：在设定显示帧的空白时间阶段中，从多个显示帧中选取一个显示帧，并针对每一条数据线，对该数据线加载选取的显示帧输入显示面板内一行子像素的数据电压对应灰阶的电压。
在本公开实施例中，从多个显示帧中选取的显示帧可以为设定显示帧相邻的上一个显示帧。
在本公开实施例中，从多个显示帧中选取的显示帧可以为设定显示帧。
在本公开实施例中，对各数据线加载补偿电压，可以包括：在设定显示帧的空白时间阶段中，从多个显示帧中选取一个显示帧，并针对每一条数据线，对数据线加载选取的显示帧输入显示面板内第一行子像素的数据电压对应灰阶的电压，以作为第一子补偿电压。例如，以显示面板共有四行子像素为例(当然，在实际应用中，显示面板具有的子像素行数并非仅有四行，其可以根据实际确定，在此不作限定)，结合图4a至图5，在显示帧F2中，选取显示帧F1中，第一个子像素列中的第一行子像素输入的数据电压对应的灰阶，作为第一个子像素列电连接的数据线输入的第一子补偿电压对应的灰阶。例如，显示帧F1中第一个子像素列的第一行子像素输入的数据电压对应120灰阶，则在显示帧F2中的空白时间阶段中，对第一个子像素列电连接的数据线加载对应120灰阶的电压作为第一子补偿电压，且该120灰阶的电压对应的极性与显示帧F2中第一个子像素列对应的极性相反。显示帧F1中第二个子像素列的第一行子像素输入的数据电压对应220灰阶，则在显示帧F2中的空白时间阶段中，对第二个子像素列电连接的数据线加载对应220灰阶的电压作为第一子补偿电压，且该220灰阶的电压对应的极性与显示帧F2中第二个子像素列对应的极性相反。第三个子像素列对应的数据线加载第一子补偿电压的方式与第一个子像素列对应的数据线加载第一子补偿电压的方式相同。第四个子像素列对应的数据线加载第一子补偿电压的方式与第二个子像素列对应的数据线加载第一子补偿电压的方式相同，在此不作赘述。
在本公开实施例中，对各数据线加载补偿电压，可以包括：在设定显示帧的空白时间阶段中，从多个显示帧中选取一个显示帧，并针对每一条数据线，对数据线加载选取的显示帧输入显示面板内中间一行子像素的数据电压对应灰阶的电压，以作为第一子补偿电压。例如，以显示面板共有四行子像素为例(当然，在实际应用中，显示面板具有的子像素行数并非仅有四行，其可以根据实际确定，在此不作限定)，结合图4a至图5，在显示帧F2中，选取显示帧F1中，第三行子像素输入的数据电压对应的灰阶，作为该子像素 电连接的数据线输入的第一子补偿电压对应的灰阶。例如，显示帧F1中第三行第一列子像素输入的数据电压对应120灰阶，则在显示帧F2中的空白时间阶段中，对第一列子像素电连接的数据线加载对应120灰阶的电压作为第一子补偿电压，且该120灰阶的电压对应的极性与显示帧F2中该第三行第一列子像素对应的极性相反。显示帧F1中第三行第二列子像素输入的数据电压对应220灰阶，则在显示帧F2中的空白时间阶段中，对第二列子像素电连接的数据线加载对应220灰阶的电压作为第一子补偿电压，且该220灰阶的电压对应的极性与显示帧F2中该第三行第二列子像素对应的极性相反。显示帧F1中第三行第三列子像素输入的数据电压对应150灰阶，则在显示帧F2中的空白时间阶段中，对第三列子像素电连接的数据线加载对应150灰阶的电压作为第一子补偿电压，且该150灰阶的电压对应的极性与显示帧F2中该第三行第三列子像素对应的极性相同。显示帧F1中第三行第四列子像素输入的数据电压对应60灰阶，则在显示帧F2中的空白时间阶段中，对第四列子像素电连接的数据线加载对应60灰阶的电压作为第一子补偿电压，且该60灰阶的电压对应的极性与显示帧F2中该第三行第四列子像素对应的极性相反。
在本公开实施例中，对各数据线加载补偿电压，可以包括：在设定显示帧的空白时间阶段中，从多个显示帧中选取一个显示帧，并针对每一条数据线，对数据线加载选取的显示帧输入显示面板内最后一行子像素的数据电压对应灰阶的电压，以作为第一子补偿电压。例如，以显示面板共有四行子像素为例(当然，在实际应用中，显示面板具有的子像素行数并非仅有四行，其可以根据实际确定，在此不作限定)，结合图4a至图5，在显示帧F2中，选取显示帧F1中，第四行子像素输入的数据电压对应的灰阶，作为该子像素电连接的数据线输入的补偿电压对应的灰阶。例如，显示帧F1中第四行第一列子像素输入的数据电压对应120灰阶，则在显示帧F2中的空白时间阶段中，对第一列子像素电连接的数据线加载对应120灰阶的电压作为第一子补偿电压，且该120灰阶的电压对应的极性与显示帧F2中该第四行第一列子像素对应的极性相同。显示帧F1中第四行第二列子像素输入的数据电压对应220灰 阶，则在显示帧F2中的空白时间阶段中，对第二列子像素电连接的数据线加载对应220灰阶的电压作为第一子补偿电压，且该220灰阶的电压对应的极性与显示帧F2中该第四行第二列子像素对应的极性相同。显示帧F1中第四行第三列子像素输入的数据电压对应150灰阶，则在显示帧F2中的空白时间阶段中，对第三列子像素电连接的数据线加载对应150灰阶的电压作为第一子补偿电压，且该150灰阶的电压对应的极性与显示帧F2中该第四行第三列子像素对应的极性相同。显示帧F1中第四行第四列子像素输入的数据电压对应60灰阶，则在显示帧F2中的空白时间阶段中，对第四列子像素电连接的数据线加载对应60灰阶的电压作为第一子补偿电压，且该60灰阶的电压对应的极性与显示帧F2中该第四行第四列子像素对应的极性相同。
需要说明的是，本实施例对应的显示面板的驱动方法其余的工作过程，可以与上述实施例中显示面板的驱动方法的其余工作过程基本相同，在此不作赘述。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，对各数据线加载补偿电压，可以包括：在设定显示帧的空白时间阶段中，从多个显示帧中选取一个显示帧，并针对每一条数据线，对数据线依次加载选取的显示帧输入数据线上的数据电压对应灰阶的电压。这样可以使补偿电压的选择更加多元化，可以使补偿更加细致。
在本公开实施例中，从多个显示帧中选取的显示帧可以为设定显示帧相邻的上一个显示帧。例如，以显示面板共有四行子像素为例(当然，在实际应用中，显示面板具有的子像素行数并非仅有四行，其可以根据实际确定，在此不作限定)，结合图4a至图8，在显示帧F2中，选取显示帧F1中，第一行至第四行子像素输入的数据电压对应的灰阶，作为该子像素电连接的数据线输入的补偿电压对应的灰阶。例如，显示帧F1中第一行第一列子像素输入的数据电压对应120灰阶，第二行第一列子像素输入的数据电压对应150灰 阶，第三行第一列子像素输入的数据电压对应60灰阶，第四行第一列子像素输入的数据电压对应220灰阶，则在显示帧F2中的补偿阶段中，对第一列子像素电连接的数据线依次输入对应120灰阶的第一子补偿电压，对应150灰阶的第一子补偿电压，对应60灰阶的第一子补偿电压，对应220灰阶的第一子补偿电压，并且显示帧F2中对第一列子像素电连接的数据线输入的第一子补偿电压对应的极性与显示帧F2中对第一列子像素输入的数据电压对应的极性相反，例如均为正极性。
显示帧F1中第一行第二列子像素输入的数据电压对应127灰阶，第二行第二列子像素输入的数据电压对应159灰阶，第三行第二列子像素输入的数据电压对应160灰阶，第四行第二列子像素输入的数据电压对应68灰阶，则在显示帧F2中的补偿阶段中，对第二列子像素电连接的数据线依次输入对应127灰阶的第一子补偿电压，对应159灰阶的第一子补偿电压，对应160灰阶的第一子补偿电压，对应68灰阶的第一子补偿电压，并且显示帧F2中对第二列子像素电连接的数据线输入的第一子补偿电压对应的极性与显示帧F2中对第二列子像素输入的数据电压对应的极性相反，例如均为负极性。
显示帧F1中第一行第三列子像素输入的数据电压对应140灰阶，第二行第三列子像素输入的数据电压对应130灰阶，第三行第三列子像素输入的数据电压对应40灰阶，第四行第三列子像素输入的数据电压对应175灰阶，则在显示帧F2中的补偿阶段中，对第三列子像素电连接的数据线依次输入对应140灰阶的第一子补偿电压，对应130灰阶的第一子补偿电压，对应40灰阶的第一子补偿电压，对应175灰阶的第一子补偿电压，并且显示帧F2中对第三列子像素电连接的数据线输入的第一子补偿电压对应的极性与显示帧F2中对第三列子像素输入的数据电压对应的极性相反，例如均为正极性。
显示帧F1中第一行第四列子像素输入的数据电压对应177灰阶，第二行第四列子像素输入的数据电压对应129灰阶，第三行第四列子像素输入的数据电压对应80灰阶，第四行第四列子像素输入的数据电压对应198灰阶，则在显示帧F2中的补偿阶段中，对第四列子像素电连接的数据线依次输入对应 177灰阶的第一子补偿电压，对应129灰阶的第一子补偿电压，对应80灰阶的第一子补偿电压，对应198灰阶的第一子补偿电压，并且显示帧F2中对第四列子像素电连接的数据线输入的第一子补偿电压对应的极性与显示帧F2中对第四列子像素输入的数据电压对应的极性相反，例如均为负极性。
在本公开实施例中，从多个显示帧中选取的显示帧可以为设定显示帧。例如，以显示面板共有四行子像素为例(当然，在实际应用中，显示面板具有的子像素行数并非仅有四行，其可以根据实际确定，在此不作限定)，结合图4a至图8，在显示帧F2中，选取显示帧F2中，第一行至第四行子像素输入的数据电压对应的灰阶，作为该子像素电连接的数据线输入的第一子补偿电压对应的灰阶。例如，显示帧F2中第一行第一列子像素输入的数据电压对应120灰阶，第二行第一列子像素输入的数据电压对应150灰阶，第三行第一列子像素输入的数据电压对应60灰阶，第四行第一列子像素输入的数据电压对应220灰阶，则在显示帧F2中的补偿阶段中，对第一列子像素电连接的数据线依次输入对应120灰阶的第一子补偿电压，对应150灰阶的第一子补偿电压，对应60灰阶的第一子补偿电压，对应220灰阶的第一子补偿电压，并且显示帧F2中对第一列子像素电连接的数据线输入的第一子补偿电压对应的极性与显示帧F2中对第一列子像素输入的数据电压对应的极性相反，例如均为正极性。
显示帧F2中第一行第二列子像素输入的数据电压对应127灰阶，第二行第二列子像素输入的数据电压对应159灰阶，第三行第二列子像素输入的数据电压对应160灰阶，第四行第二列子像素输入的数据电压对应68灰阶，则在显示帧F2中的补偿阶段中，对第二列子像素电连接的数据线依次输入对应127灰阶的第一子补偿电压，对应159灰阶的第一子补偿电压，对应160灰阶的第一子补偿电压，对应68灰阶的第一子补偿电压，并且显示帧F2中对第二列子像素电连接的数据线输入的第一子补偿电压对应的极性与显示帧F2中对第二列子像素输入的数据电压对应的极性相反，例如均为负极性。
显示帧F2中第一行第三列子像素输入的数据电压对应140灰阶，第二行 第三列子像素输入的数据电压对应130灰阶，第三行第三列子像素输入的数据电压对应40灰阶，第四行第三列子像素输入的数据电压对应175灰阶，则在显示帧F2中的补偿阶段中，对第三列子像素电连接的数据线依次输入对应140灰阶的第一子补偿电压，对应130灰阶的第一子补偿电压，对应40灰阶的第一子补偿电压，对应175灰阶的第一子补偿电压，并且显示帧F2中对第三列子像素电连接的数据线输入的第一子补偿电压对应的极性与显示帧F2中对第三列子像素输入的数据电压对应的极性相反，例如均为正极性。
显示帧F2中第一行第四列子像素输入的数据电压对应177灰阶，第二行第四列子像素输入的数据电压对应129灰阶，第三行第四列子像素输入的数据电压对应80灰阶，第四行第四列子像素输入的数据电压对应198灰阶，则在显示帧F2中的补偿阶段中，对第四列子像素电连接的数据线依次输入对应177灰阶的第一子补偿电压，对应129灰阶的第一子补偿电压，对应80灰阶的第一子补偿电压，对应198灰阶的第一子补偿电压，并且显示帧F2中对第四列子像素电连接的数据线输入的第一子补偿电压对应的极性与显示帧F2中对第四列子像素输入的数据电压对应的极性相反，例如均为负极性。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，连续多个显示帧中的部分显示帧为设定显示帧。并且，连续多个显示帧中，除设定显示帧之外的显示帧为非设定显示帧。也就是说，该连续多个显示帧中的部分显示帧为设定显示帧，其余部分显示帧为非设定显示帧。
在本公开实施例中，非设定显示帧包括：
数据刷新阶段，对显示面板中的栅线分时加载栅极开启电压，并在每一条栅线加载栅极开启电压时对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；
空白时间阶段，对显示面板中的栅线同时加载栅极关闭电压，并使各数 据线浮接。
需要说明的是，空白时间阶段中各数据线浮接，指的可以是不对各数据线加载电压。
也就是说，在非设定显示帧中数据刷新阶段的工作过程与设定显示帧中数据刷新阶段的工作过程基本相同。而在非设定显示帧中空白时间阶段中未设置补偿阶段。
在本公开实施例中，可以使相邻的两个设定显示帧之间具有至少一个非设定显示帧。例如，可以使相邻的两个设定显示帧之间具有一个非设定显示帧。也可以使相邻的两个设定显示帧之间具有两个非设定显示帧。也可以使相邻的两个设定显示帧之间具有三个非设定显示帧。例如，图9所示，显示帧F1、显示帧F3、显示帧F5为设定显示帧，显示帧F2、显示帧F4为非设定显示帧。
在本公开实施例中，可以使每相邻的两个设定显示帧之间具有的非设定显示帧的数量相同。例如，可以使每相邻的两个设定显示帧之间具有一个非设定显示帧。也可以使每相邻的两个设定显示帧之间具有两个非设定显示帧。也可以使每相邻的两个设定显示帧之间具有三个非设定显示帧。例如，图6所示，显示帧F1、显示帧F3、显示帧F5为设定显示帧，显示帧F2、显示帧F4为非设定显示帧。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，补偿电压可以包括第二子补偿电压；针对每一个数据线，在该数据线上加载的第二子补偿电压对应的极性与该数据线连接的子像素对应的极性相同。例如，如图4a与图10所示，第一个子像素列对应正极性，那么可以向第一个子像素列对应的数据线加载的第二子补偿电压Vdc31-1对应的极性为正极性，例如可以从8V～12V中选取电压施加于该数据线上。第二个子像素列对应负极性，那么可以向第二个子像素列对应的数据 线加载的第二子补偿电压对应的极性为负极性，例如可以从4V～8V中选取电压施加于该数据线上。第三个子像素列对应正极性，那么可以向第三个子像素列对应的数据线加载的第二子补偿电压对应的极性为正极性，例如可以从8V～12V中选取电压施加于该数据线上。第四个子像素列对应负极性，那么可以向第四个子像素列对应的数据线加载的第二子补偿电压对应的极性为负极性，例如可以从4V～8V中选取电压施加于该数据线上。
如图4b与图10所示，第一个子像素列对应负极性，那么可以向第一个子像素列对应的数据线加载的第二子补偿电压Vdc31-2对应的极性为负极性，例如可以从4V～8V中选取电压施加于该数据线上。第二个子像素列对应正极性，那么可以向第二个子像素列对应的数据线加载的第二子补偿电压对应的极性为正极性，例如可以从8V～12V中选取电压施加于该数据线上。第三个子像素列对应负极性，那么可以向第三个子像素列对应的数据线加载的第二子补偿电压对应的极性为负极性，例如可以从4V～8V中选取电压施加于该数据线上。第四个子像素列对应正极性，那么可以向第四个子像素列对应的数据线加载的第二子补偿电压对应的极性为正极性，例如可以从8V～12V中选取电压施加于该数据线上。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，如图11所示，在显示频率由较高频率H1(例如120Hz)切换为较低频率H2(例如60Hz，30Hz、48Hz)时，可以仅在显示器采用较低频率H2时，采用本公开实施例中的驱动方法驱动显示面板显示。例如，显示帧F1～F5的空白时间阶段TB的维持时长小于显示帧F6～F10的空白时间阶段TB的维持时长，显示帧F1～F5可以作为第一帧，显示帧F6～F10可以作为第二帧。显示器采用120Hz进行刷新时，显示帧F1～F5中，空白时间阶段TB，数据线浮接。在显示器由120Hz切换为48Hz，且采用48Hz的显示频率刷新时，在各个显示帧(例如显示帧F6～F10)中的空白时间阶段TB内，对显示 面板中的栅线加载栅极关闭电压，并对各数据线加载补偿电压。这样可以低频时显示的画面相比高频时显示的画面的亮度增加的问题，保持亮度稳定，提高显示品质和观看体验。
在本公开实施例中也可以在显示器能够采用的各个显示频率时，如图12所示，在较高频率H1和较低频率H2均采用本公开实施例中的驱动方法驱动显示面板显示。例如，显示帧F1～F5的空白时间阶段TB的维持时长小于显示帧F6～F10的空白时间阶段TB的维持时长，显示帧F1～F5可以作为第一帧，显示帧F6～F10可以作为第二帧。在显示器采用120Hz的显示频率刷新时，在各个显示帧(例如显示帧F1～F5)中的空白时间阶段内，对显示面板中的栅线加载栅极关闭电压，并对各数据线加载补偿电压，即显示帧F1～F5均采用120Hz的显示频率刷新，并对各数据线加载补偿电压。在显示器由120Hz切换为48Hz，且采用48Hz的显示频率刷新时，在各个显示帧(例如显示帧F6～F10)中的空白时间阶段内，对显示面板中的栅线加载栅极关闭电压，并对各数据线加载补偿电压，即显示帧F6～F10均采用48Hz的显示频率刷新，并对各数据线加载补偿电压。这样在不同显示频率刷新时，可以均在空白时间阶段内，对数据线加载补偿电压，从而不用额外的区分显示频率进行补偿。即可以统一对不同的显示频率均进行补偿，此时TCON时序更容易调整，简化TCON时序设计，降低功耗，需要说明的是，本案中，对于低频率刷新转化为高频率刷新时出现的显示异常，显示异常的原因在于空白时间阶段的漏电以及高刷新频率充电不足，目前显示趋于高刷新率，例如144HZ，240Hz等，刷新率越高，充电率降低，导致显示面板亮度降低，当高刷新率下的充电率不足占据主导，导致高刷新率下的显示亮度相对于低刷新率的亮度低，这样在切换刷新率时，显示会出现亮暗差异，显示异常，本发明为了简化TCON时序调整和时序设计，可以在高频率和低频率下均采用加载与数据信号相反极性的补偿电压，此时由于高刷新频率下空白时间阶段时间相对于低刷新频率下的空白阶段时间更短，此时即使增加补偿电压，仍然也可以解决显示画面异常的问题。当然本案也可以仅仅在低刷新频率下的显示帧中加载补偿电 压，而在高刷新频率下保持空白时间阶段，例如此阶段仅仅给0灰阶电压，此时通过降低刷新频率下的亮度来匹配高刷新频率的亮度，实现显示均一性好。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在所述数据线连接的子像素中的数据电压大于公共电极电压时，所述数据线上加载的补偿电压也可以大于所述数据线连接的子像素中的数据电压。在所述数据线连接的子像素中的数据电压小于公共电极电压时，所述数据线上加载的补偿电压也可以小于所述数据线连接的子像素中的数据电压。这样可以降低消隐时间内子像素中晶体管的源极和漏极之间的电压差，降低晶体管漏电。这样可以在显示器持续处于低频的显示频率时，通过降低晶体管漏电，可以保持子像素中输入的数据电压稳定，从而可以避免显示器持续处于低频的显示频率时显示画面亮度降低的问题。
本公开实施例还提供了一种显示驱动电路，其中，显示面板工作于连续的多个显示帧，每个显示帧包括数据刷新阶段和空白时间阶段；并且，显示驱动电路被配置为：
在连续的多个显示帧中的至少一个显示帧的数据刷新阶段内，对显示面板中的栅线加载栅极开启电压，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；
在至少一个显示帧的空白时间阶段内，对显示面板中的栅线加载栅极关闭电压，并对各数据线加载补偿电压；其中，在数据线连接的子像素中的数据电压大于公共电极电压时，数据线上加载的补偿电压小于数据线连接的子像素中的数据电压；在数据线连接的子像素中的数据电压小于公共电极电压时，数据线上加载的补偿电压大于数据线连接的子像素中的数据电压。
需要说明的是，该显示驱动电路的工作原理和具体实施方式与上述实施例显示面板的驱动方法的原理和实施方式相同，因此，该显示驱动电路的工 作方法可参见上述实施例中显示面板的驱动方法的具体实施方式进行实施，在此不再赘述。
本公开实施例还提供了一种显示装置，如图13所示，包括显示面板100以及时序控制器(Timing Contro-ller，TCON)200；显示面板100包括多条栅线GA1～GA5、多条数据线DA1～DA6、源极驱动电路110以及栅极驱动电路120；其中，源极驱动电路110与多条数据线耦接DA1～DA6；栅极驱动电路120与多条栅线GA1～GA5耦接。
在本公开实施例中，如图13所示，时序控制器200与源极驱动电路110以及栅极驱动电路120分别耦接。
时序控制器200被配置为在连续的多个显示帧中的至少一个显示帧的数据刷新阶段内，对栅极驱动电路120输入第一栅极驱动信号，对源极驱动电路110输入第一源极驱动信号。栅极驱动电路120被配置为根据接收到第一栅极驱动信号，对显示面板100中的栅线GA1～GA5加载栅极开启电压。源极驱动电路110被配置为根据接收到第一源极驱动信号，对各数据线DA1～DA6加载待显示图像的数据电压，从而实现一个显示帧的画面显示。
时序控制器200被配置为在至少一个显示帧的空白时间阶段内，对栅极驱动电路120输入第二栅极驱动信号，对源极驱动电路110输入第二源极驱动信号。栅极驱动电路120被配置为根据接收到的第二栅极驱动信号，对显示面板中的栅线GA1～GA5加载栅极关闭电压。源极驱动电路110被配置为根据接收到第二源极驱动信号，对各数据线DA1～DA6加载补偿电压。其中，在数据线连接的子像素中的数据电压大于公共电极电压时，数据线上加载的补偿电压小于数据线连接的子像素中的数据电压；在数据线连接的子像素中的数据电压小于公共电极电压时，数据线上加载的补偿电压大于数据线连接的子像素中的数据电压。这样可以改善显示器的显示频率从高频变换到低频时，显示画面亮度增加的问题，保持亮度稳定，提高显示品质和观看体验。
需要说明的是，该显示装置的工作原理和具体实施方式与上述实施例显示面板的驱动方法的原理和实施方式相同，因此，该显示装置的工作方法可 参见上述实施例中显示面板的驱动方法的具体实施方式进行实施，在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的显示面板的驱动方法、显示驱动电路及显示装置，通过在连续的多个显示帧中的设定显示帧的数据刷新阶段内，对显示面板中的栅线分时加载栅极开启电压，并在每一条栅线加载栅极开启电压时对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压，从而实现一个显示帧的画面显示。并且，在设定显示帧的空白时间阶段内，对显示面板中的栅线同时加载栅极关闭电压，并对各数据线加载补偿电压。这样可以降低空白时间阶段内晶体管的源极和漏极之间的电压差，从而可以降低子像素的漏电，提高显示品质和观看体验。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (20)

  1. 一种显示面板的驱动方法，所述显示面板工作于连续的多个显示帧，每个显示帧包括数据刷新阶段和空白时间阶段；
    所述显示面板的驱动方法，包括：
    在连续的多个显示帧中的至少一个所述显示帧的数据刷新阶段内，对所述显示面板中的栅线加载栅极开启电压，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；
    在至少一个所述显示帧的空白时间阶段内，对所述显示面板中的栅线加载栅极关闭电压，并对各所述数据线加载补偿电压；
    其中，在所述数据线连接的子像素中的数据电压大于公共电极电压时，所述数据线上加载的补偿电压小于所述数据线连接的子像素中的数据电压；
    和/或，在所述数据线连接的子像素中的数据电压小于公共电极电压时，所述数据线上加载的补偿电压大于所述数据线连接的子像素中的数据电压。
  2. 如权利要求1所述的显示面板的驱动方法，其中，在至少一个所述显示帧的空白时间阶段内，全部加载所述补偿电压。
  3. 如权利要求1所述的显示面板的驱动方法，其中，所述显示面板采用列反转方式或帧反转方式；所述补偿电压包括第一子补偿电压；
    针对每一条所述数据线，在所述数据线上加载的第一子补偿电压对应的极性与所述数据线连接的子像素对应的极性相反。
  4. 如权利要求3所述的显示面板的驱动方法，其中，在空白时间阶段内对各所述数据线加载所述补偿电压的显示帧中，具有第一显示帧和第二显示帧；
    所述第一显示帧对应第一刷新频率，所述第二显示帧对应第二刷新频率；并且所述第一刷新频率大于所述第二刷新频率；
    所述第一显示帧中空白时间阶段的维持时长小于所述第二显示帧中空白时间阶段的维持时长。
  5. 如权利要求3所述的显示面板的驱动方法，其中，将在空白时间阶段内对各所述数据线加载所述补偿电压的显示帧定义为设定显示帧；相邻的两个设定显示帧中，针对同一条数据线，在上一个设定显示帧中加载于所述数据线的第一子补偿电压与所述公共电极电压之间具有第一差值，在下一个设定显示帧中加载于所述数据线的第一子补偿电压与所述公共电极电压之间具有第二差值；
    所述第一差值的绝对值等于所述第二差值的绝对值。
  6. 如权利要求3所述的显示面板的驱动方法，其中，所述补偿电压还包括在所述第一子补偿电压之前出现的过渡补偿电压；
    针对每一条所述数据线，在所述数据线上加载的过渡补偿电压对应的极性与所述数据线连接的子像素对应的极性相同。
  7. 如权利要求1所述的显示面板的驱动方法，其中，所述显示面板采用列反转方式或帧反转方式；所述补偿电压包括第二子补偿电压；
    针对每一条所述数据线，在所述数据线上加载的第二子补偿电压对应的极性与所述数据线连接的子像素中的数据电压对应的极性相同。
  8. 如权利要求1-7任一项所述的显示面板的驱动方法，其中，将在空白时间阶段内对各所述数据线加载所述补偿电压的显示帧定义为设定显示帧；
    所述连续多个显示帧中的部分显示帧为所述设定显示帧；
    所述连续多个显示帧中，除所述设定显示帧之外的显示帧为非设定显示帧；
    所述非设定显示帧包括：
    数据刷新阶段，对所述显示面板中的栅线加载栅极开启电压，对数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；
    空白时间阶段，对所述显示面板中的栅线加载栅极关闭电压，并使各所述数据线浮接。
  9. 如权利要求8所述的显示面板的驱动方法，其中，相邻的两个所述设定显示帧之间具有至少一个所述非设定显示帧。
  10. 如权利要求9所述的显示面板的驱动方法，其中，每相邻的两个所述设定显示帧之间具有的所述非设定显示帧的数量相同。
  11. 如权利要求1-7任一项所述的显示面板的驱动方法，其中，各所述数据线加载的所述补偿电压对应的灰阶相同。
  12. 如权利要求11所述的显示面板的驱动方法，其中，针对每一条所述数据线，所述数据线上加载的所述补偿电压对应的灰阶与所述数据线连接的子像素中的一个数据电压对应的灰阶相同。
  13. 如权利要求12所述的显示面板的驱动方法，其中，采用如下公式，确定所述补偿电压对应的灰阶；
    VS11＝(VA12+VA12)/2；
    其中，VS11代表所述补偿电压对应的灰阶，VA11代表从所述连续的多个显示帧中选取的一个显示帧中的最大灰阶，VA12代表从所述连续的多个显示帧中选取的所述显示帧中最小灰阶，且VA11+VA12为偶数。
  14. 如权利要求12所述的显示面板的驱动方法，其中，采用如下公式，确定所述补偿电压对应的灰阶；
    VS21＝(VA21+VA22+1)/2；
    其中，VS21代表所述补偿电压对应的灰阶，VA21代表从所述连续的多个显示帧中选取的一个显示帧中的最大灰阶，VA22代表从所述连续的多个显示帧中选取的所述显示帧中最小灰阶，且VA21+VA22为奇数。
  15. 如权利要求1-7任一项所述的显示面板的驱动方法，其中，所述对各所述数据线加载补偿电压，包括：
    在所述设定显示帧的空白时间阶段中，从所述多个显示帧中选取一个显示帧，并针对每一条所述数据线，对所述数据线加载选取的所述显示帧输入所述显示面板内一行子像素的数据电压对应灰阶的电压。
  16. 如权利要求15所述的显示面板的驱动方法，其中，所述对各所述数据线加载补偿电压，包括：
    在所述设定显示帧的空白时间阶段中，从所述多个显示帧中选取一个显 示帧，并针对每一条所述数据线，对所述数据线加载选取的所述显示帧输入所述显示面板内最后一行子像素的数据电压对应灰阶的电压。
  17. 如权利要求1-7任一项所述的显示面板的驱动方法，其中，所述对各所述数据线加载补偿电压，包括：
    在所述设定显示帧的空白时间阶段中，从所述多个显示帧中选取一个显示帧，并针对每一条所述数据线，对所述数据线依次加载选取的所述显示帧输入所述数据线上的数据电压对应灰阶的电压。
  18. 如权利要求或14-17任一项所述的显示面板的驱动方法，其中，从所述多个显示帧中选取的所述显示帧为所述设定显示帧相邻的上一个显示帧和所述设定显示帧中的一个。
  19. 一种显示驱动电路，所述显示面板工作于连续的多个显示帧，每个显示帧包括数据刷新阶段和空白时间阶段；
    所述显示驱动电路被配置为：
    在连续的多个显示帧中的至少一个所述显示帧的数据刷新阶段内，对所述显示面板中的栅线加载栅极开启电压，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；
    在至少一个所述显示帧的空白时间阶段内，对所述显示面板中的栅线加载栅极关闭电压，并对各所述数据线加载补偿电压；
    其中，在所述数据线连接的子像素中的数据电压大于公共电极电压时，所述数据线上加载的补偿电压小于所述数据线连接的子像素中的数据电压；
    在所述数据线连接的子像素中的数据电压小于公共电极电压时，所述数据线上加载的补偿电压大于所述数据线连接的子像素中的数据电压。
  20. 一种显示装置，包括显示面板以及时序控制器；所述显示面板包括多条栅线、多条数据线、源极驱动电路以及栅极驱动电路；其中，所述源极驱动电路与所述多条数据线耦接；所述栅极驱动电路与所述多条栅线耦接；
    所述时序控制器与所述源极驱动电路以及所述栅极驱动电路耦接；
    所述时序控制器被配置为在连续的多个显示帧中的至少一个所述显示帧 的数据刷新阶段内，对所述栅极驱动电路输入第一栅极驱动信号，对所述源极驱动电路输入第一源极驱动信号；以及在至少一个所述显示帧的空白时间阶段内，对所述栅极驱动电路输入第二栅极驱动信号，对所述源极驱动电路输入第二源极驱动信号；
    所述栅极驱动电路被配置为根据接收到所述第一栅极驱动信号，对所述显示面板中的栅线加载栅极开启电压；以及根据接收到的所述第二栅极驱动信号，对所述显示面板中的栅线加载栅极关闭电压；
    所述源极驱动电路被配置为根据接收到所述第一源极驱动信号，对各数据线加载待显示图像的数据电压，以使各子像素输入相应的数据电压；以及根据接收到所述第二源极驱动信号，对各所述数据线加载补偿电压。
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