WO2023216385A1 - 命令处理电路及数据处理电路 - Google Patents

命令处理电路及数据处理电路 Download PDF

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Publication number
WO2023216385A1
WO2023216385A1 PCT/CN2022/101688 CN2022101688W WO2023216385A1 WO 2023216385 A1 WO2023216385 A1 WO 2023216385A1 CN 2022101688 W CN2022101688 W CN 2022101688W WO 2023216385 A1 WO2023216385 A1 WO 2023216385A1
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Prior art keywords
flip
processing circuit
flop
command
target
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PCT/CN2022/101688
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English (en)
French (fr)
Inventor
常利平
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长鑫存储技术有限公司
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Priority to US18/150,803 priority Critical patent/US20230368823A1/en
Publication of WO2023216385A1 publication Critical patent/WO2023216385A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

  • Embodiments of the present application relate to the field of semiconductor technology, and in particular, to a command processing circuit and a data processing circuit.
  • memory chips are used to store data, and the process of writing data to the memory chip is implemented under the control of the internal write command (IWR, internal write command).
  • the controller can first send the internal write command IWR to the memory chip, and then send the data to be written (DQ, data) and the corresponding data strobe signal (DQS, data strobe signal) to the memory chip after the preset clock cycle. To instruct the memory chip to store DQ according to the IWR and DQS.
  • the process of the memory chip storing DQ according to the IWR and DQS may include the following main steps: First, the memory chip inputs the IWR and DQS into an IWR processing circuit, which includes multiple sequentially arranged IWR processing circuits. The trigger is used to sample the IWR according to the switching of DQS to obtain the sampling command; then, the memory chip samples the DQ according to the sampling command to obtain the data to be written to the memory chip.
  • Embodiments of the present disclosure provide a command processing circuit and a data processing circuit to improve data writing accuracy.
  • embodiments of the present disclosure provide a command processing circuit, including: a plurality of flip-flops arranged in sequence, the output end of the previous flip-flop is connected to the input end of the next flip-flop, and the plurality of flip-flops
  • the device is used to sample the internal write command input into the command processing circuit to obtain a sampling command according to the switching of the data strobe signal, and the sampling command is used to sample the data;
  • the output end of a target flip-flop among the plurality of flip-flops is connected to the target end of the first flip-flop, and the target flip-flop is a flip-flop whose time of outputting the effective level overlaps with the target time,
  • the target time is the start time and/or end time of the pulse in the internal write command;
  • the target flip-flop is used to reset the internal write command in the first flip-flop by outputting a valid level.
  • the target terminal includes at least one of the following: a reset terminal and an input terminal.
  • the command processing circuit further includes a logic processing circuit
  • One input terminal of the logic processing circuit is connected to the output terminal of the target flip-flop, the other input terminal of the logic processing circuit inputs the internal write command, and the output terminal of the logic processing circuit is connected to the first Connect the input terminal of the above trigger;
  • the logic processing circuit is configured to input reset data into the first flip-flop when the target flip-flop outputs a valid level and the internal write command is a valid level.
  • the logic processing circuit includes an inverter and an AND gate, the output end of the target flip-flop is connected to the input end of the inverter, and the output end of the inverter is connected to the AND gate.
  • One input terminal is connected, and the other input terminal of the AND gate inputs the internal write command.
  • the output end of one of the target flip-flops is connected to the reset end of the first flip-flop, and the output end of the other target flip-flop is connected to the reset end of the first flip-flop.
  • One input terminal of the logic processing circuit is connected.
  • the target trigger includes at least one of the following: the second trigger and the sixth trigger.
  • the output terminal of the second flip-flop is connected to the input terminal of the first flip-flop, and the output terminal of the sixth flip-flop is connected to an input terminal of the logic processing circuit.
  • the pulse width of the internal write command is one or two clock cycles.
  • the effective level is high level.
  • any two adjacent flip-flops use data strobe signals with opposite phases.
  • the overlap duration between the time when the target flip-flop outputs the effective level and the target time is less than half of the pulse width.
  • the output of the seventh flip-flop is used as the sampling command.
  • an embodiment of the present disclosure provides a data processing circuit, which includes a data sampling circuit and the aforementioned command processing circuit.
  • the data sampling circuit is configured to sample data according to a sampling command output by the command processing circuit.
  • the data processing circuit further includes: a strobe signal receiving circuit, the strobe signal receiving circuit is connected to the command processing circuit through a delay circuit, the delay circuit is used to receive the strobe signal.
  • the data strobe signal received by the circuit is delayed, and the delayed data strobe signal is sent to the command processing circuit.
  • the data processing circuit further includes: a command generation circuit connected to the command processing circuit, configured to generate the internal write command and send the internal write command to the command processing circuit.
  • a command generation circuit connected to the command processing circuit, configured to generate the internal write command and send the internal write command to the command processing circuit.
  • the command processing circuit and data processing circuit include: multiple flip-flops arranged in sequence, the output end of the previous flip-flop is connected to the input end of the next flip-flop, and the multiple flip-flops are used to select communication according to the data.
  • the internal write command input to the command processing circuit is sampled to obtain the sampling command.
  • the sampling command is used to sample and process the data; the output end of the target flip-flop among multiple flip-flops is connected to the output end of the first flip-flop.
  • the target end is connected.
  • the target flip-flop is a flip-flop whose output effective level time overlaps with the target time.
  • the target time is the start time and/or end time of the pulse in the internal write command; the target flip-flop is used to pass the output Valid level, resets the internal write command in the first flip-flop.
  • This disclosure uses a target flip-flop to reset the starting position and/or end position of the internal write command in the first flip-flop, which can avoid repeated sampling of the internal write command due to rising or falling edge changes, and improve improve data writing accuracy.
  • Figure 1 is a schematic diagram of the relationship between an internal write command IWR and a data strobe signal DQS provided by an embodiment of the present application;
  • Figure 2 is a schematic diagram of a data writing error scenario provided by an embodiment of the present application.
  • FIGS. 3 to 6 are schematic structural diagrams of four command processing circuits provided by embodiments of the present application.
  • Figure 7 is a data writing timing diagram provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a data processing circuit provided by an embodiment of the present application.
  • the inventor found that when the preamble time between two adjacent internal write commands IWR is 2 clock cycles, the data writing accuracy of the memory chip is low.
  • the specification stipulates that when the above preparation time is 1 clock cycle, the phase deviation between the clock signal CKT and the data strobe signal DQS is allowed within 0.27 clock cycles.
  • the phase deviation between the clock signal CKT and the data strobe signal DQS is allowed to be within the range of 0.5 clock cycles.
  • the pulse width of the internal write command can be different. For example, when the phase deviation is allowed to be around 0.27 clocks, the pulse width of the internal write command IWR can be 0.5 clock cycles. When the phase deviation is allowed within the range around 0.5 clocks, the pulse width of the internal write command IWR needs to be set to 2 clock cycles.
  • FIG. 1 is a schematic diagram of the relationship between an internal write command IWR and a data strobe signal DQS provided by an embodiment of the present application.
  • the pulse width of the internal write command IWR1 is 1 clock cycle
  • the pulse width of the internal write command IWR2 is 2 clock cycles.
  • the data strobe signal DQS_T samples the internal write command through the rising edge
  • the data strobe signal DQS_B samples the internal write command through the falling edge.
  • the rising edge of the data strobe signal DQS_T or the falling edge of the data strobe signal DQS_B corresponds to the middle position of the pulse of IWR1, so that the pulse can be sampled. Since the width of IWR1 is one clock signal, one pulse in IWR1 corresponds to at most one rising edge of DQS_T and one falling edge of DQS_B. In other words, the next rising edge of DQS_T and the next falling edge of DQS_B both appear after the end of the pulse.
  • the rising edge of the data strobe signal DQS_T or the falling edge of the data strobe signal DQS_B corresponds to the middle position of the pulse of IWR2, so that the pulse is sampled. Since the width of IWR2 is 2 clock signals, the end position of a pulse of IWR2 corresponds to a rising edge of DQS_T and a falling edge of DQS_B.
  • the rising edge of the internal write command IWR2 may change, or the data strobe signal may change.
  • the rising edge of the DQS signal changes, resulting in repeated sampling of the internal write command, which in turn leads to data writing errors when sampling data according to the sampling command.
  • FIG. 2 is a schematic diagram of a data writing error scenario provided by an embodiment of the present application.
  • the pulse width of the internal write command IWR2 is two clock cycles of the clock signal CKT, and the preparation time between the pulses of two adjacent internal write commands is also two clock cycles of the clock signal CKT.
  • the data strobe signal DQS includes two types: DQS_T and DQS_B, both of which have opposite phases. Both can sample internal write commands, but the sampling timing is different. Among them, DQS_T can sample the internal write command IWR2 through the rising edge, and DQS_B can sample the internal write command IWR2 through the falling edge.
  • the first rising edge E1 of DQS_T can sample the first pulse of the internal write command IWR2, and thus obtain the first internal write command.
  • the first falling edge E3 of DQS_B can also sample the first pulse of the internal write command IWR2, and thus obtain the first internal write command.
  • the falling edge or rising edge of the pulse may vary.
  • E2 of DQS_T in Figure 2 if its variation becomes E2 in DQS_T' in Figure 2, Then, the two rising edges E1 and E2 of DQS_T' both sample the first pulse of the internal write command IWR2, causing the first internal write command to be repeatedly sampled.
  • the starting position of the pulse of the internal write command IWR2 may also cause repeated sampling due to the changing rising edge of DQS_T, and/or the changing falling edge of DQS_T, and/or the changing falling edge of DQS_B.
  • the embodiment of the present application can reset the starting position and/or the ending position of each pulse of the internal write command IWR2 to avoid repeated sampling caused by mutations.
  • how to accurately ensure that the start position and/or end position of the pulse of the internal write command IWR2 is reset is the key to solving the problem.
  • the inventor After analyzing the IWR2 processing circuit for sampling internal write commands, the inventor found that it includes multiple flip-flops arranged in sequence.
  • the input of the first flip-flop is the internal write command.
  • Each flip-flop can be configured according to the data strobe signal DQS.
  • the switch uses the output of the previous flip-flop as the output of the current flip-flop.
  • a target flip-flop can be selected whose output will reset the start and/or end position of the internal write command.
  • the target flip-flop is a flip-flop whose time of outputting a valid level overlaps with the target time.
  • the target time is the start time and/or end time of the pulse in the internal write command.
  • the start time corresponds to the internal write command IWR2.
  • the starting position of the pulse in and the end time corresponds to the end position of the pulse in the internal write command IWR2.
  • the target flip-flop when the target flip-flop outputs a valid level, the pulse of the internal write command IWR2 reaches the starting position or the end position, so that the valid level can accurately reset the starting position or the end position, that is, the target flip-flop can Accurately reset the starting position and/or ending position of the pulse of the internal write command IWR2.
  • the above-mentioned command processing circuit 100 may include: multiple flip-flops 101 arranged in sequence. The output end of the previous flip-flop 101 is connected to the input end of the next flip-flop 101 .
  • the multiple flip-flops 101 use According to the switching of the data strobe signal, the internal write command input to the command processing circuit 100 is sampled to obtain a sampling command, and the sampling command is used to sample data.
  • the output end of the target flip-flop in the plurality of flip-flops 101 is connected to the target end of the first flip-flop 101.
  • the target flip-flop is a flip-flop whose output effective level time overlaps with the target time.
  • the target time is an internal write command The start time and/or end time of the pulse in .
  • the target flip-flop is used to reset the internal write command in the first flip-flop by outputting a valid level.
  • the embodiment of the present application aims to solve the above-mentioned repeated sampling problem of the internal write command with a pulse width of 2 clock cycles, the first flip-flop is reset through the target flip-flop.
  • the target flip-flop in the embodiment of the present application is a flip-flop whose effective level overlaps with the target time of the pulse, so that the reset is performed by the effective level, the embodiment of the present application can also be applied to a trigger with a pulse width of 1 clock cycle.
  • the processing of internal write commands is not limited to the internal write commands of 2 clock cycles.
  • DFF D flip-flop
  • FIG. 6 is a schematic structural diagram of a command processing circuit composed of seven flip-flops provided by an embodiment of the present application. Referring to Figure 6, the input of the command processing circuit is used as the input of the first flip-flop, and the output of the last flip-flop, that is, the output of the seventh flip-flop, is used as the output of the command processing circuit, and the output is the obtained sampling command.
  • the above flip-flop has multiple ports: input terminal I, output terminal O, reset terminal R and clock terminal C.
  • the input terminal I is a port for inputting data.
  • the input data of the input terminal I of the first flip-flop is an internal command write command
  • the input data of the input terminal I of the subsequent flip-flop is the previous The data output from the output terminal O of a flip-flop.
  • the output terminal O is used to output data.
  • the output data of the output terminal O of the last flip-flop is used as the output data of the command processing circuit, and the output data of the output terminals O of the remaining flip-flops is input to the next flip-flop. input terminal.
  • the reset terminal R is used to reset the data in the flip-flop when receiving a valid level, that is, to set it to an invalid level.
  • a valid level that is, to set it to an invalid level.
  • the valid level is high level
  • the invalid level is low level.
  • the valid level is low level
  • the invalid level is high level.
  • the target terminal can be the input terminal I and/or the reset terminal R.
  • the target terminal is the reset terminal R, since the reset terminal R functions as reset, as shown in Figure 4, the output terminal O of the target flip-flop is directly connected to the reset terminal R, and reset can be achieved.
  • the target terminal is the input terminal I, since the input terminal I functions as an input and is not a reset, as shown in Figure 5, a logic processing circuit needs to be passed between the output terminal O and the input terminal I of the target flip-flop.
  • the logic processing circuit is used to logically process the output data of the target flip-flop to achieve reset.
  • the embodiment of the present application can realize reset through multiple ports of the first flip-flop, so that when one port is abnormal, reset can be realized through the remaining ports, which helps to improve the reset success rate and thereby improve the accuracy of data writing. Spend.
  • the start position and end position of the internal write command can be reset simultaneously through two ports to avoid repeated sampling caused by start position variation or end position variation to further improve writing accuracy.
  • FIG. 5 is a schematic structural diagram of another command processing circuit provided by an embodiment of the present application.
  • one input terminal of the above-mentioned logic processing circuit is connected to the output terminal O of the target flip-flop, the other input terminal of the logic processing circuit inputs an internal write command, and the output terminal of the logic processing circuit is connected to the output terminal O of the first flip-flop. Input I connection.
  • the above logic processing circuit is used to input reset data into the first flip-flop when the target flip-flop outputs a valid level and the internal write command is a valid level. It can be understood that since the target flip-flop is a flip-flop whose output valid level time overlaps with the target time, and the target time is the start time and/or end time of the pulse of the internal write command, therefore, the target flip-flop output When the level is valid, the internal write command corresponds to the end position or starting position. At this time, if the internal write command is at a valid level, the valid level of the internal write command can be reset to an invalid level, thereby resetting the start position and/or end position of the internal write command.
  • the embodiment of the present application can not only realize the reset directly through the reset terminal, but also can realize the reset by combining the input terminal and the logic processing circuit. That is to say, the reset is achieved through the auxiliary input terminal of the logic processing circuit, so that the input terminal also has the reset function.
  • the internal write command when the internal write command is at a valid level, if the internal write command is directly input into the command processing circuit, sampling is performed and the sampling command is at a valid level. At this time, if a rising edge or falling edge mutation occurs, the effective level may be repeatedly collected. In other words, the same pulse corresponding to the internal write command may correspond to two sampling commands obtained by sampling. pulse. Although the internal write command is a valid level, the signal input to the command processing circuit through the above scheme is an invalid level. Therefore, even if a rising edge mutation or falling edge mutation occurs, the sampling command obtained by sampling is also an invalid level. This will not cause internal write commands to be sampled repeatedly.
  • the logic processing circuit may include an inverter and an AND gate.
  • the output terminal O of the target flip-flop is connected to the input terminal of the inverter.
  • the output terminal of the inverter is connected to an input terminal of the AND gate.
  • the AND gate The other input of the gate enters the internal write command.
  • the input-output relationship of the logic processing circuit shown in Figure 5 above can have the following types:
  • the first type is that the target flip-flop outputs a high level and the internal write command is a high level. At this time, the output is a low level.
  • the above-mentioned valid level is high level and the invalid level is low level, this input-output relationship can realize the reset of the internal write command.
  • the target flip-flop outputs high level and the internal write command is low level. At this time, the output is low level. It can be seen that the output level is consistent with the internal write command, that is, the internal write command is not processed. At this time, the internal write command actually input to the first flip-flop is consistent with the original internal write command.
  • the third type is that the target flip-flop outputs low level and the internal write command is high level. At this time, the output is high level. Similarly, it can be seen that the output level is consistent with the internal write command, that is, the internal write command is not processed. At this time, the internal write command actually input to the first flip-flop is the same as the original internal write command. consistent.
  • the fourth type is that the target flip-flop outputs low level and the internal write command is low level. At this time, the output is low level. When the above-mentioned valid level is low level and the invalid level is high level, this input-output relationship can realize the reset of the internal write command.
  • the embodiment of the present application can not only realize the reset of the high level to the effective level through the first input-output relationship, but also realize the reset of the low level to the effective level through the fourth input-output relationship.
  • the embodiment of the present application can accurately realize reset through a logic processing circuit composed of an inverter and an AND gate, and because the inverter and the AND gate are common logic gates, its implementation cost is low and its application scenarios are wide. .
  • the above target trigger can be two.
  • the output terminal O of one target flip-flop is connected to the reset terminal R of the first flip-flop, and the output terminal O of the other target flip-flop is connected to an input terminal of the logic processing circuit.
  • the start position of the internal write command can be reset, but also the end position can be reset, while avoiding repeated sampling caused by changes in the start position and end position.
  • one target flip-flop can be set, and its output end is connected to the reset end of the first flip-flop or the logic processing circuit, thereby only avoiding repeated sampling caused by changes in the start position or the end position.
  • the target flip-flop outputs a valid level overlaps with the end time of the pulse of the internal write command, whether the output end of the target flip-flop is connected to the reset end or is connected to the input end through the logic processing circuit, the The end position can be reset.
  • the output end of the target flip-flop is connected to the reset end or is connected to the input end through the logic processing circuit. Both can achieve reset to the starting position.
  • the target flip-flop that satisfies the time when the output effective level overlaps with the target time may include at least one of the following: a second flip-flop and a sixth flip-flop.
  • the second flip-flop and the sixth flip-flop are the first target flip-flops that meet the following conditions: the time when the effective level is output overlaps with the target time. Therefore, the embodiment of the present application can realize the reset through the second flip-flop and the sixth flip-flop. In this way, the reset only needs to be ensured that the number of flip-flops is greater than or equal to 6.
  • the embodiment of the present application can reduce the number of flip-flops as much as possible, thereby reducing the circuit size.
  • FIG. 6 is a schematic structural diagram of yet another command processing circuit provided by an embodiment of the present application.
  • the command processing circuit includes seven flip-flops, and the output of the seventh flip-flop serves as the sampling command.
  • the output terminal O of the second flip-flop is connected to the input terminal I of the first flip-flop. That is to say, the output terminal O of the second flip-flop is connected to the first flip-flop through a logic processing circuit.
  • the input terminal I is connected, and the output terminal O of the sixth flip-flop is connected with the reset terminal R of the logic processing circuit.
  • the second flip-flop is closer to the first flip-flop, and the sixth flip-flop is farther from the first flip-flop.
  • the output of the second flip-flop can be connected to the input of the first flip-flop through a logic processing circuit, and the output of the sixth flip-flop can be connected.
  • the output is directly connected to the reset terminal of the first flip-flop, so that the processing of the logic processing circuit further increases the duration of the output of the second flip-flop to the input terminal of the first flip-flop, making the second flip-flop as It is close to the reset duration of the sixth flip-flop.
  • the output terminal O of the sixth flip-flop can also be connected to the input terminal I of the first flip-flop. That is to say, the output terminal O of the sixth flip-flop passes through The logic processing circuit is connected to the input terminal I of the first flip-flop, and the output terminal O of the second flip-flop is connected to the reset terminal of the logic processing circuit.
  • the overlap time between the time when the target flip-flop outputs the active level and the target time is less than half of the pulse width. In this way, it can not only ensure that the end position and/or starting position of the internal write command can be reset to avoid repeated sampling, but also avoid that the reset length is too long, causing the middle position of the internal write command to be reset, resulting in internal write errors after reset. The command cannot be sampled.
  • Figure 7 is explained using Figure 7 as an example.
  • Figure 7 is a data writing sequence diagram provided by an embodiment of the present application.
  • D1 to D7 are the outputs of each flip-flop arranged from left to right in Figure 6 respectively.
  • the effective level below is high level.
  • the high level overlaps in time with the pulse end position of the internal write command IWR2 by 1 clock cycle, which is a lot of overlap. If D1 is used for reset, the end position of the internal write command after reset is advanced by 1 clock cycle, causing the rising edge of the data strobe signal DQS_T or the falling edge of DQS_B to correspond to the end position of the internal write command after reset, resulting in The internal write command cannot be sampled.
  • the first high level overlaps in time with the end position of the first pulse of the internal write command IWR2 by 0.5 clock cycles. If D2 is used for reset, then, as shown in Figure 7, the end position of the first pulse of the internal write command IWR2’ after reset is advanced by 0.5 clock cycles. Therefore, on the one hand, the rising edge of the data strobe signal DQS_T or the falling edge of DQS_B corresponds to the high level position of IWR2' after reset, which can ensure normal sampling of this pulse.
  • next rising edge of the data strobe signal DQS_T or the next falling edge of DQS_B corresponds to the low level position of IWR2' after reset, the next rising edge of DQS_T or the next falling edge of DQS_B does not The pulse is sampled repeatedly.
  • the first high level overlaps in time with the second pulse starting position of the internal write command IWR2 by 0.5 clock cycles. If D6 is used for reset, then, as shown in Figure 7, the starting position of the second pulse of the internal write command IWR2’ after reset is delayed by 0.5 clock cycles. Therefore, on the one hand, the rising edge of the data strobe signal DQS_T or the falling edge of DQS_B corresponds to the high level position of IWR2' after reset, which can ensure normal sampling of this pulse.
  • next rising edge of the data strobe signal DQS_T or the next falling edge of DQS_B corresponds to the low level position of IWR2' after reset, the next rising edge of DQS_T or the next falling edge of DQS_B does not The pulse is sampled repeatedly.
  • the pulse width of the internal write command may be one or two clock cycles. Therefore, not only can repeated sampling under a pulse width of two clock cycles be avoided, but normal sampling of a pulse width of one clock cycle can also be supported, making the processing circuits of the two pulse widths unified.
  • any two adjacent flip-flops use data strobe signals with opposite phases.
  • FIG. 6 there are 7 flip-flops.
  • the clock terminal C of the first, third, fifth and seventh flip-flops inputs the data strobe signal DQS_T.
  • the clock terminal C of the six flip-flops inputs the data strobe signal DQS_B. Since DQS_T and DQS_B are two signals with opposite phases, any two adjacent flip-flops can use data strobe signals with opposite phases.
  • the embodiment of the present application can improve the sampling speed of internal write commands by multiple flip-flops through the above two data strobe signals with opposite phases.
  • An embodiment of the present application also provides a data processing circuit, including a data sampling circuit and the aforementioned command processing circuit.
  • the data sampling circuit is used to sample data according to the sampling command output by the command processing circuit.
  • the embodiment of the present application can ensure through the command processing circuit that the starting position and/or the ending position of the sampling command used when sampling data is reset, thereby preventing the pulse of the same internal write command from being sampled repeatedly. Furthermore, the accuracy of data sampling during data sampling can be guaranteed and the accuracy of data writing can be improved.
  • FIG. 8 is a schematic structural diagram of a data processing circuit provided by an embodiment of the present application. Please refer to Figure 8.
  • the data processing circuit 10 also includes: a strobe signal receiving circuit 12.
  • the strobe signal receiving circuit 12 is connected to the command processing circuit 100 through a delay circuit 13.
  • the delay circuit 13 is used to delay the data strobe signal received by the strobe signal receiving circuit 12, and send the delayed data strobe signal to the command processing circuit 100.
  • the function of the delay circuit is to delay the data strobe signal to ensure synchronization between the data strobe signal and the internal command signal, that is, to ensure that both arrive at the command processing circuit at the same time. In this way, it is ensured that the data strobe signal samples the corresponding internal command signal, thereby further improving the writing accuracy.
  • the delay circuit may use a delay parameter for delay, and the delay parameter may be determined based on a difference between a transmission path of the data strobe signal and a transmission path of the internal write command. That is, the delay circuit is used to compensate for the routing differences between the data strobe signal and the internal write command.
  • the starting transmission position of the data strobe signal and the starting transmission position of the internal write command are located on both sides of the entire circuit, and the transmission path of the data strobe signal is shorter than the transmission path of the internal write command.
  • the starting transmission position of the data strobe signal may be the position where the strobe signal receiving circuit 12 in FIG. 8 is located, and the starting transmission position of the internal write command may be the position where the command generating circuit 14 is located.
  • a delay circuit can be set on the transmission path of the internal write command to delay the internal write command so that It arrives at the command processing circuit synchronously with the data strobe signal.
  • the data processing circuit 10 may further include: a command generation circuit 14 connected to the command processing circuit 100 for generating an internal write command and sending the internal write command to the command processing circuit 100 .
  • the data processing circuit of the embodiment of the present application can integrate multiple functions, so that one circuit can complete the generation of internal write commands, command sampling, and data sampling, which helps to improve the integration level of the circuit.
  • the command generation circuit here can also be called TDQSS GEN (TDQSS generation, skew generation between clock signal and DQS) circuit.
  • the command generation circuit here can be externally connected to the command address line to generate an internal write command based on the electrical signal on the command address line.
  • the command address lines here can include multiple types: CSB (cloud service bus, cloud service bus), ACTB, RASB, CASB, WEB.

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Abstract

本申请提供一种命令处理电路及数据处理电路，包括：多个触发器，前一个触发器的输出端与后一个触发器的输入端连接，用于根据数据选通信号的切换，对输入到命令处理电路中的内部写命令进行采样得到采样命令，以对数据进行采样处理。目标触发器的输出端与第一个触发器的目标端连接，目标触发器为输出有效电平的时间与目标时间存在重叠的触发器，目标时间是内部写命令的脉冲的起始时间、结束时间。目标触发器用于通过输出有效电平，将第一个触发器中的内部写命令进行复位。本申请通过目标触发器对第一个触发器中的内部写命令的起始位置和/或结束位置进行复位，可以避免由于上升沿异变或下降沿异变导致的内部写命令重复采样，提高了数据写入准确度。

Description

命令处理电路及数据处理电路
本申请要求于2022年05月13日提交中国专利局、申请号为202210521967.9、申请名称为“命令处理电路及数据处理电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种命令处理电路及数据处理电路。
背景技术
在半导体技术领域中，内存芯片用于存储数据，向内存芯片写入数据的过程是在内部写命令(IWR，internal write command)的控制下实现的。控制器可以向内存芯片先发送内部写命令IWR，并在经过预设时钟周期后向内存芯片发送要写入的数据(DQ，data)和对应的数据选通信号(DQS，data strobe signal)，以指示内存芯片根据该IWR和DQS将DQ进行存储。
现有技术中，内存芯片根据该IWR和DQS将DQ进行存储的过程可以包括以下主要步骤：首先，内存芯片将IWR和DQS输入到一IWR处理电路中，该IWR处理电路包括顺序排列的多个触发器，以根据DQS的切换对IWR进行采样得到采样命令；然后，内存芯片根据采样命令对DQ进行采样得到待写入数据，以写入内存芯片。
然而，上述方案存在数据写入准确度较低的问题。
发明内容
本公开实施例提供一种命令处理电路及数据处理电路，以提高数据写入准确度。
一方面，本公开实施例提供一种命令处理电路，包括：顺序排列的多个触发器，前一个所述触发器的输出端与后一个所述触发器的输入端连接，所述多个触发器用于根据数据选通信号的切换，对输入到所述命令处理电路中的内部写命令进行采样得到采样命令，所述采样命令用于对数据进行采样处理；
所述多个触发器中的目标触发器的输出端与第一个所述触发器的目标端连接，所述目标触发器为输出所述有效电平的时间与目标时间存在重叠的触发器，所述目标时间是所述内部写命令中的脉冲的起始时间和/或结束时间；
所述目标触发器，用于通过输出有效电平，将第一个所述触发器中的内部写命令进行复位。
可选地，所述目标端包括以下至少一个：复位端和输入端。
可选地，当所述目标端包括输入端时，所述命令处理电路还包括逻辑处理电路；
所述逻辑处理电路的一个输入端与所述目标触发器的输出端连接，所述逻辑处理电路的另一输入端输入所述内部写命令，所述逻辑处理电路的输出端与第一个所述触发器的输入端连接；
所述逻辑处理电路，用于在所述目标触发器输出有效电平且所述内部写命令为有效电平时，向第一个所述触发器中输入复位数据。
可选地，所述逻辑处理电路包括反相器和与门，所述目标触发器的输出端与所述反相器的输入端连接，所述反相器的输出端与所述与门的一个输入端连接，所述与门的另一输入端输入所述内部写命令。
可选地，当所述目标触发器为两个时，其中一个所述目标触发器的输出端与第一个所述触发器的复位端连接，另一个所述目标触发器的输出端与所述逻辑处理电路的一个输入端连接。
可选地，所述目标触发器包括以下至少一个：第二个所述触发器和第六个所述触发器。
可选地，第二个所述触发器的输出端与第一个所述触发器的输入端连接，第六个所述触发器的输出端与所述逻辑处理电路的一个输入端连接。
可选地，所述内部写命令的脉冲宽度为一个或两个时钟周期。
可选地，所述有效电平为高电平。
可选地，任意相邻两个所述触发器使用相位相反的数据选通信号。
可选地，所述目标触发器输出所述有效电平的时间与所述目标时间的重叠时长小于脉冲宽度的一半。
可选地，所述触发器为7个，第七个所述触发器的输出作为所述采样命令。
另一方面，本公开实施例提供一种数据处理电路，包括数据采样电路和前述命令处理电路，所述数据采样电路用于根据所述命令处理电路输出的采样命令，对数据进行采样。
可选地，所述数据处理电路还包括：选通信号接收电路，所述选通信号接收电路通过一延迟电路与所述命令处理电路连接，所述延迟电路用于对所述选通信号接收电路接收到的数据选通信号进行延迟，并将延迟处理之后的数据选通信号发送给所述命令处理电路。
可选地，所述数据处理电路还包括：与所述命令处理电路连接的命令生成电路，用于生成所述内部写命令，并将所述内部写命令发送给所述命令处理电路。
本公开实施例提供的命令处理电路及数据处理电路，包括：顺序排列的多个触发器，前一个触发器的输出端与后一个触发器的输入端连接，多个触发器用于根据数据选通信号的切换，对输入到命令处理电路中的内部写命令进行采样得到采样命令，采样命令用于对数据进行采样处理；多个触发器中的目标触发器的输出端与第一个触发器的目标端连接，目标触发器为输出有效电平的时间与目标时间存在重叠的触发器，目标时间是内部写命令中的脉冲的起始时间和/或结束时间；目标触发器，用于通过输出有效电平，将第一个触发器中的内部写命令进行复位。本公开通过目标触发器对第一个触发器中的内部写命令的起始位置和/或结束位置进行复位，可以避免由于上升沿异变或下降沿异变导致的内部写命令重复采样，提高了数据写入准确度。
附图说明
图1是本申请实施例提供的一种内部写命令IWR和数据选通信号DQS之间的关系示意图；
图2是本申请实施例提供的一种数据写入错误场景示意图；
图3至图6是本申请实施例提供的四种命令处理电路的结构示意图；
图7是本申请实施例提供的一种数据写入时序图；
图8是本申请实施例提供的一种数据处理电路的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
发明人对内存芯片的数据写入过程进行分析之后发现，在相邻两个内部写命令IWR之间的准备(preamble)时间为2个时钟周期时，内存芯片的数据写入准确度较低。规范规定，在上述准备时间为1个时钟周期时，时钟信号CKT和数据选通信号DQS之间的相位偏差允许在0.27个时钟周期内。而在上述准备时间为2个时钟周期时，时钟信号CKT和数据选通信号DQS之间的相位偏差允许在0.5个时钟周期范围内。在这两种不同的相位偏差要求下，内部写命令的脉冲宽度可以不同。例如，在相位偏差允许在0.27个时钟周围时，内部写命令IWR的脉冲宽度可以为0.5个时钟周期即可。而在相位偏差允许在0.5个时钟周围范围内时，内部写命令IWR的脉冲宽度需要设置为2个时钟周期。
然而，随着上述内部写命令的脉冲宽度增大，可能会导致一个脉冲宽度可能对应两个或以上的上升沿，或两个或以上的下降沿。图1是本申请实施例提供的一种内部写命令IWR和数据选通信号DQS之间的关系示意图。参照图1所示，内部写命令IWR1的脉冲宽度为1个时钟周期，内部写命令IWR2的脉冲宽度为2个时钟周期。数据选通信号DQS_T通过上升沿采样内部写命令，数据选通信号DQS_B通过下降沿采样内部写命令。
可以看出，对于脉冲宽度为1个时钟周期的内部写命令IWR1，数据选通信号DQS_T的上升沿或数据选通信号DQS_B的下降沿对应IWR1的脉冲中间位置，以使可以采样到该脉冲。由于IWR1的宽度为一个时钟信号，从而在IWR1的一个脉冲最多对应DQS_T的一个上升沿，以及DQS_B的一个下降沿。也就是说，DQS_T的下一个上升沿，以及DQS_B的下一个下降沿，均在该脉冲结束之后出现。
而对于脉冲宽度为2个时钟周期的内部写命令IWR2，数据选通信号DQS_T的上升沿或数据选通信号DQS_B的下降沿对应IWR2的脉冲中间位置，以使采样到该脉冲。由于IWR2的宽度为2个时钟信号，从而IWR2的一个脉冲结束位置对应DQS_T的一个上升沿，以及DQS_B的一个下降沿。
对于上述脉冲宽度为2个时钟周期的内部写命令IWR2，在通过数据选通信号DQS对 内部写命令IWR2进行采样得到采样命令时，可能出现内部写命令IWR2的上升沿异变，或数据选通信号DQS的上升沿异变，从而，导致对内部写命令的重复采样，进而导致根据采样命令采样数据时，数据写入错误。
图2是本申请实施例提供的一种数据写入错误场景示意图。参照图2所示，内部写命令IWR2的脉冲宽度是时钟信号CKT的两个时钟周期，相邻两个内部写命令的脉冲之间的准备时间也为时钟信号CKT的两个时钟周期。数据选通信号DQS包括DQS_T和DQS_B两种，两者相位相反。两者都可以对内部写命令进行采样，只是采样时机不同。其中，DQS_T可以通过上升沿对内部写命令IWR2进行采样，DQS_B可以通过下降沿对内部写命令IWR2进行采样。
从图2中可以看出，DQS_T的第一个上升沿E1可以采样到内部写命令IWR2的第一个脉冲，也就得到第一个内部写命令。同样地，DQS_B的第一个下降沿E3也可以采样到内部写命令IWR2的第一个脉冲，也就得到第一个内部写命令。
然而，在实际应用中，脉冲的下降沿或上升沿可能出现异变，例如，对于图2中的DQS_T的第二个上升沿E2，如果其异变为图2中的DQS_T’中的E2，那么，DQS_T’的两个上升沿E1和E2均采样到内部写命令IWR2的第一个脉冲，导致第一个内部写命令被重复采样。
同样地，参照图2所示，对于图2中的DQS_B的第二个下降沿E4，如果其异变为图2中的DQS_B’中的E4，那么，DQS_B’的两个上升沿E3和E4均采样到内部写命令IWR2的第一个脉冲，导致第一个内部写命令被重复采样。
可以看出，对于内部写命令IWR2的每个脉冲，其结束位置也可能异变。例如，如图2所示，内部写命令IWR2的第一个脉冲的结束位置可能推后(图2中未给出推后的示例)，这样，也会导致内部写命令IWR2的第一个脉冲被DQS_T的两个上升沿重复采样，或被DQS_B的两个下降沿重复采样。
此外，内部写命令IWR2的脉冲的起始位置也可能由于DQS_T的上升沿异变、和/或DQS_T的下降沿异变、和/或DQS_B的下降沿异变，而导致重复采样。
需要说明的是，在实际应用中，内部写命令IWR的每个脉冲的结束位置都会可能存在上述重复采样的问题。
为了解决上述问题，本申请实施例可以对内部写命令IWR2的每个脉冲的开始位置和/或结束位置进行复位，以避免异变导致的重复采样。但是，如何准确的保证对内部写命令IWR2的脉冲的开始位置和/或结束位置进行复位是解决问题的关键。
发明人对内部写命令进行采样的IWR2处理电路进行分析之后发现，其中包括多个顺序排列的触发器，第一个触发器的输入是内部写命令，每个触发器可以根据数据选通信号DQS的切换将上一触发器的输出作为当前触发器的输出。
基于该发现，可以选取目标触发器，将通过目标触发器的输出对内部写命令的起始位置和/或结束位置进行复位。具体地，该目标触发器是输出有效电平的时间与目标时间存在重叠的触发器，目标时间是内部写命令中的脉冲的起始时间和/或结束时间，起始时间对应内部写命令IWR2中的脉冲的起始位置，结束时间对应内部写命令IWR2中的脉冲的结束位置。可以看出，目标触发器输出有效电平时，内部写命令IWR2的脉冲到达起始位置或结束位置，从而该有效电平可以准确的对起始位置或结束位置进行复位，也就是目标触发 器可以对内部写命令IWR2的脉冲的起始位置和/或结束位置进行准确的复位。
下面以具体地实施例对本申请实施例的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本申请实施例进行描述。
图3至6是本申请实施例提供的多种命令处理电路的结构示意图。请参照图3至图6，上述命令处理电路100可以包括：顺序排列的多个触发器101，前一个触发器101的输出端与后一个触发器101的输入端连接，多个触发器101用于根据数据选通信号的切换，对输入到命令处理电路100中的内部写命令进行采样得到采样命令，采样命令用于对数据进行采样处理。多个触发器101中的目标触发器的输出端与第一个触发器101的目标端连接，目标触发器为输出有效电平的时间与目标时间存在重叠的触发器，目标时间是内部写命令中的脉冲的起始时间和/或结束时间。目标触发器用于通过输出有效电平，将第一个触发器中的内部写命令进行复位。
首先需要说明的是，虽然本申请实施例旨在解决上述脉冲宽度为2个时钟周期的内部写命令的重复采样问题，而通过目标触发器对第一个触发器进行复位。但，由于本申请实施例的目标触发器是有效电平与脉冲的目标时间重叠的触发器，以通过有效电平进行复位，从而本申请实施例还可以适用于脉冲宽度为1个时钟周期的内部写命令的处理过程，并不局限于2个时钟周期的内部写命令。
可以看出，上述触发器用于对内部写命令进行缓存，每个触发器可以将内部写命令缓存一个时钟周期。常用的触发器为D触发器(DFF)。
在实际应用中，上述触发器的数量可以灵活设置。图6是本申请实施例提供的7个触发器构成的命令处理电路的结构示意图。参照图6所示，命令处理电路的输入作为第一个触发器的输入，最后一个触发器的输出也就是第七个触发器的输出作为命令处理电路的输出，该输出为得到的采样命令。
上述触发器具有多个端口：输入端I、输出端O、复位端R和时钟端C。
其中，输入端I是用于输入数据的端口，在本申请实施例中，第一个触发器的输入端I的输入数据是内部命写命令，后续触发器的输入端I的输入数据是前一个触发器的输出端O输出的数据。
输出端O用于输出数据，在本申请实施例中，最后一个触发器的输出端O的输出数据作为命令处理电路的输出数据，其余触发器的输出端O的输出数据输入到下一个触发器的输入端。
复位端R用于在接收到有效电平时，对触发器中的数据进行复位，也就是置为无效电平。当有效电平为高电平时，无效电平为低电平。当有效电平为低电平时，无效电平为高电平。
需要说明的是，目标端可以为输入端I和/或复位端R。当目标端为复位端R时，由于复位端R的作用为复位，从而，参照图4所示，目标触发器的输出端O与复位端R直接连接，即可实现复位。当目标端为输入端I时，由于输入端I的作用为输入，并不是复位，从而，参照图5所示，目标触发器的输出端O与输入端I之间需要经过一逻辑处理电路，该逻辑处理电路用于对目标触发器的输出数据进行逻辑处理，以实现复位。
可以看出，本申请实施例可以通过第一个触发器的多个端口实现复位，从而可以在一 个端口异常时，通过其余端口实现复位，有助于提高复位成功率，进而提高数据写入准确度。并且，还可以通过两个端口同时实现对内部写命令的起始位置和结束位置进行复位，以同时避免起始位置变异或结束位置变异导致的重复采样，以进一步提高写入准确度。
图5是本申请实施例提供的另一种命令处理电路的结构示意图。参照图5所示，上述逻辑处理电路的一个输入端与目标触发器的输出端O连接，逻辑处理电路的另一输入端输入内部写命令，逻辑处理电路的输出端与第一个触发器的输入端I连接。
上述逻辑处理电路，用于在目标触发器输出有效电平且内部写命令为有效电平时，向第一个触发器中输入复位数据。可以理解的是，由于目标触发器为输出有效电平的时间与目标时间存在重叠的触发器，且目标时间是内部写命令的脉冲的起始时间和/或结束时间，从而，目标触发器输出有效电平时，内部写命令对应结束位置或起始位置。此时，如果内部写命令为有效电平，那么可以将内部写命令的有效电平复位为无效电平，也就实现了将内部写命令的起始位置和/或结束位置进行复位。
可以看出，本申请实施例不仅可以通过复位端直接实现复位，还可以结合输入端和逻辑处理电路实现复位。也就是说通过逻辑处理电路辅助输入端实现复位，以使输入端也具有复位的功能。
需要说明的是，当内部写命令为有效电平时，若内部写命令直接输入到命令处理电路中时，进行采样得到采样命令为有效电平。此时，如果出现上升沿或下降沿异变，那么可能会导致该有效电平被重复采集到，也就是说，对应内部写命令的同一个脉冲，在采样得到的采样命令中可能对应两个脉冲。而虽然内部写命令为有效电平，但通过上述方案输入到命令处理电路中的信号是无效电平，从而即使出现上升沿异变或下降沿异变，采样得到的采样命令也是无效电平，从而不会导致内部写命令被重复采样。
可选地，为了使逻辑处理电路实现上述目的：在目标触发器输出有效电平且内部写命令为有效电平时，向第一个触发器中输入复位数据。参照图5所示，逻辑处理电路可以包括反相器和与门，目标触发器的输出端O与反相器的输入端连接，反相器的输出端与与门的一个输入端连接，与门的另一输入端输入内部写命令。
上述图5所示的逻辑处理电路的输入输出关系可以有以下多种：
第一种，目标触发器输出高电平，内部写命令为高电平，此时，输出为低电平。当上述有效电平为高电平时，无效电平为低电平时，这种输入输出关系可以实现对内部写命令的复位。
第二种，目标触发器输出高电平，内部写命令为低电平，此时，输出为低电平。可以看出，输出和内部写命令的电平一致，也就是对内部写命令并未进行处理，此时，实际输入到第一个触发器中的内部写命令和原始的内部写命令一致。
第三种，目标触发器输出低电平，内部写命令为高电平，此时，输出为高电平。同样地，可以看出，输出和内部写命令的电平一致，也就是对内部写命令并未进行处理，此时，实际输入到第一个触发器中的内部写命令和原始的内部写命令一致。
第四种，目标触发器输出低电平，内部写命令为低电平，此时，输出为低电平。当上述有效电平为低电平时，无效电平为高电平时，这种输入输出关系可以实现对内部写命令的复位。
可以看出，本申请实施例不仅可以通过第一种输入输出关系实现高电平为有效电平的 复位，还可以通过第四种输入输出关系实现低电平为有效电平的复位。此外，在第二和第三种方式中，可以保证对内部写命令不进行处理。从而本申请实施例可以通过反相器和与门构成的逻辑处理电路准确的实现了复位，并且由于反相器和与门是常见的逻辑门，从而，其实现成本较低，应用场景较广。
上述目标触发器可以是两个。当目标触发器为两个时，其中一个目标触发器的输出端O与第一个触发器的复位端R连接，另一个目标触发器的输出端O与逻辑处理电路的一个输入端连接。在这种场景下，不仅可以将内部写命令的起始位置进行复位，还可以将结束位置进行复位，同时避免起始位置和结束位置异变导致的重复采样。
当然，在实际应用中，目标触发器可以设置一个，其输出端与第一个触发器的复位端或逻辑处理电路连接，从而，仅可以避免起始位置或结束位置异变导致的重复采样。当目标触发器为输出有效电平的时间与内部写命令的脉冲的结束时间存在重叠的触发器时，目标触发器的输出端无论与复位端连接，还是通过逻辑处理电路与输入端连接，均可以实现对结束位置的复位。
当目标触发器为输出有效电平的时间与内部写命令的脉冲的起始时间存在重叠的触发器时，目标触发器的输出端无论与复位端连接，还是通过逻辑处理电路与输入端连接，均可以实现对起始位置的复位。
可选地，满足输出有效电平的时间与目标时间存在重叠的目标触发器可以包括以下至少一个：第二个触发器和第六个触发器。通过分析发现，顺序排列的多个触发器中，第二个触发器和第六个触发器是最先出现的满足以下条件的目标触发器：输出有效电平的时间与目标时间存在重叠。从而，本申请实施例可以通过第二个触发器和第六个触发器实现复位，如此，只需要保证触发器的数量大于或等于6即可实现复位。相较于目标触发器为第六个触发器之后的触发器，本申请实施例可以尽量的减少触发器的数量，进而减小电路尺寸。
图6是本申请实施例提供的再一种命令处理电路的结构示意图。参照图6所示，命令处理电路包括7个触发器，第七个触发器的输出作为采样命令。参照图6所示，第二个触发器的输出端O与第一个触发器的输入端I连接，也就是说，第二个触发器的输出端O通过逻辑处理电路与第一个触发器的输入端I连接，第六个触发器的输出端O与逻辑处理电路的复位端R连接。从图6中可以看出，第二个触发器与第一个触发器的距离较近，第六个触发器与第一个触发器的距离较远。此时，考虑到该距离会影响到信号传输速度，进而影响复位延迟，可以将第二个触发器的输出通过逻辑处理电路与第一个触发器的输入端连接，将第六个触发器的输出直接与第一个触发器的复位端连接，以使逻辑处理电路的处理进一步增大第二个触发器的输出到第一个触发器的输入端的时长，尽可能的使第二个触发器和第六个触发器的复位时长接近。
当然，除图6所示的连接方式外，还可以是第六个触发器的输出端O与第一个触发器的输入端I连接，也就是说，第六个触发器的输出端O通过逻辑处理电路与第一个触发器的输入端I连接，第二个触发器的输出端O与逻辑处理电路的复位端连接。
在一种可选的示例中，目标触发器输出有效电平的时间与目标时间的重叠时长小于脉冲宽度的一半。这样，既可以保证内部写命令的结束位置和/或起始位置可以被复位，以避免重复采样，还可以避免复位长度过长，使内部写命令的中间位置被复位，导致复位后的 内部写命令无法被采样到。下面以图7为例进行说明。
图7是本申请实施例提供的一种数据写入时序图。参照图7所示，D1至D7分别是图6中从左向右排列的每个触发器的输出。下面有效电平为高电平。
对于图7中的第一个触发器的输出D1，其中的高电平与内部写命令IWR2的脉冲结束位置在时间上重叠1个时钟周期，重叠较多。如果使用D1进行复位，那么复位后的内部写命令的结束位置提前1个时钟周期，导致数据选通信号DQS_T的上升沿或DQS_B的下降沿对应复位后的内部写命令的结束位置，导致复位后的内部写命令无法被采样到。
对于图7中的第二个触发器的输出D2，其中的第一个高电平与内部写命令IWR2的第一个脉冲结束位置在时间上重叠0.5个时钟周期。如果使用D2进行复位，那么，参照图7所示，复位后的内部写命令IWR2’的第一个脉冲结束位置提前0.5个时钟周期。因此，一方面，数据选通信号DQS_T的上升沿或DQS_B的下降沿对应复位后的IWR2’的高电平位置，可以保证对该脉冲的正常采样。另一方面，由于数据选通信号DQS_T的下一个上升沿或DQS_B的下一个下降沿对应复位后的IWR2’的低电平位置，从而，DQS_T的下一个上升沿或DQS_B的下一个下降沿不会对该脉冲进行重复采样。
对于图7中的第六个触发器的输出D6，其中的第一个高电平与内部写命令IWR2的第二个脉冲起始位置在时间上重叠0.5个时钟周期。如果使用D6进行复位，那么，参照图7所示，复位后的内部写命令IWR2’的第二个脉冲起始位置推后0.5个时钟周期。因此，一方面，数据选通信号DQS_T的上升沿或DQS_B的下降沿对应复位后的IWR2’的高电平位置，可以保证对该脉冲的正常采样。另一方面，由于数据选通信号DQS_T的下一个上升沿或DQS_B的下一个下降沿对应复位后的IWR2’的低电平位置，从而，DQS_T的下一个上升沿或DQS_B的下一个下降沿不会对该脉冲进行重复采样。
对于图7中的第三个触发器的输出D3至D5以及D7，其中的高电平和内部写命令IWR2的脉冲不存在时间重叠，从而，其无法实现对内部写命令IWR2的复位。
可以理解的是，在本公开实施例中，内部写命令的脉冲宽度可以为一个或两个时钟周期。从而，不仅可以避免两个时钟周期的脉冲宽度下的重复采样，还可以支持一个时钟周期的脉冲宽度的正常采样，使两种脉冲宽度的处理电路统一。
在一种可选的示例中，任意相邻两个触发器使用相位相反的数据选通信号。参照图6所示，其中存在7个触发器，第一个、第三个、第五个、第七个触发器的时钟端C输入数据选通信号DQS_T，第二个、第四个、第六个触发器的时钟端C输入数据选通信号DQS_B。由于DQS_T和DQS_B是相位相反的两个信号，从而实现了任意相邻两个触发器使用相位相反的数据选通信号。
本申请实施例可以通过上述两个相位相反的数据选通信号，可以提高多个触发器对内部写命令的采样速度。
本申请实施例还提供一种数据处理电路，包括数据采样电路和前述命令处理电路。数据采样电路用于根据命令处理电路输出的采样命令，对数据进行采样。如此，本申请实施例可以通过命令处理电路保证，对数据进行采样时使用的采样命令的起始位置和/或结束位置是复位过的，从而可以避免同一个内部写命令的脉冲被重复采样。进而，可以保证数据采样时数据采样的准确度，提高数据的写入准确度。
图8是本申请实施例提供的一种数据处理电路的结构示意图。请参照图8，数据处理 电路10除包括命令处理电路100和数据采样电路11之外，还包括：选通信号接收电路12，选通信号接收电路12通过一延迟电路13与命令处理电路100连接，延迟电路13用于对选通信号接收电路12接收到的数据选通信号进行延迟，并将延迟处理之后的数据选通信号发送给命令处理电路100。
其中，延迟电路的作用是对数据选通信号进行延迟，以保证数据选通信号和内部命令信号之间的同步性，也就是说，保证两者同时到达命令处理电路。这样，才可以保证数据选通信号对对应的内部命令信号进行采样处理，从而可以以进一步提高写入准确度。
具体地，延迟电路可以使用一个延迟参数进行延迟，该延迟参数可以根据数据选通信号的传输路径和内部写命令的传输路径之间的差值确定。也就是说，该延迟电路用于补偿数据选通信号和内部写命令的走线差异。通常情况下，数据选通信号的起始传输位置、内部写命令的起始传输位置位于整个电路的两侧，数据选通信号的传输路径比内部写命令的传输路径短。其中，数据选通信号的起始传输位置可以为图8中的选通信号接收电路12所在的位置，内部写命令的起始传输位置可以为命令生成电路14所在的位置。
当然，在某些特殊场景中，如果数据选通信号的传输路径比内部写命令的传输路径长，那么可以在内部写命令的传输路径上设置延迟电路，以对内部写命令进行延迟，以使其和数据选通信号同步到达命令处理电路。
可选地，参照图8所示，数据处理电路10还可以包括：与命令处理电路100连接的命令生成电路14，用于生成内部写命令，并将内部写命令发送给命令处理电路100。本申请实施例的数据处理电路可以集成多种功能，以使一个电路完成内部写命令的生成、命令采样以及数据采样，有助于提高电路的集成度。这里的命令生成电路也可以称为TDQSS GEN(TDQSS generation，时钟信号和DQS之间的偏斜生成)电路。
这里的命令生成电路可以外接命令地址线，以根据命令地址线上的电信号生成内部写命令。这里的命令地址线可以包括多种：CSB(cloud service bus，云服务总线)、ACTB、RASB、CASB、WEB。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。
为了方便解释，已经结合具体的实施方式进行了上述说明。但是，上述示例性的讨论不是意图穷尽或者将实施方式限定到上述公开的具体形式。根据上述的教导，可以得到多种修改和变形。上述实施方式的选择和描述是为了更好的解释原理以及实际的应用，从而使得本领域技术人员更好的使用所述实施方式以及适于具体使用考虑的各种不同的变形的实施方式。

Claims (15)

  1. 一种命令处理电路，包括：顺序排列的多个触发器，前一个所述触发器的输出端与后一个所述触发器的输入端连接，所述多个触发器用于根据数据选通信号的切换，对输入到所述命令处理电路中的内部写命令进行采样得到采样命令，所述采样命令用于对数据进行采样处理；
    所述多个触发器中的目标触发器的输出端与第一个所述触发器的目标端连接，所述目标触发器为输出有效电平的时间与目标时间存在重叠的触发器，所述目标时间是所述内部写命令中的脉冲的起始时间和/或结束时间；
    所述目标触发器，用于通过输出有效电平，将第一个所述触发器中的内部写命令进行复位。
  2. 根据权利要求1所述的命令处理电路，其中，所述目标端包括以下至少一个：复位端和输入端。
  3. 根据权利要求2所述的命令处理电路，其中，当所述目标端包括输入端时，所述命令处理电路还包括逻辑处理电路；
    所述逻辑处理电路的一个输入端与所述目标触发器的输出端连接，所述逻辑处理电路的另一输入端输入所述内部写命令，所述逻辑处理电路的输出端与第一个所述触发器的输入端连接；
    所述逻辑处理电路，用于在所述目标触发器输出有效电平且所述内部写命令为有效电平时，向第一个所述触发器中输入复位数据。
  4. 根据权利要求3所述的命令处理电路，其中，所述逻辑处理电路包括反相器和与门，所述目标触发器的输出端与所述反相器的输入端连接，所述反相器的输出端与所述与门的一个输入端连接，所述与门的另一输入端输入所述内部写命令。
  5. 根据权利要求3所述的命令处理电路，其特征在于，当所述目标触发器为两个时，其中一个所述目标触发器的输出端与第一个所述触发器的复位端连接，另一个所述目标触发器的输出端与所述逻辑处理电路的一个输入端连接。
  6. 根据权利要求3至5任一项所述的命令处理电路，其特征在于，所述目标触发器包括以下至少一个：第二个所述触发器和第六个所述触发器。
  7. 根据权利要求6所述的命令处理电路，其中，第二个所述触发器的输出端与第一个所述触发器的输入端连接，第六个所述触发器的输出端与所述逻辑处理电路的一个输入端连接。
  8. 根据权利要求1至5任一项所述的命令处理电路，其中，所述内部写命令的脉冲宽度为一个或两个时钟周期。
  9. 根据权利要求1至5任一项所述的命令处理电路，其中，所述有效电平为高电平。
  10. 根据权利要求1至5任一项所述的命令处理电路，其中，任意相邻两个所述触发器使用相位相反的数据选通信号。
  11. 根据权利要求8所述的命令处理电路，其中，所述目标触发器输出所述有效电平的时间与所述目标时间的重叠时长小于所述脉冲宽度的一半。
  12. 根据权利要求1至5任一项所述的命令处理电路，其中，所述触发器为7个，第七个所述触发器的输出作为所述采样命令。
  13. 一种数据处理电路，包括数据采样电路和权利要求1至12任一项所述的命令处理电路，所述数据采样电路用于根据所述命令处理电路输出的采样命令，对数据进行采样。
  14. 根据权利要求13所述的数据处理电路，其中，所述数据处理电路还包括：选通信号接收电路，所述选通信号接收电路通过一延迟电路与所述命令处理电路连接，所述延迟电路用于对所述选通信号接收电路接收到的数据选通信号进行延迟，并将延迟处理之后的数据选通信号发送给所述命令处理电路。
  15. 根据权利要求14所述的数据处理电路，其中，所述数据处理电路还包括：与所述命令处理电路连接的命令生成电路，用于生成所述内部写命令，并将所述内部写命令发送给所述命令处理电路。
PCT/CN2022/101688 2022-05-13 2022-06-27 命令处理电路及数据处理电路 WO2023216385A1 (zh)

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