WO2023216296A1 - 一种驱动电路及显示装置 - Google Patents

一种驱动电路及显示装置 Download PDF

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Publication number
WO2023216296A1
WO2023216296A1 PCT/CN2022/093930 CN2022093930W WO2023216296A1 WO 2023216296 A1 WO2023216296 A1 WO 2023216296A1 CN 2022093930 W CN2022093930 W CN 2022093930W WO 2023216296 A1 WO2023216296 A1 WO 2023216296A1
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WO
WIPO (PCT)
Prior art keywords
gate
driving circuit
line
driver
data lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/093930
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English (en)
French (fr)
Inventor
刘汉先
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
Original Assignee
TCL China Star Optoelectronics Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
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Filing date
Publication date
Application filed by TCL China Star Optoelectronics Technology Co Ltd, Huizhou China Star Optoelectronics Display Co Ltd filed Critical TCL China Star Optoelectronics Technology Co Ltd
Priority to US17/785,440 priority Critical patent/US12140843B2/en
Publication of WO2023216296A1 publication Critical patent/WO2023216296A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present application relates to the field of display technology, and in particular, to a driving circuit and a display device.
  • GOA Gate On Array
  • GOA technology can reduce the bonding process of external ICs, but the disadvantage is that the GOA circuits at both ends of the GOA LCD panel limit the design of ultra-narrow frames.
  • a COF driving solution in which the Gate signal is connected from the source side can realize ultra-narrow bezel display panels.
  • the purpose of this application is to provide a driving circuit and a display device, aiming to reduce the manufacturing cost of the driving circuit.
  • this application provides a driving circuit, which at least includes:
  • a source driver and a gate driver located above the data line and the gate line, the data line is connected to the source driver, and the gate line is connected to the gate driver;
  • the data line and the gate line are arranged in the same layer.
  • the data lines further include a plurality of first data lines and a plurality of second data lines.
  • the plurality of first data lines pass through the gate driver.
  • the plurality of second data lines bypasses the gate driver.
  • the driving circuit further includes:
  • a plurality of first conductive pads are arranged in the same layer as the gate line and covered by the gate driver. Each of the first conductive pads is connected to one of the gate lines.
  • the driving circuit further includes:
  • a substrate, the data line, the gate line and the first conductive pad are provided on the substrate;
  • An insulating layer is located on the substrate and covers the data lines and the gate lines.
  • the plurality of first conductive pads are arranged at intervals, and the plurality of first data lines are located between the plurality of first conductive pads.
  • the driving circuit further includes an input signal binding area and an output signal binding area, and the source driver and the gate driver are located in the input signal binding area and the output signal binding area. between regions, and the gate driver is located on a side of the source driver close to the output signal binding region.
  • the driving circuit further includes:
  • a plurality of second conductive pads are arranged in the same layer as the gate line and covered by the gate driver;
  • the first conductive pad is used to transmit the gate output signal
  • the second conductive pad is used to transmit the gate input signal
  • the present application provides a display device, which at least includes:
  • the driving circuit in any of the above embodiments is bound to the display panel.
  • this application provides a driving circuit and a display device.
  • the driving circuit at least includes data lines and gate lines arranged on the same layer, and source drivers and gate drivers located above the data lines and gate lines. , the data line is connected to the source driver, and the gate line is connected to the gate driver. Since the data lines and the gate lines are arranged on the same layer, a single-layer film wiring design can be realized, so that no via holes are required during subsequent bonding, thus saving or reducing production costs.
  • Figure 1 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application.
  • Figure 2 is a perspective view of position A in Figure 1 provided by an embodiment of the present application;
  • Figure 3 is a schematic cross-sectional structural diagram along B-B1 in Figure 2 provided by the embodiment of the present application;
  • Figure 4 is a perspective view of C in Figure 1 provided by an embodiment of the present application.
  • first and second are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more of the described features. In the description of this application, “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • the term “above” or “below” a first feature on a second feature may include direct contact between the first and second features, or may also include the first and second features. Not in direct contact but through additional characteristic contact between them.
  • the terms “above”, “above” and “above” a first feature on a second feature include the first feature being directly above and diagonally above the second feature, or simply mean that the first feature is higher in level than the second feature.
  • “Below”, “under” and “under” the first feature is the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature is less horizontally than the second feature.
  • Figure 1 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application.
  • Figure 2 is a perspective view of A in Figure 1 provided by an embodiment of the present application.
  • Figure 3 is a perspective view provided by an embodiment of the present application. Schematic diagram of the cross-sectional structure along B-B1 in Figure 2.
  • the driving circuit 100 at least includes a data line 10 and a gate line 11 arranged in the same layer, and a source driver 101 and a gate driver 111 located above the data line 10 and the gate line 11 .
  • the source driver 101 and the gate driver 111 can be arranged on the same layer.
  • the data line 10 is connected to the source driver 101
  • the gate line 11 is connected to the gate driver 111 .
  • the gate line 11 is represented by a thicker black line
  • the data line 10 is represented by a thinner black line.
  • the number of source drivers 101 and gate drivers 111 can be set according to the number of data lines 10 and gate lines 11 .
  • the driving circuit 100 can include two source drivers 101 and one gate driver. 111.
  • one source driver 101 may also be provided, that is, this application does not limit the number of source drivers 101 and gate drivers 111 .
  • both the gate driver 111 and the source driver 101 may have a rectangular top view, and the length direction of the gate driver 111 is parallel to the length direction of the source driver 101 .
  • the driving circuit 100 may further include an input signal binding area 20 and an output signal binding area 21.
  • the source driver 101 and the gate driver 111 are located in the input signal binding area 20 and the output signal binding area 21. Between the output signal binding areas 21 , and the gate driver 111 is located on the side of the source driver 101 close to the output signal binding area 21 .
  • two source drivers 101 are arranged side by side between the gate driver 111 and the input signal binding area 20 , and the two source drivers 101 correspond to two ends of the gate driver 111 respectively.
  • the left source driver 101 extends beyond the left end of the gate driver 111 toward the left side of Figure 1 (referring to the orientation shown in the figure), and the right source driver 101 extends beyond the gate driver 111 toward the right side of Figure 1 (referring to the orientation shown in the figure). right end.
  • the driving circuit 100 may further include a gate input signal line 201 and a source input signal line 202, and the gate input signal line 201, the source input signal line 202, the gate line 11 and the data line 10 They are all arranged on the same layer.
  • the gate input signal line 201 is electrically connected to the gate driver 111
  • the source input signal line 202 is electrically connected to the source driver 101. From the plane orientation of FIG. 1 , the gate input signal line 201 is located between two source drivers 101 arranged side by side, and the source input signal line 202 is located on the side of the source driver 101 away from the data line 10 .
  • the gate input signal line 201 and the source input signal line 202 are both introduced from the input signal binding area 20 to achieve binding with the flexible circuit board. It can also be said that the gate input signal line 201 is introduced from the source input signal line. 202 side access.
  • the gate line 11 and the data line 10 are connected to the output signal binding area 21 to achieve binding with the display panel. It should be noted that the number of gate input signal lines 201 may be less than the number of gate lines 11 , and the number of source input signal lines 202 may be less than the number of data lines 10 .
  • the data line 10 may include or be divided into a plurality of first data lines 10 a and a plurality of second data lines 10 b , wherein the first data lines 10 a are connected from the gate driver 111 Passing underneath, the second data line 10b bypasses the gate driver 111, that is, the gate driver 111 does not cover the second data line 10b.
  • the first data line 10a corresponds to the position where the source driver 101 and the gate driver 111 are aligned up and down (referring to the orientation shown in the figure), and the first data line 10a can pass through the gate driver 111
  • the second data line 10b corresponds to the source driver 101 and the gate driver 111.
  • the gate driver 101 extends beyond the gate driver 111, so the second data line 10b can bypass or not pass through the gate driver 111.
  • the driving circuit 100 may further include a plurality of first conductive pads 112 arranged in the same layer as the gate line 11 , and the gate line 11 is connected through a plurality of first conductive pads 112 .
  • Pad 112 is electrically connected to the gate driver 111 (shown as a dashed box in the figure). Specifically, each gate line 11 is connected to a first conductive pad 112, and the gate driver 111 is covered or bound on multiple first conductive pads 112 to realize the connection between the gate line 11 and the gate driver 111. Electrical connection.
  • Each gate line 11 is led out from the side of a first conductive pad 112 , for example, from above the first conductive pad 112 (referring to the direction shown in the figure).
  • a plurality of first conductive pads 112 are arranged at intervals along the length direction of the gate driver 111 , and the first data line 10 a is located between the plurality of first conductive pads 112 .
  • first data lines 10a there may be two, three, four or five first data lines 10a between two adjacent first conductive pads 112 .
  • the sequence arranged in the length direction is: two first conductive pads 112, three first data lines 10a, two first conductive pads 112, and three first data lines 10a. Therefore, this application does not limit the arrangement of the first conductive pad 112 (or the gate line 11) and the first data line 10a.
  • the driving circuit 100 may also include a plurality of second conductive pads 113 .
  • the second conductive pads 113 are arranged in the same layer as the first conductive pads 112 .
  • the pole driver 111 is covered or bonded on the first conductive pad 112 and the second conductive pad 113 .
  • Each second conductive pad 113 is connected to a gate input signal line 201.
  • the gate input signal line 201 is led from below the second conductive pad 113 (referring to the direction shown in the figure), so gate input can be realized.
  • the signal line 201 is electrically connected to the gate driver 111 . Since the number of gate input signal lines 201 is smaller than the number of gate lines 11 , the number of second conductive pads 113 is smaller than the number of first conductive pads 112 .
  • the second conductive pad 113 is located on the side of the first conductive pad 112 close to the input signal binding area 20.
  • the second conductive pad 113 is used to transmit the gate input signal.
  • the first conductive pad 112 Used to transmit gate output signals.
  • the gate signal transmission process is: the gate input signal generated by the flexible circuit board is connected from the input signal binding area 20, and is sequentially transmitted to the gate driver 111 through the gate input signal line 201 and the second conductive pad 113.
  • the gate driver 111 generates a gate output signal after processing and transmits it to the first conductive pad 112.
  • the first conductive pad 112 transmits the gate output signal to the gate line 11 to realize pixel driving of the display panel.
  • the driving circuit 100 may further include a substrate 12 , and the material of the substrate 12 may include polyimide.
  • the data line 10, the gate line 11 and the first conductive pad 112 are all located on the substrate 12.
  • the input signal lines 201 may all be located on the substrate 12 .
  • the driving circuit 100 may further include an insulating layer 13 located on the substrate 12 and covering the data line 10 and the gate line 11 , thereby preventing short circuits between the gate line 11 and the data line 10 arranged on the same layer.
  • the insulating layer 13 also covers the gate lines. 11. Data line 10, gate input signal line 201 and source input signal line 202.
  • the first conductive pad 112 and the circuit layer are also arranged on the same layer, the height of the first conductive pad 112 is relatively high, so the insulating layer 13 does not cover the first conductive pad 112. It can also be said that the first conductive pad 112 is partially located in the insulating layer 13 .
  • the material of the insulating layer 13 may include oxides such as silicon oxide and silicon nitride.
  • the substrate 12, the insulating layer 13 and the circuit layer (including the gate line 11, the data line 10, the gate input signal line 201 and the source input signal line 202) can be collectively referred to as a single layer film, the gate driver 111 and the source driver 101 is bound to the single-layer film, so it can be called a chip-on-membrane (Chip-on-membrane). On film, COF).
  • the perspective view of FIG. 2 shows the insulating layer 13, as well as the first data line 10a, the gate line 11 and the gate input signal line 201. If it is a top view, the first data line 10a will not be shown. , gate line 11 and gate input signal line 201 because they are covered by the insulating layer 13 .
  • Figure 4 is a perspective view of C in Figure 1 provided by an embodiment of the present application.
  • the driving circuit 100 may also include a plurality of third conductive pads 102 and a plurality of fourth conductive pads 103.
  • the third conductive pads 102, the fourth conductive pads 103, the data line 10, and the source input signal line 202 are all set in the same layer.
  • the source driver 101 (indicated by a dotted box) is covered or bound on the third conductive pad 102 and the fourth conductive pad 103, and the fourth conductive pad 103 is located on the third conductive pad 102 The side close to the input signal binding area 20.
  • the third conductive pad 102 is used to transmit the source output signal
  • the fourth conductive pad 103 is used to transmit the source input signal.
  • Each third conductive pad 102 is connected to a data line 10
  • each fourth conductive pad 103 is connected to a source input signal line 202 . Since the number of source input signal lines 202 is less than the number of data lines 10 , the number of fourth conductive pads 103 is less than the number of third conductive pads 102 .
  • the process of source signal transmission is: the source input signal generated by the flexible circuit board is connected from the input signal binding area 20, and is sequentially transmitted to the source driver 101 through the source input signal line 202 and the fourth conductive pad 103.
  • the source output signal is generated after processing by the electrode driver 101 and transmitted to the third conductive pad 102.
  • the third conductive pad 102 transmits the source output signal to the data line 10 to realize pixel driving of the display panel.
  • the driving circuit 100 provided by the embodiment of the present application includes a data line 10 and a gate line 11 arranged on the same layer, and a source driver 101 and a gate driver 111 located above the data line 10 and the gate line 11 , wherein the data line 10 It is connected to the source driver 101, and the gate line 11 is connected to the gate driver 111. Since the data line 10 and the gate line 11 are arranged on the same layer, a single-layer film wiring design can be realized, so that no via holes are required during subsequent bonding, thus saving or reducing production costs.
  • An embodiment of the present application also provides a display device, including the driving circuit 100 provided in any of the above embodiments and a display panel, and the driving circuit 100 is bound to the display panel. Specifically, the output signal binding area 21 of the driving circuit 100 is bound to the display panel.
  • the display panel may be a liquid crystal display panel or other types of display panels. This display device has the same beneficial effects as the above-mentioned driving circuit 100, which will not be described again here.

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  • Engineering & Computer Science (AREA)
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
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Abstract

一种驱动电路及显示装置，该驱动电路包括同层设置的数据线（10）和栅极线（11），以及位于数据线（10）和栅极线（11）上方的源极驱动器（101）和栅极驱动器（111），其中数据线（10）与源极驱动器（101）连接，栅极线（11）与栅极驱动器（111）连接。

Description

一种驱动电路及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种驱动电路及显示装置。
 背景技术
目前液晶面板的驱动集成电路(Integrated Circuit, IC)通常使用膜上芯片(Chip On film, COF)的形式绑定在液晶面板上运用，为缩减产品开发成本，驱动液晶面板的栅极(Gate)信号驱动电路直接设计在液晶面板中，因此GOA(Gate On Array)液晶面板成为市场的主流。GOA技术是将扫描线的驱动电路制作在液晶显示面板的显示区周围的基板上，使之替代外接IC来完成各级扫描线的驱动。
GOA技术能够减少外接IC的焊接(bonding)工序，但缺点是GOA液晶面板的两端的GOA电路限制了超窄边框的设计。随着人们对全面屏高分辨率显示的追求，一种Gate信号从source侧接入的COF驱动方案可以实现超窄边框的显示面板。
但是这种Gate信号从source侧接入的COF驱动方案，成本较高。
 技术问题
本申请的目的在于提供一种驱动电路及显示装置，旨在降低驱动电路的制作成本。
 技术解决方案
一方面，本申请提供一种驱动电路，所述驱动电路至少包括：
数据线和栅极线；
源极驱动器和栅极驱动器，位于所述数据线和所述栅极线上方，所述数据线与所述源极驱动器连接，所述栅极线与所述栅极驱动器连接；
其中，所述数据线与所述栅极线同层设置。
在一些实施例中，所述数据线还包括多条第一数据线和多条第二数据线，所述多条第一数据线穿过所述栅极驱动器，所述多条第二数据线绕过所述栅极驱动器。
在一些实施例中，所述驱动电路还包括：
多个第一导电焊垫，与所述栅极线同层设置，且被所述栅极驱动器覆盖，每个所述第一导电焊垫与一条所述栅极线连接。
在一些实施例中，所述驱动电路还包括：
基底，所述数据线、所述栅极线和所述第一导电焊垫设置在所述基底上；
绝缘层，位于所述基底上且覆盖所述数据线和所述栅极线。
在一些实施例中，所述多个第一导电焊垫间隔排列，所述多条第一数据线位于所述多个第一导电焊垫之间。
在一些实施例中，相邻两个所述第一导电焊垫之间具有至少一条所述第一数据线。
在一些实施例中，每两个所述第一导电焊垫之间具有三条所述第一数据线。
在一些实施例中，所述驱动电路还包括输入信号绑定区和输出信号绑定区，所述源极驱动器和所述栅极驱动器位于所述输入信号绑定区和所述输出信号绑定区之间，且所述栅极驱动器位于所述源极驱动器靠近所述输出信号绑定区的一侧。
在一些实施例中，所述驱动电路还包括：
多个第二导电焊垫，与所述栅极线同层设置，且被所述栅极驱动器覆盖；
其中，所述第一导电焊垫用于传输栅极输出信号，所述第二导电焊垫用于传输栅极输入信号。
另一方面，本申请提供一种显示装置，所述显示装置至少包括：
显示面板；
上述任一实施例中的驱动电路，所述驱动电路绑定在所述显示面板上。
 有益效果
本申请的有益效果是：本申请提供一种驱动电路及显示装置，驱动电路至少包括同层设置的数据线和栅极线，以及位于数据线和栅极线上方的源极驱动器和栅极驱动器，数据线与源极驱动器连接，栅极线与栅极驱动器连接。由于数据线和栅极线设置在同层，即可以实现单层薄膜走线设计，这样在后续进行绑定时不需要设置过孔，因此可以节省或降低制作成本。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1是本申请实施例提供的驱动电路的结构示意图；
图2是本申请实施例提供的图1中A处的透视图；
图3是本申请实施例提供的图2中沿B-B1处的剖面结构示意图；
图4是本申请实施例提供的图1中C处的透视图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参阅图1-图3，图1是本申请实施例提供的驱动电路的结构示意图，图2是本申请实施例提供的图1中A处的透视图，图3是本申请实施例提供的图2中沿B-B1处的剖面结构示意图。
该驱动电路100至少包括同层设置的数据线10和栅极线11，以及位于数据线10和栅极线11上方的源极驱动器101和栅极驱动器111。其中，源极驱动器101和栅极驱动器111可以同层设置。如图1所示，数据线10与源极驱动器101连接，栅极线11与栅极驱动器111连接。需要说明的是，图1中用较粗的黑线表示栅极线11，用较细的黑线表示数据线10。
在本实施例中，可以根据数据线10和栅极线11的数量来设置源极驱动器101和栅极驱动器111的数量，例如该驱动电路100可以包括两个源极驱动器101和一个栅极驱动器111。在一些实施例中，若数据线10的数量较少，也可以设置一个源极驱动器101，即本申请不对源极驱动器101和栅极驱动器111的数量进行限制。
在一些实施例中，栅极驱动器111和源极驱动器101的俯视图形都可以为长方形，且栅极驱动器111的长度方向与源极驱动器101的长度方向平行。
在一些实施例中，该驱动电路100还可以包括输入信号绑定区20和输出信号绑定区21，所述源极驱动器101和所述栅极驱动器111位于所述输入信号绑定区20和所述输出信号绑定区21之间，且所述栅极驱动器111位于所述源极驱动器101靠近所述输出信号绑定区21的一侧。如图1所示，两个源极驱动器101并排设置在栅极驱动器111和输入信号绑定区20之间，且两个源极驱动器101分别对应栅极驱动器111的两端。左边的源极驱动器101向图1的左边（指图示的方位）超出栅极驱动器111的左端，右边的源极驱动器101向图1的右边（指图示的方位）超出栅极驱动器111的右端。
在一些实施例中，该驱动电路100还可以包括栅极输入信号线201和源极输入信号线202，且栅极输入信号线201、源极输入信号线202、栅极线11和数据线10都是同层设置，栅极输入信号线201与栅极驱动器111电连接，源极输入信号线202与源极驱动器101电连接。从图1平面的方位来看，栅极输入信号线201位于两个并排设置的源极驱动器101之间，源极输入信号线202位于源极驱动器101远离数据线10的一侧。其中，栅极输入信号线201和源极输入信号线202都从输入信号绑定区20引入，以实现与柔性电路板的绑定，也可以说栅极输入信号线201从源极输入信号线202的一侧接入。另一方面，栅极线11和数据线10连接到输出信号绑定区21，以实现与显示面板的绑定。需要说明的是，栅极输入信号线201的数量可以小于栅极线11的数量，且源极输入信号线202的数量可以小于数据线10的数量。
在一些实施例中，如图1和图2所示，数据线10可以包括或分成多条第一数据线10a和多条第二数据线10b，其中第一数据线10a从栅极驱动器111的下方穿过，第二数据线10b绕过该栅极驱动器111，即栅极驱动器111没有覆盖第二数据线10b。其中，第一数据线10a对应源极驱动器101与栅极驱动器111上下（指图示的方位）对齐的位置，进而第一数据线10a可以穿过栅极驱动器111，第二数据线10b对应源极驱动器101超出栅极驱动器111的部分，进而第二数据线10b可以绕过或者说不穿过栅极驱动器111。
在一些实施例中，如图2所示，该驱动电路100还可以包括与栅极线11同层设置的多个第一导电焊垫112，所述栅极线11通过多个第一导电焊垫112与所述栅极驱动器111（图中用虚线框表示）电连接。具体的，每条栅极线11与一个第一导电焊垫112连接，栅极驱动器111覆盖或绑定在多个第一导电焊垫112上，以实现栅极线11与栅极驱动器111的电连接。每条栅极线11从一个第一导电焊垫112的侧面引出，例如从第一导电焊垫112的上方（指图示的方位）引出。
结合图2和图3，多个第一导电焊垫112沿栅极驱动器111的长度方向间隔排列，第一数据线10a位于多个第一导电焊垫112之间。在一些实施例中，相邻两个第一导电焊垫112之间具有至少一条第一数据线10a，例如相邻两个第一导电焊垫112之间具有一条第一数据线10a，因此栅极线11和第一数据线10a交替从栅极驱动器111引出。
在一些实施例中，相邻两个第一导电焊垫112之间可以具有两条、三条、四条或五条第一数据线10a。在另一些实施例中，每两个所述第一导电焊垫112之间具有三条第一数据线10a，也就是说，第一导电焊垫112和第一数据线10a的沿栅极驱动器111的长度方向排列的顺序为：两个第一导电焊垫112、三条第一数据线10a、两个第一导电焊垫112、三条第一数据线10a。因此本申请对第一导电焊垫112（或栅极线11）与第一数据线10a的排列方式不进行限制。
在一些实施例中，如图2所示，该驱动电路100还可以包括多个第二导电焊垫113，所述第二导电焊垫113与所述第一导电焊垫112同层设置，栅极驱动器111覆盖或绑定在第一导电焊垫112和第二导电焊垫113上。每个第二导电焊垫113连接一条栅极输入信号线201，具体的，栅极输入信号线201从第二导电焊垫113的下方（指图示的方位）引出，因此可以实现栅极输入信号线201与栅极驱动器111的电连接。由于栅极输入信号线201的数量小于栅极线11的数量，因此第二导电焊垫113的数量小于第一导电焊垫112的数量。
其中，第二导电焊垫113位于所述第一导电焊垫112靠近所述输入信号绑定区20的一侧，第二导电焊垫113用于传输栅极输入信号，第一导电焊垫112用于传输栅极输出信号。栅极信号传输的过程是：柔性电路板产生的栅极输入信号从输入信号绑定区20接入，依次经过栅极输入信号线201、第二导电焊垫113传输到栅极驱动器111，栅极驱动器111处理后生成栅极输出信号，并传输到第一导电焊垫112，最后第一导电焊垫112将栅极输出信号传输到栅极线11，以实现对显示面板的像素驱动。
在一些实施例中，如图3所示，该驱动电路100还可以包括基底12，所述基底12的材质可以包括聚酰亚胺。数据线10、栅极线11和第一导电焊垫112都位于基底12上，第二导电焊垫113、第三导电焊垫102、第四导电焊垫103、源极输入信号线202和栅极输入信号线201也可以都位于基底12上。
该驱动电路100还可以包括位于基底12上且覆盖数据线10和栅极线11的绝缘层13，因此可以避免同层设置的栅极线11和数据线10之间发生短路。可以理解的是，由于栅极线11、数据线10、栅极输入信号线201和源极输入信号线202（可以统称为电路层）都是同层设置，因此绝缘层13同时覆盖栅极线11、数据线10、栅极输入信号线201和源极输入信号线202。虽然第一导电焊垫112与所述电路层也是同层设置，但是第一导电焊垫112高度较高，因此绝缘层13没有覆盖第一导电焊垫112，也可以说第一导电焊垫112部分位于绝缘层13中。
其中，绝缘层13的材质可以包括氧化硅、氮化硅等氧化物。基底12、绝缘层13和电路层（包括栅极线11、数据线10、栅极输入信号线201和源极输入信号线202）可以统称为单层薄膜，栅极驱动器111和源极驱动器101绑定在所述单层薄膜上，因此可以称为膜上芯片(Chip On film, COF)。需要说明的是，图2透视图中显示出了绝缘层13，以及第一数据线10a、栅极线11和栅极输入信号线201，若是在俯视图中，则不会显示第一数据线10a、栅极线11和栅极输入信号线201，因为它们被绝缘层13覆盖了。
请参阅图4，图4是本申请实施例提供的图1中C处的透视图。
该驱动电路100还可以包括多个第三导电焊垫102和多个第四导电焊垫103，所述第三导电焊垫102、第四导电焊垫103、数据线10、源极输入信号线202都是同层设置。所述源极驱动器101（用虚线框表示）覆盖或绑定在第三导电焊垫102和第四导电焊垫103上，且所述第四导电焊垫103位于所述第三导电焊垫102靠近所述输入信号绑定区20的一侧。第三导电焊垫102用于传输源极输出信号，第四导电焊垫103用于传输源极输入信号。每个第三导电焊垫102与一条数据线10连接，每个第四导电焊垫103与一条源极输入信号线202连接。由于源极输入信号线202的数量小于数据线10的数量，因此第四导电焊垫103的数量小于第三导电焊垫102的数量。源极信号传输的过程是：柔性电路板产生的源极输入信号从输入信号绑定区20接入，依次经过源极输入信号线202、第四导电焊垫103传输到源极驱动器101，源极驱动器101处理后生成源极输出信号，并传输到第三导电焊垫102，最后第三导电焊垫102将源极输出信号传输到数据线10，以实现对显示面板的像素驱动。
本申请实施例提供的驱动电路100，包括同层设置的数据线10和栅极线11，以及位于数据线10和栅极线11上方的源极驱动器101和栅极驱动器111，其中数据线10与源极驱动器101连接，栅极线11与栅极驱动器111连接。由于数据线10和栅极线11同层设置，即可以实现单层薄膜走线设计，这样在后续进行绑定时不需要设置过孔，因此可以节省或降低制作成本。
本申请实施例还提供一种显示装置，包括上述任一实施例提供的驱动电路100和显示面板，所述驱动电路100绑定在所述显示面板上。具体的，驱动电路100的输出信号绑定区21与所述显示面板进行绑定。该显示面板可以为液晶显示面板或其他类型的显示面板。该显示装置具有与上述驱动电路100相同的有益效果，在此不再赘述。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种驱动电路，其中，所述驱动电路至少包括：
    数据线和栅极线；
    源极驱动器和栅极驱动器，位于所述数据线和所述栅极线上方，所述数据线与所述源极驱动器连接，所述栅极线与所述栅极驱动器连接；
    其中，所述数据线与所述栅极线同层设置。
  2. 根据权利要求1所述的驱动电路，其中，所述数据线还包括多条第一数据线和多条第二数据线，所述多条第一数据线穿过所述栅极驱动器，所述多条第二数据线绕过所述栅极驱动器。
  3. 根据权利要求2所述的驱动电路，其中，所述驱动电路还包括：
    多个第一导电焊垫，与所述栅极线同层设置，且被所述栅极驱动器覆盖，每个所述第一导电焊垫与一条所述栅极线连接。
  4. 根据权利要求3所述的驱动电路，其中，所述驱动电路还包括：
    基底，所述数据线、所述栅极线和所述第一导电焊垫设置在所述基底上；
    绝缘层，位于所述基底上且覆盖所述数据线和所述栅极线。
  5. 根据权利要求3所述的驱动电路，其中，所述多个第一导电焊垫间隔排列，所述多条第一数据线位于所述多个第一导电焊垫之间。
  6. 根据权利要求5所述的驱动电路，其中，相邻两个所述第一导电焊垫之间具有至少一条所述第一数据线。
  7. 根据权利要求5所述的驱动电路，其中，每两个所述第一导电焊垫之间具有三条所述第一数据线。
  8. 根据权利要求2所述的驱动电路，其中，所述驱动电路还包括输入信号绑定区和输出信号绑定区，所述源极驱动器和所述栅极驱动器位于所述输入信号绑定区和所述输出信号绑定区之间，且所述栅极驱动器位于所述源极驱动器靠近所述输出信号绑定区的一侧。
  9. 根据权利要求3所述的驱动电路，其中，所述驱动电路还包括：
    多个第二导电焊垫，与所述栅极线同层设置，且被所述栅极驱动器覆盖；
    其中，所述第一导电焊垫用于传输栅极输出信号，所述第二导电焊垫用于传输栅极输入信号。
  10. 根据权利要求1所述的驱动电路，其中，所述驱动电路还包括：
    多个第三导电焊垫和多个第四导电焊垫，与所述数据线同层设置，且被所述源极驱动器覆盖；
    其中，所述第三导电焊垫用于传输源极输出信号，第四导电焊垫用于传输源极输入信号。
  11. 一种显示装置，其中，所述显示装置至少包括：
    显示面板；
    权利要求1所述的驱动电路，所述驱动电路绑定在所述显示面板上。
  12. 根据权利要求11所述的显示装置，其中，所述数据线还包括多条第一数据线和多条第二数据线，所述多条第一数据线穿过所述栅极驱动器，所述多条第二数据线绕过所述栅极驱动器。
  13. 根据权利要求12所述的显示装置，其中，所述驱动电路还包括：
    多个第一导电焊垫，与所述栅极线同层设置，且被所述栅极驱动器覆盖，每个所述第一导电焊垫与一条所述栅极线连接。
  14. 根据权利要求13所述的显示装置，其中，所述驱动电路还包括：
    基底，所述数据线、所述栅极线和所述第一导电焊垫设置在所述基底上；
    绝缘层，位于所述基底上且覆盖所述数据线和所述栅极线。
  15. 根据权利要求13所述的显示装置，其中，所述多个第一导电焊垫间隔排列，所述多条第一数据线位于所述多个第一导电焊垫之间。
  16. 根据权利要求15所述的显示装置，其中，相邻两个所述第一导电焊垫之间具有至少一条所述第一数据线。
  17. 根据权利要求15所述的显示装置，其中，每两个所述第一导电焊垫之间具有三条所述第一数据线。
  18. 根据权利要求12所述的显示装置，其中，所述驱动电路还包括输入信号绑定区和输出信号绑定区，所述源极驱动器和所述栅极驱动器位于所述输入信号绑定区和所述输出信号绑定区之间，且所述栅极驱动器位于所述源极驱动器靠近所述输出信号绑定区的一侧。
  19. 根据权利要求13所述的显示装置，其中，所述驱动电路还包括：
    多个第二导电焊垫，与所述栅极线同层设置，且被所述栅极驱动器覆盖；
    其中，所述第一导电焊垫用于传输栅极输出信号，所述第二导电焊垫用于传输栅极输入信号。
  20. 根据权利要求11所述的显示装置，其中，所述驱动电路还包括：
    多个第三导电焊垫和多个第四导电焊垫，与所述数据线同层设置，且被所述源极驱动器覆盖；
    其中，所述第三导电焊垫用于传输源极输出信号，第四导电焊垫用于传输源极输入信号。
PCT/CN2022/093930 2022-05-10 2022-05-19 一种驱动电路及显示装置 Ceased WO2023216296A1 (zh)

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