WO2023216026A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023216026A1
WO2023216026A1 PCT/CN2022/091459 CN2022091459W WO2023216026A1 WO 2023216026 A1 WO2023216026 A1 WO 2023216026A1 CN 2022091459 W CN2022091459 W CN 2022091459W WO 2023216026 A1 WO2023216026 A1 WO 2023216026A1
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Prior art keywords
light
pixel
sub
base substrate
display substrate
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PCT/CN2022/091459
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English (en)
French (fr)
Inventor
刘彪
尚庭华
龙祎璇
陈家兴
牛佐吉
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001122.5A priority Critical patent/CN117396928A/zh
Priority to PCT/CN2022/091459 priority patent/WO2023216026A1/zh
Publication of WO2023216026A1 publication Critical patent/WO2023216026A1/zh

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  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • display devices usually also have multiple functions such as fingerprint recognition. At this time, the structure of the display device can be adjusted accordingly for these functions.
  • At least one embodiment of the present disclosure provides a display substrate, which has a display side and includes a base substrate, a driving circuit layer, a first electrode layer and a pixel defining layer, and the driving circuit layer is disposed on the base substrate, It includes a plurality of first gaps, the plurality of first gaps allow light from the display side to pass through, and a first electrode layer is provided on a side of the driving circuit layer away from the base substrate, including a plurality of A first electrode pattern and a plurality of light-shielding patterns.
  • the pixel defining layer is disposed on a side of the first electrode layer away from the base substrate and includes a plurality of sub-pixel openings.
  • the plurality of sub-pixel openings respectively expose the plurality of The first electrode pattern, wherein at least part of the plurality of light-shielding patterns does not overlap with the plurality of sub-pixel openings in a direction perpendicular to the base substrate, and at least part of the plurality of light-shielding patterns respectively Corresponding to and at least partially overlapping at least part of the first gaps among the plurality of first gaps, so as to at least partially block light from the display side.
  • the widths of the plurality of first gaps are less than or equal to 4.0 microns.
  • the distance between the plurality of first gaps and the centers of the plurality of sub-pixel openings is less than 33 microns.
  • the light-shielding patterns are integrally connected to the plurality of first electrode patterns.
  • each of the plurality of first electrode patterns includes a main body part and a connecting part, and the planar shape of the main body part is respectively a polygon or a figure with arc edges, so Each of the plurality of light shielding patterns has a polygonal planar shape.
  • the display substrate has a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting device, and the plurality of first electrode patterns serve as the plurality of sub-pixels respectively.
  • the anode of the pixel's light-emitting device is not limited to, but not limited to, a light-emitting device, a light-emitting device, and the plurality of first electrode patterns serve as the plurality of sub-pixels respectively.
  • the plurality of sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels, wherein the main body of the first electrode pattern of the light-emitting device of the red sub-pixel
  • the planar shape of the portion is hexagonal, and the light-shielding pattern integrally connected with the first electrode pattern of the light-emitting device of the red sub-pixel is triangular.
  • the number of light-shielding patterns integrally connected with the first electrode pattern of the light-emitting device of the red sub-pixel is two, and the number of light-shielding patterns integrally connected with the first electrode pattern of the light-emitting device of the red sub-pixel is The two light-shielding patterns integrally connected to the first electrode pattern are symmetrically distributed.
  • the planar shape of the main body portion of the first electrode pattern of the light-emitting device of the blue sub-pixel is a hexagon, which is different from the shape of the main body of the first electrode pattern of the light-emitting device of the blue sub-pixel.
  • the light-shielding pattern integrally connected with the first electrode pattern is triangular or rectangular.
  • the number of light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the blue sub-pixel is three, and the number of light-shielding patterns is not related to the light-emitting pattern of the blue sub-pixel.
  • the three light-shielding patterns integrally connected to the first electrode pattern of the device are respectively integrally connected to three sides of the first electrode pattern of the light-emitting device of the blue sub-pixel.
  • the planar shape of the main body part of the first electrode pattern of the light-emitting device of the green sub-pixel is a pentagon, which is different from the first electrode pattern of the light-emitting device of the green sub-pixel.
  • the light-shielding pattern in which the electrode patterns are integrally connected is rectangular.
  • the number of light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the green sub-pixel is one or two, and the number of light-shielding patterns is not related to the light-emitting pattern of the green sub-pixel.
  • One or two light-shielding patterns integrally connected to the first electrode pattern of the device are respectively integrally connected to one or two sides of the first electrode pattern of the light-emitting device of the green sub-pixel.
  • the sub-pixel opening in the corresponding sub-pixel opening and the first electrode pattern, has the same shape as the main body part of the first electrode pattern, and the sub-pixel opening has the same shape as the main body of the first electrode pattern.
  • the first orthographic projection of the opening on the base substrate is located inside the second orthographic projection of the main part of the first electrode pattern on the base substrate, and the first orthographic projection and the second orthogonal projection are The minimum distance of the projected edge is 1.5 microns - 3.5 microns.
  • the light-emitting devices of the red sub-pixel and the blue sub-pixel are located in the same row
  • the light-emitting devices of the green sub-pixel are located in approximately the same row
  • the light-emitting devices of the red sub-pixel are located in the same row.
  • the rows of pixels and the light-emitting devices of the blue sub-pixels are alternately arranged with the rows of the light-emitting devices of the green sub-pixels.
  • the driving circuit layer further includes a plurality of second gaps.
  • the plurality of second gaps allow light from the display side to pass through. In the direction of the base substrate, the second gap does not overlap with the plurality of first electrode patterns and the plurality of light shielding patterns.
  • the distance between the plurality of second gaps and the centers of the plurality of sub-pixel openings is greater than 33 microns.
  • the orthographic projections of the plurality of second gaps on the base substrate are respectively located between the orthographic projections of the light-emitting control signal lines on the base substrate and the orthographic projections of the second gaps on the base substrate.
  • the nearest reset voltage line of the light emitting control signal line is between the orthographic projections on the base substrate.
  • the orthographic projections of at least part of the plurality of second gaps on the base substrate are respectively located where the light emission control signal lines for the blue sub-pixels are located.
  • the orthographic projection on the base substrate and the orthographic projection of the reset voltage line on the base substrate for the red sub-pixel which is located in the next row of the blue sub-pixel and is connected to the orthographic projection on the base substrate.
  • the blue sub-pixels are adjacent; and/or the orthographic projections of at least part of the plurality of second gaps on the substrate are respectively located on the light-emitting control signal lines for the red sub-pixels on the substrate.
  • the orthographic projection on the substrate and the orthographic projection on the substrate of the reset voltage line for the blue sub-pixel, which is located in the next row of the red sub-pixel and is connected to the Red sub-pixels are adjacent.
  • the width of at least some of the second gaps among the plurality of second gaps is greater than 4.0 microns.
  • the drive circuit layer includes a plurality of pixel drive circuits and a first planarization layer, and the first planarization layer is disposed away from the plurality of pixel drive circuits.
  • One side of the base substrate includes a plurality of first via holes, the plurality of first via holes respectively expose the output terminals of the plurality of pixel driving circuits, and the first electrode layer is disposed on the first planarization surface.
  • the display substrate further It includes a spacer layer disposed on the side of the pixel definition layer away from the base substrate, the spacer layer includes a plurality of spacers; wherein, in a direction perpendicular to the base substrate, the spacers The plurality of spacers do not overlap the plurality of first via holes.
  • the minimum distance between the plurality of spacers and the plurality of first via holes is greater than 2.0 microns.
  • the driving circuit layer includes a plurality of pixel driving circuits, a first planarization layer, a connection electrode layer and a second planarization layer, and the first planarization layer is disposed on the display substrate.
  • the side of the plurality of pixel driving circuits away from the base substrate includes a plurality of first via holes.
  • the plurality of first via holes respectively expose the output terminals of the plurality of pixel driving circuits and connect the electrode layers.
  • a side of the first planarization layer away from the base substrate includes a plurality of connection electrodes, and the plurality of connection electrodes are electrically connected to the plurality of pixel drivers through the first via holes.
  • the second planarization layer is disposed on a side of the connection electrode layer away from the base substrate, and includes a plurality of second via holes, and the plurality of second via holes respectively expose the plurality of Connecting electrodes;
  • the first electrode layer is disposed on a side of the second planarization layer away from the base substrate, and the plurality of first electrode patterns are connected to the plurality of second via holes respectively.
  • the plurality of connection electrodes are electrically connected;
  • the display substrate further includes a spacer layer disposed on a side of the pixel defining layer away from the base substrate, and the spacer layer includes a plurality of spacers; wherein, In a direction perpendicular to the base substrate, the spacers do not overlap with the second via holes.
  • the minimum distance between the plurality of spacers and the plurality of second via holes is greater than 2.0 microns.
  • the heights of the plurality of spacers in a direction perpendicular to the base substrate are 1.8 microns to 2.4 microns.
  • the plurality of pixel driving circuits at least partially overlap the plurality of sub-pixel openings in a direction perpendicular to the base substrate.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure.
  • Figure 1 is a partial plan view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 2 is a partial plan view of the first electrode layer of the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 3 is a partial plan view of the driving circuit layer of the display substrate provided by at least one embodiment of the present disclosure
  • Figure 4 is a partial cross-sectional schematic diagram of a sub-pixel in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 5 is a partial plan view of the overlap of the first electrode layer and the pixel definition layer of the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of the overlapping of a sub-pixel opening and a first electrode pattern of a sub-pixel in a display substrate according to at least one embodiment of the present disclosure
  • Figure 7 is a planar arrangement view of multiple spacers in a display substrate according to at least one embodiment of the present disclosure
  • Figure 8 is another partial cross-sectional schematic diagram of a sub-pixel in a display substrate provided by at least one embodiment of the present disclosure
  • Figure 9 is a circuit diagram of a pixel driving circuit of a display substrate provided by at least one embodiment of the present disclosure.
  • 10 to 14 are partial plan views of each conductive layer of the driving circuit layer of the display substrate provided in at least one embodiment of the present disclosure being stacked in sequence;
  • FIG. 15 is a partial cross-sectional schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the image sensor used for fingerprint recognition is usually combined on the non-display side of the display substrate of the display device.
  • the display substrate needs to have a light-transmitting gap.
  • the display substrate needs to have stable light transmittance to ensure that the image sensor can fully obtain the signal light with fingerprint information for fingerprint collection and identification functions.
  • circuit patterns in the display substrate. These circuit patterns are superimposed together so that the display substrate has irregular light-transmitting gaps at some locations. The larger light-transmitting gaps can be used to transmit fingerprint information.
  • small light-transmitting gaps are often unstable, and their size, quantity, and existence are uncertain. , thus causing the overall transmittance of the display substrate to be unstable and affecting the production yield of the display substrate.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate has a display side and includes a base substrate, a drive circuit layer, a first electrode layer and a pixel definition layer.
  • the drive circuit layer is disposed on the base substrate.
  • the pixel definition layer is disposed on a side of the first electrode layer away from the base substrate, and includes a plurality of sub-pixel openings, the plurality of sub-pixel openings respectively expose a plurality of first electrode patterns, wherein, on the side perpendicular to the base substrate direction, at least part of the plurality of light shielding patterns does not overlap with the plurality of sub-pixel openings, and at least part of the plurality of light shielding patterns respectively corresponds to and at least partially overlaps at least part of the first gaps among the plurality of first gaps, so as to at least partially overlap. Blocks light from the display side.
  • the first gap is blocked by the light-shielding pattern, thereby eliminating the instability of the first gap due to process fluctuations, thereby avoiding the instability zone of the first gap.
  • the light transmittance of the entire display substrate is unstable, that is, the light transmittance stability of the display substrate is improved; on the other hand, the light shielding pattern and the first electrode pattern are provided in the same first electrode layer, so that the light transmittance of the display substrate can be improved.
  • the same materials and the same patterning process are used to form, thereby simplifying the preparation process of the display substrate.
  • FIG. 1 shows a partial plan view of the display substrate.
  • Figure 2 shows a partial plan view of the first electrode layer of the display substrate in Figure 1.
  • Figure 3 shows 1 shows a partial plan view of a pixel driving circuit of the display substrate in FIG. 1
  • FIG. 4 shows a partial cross-sectional schematic view of a sub-pixel of the display substrate in FIG. 1 .
  • the display substrate has a display side, that is, the upper side in Figure 4, and a non-display side, that is, the lower side in Figure 4, and includes a base substrate 110, a driving circuit layer 120, The first electrode layer 1041 and the pixel defining layer 1017 and so on.
  • the driving circuit layer 120 is disposed on the base substrate and includes a plurality of first gaps D1.
  • the plurality of first gaps D1 allow light from the display side to pass through.
  • the first electrode layer is provided on a side of the driving circuit layer 120 away from the base substrate 110 and includes a plurality of first electrode patterns 1041 and a plurality of light shielding patterns SH.
  • the pixel definition layer 1017 is provided on a side of the first electrode layer 1041 away from the base substrate 110 and includes a plurality of sub-pixel openings PO.
  • the plurality of sub-pixel openings PO respectively expose a plurality of first electrode patterns 1041.
  • At least part (eg, all) of the plurality of light-shielding patterns SH does not overlap with the plurality of sub-pixel openings PO.
  • At least part (for example, all) of them respectively correspond to at least part of the first gaps D1 among the plurality of first gaps D1 and at least partially overlap, so as to at least partially block the light from the display side.
  • the first gap D1 is blocked by the light-shielding pattern SH, thereby avoiding the overall light transmission of the display substrate caused by the instability of the size, number, etc. of the first gap D1
  • the rate is unstable, that is, the stability of the light transmittance of the display substrate is improved.
  • the light-shielding pattern and the first electrode pattern are disposed in the same first electrode layer, so that they can be formed using the same material and the same patterning process during the preparation process, thereby simplifying the preparation process of the display substrate.
  • the width of the plurality of first gaps D1 is less than or equal to 4.0 microns, such as less than or equal to 3.0 microns, less than or equal to 2.0 microns, less than or equal to 1.5 microns, or less than or equal to 1.0 microns.
  • the width of the first gap D1 refers to the size of the first gap D1 perpendicular to its extension direction. For example, when the first gap D1 is a rectangle (or approximately rectangular), its width is the length of the short side of the rectangle. When a gap D1 is an irregular pattern, the longest span direction of the irregular pattern is the extension direction, and the dimension perpendicular to the extension direction is the width of the first gap D1.
  • the first gap D1 with a smaller width is more prone to large process fluctuations during the preparation process, such as large size deviations, etc.
  • the first gap D1 with a smaller width is more likely to cause a decrease in the overall light transmittance of the display substrate. If a large deviation occurs, by using the light-shielding pattern SH to block the first gap D1 with a smaller width, the stability of the overall light transmittance of the display substrate can be improved to a greater extent.
  • the distance W1 between the plurality of first gaps D1 and the centers of the plurality of sub-pixel openings PO is less than 33 microns.
  • the distance W1 between the edges of the plurality of first gaps D1 away from the plurality of sub-pixel openings PO and the centers of the plurality of sub-pixel openings PO is less than 33 microns. That is, the plurality of first gaps D1 are distributed within a range of 33 micrometers from the center of the plurality of sub-pixel openings PO.
  • At least part of the light-shielding patterns SH among the plurality of light-shielding patterns SH are integrally connected to the plurality of first electrode patterns 1041 respectively.
  • the integrally connected first electrode pattern 1041 and the light shielding pattern SH present an irregular pattern as a whole.
  • the display substrate has a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels includes a light-emitting device EM, and the plurality of first electrode patterns 1041 respectively serve as anodes of the light-emitting devices EM of the plurality of sub-pixels.
  • the light-emitting device EM further includes a luminescent material layer 1042 disposed on a side of the first electrode pattern 1041 away from the base substrate 110 and a second electrode disposed on a side of the luminescent material layer 1042 away from the base substrate 110 Layer 1043.
  • the first electrode pattern 1041 includes a main body part M and a connection part CL, and the connection part CL extends from the main body part M.
  • the main body part M is a part used to drive the light emitting device to emit light.
  • the luminescent material layer 1042 directly contacts at least part of the main body part M to be driven by the main body part M.
  • the connection portion CL is used to electrically connect the main body portion M and the pixel driving circuit, and the connection portion CL does not directly contact the portion of the light-emitting material layer 1042 used for light emission.
  • the planar shapes of the main body parts M of the plurality of first electrode patterns 1041 are respectively polygons (such as hexagons, pentagons, quadrilaterals, etc.) or graphics with arc edges (such as circles, elliptical, mango-shaped, etc.), the planar shapes of the plurality of light-shielding patterns SH are respectively polygonal, such as triangles or quadrilaterals (such as rectangles, parallelograms, rhombuses, etc.).
  • the plurality of sub-pixels includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.
  • the planar shape of the main body part M of the first electrode pattern 1041 of the light emitting device of the red subpixel R is a hexagon (hereinafter referred to as a first hexagon), which is different from that of the red subpixel.
  • the first electrode pattern 1041 of the light-emitting device is integrally connected to the light-shielding pattern RSH in a triangular shape.
  • the number of light-shielding patterns RSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the red sub-pixel R is two, and the two light-shielding patterns RSH are symmetrically distributed.
  • the planar shape of the main body part M of the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is a hexagon (hereinafter referred to as a second hexagon). shape), the second hexagon and the first hexagon are, for example, similar figures, and the size of the second hexagon is larger than the size of the first hexagon.
  • the light-shielding pattern BSH integrally connected with the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is triangular or rectangular.
  • the number of light-shielding patterns BSH integrally connected with the first electrode pattern 1041 of the light-emitting device of blue sub-pixel B is three, and the three light-shielding patterns BSH are respectively connected with the first electrode pattern 1041 of the light-emitting device of blue sub-pixel B.
  • the three sides of pattern 1041 are connected in one piece.
  • the three light-shielding patterns BSH include two triangular light-shielding patterns and one rectangular pattern.
  • the two triangular light-shielding patterns are symmetrically distributed.
  • the one rectangular pattern is aligned with the left side of the first electrode pattern 1041 sides and the left side of the triangle.
  • the planar shape of the main body part M of the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is a pentagon, which is different from that of the light-emitting device of the green sub-pixel G.
  • the light-shielding pattern GSH integrally connected to the first electrode pattern 1041 is rectangular.
  • the number of light-shielding patterns GSH integrally connected with the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is one or two, and the one or two light-shielding patterns GSH are respectively connected with the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G.
  • One or two sides of an electrode pattern 1041 are integrally connected.
  • one red sub-pixel R, two green sub-pixels G and one blue sub-pixel B form a pixel unit, and multiple pixel units are arranged in an array on the base substrate 110 .
  • the first electrode pattern 1041 of the light-emitting device of one of the two green sub-pixels G is connected to a rectangular light-shielding pattern GSH, and the light-emitting device of the other green sub-pixel G is connected.
  • the first electrode pattern 1041 connects two rectangular light-shielding patterns GSH.
  • the light-emitting devices of the red sub-pixel R and the blue sub-pixel B are located in the same row
  • the light-emitting devices of the green sub-pixel G are approximately located in the same row
  • the light-emitting devices of the red sub-pixel R and the blue sub-pixel B are located in the same row as the green sub-pixel.
  • the rows of the light-emitting devices of G are alternately arranged, thereby forming multiple pixel units arranged periodically.
  • the light-emitting devices of the green sub-pixels G are generally located in the same row means that, with reference to Figure 5, at least part of the light-emitting devices of any two adjacent green sub-pixels G are located on the same straight line,
  • the light-emitting devices of two adjacent green sub-pixels G may be offset relative to the row direction. That is, the line connecting the centers of the light-emitting devices of any two adjacent green sub-pixels G may be in the shape of a zigzag line Z.
  • FIG. 5 shows a schematic plan view of the first electrode layer and the pixel defining layer stack
  • FIG. 6 shows a schematic plan view of the main body part of the blue sub-pixel and the sub-pixel opening stack.
  • the sub-pixel opening PO has the same shape as the main body part M of the first electrode pattern 1041
  • the sub-pixel opening PO has the same shape as the main body part M of the first electrode pattern 1041 .
  • the first orthographic projection of the opening PO on the base substrate 110 is located inside the second orthographic projection of the main body part M of the first electrode pattern 1041 on the base substrate 110 , and the edge of the first orthographic projection and the second orthogonal projection is minimum.
  • the distance L1 is 1.5 microns to 3.5 microns, such as 2.0 microns, 2.5 microns or 3.0 microns.
  • the sub-pixel opening PO fully exposes the first electrode pattern 1041.
  • the area defined by the sub-pixel opening PO is the effective light-emitting area of the light-emitting device EM. In this area, the light-emitting material layer 1042 is in contact with the main body part M of the first electrode pattern 1041. Direct contact to be driven.
  • the first electrode pattern 1041 of a green sub-pixel G in each pixel unit may also include a transistor light-shielding pattern TSH, which is used to block the transistor light-shielding pattern TSH provided below it.
  • Thin film transistor (such as the thin film transistor T2 described later) to prevent light from irradiating the thin film transistor and affecting the switching performance of the thin film transistor.
  • the driving circuit layer 120 further includes a plurality of second gaps D2.
  • the plurality of second gaps D2 allow light from the display side to pass through, perpendicular to the substrate.
  • the second gap D2 does not overlap with the plurality of first electrode patterns 1041 and the plurality of light shielding patterns SH.
  • the second gap D2 can allow light from the display side to transmit to the non-display side of the display substrate.
  • the second gap D2 can transmit signal light with fingerprint information to the image sensor S.
  • the width of at least part of the plurality of second gaps D2 is greater than 1.0 micrometer, or greater than 1.5 micrometer, or greater than 2.0 micrometer, or greater than 3.0 micrometer, or greater than 4.0 micrometer.
  • the width of the second gap D2 refers to the size of the second gap D2 perpendicular to its extension direction. Therefore, the size of the second gap D2 is larger, which can fully realize the light transmission effect; and because the size of the second gap D2 is larger, it will not have a large deviation during the preparation process. Even if a small deviation occurs, its It also has little impact on the stability of the light transmittance of the entire display substrate.
  • the distance W2 between the plurality of second gaps D2 and the centers of the plurality of sub-pixel openings PO is greater than 33 microns.
  • the distance W2 between the edges of the plurality of second gaps D2 away from the sub-pixel opening PO and the center of the sub-pixel opening PO is greater than 33 micrometers.
  • the orthographic projections of the plurality of second gaps D2 on the base substrate 110 are respectively located at the orthographic projections of the light-emitting control signal line EM on the base substrate 110 and the orthogonal projections of the light-emitting control signal lines EM on the base substrate 110 .
  • Line EM is between the orthogonal projection of the nearest reset voltage line VINT on base substrate 110 . The connection relationship and usage of the light emission control signal line EM and the reset voltage line VINT will be described in detail later.
  • the orthographic projections of at least part of the plurality of second gaps D2 (for example, the second gaps D2 on the right side in the figure) on the substrate 110 are respectively located at the luminous positions for the blue sub-pixel B.
  • the red sub-pixel R is located between the blue sub-pixel B and the base substrate 110. The next row is adjacent to the above-mentioned blue sub-pixel B.
  • the orthographic projections of at least part of the plurality of second gaps D2 (for example, the second gap D2 on the left side in the figure) on the substrate 110 are respectively located at the light emission control for the red sub-pixel R.
  • the above-mentioned blue sub-pixel B is located between the above-mentioned red sub-pixel R
  • the next row is adjacent to the above-mentioned red sub-pixel R.
  • the plurality of second gaps D2 are located in the gaps of the pixel driving circuits of the blue sub-pixel B and the red sub-pixel R.
  • the driving circuit layer 120 includes a plurality of pixel driving circuits and a first planarization layer 1016 .
  • the pixel driving circuit includes a plurality of thin film transistors and at least one storage capacitor, and may be formed, for example, as 2T1C (ie, two thin film transistors and one storage capacitor), 7T1C (ie, seven thin film transistors and one storage capacitor), or 8T2C (ie, eight thin film transistors and one storage capacitor). transistor and a storage capacitor) and other structures.
  • 2T1C ie, two thin film transistors and one storage capacitor
  • 7T1C ie, seven thin film transistors and one storage capacitor
  • 8T2C ie, eight thin film transistors and one storage capacitor
  • FIG. 4 shows a thin film transistor T and a storage capacitor C electrically connected to the light emitting device EM.
  • the thin film transistor T includes an active layer 1021 , a gate electrode 1022 , a first source-drain electrode 1023 and a second source-drain electrode 1024 .
  • the storage capacitor C includes a first capacitor electrode 1031 and a second capacitor electrode 1032 .
  • the first capacitor electrode 1031 and the gate electrode 1022 are arranged in the same layer.
  • “same layer arrangement” means that two functional layers or structural layers are formed on the same layer and with the same material in the hierarchical structure of the display substrate. That is, in the preparation process, the two functional layers or structural layers are formed on the same layer.
  • the layers or structural layers can be formed from the same material layer and can be formed into the desired patterns and structures by the same patterning process.
  • the first planarization layer 1016 is provided on a side of the plurality of pixel driving circuits away from the base substrate 1011 , and includes a plurality of first via holes VH1 , and the plurality of first via holes VH1 respectively expose the
  • the output terminals of the plurality of pixel driving circuits such as the first source and drain electrodes 1023 of the thin film transistor T
  • the first electrode layer is disposed on the side of the first planarization layer 1016 away from the base substrate 110, and the plurality of first electrodes
  • the pattern 1041 is electrically connected to the output terminals of the plurality of pixel driving circuits through a plurality of first via holes VH1 respectively.
  • the pixel driving circuit can control the voltage applied to the first electrode pattern 1041 through the thin film transistor T.
  • the display substrate further includes a spacer layer 1018 disposed on a side of the pixel definition layer 1017 away from the base substrate 110 .
  • the spacer layer 1018 includes a plurality of spacers PS.
  • the height of the spacers PS is 1.8 microns to 2.4 microns, such as 2.0 microns or 2.2 microns. Therefore, the spacers PS can have sufficient height, so that during the preparation process of the display substrate, for example, when forming the luminescent material layer 1042 by evaporation or other methods, the mask plate used can be fully supported on the multiple spacers PS. , without causing undesirable phenomena such as deformation of the mask plate and scratching of the display substrate structure.
  • the plurality of spacers PS do not overlap the plurality of first vias VH1 in a direction perpendicular to the base substrate 110 . Since the first via hole VH1 is formed by hollowing out part of the material of the first planarization layer 1016, the material above the first via hole VH1 is prone to dents. If the spacer PS is formed above the first via hole VH1, it will cause spacers. The spacer PS sinks, and the height of the spacer PS relative to the base substrate 110 is reduced, which affects the supporting function of the spacer PS. By disposing the plurality of spacers PS and the plurality of first vias VH1 without overlapping, the plurality of spacers PS can effectively achieve the supporting function.
  • FIG. 7 shows a schematic planar arrangement of multiple spacers PS.
  • the minimum distance L2 between the plurality of spacers PS and the plurality of first vias VH1 is greater than 2.0 microns. Since the sidewalls of the first via hole VH1 are usually inclined sidewalls, the material formed above the first via hole VH1 around the first via hole VH1 is also prone to dents.
  • the via holes VH1 are spaced at a certain distance, which can fully avoid the possible impact of the first via hole VH1 on the spacer PS, so that the spacer PS has a sufficient height to fully realize the supporting function.
  • FIG. 8 shows another partial cross-sectional view of a sub-pixel on the display substrate.
  • the driving circuit layer includes a plurality of pixel driving circuits, a first planarization layer 1016 , a connection electrode layer and a second planarization layer 1019 .
  • the specific form of the pixel driving circuit can be referred to the above embodiments and will not be described again here.
  • the first planarization layer 1016 is disposed on a side of the plurality of pixel driving circuits away from the base substrate 110 , and includes a plurality of first via holes VH1 , and the plurality of first via holes VH1 respectively exposes a plurality of pixels.
  • the output end of the driving circuit, such as the first source and drain electrode 1023 of the thin film transistor T, the connection electrode layer is disposed on the side of the first planarization layer 1016 away from the base substrate 110, and includes a plurality of connection electrodes CEL, a plurality of connection electrodes CEL is electrically connected to the output terminals of a plurality of the pixel driving circuits through first via holes VH1 respectively.
  • the second planarization layer 1019 is provided on a side of the connection electrode layer away from the base substrate 110 and includes a plurality of second via holes VH2.
  • the plurality of second via holes VH2 respectively expose a plurality of connection electrodes CEL.
  • the first electrode layer is disposed on a side of the second planarization layer 1019 away from the base substrate 110 , and the plurality of first electrode patterns 1041 are electrically connected to the plurality of connection electrodes CEL through a plurality of second via holes VH2 respectively.
  • the display substrate further includes a spacer layer 1018 disposed on a side of the pixel definition layer 1017 away from the base substrate 110 .
  • the spacer layer 1018 includes a plurality of spacers PS.
  • the height of the spacers PS is 1.8 microns to 2.4 microns, such as 2.0 microns or 2.2 microns.
  • the plurality of spacers PS and the plurality of second via holes VH2 do not overlap. For example, referring to FIG.
  • the minimum distance L2 between the plurality of spacers PS and the plurality of second via holes VH2 is greater than 2.0 microns. This can fully avoid the possible impact of the second via hole VH2 on the spacer PS, so that the spacer PS has a sufficient height to fully realize the supporting function.
  • a plurality of pixel driving circuits at least partially overlap with a plurality of sub-pixel openings PO in a direction perpendicular to the base substrate 110.
  • the light-emitting device formed in the sub-pixel opening PO can It is a top-emission light-emitting device.
  • the display substrate may further include a barrier layer 1012 and a buffer layer 1013 disposed on the base substrate 110 .
  • the barrier layer 1012 and the buffer layer 1013 can prevent impurities in the base substrate 110 from entering. multiple functional layers on the display substrate 110, thereby playing a protective role.
  • the barrier layer 1012 and the buffer layer 1013 may be made of one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the display substrate may further include a first gate insulating layer 1014A disposed on a side of the active layer 1021 away from the base substrate 110 , and a first gate insulating layer 1014A disposed on the gate electrode 1022 and the first capacitor electrode 1031 .
  • the second gate insulating layer 1014B on the side away from the base substrate 110 and the interlayer insulating layer 1015 provided on the side of the second capacitor electrode 1032 away from the base substrate 110 .
  • the first gate insulating layer 1014A, the second gate insulating layer 1014B, and the interlayer insulating layer 1015 may be made of one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the display substrate may also include an encapsulation layer EN disposed on a side of the light-emitting device EM away from the substrate substrate 110 .
  • the encapsulation layer EN may be a composite encapsulation layer, including the first inorganic encapsulation layer 1051 , the first organic encapsulation layer 1052 and the second inorganic encapsulation layer 1053.
  • the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be made of one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the first organic encapsulation layer 1052 may be made of one or more organic insulating materials such as resin and polyimide.
  • the pixel driving circuit of the sub-pixel adopts a 7T1C structure.
  • FIG. 9 shows a circuit diagram of the pixel driving circuit of the 7T1C structure.
  • the pixel driving circuit of the 7T1C structure includes seven thin film transistors T1-T7 and a storage capacitor C1, and has a connection relationship as shown in the accompanying figure.
  • the pixel driving circuit has, for example, the following four-stage driving process.
  • the seven thin film transistors T1-T7 are all P-type transistors, that is, the gate of each transistor is turned on when the low level is connected, and is turned off when the high level is connected.
  • the first reset signal RST1 is input, the fourth transistor T4 is turned on, and the reset voltage VINT is applied to the control terminal (such as the gate) of the driving transistor T1; the first light-emitting control signal EM1 is input, the fifth transistor T5 is turned on, The first voltage VDD is applied to the second node N2.
  • the fourth transistor T4 is turned on by the low level of the first reset signal RST1, and the fifth transistor T5 is turned on by the low level of the first light emission control signal EM1; at the same time, the second transistor T2, the The third transistor T3, the sixth transistor T6 and the seventh transistor T7 are turned off by the high-level signals respectively connected to them.
  • the reset voltage VINT (a low-level signal, which may be grounded or another low-level signal, for example) can be applied to the gate of the first transistor T1.
  • the first voltage VDD (high level signal) can be applied to the source of the first transistor T1, so that the gate and source of the first transistor T1 can be connected during the initialization phase 1.
  • the voltage VGS satisfies:
  • the scanning signal GATE and the data signal DATA are input, the second transistor T2, the driving transistor T1 and the third transistor T3 are turned on, the data signal DATA is written into the driving transistor T1, and the third transistor T3 is opposite to the driving transistor T1 Perform threshold compensation.
  • the second transistor T2 and the third transistor T3 are turned on by the low level of the scan signal GATE.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off by the high-level signals respectively connected to them.
  • the data signal DATA charges the first node N1 (that is, charges the storage capacitor C1) after passing through the second transistor T2, the first transistor T1, and the third transistor T3. That is to say, the first node The potential of N1 gradually increases. It is easy to understand that since the second transistor T2 is turned on, the potential of the second node N2 remains at Vdata. At the same time, according to the own characteristics of the first transistor T1, when the potential of the first node N1 increases to Vdata+Vth, the first transistor T1 is turned off. , the charging process ends. It should be noted that Vdata represents the voltage value of the data signal DATA, and Vth represents the threshold voltage of the first transistor.
  • the potentials of the first node N1 and the third node N3 are both Vdata+Vth, that is to say, the voltage information with the data signal DATA and the threshold voltage Vth is stored in the storage capacitor C1 , to provide grayscale display data and compensate the threshold voltage of the first transistor T1 itself during the subsequent light-emitting phase.
  • the second light emitting control signal EM2 and the second reset signal RST2 are input, the sixth transistor T6 and the seventh transistor T7 are turned on, and the first transistor T1, the third transistor T3 and the sixth transistor T6 are reset.
  • the sixth transistor T6 is turned on by the low level of the second light emitting control signal EM2, and the seventh transistor T7 is turned on by the low level of the second reset signal RST2; at the same time, the second transistor T2 and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are cut off by the high levels connected to them respectively.
  • the reset voltage VINT is a low-level signal (for example, it can be grounded or another low-level signal)
  • the drain of the first transistor T1 is discharged through the sixth transistor T6 and the seventh transistor T7, thereby discharging the third transistor.
  • the potentials of the node N3 and the fourth node N4 are reset simultaneously.
  • the drain of the first transistor T1 is reset, so that it can be maintained at a fixed potential without affecting the display effect of the display device using the above pixel circuit due to the uncertainty of the drain potential.
  • the fourth node N4 is also reset, that is, the OLED is reset, so that the OLED can be displayed in a black state and not emit light before the light-emitting stage 4, thereby improving the contrast and other display effects of the display device using the above-mentioned pixel circuit.
  • the first light emitting control signal EM1 and the second light emitting control signal EM2 are input, and the thin film transistor T5, the thin film transistor T6 and the driving circuit thin film transistor T1 are turned on.
  • the thin film transistor T6 applies the driving current to the light emitting element 600 to make it emit light. .
  • the fifth transistor T5 is turned on by the low level of the first light-emitting control signal EM1
  • the sixth transistor T6 is turned on by the low-level of the second light-emitting control signal EM2
  • the second transistor T2 and the third transistor T3 , the fourth transistor T4 and the seventh transistor T7 are turned off by their respective high levels; at the same time, the potential of the first node N1 is Vdata+Vth, and the potential of the second node N2 is VDD, so at this stage, the first transistor T1 Also remains on.
  • the first electrode pattern (such as anode) and the second electrode layer (such as cathode) of the light-emitting device D1 are respectively connected to the first voltage VDD (high voltage) and the second voltage VSS (low voltage). ), thereby emitting light under the action of the driving current flowing through the first transistor T1.
  • Figures 10 to 14 show partial plan views of various conductive layers of the driving circuit layer stacked in sequence.
  • There are insulating layers between adjacent conductive layers such as the above-mentioned gate insulating layer and interlayer insulating layer. These insulating layers The layers have multiple via holes for electrical connection.
  • each conductive layer is focused on, and the insulating layer is not described again.
  • FIG. 10 shows a schematic plan view of a semiconductor layer of a driving circuit layer, including the active layer of each thin film transistor T1-T7.
  • the active layers of the thin film transistors T1 - T7 are connected to each other to form an integrated structure.
  • the part of the semiconductor layer circled by the dotted line in FIG. 10 is the active layer of the thin film transistors T1 - T7 in the pixel driving circuit of a sub-pixel.
  • a first gate insulating layer 1014A is provided above the semiconductor layer, which is not shown in the figure.
  • FIG. 11 shows a schematic plan view of the first conductive layer of the driving circuit layer superimposed on the semiconductor layer of FIG. 10.
  • the first conductive layer includes the gate of each transistor, the first conductive layer of the storage capacitor.
  • the capacitor plate 1031 and some scanning lines GATE, light emission control lines EM and reset control lines RST.
  • the gate electrode of each transistor is a portion of the scanning line GATE, the emission control line EM, and the reset control line RST that overlaps with the active layer.
  • each row of sub-pixels is respectively connected to one scanning line GATE, two reset control lines RST, and one emission control line EM.
  • a first gate insulating layer 1014B is provided above the first conductive layer, which is not shown in the figure.
  • FIG. 12 shows a schematic plan view of the second conductive layer of the driving circuit layer superimposed on the stacked structure of FIG. 11.
  • the second conductive layer includes a second capacitor plate 1032 of the storage capacitor and a plurality of reset voltage line VINT.
  • An interlayer insulating layer 1015 is provided above the second conductive layer, which is not shown in the figure.
  • FIG. 13 shows a schematic plan view of the third conductive layer of the driving circuit layer superimposed on the stacked structure of FIG. 12.
  • the third conductive layer includes the first power line VDD, part of the data line Data and Source and drain electrodes of thin film transistors T1-T7, etc.
  • a planarization layer 1016 is provided above the third conductive layer, which is not shown in the figure.
  • Figure 14 shows a schematic plan view of a fourth conductive layer of the driving circuit layer superimposed on the stacked structure of Figure 13.
  • the fourth conductive layer includes another portion of the data line Data.
  • the fourth conductive layer may further include a connection electrode CEL.
  • a planarization layer 1019 is provided above the third conductive layer, which is not shown in the figure. Therefore, in this embodiment, the data line Data is distributed in two conductive layers to facilitate the arrangement of the data line Data.
  • FIG. 1 shows a schematic plan view of the first electrode layer stacked on the stacked structure of FIG. 14.
  • FIG. 1 shows a schematic plan view of the first electrode layer stacked on the stacked structure of FIG. 14.
  • FIG. 1 shows a schematic plan view of the first electrode layer stacked on the stacked structure of FIG. 14.
  • the substrate substrate 110 can be a rigid substrate such as glass or quartz or a flexible substrate such as polyimide
  • the gate 1022 can be copper (Cu), aluminum (Al), titanium (Ti),
  • Metal materials such as molybdenum (Mo) or alloy materials are, for example, formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure such as titanium/aluminum/titanium.
  • the first source and drain electrodes 1023 and 1024 can be made of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo) and other metal materials or alloy materials, for example, formed into a single-layer metal layer structure or Multi-layer metal layer structures, such as titanium/aluminum/titanium and other multi-layer metal layer structures.
  • the materials of the first electrode 1031 and the second electrode 1032 include metals or alloy materials such as aluminum, titanium, cobalt, and copper.
  • the active layer 1021 may be made of materials such as polysilicon and metal oxide.
  • the first planarization layer 1016, the second planarization layer 1019, the pixel definition layer 1017, the spacer layer 1018, and the first organic encapsulation layer 1052 of the encapsulation layer EN may use organic insulating materials such as polyimide and resin.
  • the display substrate may also include other structures besides the above-mentioned structures.
  • the display substrate may also include other structures besides the above-mentioned structures.
  • other structures please refer to related technologies, which will not be described again here.
  • each thin film transistor may be a P-type thin film transistor or an N-type thin film transistor, and the structure may be a bottom gate type, a top gate type, or a double gate type.
  • the structures shown in the drawings are only exemplary. , the embodiments of the present disclosure do not limit the specific form of each thin film transistor.
  • the display substrate in Figures 4 and 8 has at least one more conductive layer and one more insulating layer, and another gate is disposed in the conductive layer.
  • the two The two gate electrodes may be respectively located on a side of the active layer of the thin film transistor close to the base substrate and a side far away from the base substrate.
  • FIG. 15 shows a partial cross-sectional schematic view of the display device.
  • the display device may further include an image sensor S.
  • the image sensor S is coupled to the non-display side of the display substrate and is configured to receive data from the second gap. D2 passes through the light.
  • the orthographic projection of the image sensor S on the base substrate 110 at least partially overlaps the orthographic projection of the second gap D2 on the base substrate 110 .
  • the image sensor S may be a charge coupled device (CCD) image sensor, a complementary metal oxide semiconductor (CMOS) image sensor, or a photosensitive diode (such as a PIN photodiode, etc.) and other appropriate types of image sensors.
  • CCD charge coupled device
  • CMOS complementary metal oxide semiconductor
  • photosensitive diode such as a PIN photodiode, etc.
  • the image sensor can, for example, only sense light of a certain wavelength (such as red light or green light), or can sense all visible light.
  • the display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

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Abstract

一种显示基板和显示装置。显示基板具有显示侧，且包括衬底基板(110)、驱动电路层(120)、第一电极层和像素界定层(1017)。驱动电路层(120)设置在衬底基板(110)上，包括多个第一间隙(D1)，多个第一间隙(D1)允许来自显示侧的光透过。第一电极层设置在驱动电路层(120)的远离衬底基板(110)的一侧，包括多个第一电极图案(1041)和多个遮光图案(SH)。像素界定层(1017)设置在第一电极层的远离衬底基板(110)的一侧，包括多个子像素开口(PO)，多个子像素开口(PO)分别暴露多个第一电极图案(1041)。在垂直于衬底基板(110)的方向上，至少部分遮光图案(SH)与多个子像素开口(PO)不重叠，至少部分遮光图案(SH)分别与多个第一间隙(D1)中至少部分第一间隙(D1)对应且至少部分交叠，以至少部分遮挡来自显示侧的光。

Description

显示基板和显示装置 技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示装置具有自发光、对比度高、清晰度高、视角宽、功耗低、响应速度快、以及制造成本低等一系列优势，已经成为新一代显示装置的重点发展方向之一，因此受到越来越多的关注。
目前，显示装置通常还具有指纹识别等多种功能，此时，显示装置的结构可以针对这些功能做出相应的调整。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有显示侧，且包括衬底基板、驱动电路层、第一电极层和像素界定层，驱动电路层设置在所述衬底基板上，包括多个第一间隙，所述多个第一间隙允许来自所述显示侧的光透过，第一电极层设置在所述驱动电路层的远离所述衬底基板的一侧，包括多个第一电极图案和多个遮光图案，像素界定层设置在所述第一电极层的远离所述衬底基板的一侧，包括多个子像素开口，所述多个子像素开口分别暴露所述多个第一电极图案，其中，在垂直于所述衬底基板的方向上，所述多个遮光图案中的至少部分与所述多个子像素开口不重叠，所述多个遮光图案中的至少部分分别与所述多个第一间隙中至少部分第一间隙对应且至少部分交叠，以至少部分遮挡来自所述显示侧的光。
例如，本公开至少一实施例提供的显示基板中，所述多个第一间隙的宽度小于等于4.0微米。
例如，本公开至少一实施例提供的显示基板中，所述多个第一间隙与所述多个子像素开口的中心的距离小于33微米。
例如，本公开至少一实施例提供的显示基板中，所述多个遮光图案 中至少部分遮光图案分别与所述多个第一电极图案一体连接。
例如，本公开至少一实施例提供的显示基板中，所述多个第一电极图案每个包括主体部和连接部，所述主体部的平面形状分别呈多边形或者具有弧形边缘的图形，所述多个遮光图案的平面形状分别呈多边形。
例如，本公开至少一实施例提供的显示基板中，所述显示基板具有多个子像素，所述多个子像素中的每个包括发光器件，所述多个第一电极图案分别作为所述多个子像素的发光器件的阳极。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，其中，所述红色子像素的发光器件的第一电极图案的主体部的平面形状为六边形，与所述红色子像素的发光器件的第一电极图案一体连接的遮光图案呈三角形。
例如，本公开至少一实施例提供的显示基板中，与所述红色子像素的发光器件的第一电极图案一体连接的遮光图案的数量为两个，且与所述红色子像素的发光器件的第一电极图案一体连接的两个遮光图案对称分布。
例如，本公开至少一实施例提供的显示基板中，所述蓝色子像素的发光器件的第一电极图案的主体部的平面形状为六边形，与所述蓝色子像素的发光器件的第一电极图案一体连接的遮光图案呈三角形或矩形。
例如，本公开至少一实施例提供的显示基板中，与所述蓝色子像素的发光器件的第一电极图案一体连接的遮光图案的数量为三个，且与所述蓝色子像素的发光器件的第一电极图案一体连接的三个遮光图案分别与蓝色子像素的发光器件的第一电极图案的三个边一体连接。
例如，本公开至少一实施例提供的显示基板中，所述绿色子像素的发光器件的第一电极图案的主体部的平面形状为五边形，与所述绿色子像素的发光器件的第一电极图案一体连接的遮光图案呈矩形。
例如，本公开至少一实施例提供的显示基板中，与所述绿色子像素的发光器件的第一电极图案一体连接的遮光图案的数量为一个或两个，且与所述绿色子像素的发光器件的第一电极图案一体连接的一个或两个遮光图案分别与绿色子像素的发光器件的第一电极图案的一个或两个边一体连接。
例如，本公开至少一实施例提供的显示基板中，在对应的子像素开 口和第一电极图案中，所述子像素开口与所述第一电极图案的主体部的形状相同，所述子像素开口在所述衬底基板上的第一正投影位于所述第一电极图案的主体部在所述衬底基板上的第二正投影内部，且所述第一正投影和所述第二正投影的边缘的最小距离为1.5微米-3.5微米。
例如，本公开至少一实施例提供的显示基板中，所述红色子像素和所述蓝色子像素的发光器件位于同一行，所述绿色子像素的发光器件大致位于同一行，所述红色子像素和所述蓝色子像素的发光器件所在行与所述绿色子像素的发光器件所在行交替排布。
例如，本公开至少一实施例提供的显示基板中，所述驱动电路层还包括多个第二间隙，所述多个第二间隙允许来自所述显示侧的光透过，在垂直于所述衬底基板的方向上，所述第二间隙与所述多个第一电极图案和所述多个遮光图案不交叠。
例如，本公开至少一实施例提供的显示基板中，所述多个第二间隙与所述多个子像素开口的中心的距离大于33微米。
例如，本公开至少一实施例提供的显示基板中，所述多个第二间隙在所述衬底基板上的正投影分别位于发光控制信号线在所述衬底基板上的正投影和与所述发光控制信号线最近的复位电压线在所述衬底基板上的正投影之间。
例如，本公开至少一实施例提供的显示基板中，所述多个第二间隙中的至少部分在所述衬底基板上的正投影分别位于用于蓝色子像素的发光控制信号线在所述衬底基板上的正投影与用于红色子像素的复位电压线在所述衬底基板上的正投影之间，其中，所述红色子像素位于所述蓝色子像素的下一行且与所述蓝色子像素相邻；和/或所述多个第二间隙中的至少部分在所述衬底基板上的正投影分别位于用于红色子像素的发光控制信号线在所述衬底基板上的正投影与用于蓝色子像素的复位电压线在所述衬底基板上的正投影之间，其中，所述蓝色子像素位于所述红色子像素的下一行且与所述红色子像素相邻。
例如，本公开至少一实施例提供的显示基板中，所述多个第二间隙中至少部分第二间隙的宽度大于4.0微米。
例如，本公开至少一实施例提供的显示基板中，所述驱动电路层包括多个像素驱动电路以及第一平坦化层，第一平坦化层设置在所述多个 像素驱动电路的远离所述衬底基板的一侧，包括多个第一过孔，所述多个第一过孔分别暴露所述多个像素驱动电路的输出端，所述第一电极层设置在所述第一平坦化层的远离所述衬底基板的一侧，且所述多个第一电极图案分别通过所述多个第一过孔与所述多个像素驱动电路的输出端电连接；所述显示基板还包括设置在所述像素界定层远离所述衬底基板一侧的隔垫物层，所述隔垫物层包括多个隔垫物；其中，在垂直于所述衬底基板的方向上，所述多个隔垫物与所述多个第一过孔不重叠。
例如，本公开至少一实施例提供的显示基板中，在平行于所述衬底基板的方向上，所述多个隔垫物与所述多个第一过孔的最小距离大于2.0微米。
例如，本公开至少一实施例提供的显示基板中，所述驱动电路层包括多个像素驱动电路、第一平坦化层、连接电极层和第二平坦化层，第一平坦化层设置在所述多个像素驱动电路的远离所述衬底基板的一侧，包括多个第一过孔，所述多个第一过孔分别暴露所述多个像素驱动电路的输出端，连接电极层设置在所述第一平坦化层的远离所述衬底基板的一侧，包括多个连接电极，所述多个连接电极分别通过所述第一过孔电连接至所述多个所述像素驱动电路的输出端，第二平坦化层设置在所述连接电极层的远离所述衬底基板的一侧，包括多个第二过孔，所述多个第二过孔分别暴露所述多个连接电极；所述第一电极层设置在所述第二平坦化层的远离所述衬底基板的一侧，且所述多个第一电极图案分别通过所述多个第二过孔与所述多个连接电极电连接；所述显示基板还包括设置在所述像素界定层远离所述衬底基板一侧的隔垫物层，所述隔垫物层包括多个隔垫物；其中，在垂直于所述衬底基板的方向上，所述多个隔垫物与所述多个第二过孔不重叠。
例如，本公开至少一实施例提供的显示基板中，在平行于所述衬底基板的方向上，所述多个隔垫物与所述多个第二过孔的最小距离大于2.0微米。
例如，本公开至少一实施例提供的显示基板中，在垂直于所述衬底基板的方向上，所述多个隔垫物的高度为1.8微米-2.4微米。
例如，本公开至少一实施例提供的显示基板中，在垂直于所述衬底基板的方向上，所述多个像素驱动电路与所述多个子像素开口至少部分交 叠。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的显示基板的部分平面示意图；
图2为本公开至少一实施例提供的显示基板的第一电极层的部分平面示意图；
图3为本公开至少一实施例提供的显示基板的驱动电路层的部分平面示意图；
图4为本公开至少一实施例提供的显示基板中一个子像素的部分截面示意图；
图5为本公开至少一实施例提供的显示基板的第一电极层和像素界定层交叠的部分平面示意图；
图6为本公开至少一实施例提供的显示基板中一个子像素的子像素开口与第一电极图案的交叠示意图；
图7为本公开至少一实施例提供的显示基板中多个隔垫物的平面排布图；
图8为本公开至少一实施例提供的显示基板中一个子像素的另一部分截面示意图；
图9为本公开至少一实施例提供的显示基板的像素驱动电路的电路图；
图10-图14为本公开至少一实施例提供的显示基板的驱动电路层的各个导电层依次叠层的部分平面示意图；以及
图15为本公开至少一实施例提供的显示装置的部分截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公 开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在具有指纹识别功能的显示装置中，用于指纹识别的图像传感器通常结合在显示装置的显示基板的非显示侧，此时，显示基板中需要具有透光间隙，当手指触摸显示装置的显示侧表面时，被手指反射的具有指纹信息的信号光会通过上述透光间隙透射至图像传感器，从而图像传感器可以获取该信号光，以进行指纹采集以及识别等操作。
在上述显示装置中，显示基板需要具有稳定的光透过率，以保证图像传感器可以充分获取具有指纹信息的信号光，以进行指纹采集以及识别功能。通常来说，显示基板中具有多种电路图案，这些电路图案叠加在一起，以使得显示基板在一些位置具有不规则的透光间隙，其中较大的透光间隙可以用于透过具有指纹信息的信号光，由于制备过程的误差，例如多个功能层的对位误差以及电路图案的尺寸误差等，较小的透光间隙往往不稳定，其大小、数量、是否存在等都具有不确定性，因此导致显示基板的整体透过率不稳定，影响显示基板的制备良率。
本公开至少一实施例提供一种显示基板和显示装置，该显示基板具有显示侧，且包括衬底基板、驱动电路层、第一电极层和像素界定层，驱动电路层设置在衬底基板上，包括多个第一间隙，多个第一间隙允许来自显示侧的光透过，第一电极层设置在驱动电路层的远离衬底基板的一侧，包括多个第一电极图案和多个遮光图案，像素界定层设置在第一 电极层的远离衬底基板的一侧，包括多个子像素开口，该多个子像素开口分别暴露多个第一电极图案，其中，在垂直于衬底基板的方向上，多个遮光图案中的至少部分与多个子像素开口不重叠，多个遮光图案中的至少部分分别与多个第一间隙中至少部分第一间隙对应且至少部分交叠，以至少部分遮挡来自显示侧的光。
在本公开实施例提供的上述显示基板中，至少部分第一间隙被遮光图案遮挡，由此可以消除由于工艺波动带来的第一间隙的不稳定性，从而避免第一间隙的不稳定性带来的显示基板整体的光透过率不稳定，也即提高显示基板的光透过率稳定性；另一方面，该遮光图案与第一电极图案设置在相同的第一电极层中，从而可以在制备工艺中采用相同的材料以及相同的构图工艺形成，由此可以简化显示基板的制备工艺。
下面，通过几个具体的实施例来详细介绍本公开实施例提供的显示基板和显示装置。
本公开至少一实施例提供一种显示基板，图1示出了该显示基板的部分平面示意图，图2示出了图1中的显示基板的第一电极层的部分平面示意图，图3示出了图1中的显示基板的像素驱动电路的部分平面示意图，图4示出了图1中的显示基板的一个子像素的部分截面示意图。
如图1-图4所示，该显示基板具有显示侧，即图4中的上侧，还具有非显示侧，即图4中的下侧，且包括衬底基板110、驱动电路层120、第一电极层1041和像素界定层1017等。
驱动电路层120设置在衬底基板上，包括多个第一间隙D1，多个第一间隙D1允许来自显示侧的光透过。第一电极层设置在驱动电路层120的远离衬底基板110的一侧，包括多个第一电极图案1041和多个遮光图案SH。像素界定层1017设置在第一电极层1041的远离衬底基板110的一侧，包括多个子像素开口PO，多个子像素开口PO分别暴露多个第一电极图案1041。
在垂直于衬底基板110的方向上，也即图4中的竖直方向上，多个遮光图案SH中的至少部分(例如全部)与多个子像素开口PO不重叠，多个遮光图案SH中的至少部分(例如全部)分别与多个第一间隙D1中至少部分第一间隙D1对应且至少部分交叠，以至少部分遮挡来自显示侧的光。
由此，在本公开的实施例中，至少部分第一间隙D1被遮光图案SH遮挡，由此可以避免第一间隙D1的大小、数量等的不稳定性带来的显示基板整体的光透过率不稳定，也即提高显示基板的光透过率稳定性。另一方面，该遮光图案与第一电极图案设置在相同的第一电极层中，从而可以在制备工艺中采用相同的材料以及相同的构图工艺形成，由此可以简化显示基板的制备工艺。
例如，在一些实施例中，多个第一间隙D1的宽度小于等于4.0微米，例如小于等于3.0微米、小于等于2.0微米、小于等于1.5微米或者小于等于1.0微米。第一间隙D1的宽度指的是第一间隙D1在垂直于其延伸方向的尺寸，例如，当第一间隙D1为长方形(或者近似长方形)时，其宽度为长方形的短边边长，当第一间隙D1为不规则图形时，该不规则图形跨度最长的方向为延伸方向，垂直于该延伸方向的尺寸为第一间隙D1的宽度。
由于宽度较小的第一间隙D1在制备过程中更容易出现较大的工艺波动，例如出现尺寸较大偏差等，因此宽度较小的第一间隙D1更容易引起显示基板整体的光透过率出现较大偏差，通过采用遮光图案SH遮挡宽度较小的第一间隙D1，可以在更大程度上提高显示基板整体的光透过率稳定性。
例如，在一些实施例中，多个第一间隙D1与多个子像素开口PO的中心的距离W1小于33微米。例如，参考图1，多个第一间隙D1的远离多个子像素开口PO的边缘与多个子像素开口PO的中心的距离W1小于33微米。也即，多个第一间隙D1分布在距离多个子像素开口PO的中心33微米的范围内。
例如，在一些实施例中，多个遮光图案SH中至少部分遮光图案SH分别与多个第一电极图案1041一体连接。此时，如图1和图2所示，一体连接的第一电极图案1041与遮光图案SH的整体呈现不规则图形。
例如，在一些实施例中，显示基板具有阵列排布的多个子像素，多个子像素中的每个包括发光器件EM，多个第一电极图案1041分别作为多个子像素的发光器件EM的阳极。如图4所示，发光器件EM还包括设置在第一电极图案1041的远离衬底基板110一侧的发光材料层1042以及设置在发光材料层1042的远离衬底基板110一侧的第二电极 层1043。
例如，在一些实施例中，如图2所示，第一电极图案1041包括主体部M和连接部CL，连接部CL从主体部M延伸。主体部M为用于驱动发光器件发光的部分，例如，发光材料层1042直接接触主体部M的至少部分，以被主体部M驱动。连接部CL用于将主体部M与像素驱动电路电连接，连接部CL不会与发光材料层1042的用于发光的部分直接接触。
例如，如图2所示，多个第一电极图案1041的主体部M的平面形状分别呈多边形(例如六边形、五边形、四边形等)或者具有弧形边缘的图形(例如圆形、椭圆形、芒果形等)，多个遮光图案SH的平面形状分别呈多边形，例如三角形或者四边形(例如矩形、平行四边形、菱形等)等。
例如，在一些实施例中，多个子像素包括红色子像素R、绿色子像素G和蓝色子像素B。例如，如图1和图2所示，红色子像素R的发光器件的第一电极图案1041的主体部M的平面形状为六边形(后面称为第一六边形)，与红色子像素的发光器件的第一电极图案1041一体连接的遮光图案RSH呈三角形。例如，与红色子像素R的发光器件的第一电极图1041案一体连接的遮光图案RSH的数量为两个，且该两个遮光图案RSH对称分布。
例如，在一些实施例中，如图1和图2所示，蓝色子像素B的发光器件的第一电极图案1041的主体部M的平面形状为六边形(后面称为第二六边形)，第二六边形与第一六边形例如为相似图形，且第二六边形的尺寸大于第一六边形的尺寸。例如，与蓝色子像素B的发光器件的第一电极图案1041一体连接的遮光图案BSH呈三角形或矩形。例如，与蓝色子像素B的发光器件的第一电极图案1041一体连接的遮光图案BSH的数量为三个，且该三个遮光图案BSH分别与蓝色子像素B的发光器件的第一电极图案1041的三个边一体连接。
例如，如图1和图2所示，该三个遮光图案BSH包括两个三角形遮光图案和一个长方形图案，该两个三角形遮光图案对称分布，该一个长方形图案与第一电极图案1041的左侧边以及三角形的左侧边连接。
例如，在一些实施例中，如图1和图2所示，绿色子像素G的发 光器件的第一电极图案1041的主体部M的平面形状为五边形，与绿色子像素G的发光器件的第一电极图案1041一体连接的遮光图案GSH呈矩形。例如，与绿色子像素G的发光器件的第一电极图案1041一体连接的遮光图案GSH的数量为一个或两个，且该一个或两个遮光图案GSH分别与绿色子像素G的发光器件的第一电极图案1041的一个或两个边一体连接。
例如，在一些实施例中，一个红色子像素R、两个绿色子像素G和一个蓝色子像素B组成一个像素单元，多个像素单元在衬底基板110上阵列排布。例如，如图1和图2所示，两个绿色子像素G中的一个绿色子像素G的发光器件的第一电极图案1041连接一个长方形的遮光图案GSH，另一个绿色子像素G的发光器件的第一电极图案1041连接两个长方形的遮光图案GSH。
例如，红色子像素R和蓝色子像素B的发光器件位于同一行，绿色子像素G的发光器件大致位于同一行，红色子像素R和蓝色子像素B的发光器件所在行与绿色子像素G的发光器件所在行交替排布，由此形成周期排布的多个像素单元。
例如，在本公开的实施例中，绿色子像素G的发光器件大致位于同一行指的是，参考图5，任意相邻的两个绿色子像素G的发光器件的至少部分位于同一直线上，相邻的两个绿色子像素G的发光器件相对于行方向可以有所偏移，也即，任意相邻的两个绿色子像素G的发光器件的中心的连线可以为折线形Z。
例如，图5示出了第一电极层与像素界定层叠层的平面示意图，图6示出了蓝色子像素的主体部与子像素开口叠层的平面示意图。在一些实施例中，如图5和图6所示，在对应的子像素开口PO和第一电极图案1041中，子像素开口PO与第一电极图案1041的主体部M的形状相同，子像素开口PO在衬底基板110上的第一正投影位于第一电极图案1041的主体部M在衬底基板110上的第二正投影内部，且第一正投影和第二正投影的边缘的最小距离L1为1.5微米-3.5微米，例如2.0微米、2.5微米或者3.0微米等。由此，子像素开口PO充分暴露第一电极图案1041，子像素开口PO所限定的区域即为发光器件EM的有效发光区域，发光材料层1042在该区域与第一电极图案1041的主体部M 直接接触，以被驱动。
例如，在一些实施例中，如图5所示，每个像素单元中的一个绿色子像素G的第一电极图案1041还可以包括晶体管遮光图案TSH，晶体管遮光图案TSH用于遮挡其下方设置的薄膜晶体管(例如后续描述的薄膜晶体管T2)，以防止有光照射到该薄膜晶体管而影响到该薄膜晶体管的开关性能。
例如，在一些实施例中，如图1和图3所示，驱动电路层120还包括多个第二间隙D2，多个第二间隙D2允许来自显示侧的光透过，在垂直于衬底基板110的方向上，第二间隙D2与多个第一电极图案1041和多个遮光图案SH不交叠。由此，第二间隙D2可以允许来自显示侧的光透过至显示基板的非显示侧。例如，在显示基板的非显示侧设置有图像传感器S时，该第二间隙D2可以透过具有指纹信息的信号光至图像传感器S。
例如，在一些实施例中，多个第二间隙D2中至少部分第二间隙D2的宽度大于1.0微米，或者大于1.5微米、或者大于2.0微米、或者大于3.0微米、或者大于4.0微米。第二间隙D2的宽度指的是第二间隙D2在垂直于其延伸方向的尺寸。由此，第二间隙D2的尺寸较大，可以充分实现透光作用；并且，由于第二间隙D2的尺寸较大，其在制备过程中不会出现大幅度偏差，即使出现较小偏差，其对显示基板整体的透光率稳定性影响也较小。
例如，在一些实施例中，多个第二间隙D2与多个子像素开口PO的中心的距离W2大于33微米。例如，参考图1，多个第二间隙D2的远离子像素开口PO的边缘与子像素开口PO的中心的距离W2大于33微米。
例如，在一些实施例中，如图1所示，多个第二间隙D2在衬底基板110上的正投影分别位于发光控制信号线EM在衬底基板110上的正投影和与发光控制信号线EM最近的复位电压线VINT在衬底基板110上的正投影之间。发光控制信号线EM和复位电压线VINT的连接关系以及用途等稍后详细介绍。
例如，如图1所示，多个第二间隙D2中的至少部分(例如图中右侧的第二间隙D2)在衬底基板110上的正投影分别位于用于蓝色子像 素B的发光控制信号线EM在衬底基板110上的正投影与用于红色子像素R的复位电压线VINT在衬底基板110上的正投影之间，上述红色子像素R位于上述蓝色子像素B的下一行且与上述蓝色子像素B相邻。
例如，如图1所示，多个第二间隙D2中的至少部分(例如图中左侧的第二间隙D2)在衬底基板110上的正投影分别位于用于红色子像素R的发光控制信号线EM在衬底基板110上的正投影与用于蓝色子像素B的复位电压线VINT在衬底基板110上的正投影之间，上述蓝色子像素B位于上述红色子像素R的下一行且与上述红色子像素R相邻。
也即，在本公开的实施例中，多个第二间隙D2位于蓝色子像素B和红色子像素R的像素驱动电路的间隙中。
例如，在一些实施例中，如图4所示，驱动电路层120包括多个像素驱动电路以及第一平坦化层1016。像素驱动电路包括多个薄膜晶体管和至少一个存储电容，例如可以形成为2T1C(即两个薄膜晶体管和一个存储电容)、7T1C(即七个薄膜晶体管和一个存储电容)或者8T2C(即八个薄膜晶体管和一个存储电容)等结构，本公开的实施例对像素驱动电路的具体形式不做限定。
例如，图4中示出了与发光器件EM电连接的薄膜晶体管T和一个存储电容C。如图4所示，薄膜晶体管T包括有源层1021、栅极1022、第一源漏电极1023和第二源漏电极1024。存储电容C包括第一电容电极1031和第二电容电极1032。第一电容电极1031与栅极1022同层设置。
需要注意的是，在本公开的实施例中，“同层设置”为两个功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，如图4所示，第一平坦化层1016设置在多个像素驱动电路的远离衬底基板1011的一侧，包括多个第一过孔VH1，多个第一过孔VH1分别暴露所述多个像素驱动电路的输出端，例如薄膜晶体管T的第一源漏电极1023，第一电极层设置在第一平坦化层1016的远离衬底基板110的一侧，且多个第一电极图案1041分别通过多个第一过孔VH1与多个像素驱动电路的输出端电连接。由此，像素驱动电路可以通过薄 膜晶体管T控制施加在第一电极图案1041上的电压。
例如，如图4所示，显示基板还包括设置在像素界定层1017远离衬底基板110一侧的隔垫物层1018，隔垫物层1018包括多个隔垫物PS。例如，在垂直于衬底基板110的方向上，即图中的竖直方向上，多个隔垫物PS的高度为1.8微米-2.4微米，例如2.0微米或者2.2微米等。由此隔垫物PS可以具有足够的高度，以在显示基板的制备过程中，例如在通过蒸镀等方式形成发光材料层1042时，采用的掩模板可以充分支撑在多个隔垫物PS上，而不会发生掩模板变形而刮坏显示基板结构等不良现象。
例如，在一些实施例中，在垂直于衬底基板110的方向上，多个隔垫物PS与多个第一过孔VH1不重叠。由于第一过孔VH1通过挖空第一平坦化层1016的部分材料形成，因此第一过孔VH1上方的材料容易出现凹陷，若隔垫物PS形成在第一过孔VH1上方，会导致隔垫物PS下陷，进而隔垫物PS相对于衬底基板110的高度减小，影响隔垫物PS的支撑作用。通过多个隔垫物PS与多个第一过孔VH1不重叠设置，可以使多个隔垫物PS有效实现支撑作用。
例如，图7示出了多个隔垫物PS的平面排布示意图。如图7所示，在一些实施例中，在平行于衬底基板110的方向上，多个隔垫物PS与多个第一过孔VH1的最小距离L2大于2.0微米。由于第一过孔VH1的侧壁通常为倾斜的侧壁，因此在第一过孔VH1四周，在第一过孔VH1上方形成的材料也容易出现凹陷，因此通过将隔垫物PS与第一过孔VH1间隔一定距离，可以充分避免第一过孔VH1可能对隔垫物PS造成的影响，使隔垫物PS具有足够的高度以充分实现支撑作用。
例如，在另一些实施例中，图8示出了显示基板上一个子像素的另一部分截面示意图。如图8所示，驱动电路层包括多个像素驱动电路、第一平坦化层1016、连接电极层和第二平坦化层1019。像素驱动电路的具体形式可以参见上述实施例，在此不再赘述。
如图8所示，第一平坦化层1016设置在多个像素驱动电路的远离衬底基板110的一侧，包括多个第一过孔VH1，多个第一过孔VH1分别暴露多个像素驱动电路的输出端，例如薄膜晶体管T的第一源漏电极1023，连接电极层设置在第一平坦化层1016的远离衬底基板110的一 侧，包括多个连接电极CEL，多个连接电极CEL分别通过第一过孔VH1电连接至多个所述像素驱动电路的输出端。第二平坦化层1019设置在连接电极层的远离衬底基板110的一侧，包括多个第二过孔VH2，多个第二过孔VH2分别暴露多个连接电极CEL。第一电极层设置在第二平坦化层1019的远离衬底基板110的一侧，且多个第一电极图案1041分别通过多个第二过孔VH2与多个连接电极CEL电连接。
如图8所示，显示基板还包括设置在像素界定层1017远离衬底基板110一侧的隔垫物层1018，隔垫物层1018包括多个隔垫物PS。例如，在垂直于衬底基板110的方向上，即图中的竖直方向上，多个隔垫物PS的高度为1.8微米-2.4微米，例如2.0微米或者2.2微米等。例如，在垂直于衬底基板110的方向上，多个隔垫物PS与多个第二过孔VH2不重叠。例如，参考图7，在平行于衬底基板110的方向上，多个隔垫物PS与多个第二过孔VH2的最小距离L2大于2.0微米。由此可以充分避免第二过孔VH2可能对隔垫物PS造成的影响，使隔垫物PS具有足够的高度以充分实现支撑作用。
例如，在本公开的实施例中，在垂直于衬底基板110的方向上，多个像素驱动电路与多个子像素开口PO至少部分交叠，此时，子像素开口PO中形成的发光器件可以为顶发射型发光器件。
例如，如图4和图8所示，显示基板还可以包括设置在衬底基板110上的阻挡层1012和缓冲层1013，阻挡层1012和缓冲层1013可以防止衬底基板110中的杂质进入到显示基板110上的多个功能层中，从而起到保护作用。例如，阻挡层1012、缓冲层1013可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料中的一种或多种。
例如，如图4和图8所示，显示基板还可以包括设置在有源层1021的远离衬底基板110一侧的第一栅绝缘层1014A、设置在栅极1022和第一电容电极1031的远离衬底基板110一侧的第二栅绝缘层1014B以及设置在第二电容电极1032的远离衬底基板110一侧的层间绝缘层1015。例如，第一栅绝缘层1014A、第二栅绝缘层1014B、层间绝缘层1015可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料中的一种或多种。
例如，如图4和图8所示，显示基板还可以包括设置在发光器件 EM的远离衬底基板110一侧的封装层EN，封装层EN可以为复合封装层，包括第一无机封装层1051、第一有机封装层1052和第二无机封装层1053。第一无机封装层1051和第二无机封装层1053可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料中的一种或多种。第一有机封装层1052可以采用树脂、聚酰亚胺等有机绝缘材料中的一种或多种。
例如，在一个实施例中，子像素的像素驱动电路采用7T1C结构，图9示出了7T1C结构的像素驱动电路的电路图。如图9所示，该7T1C结构的像素驱动电路包括七个薄膜晶体管T1-T7以及一个存储电容C1，并具有如附图所示的连接关系。该像素驱动电路例如具有如下四个阶段的驱动过程。在下面的描述中，以七个薄膜晶体管T1-T7均为P型晶体管为例，即各个晶体管的栅极在接入低电平时导通，而在接入高电平时截止。
在初始化阶段1，输入第一复位信号RST1，开启第四晶体管T4，将复位电压VINT施加至驱动晶体管T1的控制端(例如栅极)；输入第一发光控制信号EM1，开启第五晶体管T5，将第一电压VDD施加至第二节点N2。
例如，在初始化阶段1，第四晶体管T4被第一复位信号RST1的低电平导通，第五晶体管T5被第一发光控制信号EM1的低电平导通；同时，第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7被各自接入的高电平信号截止。
在初始化阶段1，由于第四晶体管T4导通，可以将复位电压VINT(低电平信号，例如可以接地或为其他低电平信号)施加至第一晶体管T1的栅极。同时，由于第五晶体管T5导通，可以将第一电压VDD(高电平信号)施加至第一晶体管T1的源极，从而在初始化阶段1可以使第一晶体管T1的栅极和源极的电压VGS满足：|VGS|>|Vth|(Vth为第一晶体管T1的阈值电压，例如在第一晶体管T1为P型晶体管时，Vth为负值)，从而使第一晶体管T1处于VGS为固定偏置的开态状态。
在数据写入和补偿阶段2，输入扫描信号GATE和数据信号DATA，开启第二晶体管T2、驱动晶体管T1和第三晶体管T3，数据信号DATA写入驱动晶体管T1，第三晶体管T3对驱动晶体管T1进行阈值补偿。
在数据写入和补偿阶段2，第二晶体管T2和第三晶体管T3被扫描信号GATE的低电平导通。同时，第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7被各自接入的高电平信号截止。
在数据写入和补偿阶段2，数据信号DATA经过第二晶体管T2、第一晶体管T1和第三晶体管T3后对第一节点N1进行充电(即对存储电容C1充电)，也就是说第一节点N1的电位逐渐增大。容易理解，由于第二晶体管T2开启，第二节点N2的电位保持为Vdata，同时根据第一晶体管T1的自身特性，当第一节点N1的电位增大到Vdata+Vth时，第一晶体管T1截止，充电过程结束。需要说明的是，Vdata表示数据信号DATA的电压值，Vth表示第一晶体管的阈值电压。
经过数据写入和补偿阶段2后，第一节点N1和第三节点N3的电位均为Vdata+Vth，也就是说将带有数据信号DATA和阈值电压Vth的电压信息被存储在存储电容C1中，以用于后续在发光阶段时，提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在复位阶段3，输入第二发光控制信号EM2和第二复位信号RST2，开启第六晶体管T6和第七晶体管T7，对第一晶体管T1、第三晶体管T3和第六晶体管T6进行复位。
在复位阶段3，第六晶体管T6被第二发光控制信号EM2的低电平导通，第七晶体管T7被第二复位信号RST2的低电平导通；同时，第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5被各自接入的高电平截止。
在复位阶段3，由于复位电压VINT为低电平信号(例如可以接地或为其他低电平信号)，第一晶体管T1的漏极经过第六晶体管T6和第七晶体管T7放电，从而将第三节点N3和第四节点N4的电位同时复位。
在复位阶段3，第一晶体管T1的漏极被复位，从而可以使其保持在一个固定的电位，而不会因为漏极电位的不确定而影响采用上述像素电路的显示装置的显示效果。同时，第四节点N4也被复位，即将OLED复位，从而可以使OLED在发光阶段4之前显示为黑态不发光，改善采用上述像素电路的显示装置的对比度等显示效果。
在发光阶段4，输入第一发光控制信号EM1和第二发光控制信号EM2，开启薄膜晶体管T5、薄膜晶体管T6和驱动电路薄膜晶体管T1，薄膜晶体管T6将驱动电流施加至发光元件600以使其发光。
在发光阶段4，第五晶体管T5被第一发光控制信号EM1的低电平导通，第六晶体管T6被第二发光控制信号EM2的低电平导通；第二晶体管T2、第三晶体管T3、第四晶体管T4和第七晶体管T7被各自接入的高电平而截 至；同时，第一节点N1的电位Vdata+Vth，第二节点N2的电位为VDD，所以在此阶段第一晶体管T1也保持导通。
如图8所示，在发光阶段4，发光器件D1的第一电极图案(例如阳极)和第二电极层(例如阴极)分别接入了第一电压VDD(高压)和第二电压VSS(低压)，从而在流经第一晶体管T1的驱动电流的作用下发光。
例如，图10-图14示出了驱动电路层的各个导电层依次叠层的部分平面示意图，相邻的导电层之间具有绝缘层，例如上述栅绝缘层以及层间绝缘层等，这些绝缘层中具有用于电连接的多个过孔，下面的实施例中着重描述各个导电层，绝缘层不再赘述。
例如，图10示出了驱动电路层的半导体层的平面示意图，半导体层包括各个薄膜晶体管T1-T7的有源层。例如，薄膜晶体管T1-T7的有源层彼此连接为一体的结构，例如图10中虚线框圈出的部分半导体层为一个子像素的像素驱动电路中薄膜晶体管T1-T7的有源层。例如，半导体层上方设置有第一栅绝缘层1014A，图中未示出。
例如，图11示出了驱动电路层的第一导电层叠加到图10的半导体层的平面示意图，如图11所示，该第一导电层包括每个晶体管的栅极、存储电容的第一电容极板1031以及一些扫描线GATE、发光控制线EM和复位控制线RST。例如，每个晶体管的栅极分别为扫描线GATE、发光控制线EM和复位控制线RST的与有源层交叠的部分。例如，每行子像素分别对应连接一条扫描线GATE、两条复位控制线RST和一条发光控制线EM。第一导电层上方设置有第一栅绝缘层1014B，图中未示出。
例如，图12示出了驱动电路层的第二导电层叠加到图11的叠层结构的平面示意图，如图12所示，该第二导电层包括存储电容的第二电容极板1032以及多条复位电压线VINT。第二导电层上方设置有层间绝缘层1015，图中未示出。
例如，图13示出了驱动电路层的第三导电层叠加到图12的叠层结构的平面示意图，如图13所示，该第三导电层包括第一电源线VDD、部分数据线Data以及薄膜晶体管T1-T7的源漏电极等。第三导电层上方设置有平坦化层1016，图中未示出。
例如，图14示出了驱动电路层的第四导电层叠加到图13的叠层结 构的平面示意图，如图13所示，该第四导电层包括另一部分数据线Data。例如，在一些实施例中，第四导电层还可包括连接电极CEL。第三导电层上方设置有平坦化层1019，图中未示出。由此，该实施例中，数据线Data分布在两个导电层中，以便于数据线Data的排布。
例如，图1示出了第一电极层叠加在图14的叠层结构的平面示意图，具体可以参见对图1的描述，这里不再赘述。
例如，本公开的实施例中，衬底基板110可以采用玻璃、石英等刚性基板或者聚酰亚胺等柔性基板，栅极1022可以采用铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)等金属材料或者合金材料，例如形成为单层金属层结构或者多层金属层结构，例如钛/铝/钛等多层金属层结构。第一源漏电极1023和第一源漏电极1024可以采用铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)等金属材料或者合金材料，例如形成为单层金属层结构或者多层金属层结构，例如钛/铝/钛等多层金属层结构。第一电极电极1031以及第二电极电极1032的材料包括铝、钛、钴、铜等金属或者合金材料。有源层1021可以采用多晶硅和金属氧化物等材料。
例如，第一平坦化层1016、第二平坦化层1019、像素界定层1017、隔垫物层1018以及封装层EN的第一有机封装层1052可以采用聚酰亚胺、树脂等有机绝缘材料。
例如，显示基板还可以包括除上述结构以外的其他结构，具体可以参考相关技术，这里不再赘述。
另外，需要说明的是，本公开的实施例对各功能层的材料不做限定，且各功能层的材料并不局限于上述示例。在本公开的实施例中，各薄膜晶体管可以为P型薄膜晶体管或者N型薄膜晶体管，结构可以为底栅型、顶栅型或者双栅型，附图中示出的结构仅仅是示例性的，本公开的实施例对各薄膜晶体管的具体形式不做限定。例如，在一些实施例中，当薄膜晶体管为双栅型时，图4和图8中的显示基板至少多一个导电层和一个绝缘层，该导电层中设置另一个栅极，此时，两个栅极可以分别位于薄膜晶体管的有源层的靠近衬底基板的一侧和远离衬底基板的一侧。
本公开至少一实施例提供一种显示装置，该显示装置包括上述任一 的显示基板。例如，图15示出了该显示装置的部分截面示意图，如图15所示，该显示装置还可以包括图像传感器S，图像传感器S结合在显示基板的非显示侧，配置为接收从第二间隙D2透过的光。例如，在一些实施例中，图像传感器S在衬底基板110上的正投影与第二间隙D2在衬底基板110上的正投影至少部分重叠。
例如，图像传感器S可以为电荷耦合装置(CCD)图像传感器、互补金属氧化物半导体(CMOS)型图像传感器或者光敏二极管(例如PIN光敏二极管等)等各种适当类型的图像传感器。根据需要，该图像传感器例如可以仅对某个波长的光(例如红光或绿光)感测，也可以对全部可见光进行感测。
例如，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (26)

  1. 一种显示基板，具有显示侧，且包括：
    衬底基板，
    驱动电路层，设置在所述衬底基板上，包括多个第一间隙，所述多个第一间隙允许来自所述显示侧的光透过，
    第一电极层，设置在所述驱动电路层的远离所述衬底基板的一侧，包括多个第一电极图案和多个遮光图案，
    像素界定层，设置在所述第一电极层的远离所述衬底基板的一侧，包括多个子像素开口，所述多个子像素开口分别暴露所述多个第一电极图案，
    其中，在垂直于所述衬底基板的方向上，所述多个遮光图案中的至少部分与所述多个子像素开口不重叠，所述多个遮光图案中的至少部分分别与所述多个第一间隙中至少部分第一间隙对应且至少部分交叠，以至少部分遮挡来自所述显示侧的光。
  2. 根据权利要求1所述的显示基板，其中，所述多个第一间隙的宽度小于等于4.0微米。
  3. 根据权利要求1或2所述的显示基板，其中，所述多个第一间隙距离所述多个子像素开口的中心的距离小于33微米。
  4. 根据权利要求1-3任一所述的显示基板，其中，所述多个遮光图案中至少部分遮光图案分别与所述多个第一电极图案一体连接。
  5. 根据权利要求1-4任一所述的显示基板，其中，所述多个第一电极图案的每个包括主体部和连接部，所述主体部平面形状分别呈多边形或者具有弧形边缘的图形，
    所述多个遮光图案的平面形状分别呈多边形。
  6. 根据权利要求1-5任一所述的显示基板，其中，所述显示基板具有多个子像素，所述多个子像素中的每个包括发光器件，所述多个第一电极图案分别作为所述多个子像素的发光器件的阳极。
  7. 根据权利要求6所述的显示基板，其中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，
    其中，所述红色子像素的发光器件的第一电极图案的主体部的平面形状为六边形，与所述红色子像素的发光器件的第一电极图案一体连接 的遮光图案呈三角形。
  8. 根据权利要求7所述的显示基板，其中，与所述红色子像素的发光器件的第一电极图案一体连接的遮光图案的数量为两个，且与所述红色子像素的发光器件的第一电极图案一体连接的两个遮光图案对称分布。
  9. 根据权利要求7或8所述的显示基板，其中，所述蓝色子像素的发光器件的第一电极图案的主体部的平面形状为六边形，与所述蓝色子像素的发光器件的第一电极图案一体连接的遮光图案呈三角形或矩形。
  10. 根据权利要求9所述的显示基板，其中，与所述蓝色子像素的发光器件的第一电极图案一体连接的遮光图案的数量为三个，且与所述蓝色子像素的发光器件的第一电极图案一体连接的三个遮光图案分别与蓝色子像素的发光器件的第一电极图案的三个边一体连接。
  11. 根据权利要求7-10任一所述的显示基板，其中，所述绿色子像素的发光器件的第一电极图案的主体部的平面形状为五边形，与所述绿色子像素的发光器件的第一电极图案一体连接的遮光图案呈矩形。
  12. 根据权利要求11所述的显示基板，其中，与所述绿色子像素的发光器件的第一电极图案一体连接的遮光图案的数量为一个或两个，且与所述绿色子像素的发光器件的第一电极图案一体连接的一个或两个遮光图案分别与绿色子像素的发光器件的第一电极图案的一个或两个边一体连接。
  13. 根据权利要求1-12任一所述的显示基板，其中，在对应的子像素开口和第一电极图案中，所述子像素开口与所述第一电极图案的主体部的形状相同，
    所述子像素开口在所述衬底基板上的第一正投影位于所述第一电极图案的主体部在所述衬底基板上的第二正投影内部，且所述第一正投影和所述第二正投影的边缘的最小距离为1.5微米-3.5微米。
  14. 根据权利要求7-13任一所述的显示基板，其中，所述红色子像素和所述蓝色子像素的发光器件位于同一行，所述绿色子像素的发光器件大致位于同一行，所述红色子像素和所述蓝色子像素的发光器件所在行与所述绿色子像素的发光器件所在行交替排布。
  15. 根据权利要求1-14任一所述的显示基板，其中，所述驱动电 路层还包括多个第二间隙，所述多个第二间隙允许来自所述显示侧的光透过，
    在垂直于所述衬底基板的方向上，所述第二间隙与所述多个第一电极图案和所述多个遮光图案不交叠。
  16. 根据权利要求15所述的显示基板，其中，所述多个第二间隙距离所述多个子像素开口的中心的距离大于33微米。
  17. 根据权利要求15或16所述的显示基板，其中，所述多个第二间隙在所述衬底基板上的正投影分别位于发光控制信号线在所述衬底基板上的正投影和与所述发光控制信号线最近的复位电压线在所述衬底基板上的正投影之间。
  18. 根据权利要求17所述的显示基板，其中，所述多个第二间隙中的至少部分在所述衬底基板上的正投影分别位于用于蓝色子像素的发光控制信号线在所述衬底基板上的正投影与用于红色子像素的复位电压线在所述衬底基板上的正投影之间，其中，所述红色子像素位于所述蓝色子像素的下一行且与所述蓝色子像素相邻；和/或
    所述多个第二间隙中的至少部分在所述衬底基板上的正投影分别位于用于红色子像素的发光控制信号线在所述衬底基板上的正投影与用于蓝色子像素的复位电压线在所述衬底基板上的正投影之间，其中，所述蓝色子像素位于所述红色子像素的下一行且与所述红色子像素相邻。
  19. 根据权利要求15-18任一所述的显示基板，其中，所述多个第二间隙中至少部分第二间隙的宽度大于4.0微米。
  20. 根据权利要求1-19任一所述的显示基板，其中，所述驱动电路层包括：
    多个像素驱动电路，以及
    第一平坦化层，设置在所述多个像素驱动电路的远离所述衬底基板的一侧，包括多个第一过孔，所述多个第一过孔分别暴露所述多个像素驱动电路的输出端，
    所述第一电极层设置在所述第一平坦化层的远离所述衬底基板的一侧，且所述多个第一电极图案分别通过所述多个第一过孔与所述多个像素驱动电路的输出端电连接；
    所述显示基板还包括设置在所述像素界定层远离所述衬底基板一侧的隔垫物层，所述隔垫物层包括多个隔垫物；
    其中，在垂直于所述衬底基板的方向上，所述多个隔垫物与所述多个第一过孔不重叠。
  21. 根据权利要求20所述的显示基板，其中，在平行于所述衬底基板的方向上，所述多个隔垫物与所述多个第一过孔的最小距离大于2.0微米。
  22. 根据权利要求1-19任一所述的显示基板，其中，所述驱动电路层包括：
    多个像素驱动电路，
    第一平坦化层，设置在所述多个像素驱动电路的远离所述衬底基板的一侧，包括多个第一过孔，所述多个第一过孔分别暴露所述多个像素驱动电路的输出端，
    连接电极层，设置在所述第一平坦化层的远离所述衬底基板的一侧，包括多个连接电极，所述多个连接电极分别通过所述第一过孔电连接至所述多个所述像素驱动电路的输出端，以及
    第二平坦化层，设置在所述连接电极层的远离所述衬底基板的一侧，包括多个第二过孔，所述多个第二过孔分别暴露所述多个连接电极；
    所述第一电极层设置在所述第二平坦化层的远离所述衬底基板的一侧，且所述多个第一电极图案分别通过所述多个第二过孔与所述多个连接电极电连接；
    所述显示基板还包括设置在所述像素界定层远离所述衬底基板一侧的隔垫物层，所述隔垫物层包括多个隔垫物；
    其中，在垂直于所述衬底基板的方向上，所述多个隔垫物与所述多个第二过孔不重叠。
  23. 根据权利要求22所述的显示基板，其中，在平行于所述衬底基板的方向上，所述多个隔垫物与所述多个第二过孔的最小距离大于2.0微米。
  24. 根据权利要求20-23任一所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述多个隔垫物的高度为1.8微米-2.4微米。
  25. 根据权利要求22-24任一所述的显示基板，其中，在垂直于所述 衬底基板的方向上，所述多个像素驱动电路与所述多个子像素开口至少部分交叠。
  26. 一种显示装置，包括权利要求1-25任一所述的显示基板。
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CN111477635A (zh) * 2020-04-13 2020-07-31 合肥维信诺科技有限公司 显示面板及其制作方法、显示装置
CN112070057A (zh) * 2020-09-18 2020-12-11 京东方科技集团股份有限公司 一种显示面板及显示装置
CN213519978U (zh) * 2020-10-30 2021-06-22 深圳市汇顶科技股份有限公司 显示屏、指纹识别装置和电子设备

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