WO2023213014A1

WO2023213014A1 - Anti-fuse structure and manufacturing method therefor, anti-fuse array and storage device

Info

Publication number: WO2023213014A1
Application number: PCT/CN2022/107098
Authority: WO
Inventors: 黄金荣
Original assignee: 长鑫存储技术有限公司; 长鑫集电(北京)存储技术有限公司
Priority date: 2022-05-05
Filing date: 2022-07-21
Publication date: 2023-11-09
Also published as: CN114582835A; CN114582835B

Abstract

Disclosed are an anti-fuse structure and a manufacturing method therefor, an anti-fuse array and a storage device. The anti-fuse structure comprises: a substrate comprising a first doped region and a second doped region; a first gate and a second gate located on the substrate, the first gate and the second gate being located on two sides of the first doped region, and the second gate being located between the first doped region and the second doped region; an isolation material layer located on the substrate and covering the first gate, the second gate and the substrate; and an air gap located between the first doped region and the isolation material layer in a direction perpendicular to the substrate, the air gap extending toward the first doped region.

Description

Antifuse structure and manufacturing method, antifuse array, storage device

This disclosure is based on a Chinese patent application with the application number 202210478057.7, the filing date being May 5, 2022, and the application name being "Antifuse structure and its manufacturing method, antifuse array, and storage device", and claims the Chinese patent Priority of the application, the entire content of this Chinese patent application is hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to, but is not limited to, an antifuse structure and a manufacturing method thereof, an antifuse array, and a storage device.

Background technique

One-time programmable devices based on anti-fuse technology are widely used in various types of chips. For example, anti-fuse programmable modules in DRAM (Dynamic Random Access Memory) chips can be used through Break down the antifuse unit to achieve redundant repair (including row repair and column repair); you can also program the antifuse programmable module to achieve various internal parameters of the chip (such as voltage, current, frequency, etc.) precise adjustment. With the continuous advancement of technology nodes, the shrinkage of anti-fuse related space dimensions is of great help to save costs and create revenue.

Contents of the invention

The present disclosure provides an overview of the subject matter that is described in detail. This summary is not intended to limit the scope of the claims.

The present disclosure provides an antifuse structure and a manufacturing method thereof, an antifuse array, and a storage device.

A first aspect of the present disclosure provides an antifuse structure, the antifuse structure including:

A substrate, including a first doped region and a second doped region;

The first gate electrode and the second gate electrode are located on the substrate, and the first gate electrode and the second gate electrode are located on both sides of the first doped region, and the second gate electrode is located on the between the first doped region and the second doped region;

A layer of isolation material, located on the substrate, covering the first gate, the second gate and the substrate;

An air gap is located between the first doped region and the isolation material layer in a direction perpendicular to the substrate, and the air gap extends toward the first doped region.

According to some embodiments of the present disclosure, the antifuse structure further includes:

A dielectric layer is located above the first doped region, and the air gap is located above the dielectric layer.

According to some embodiments of the present disclosure, the first doped region includes a first heavily doped region, and the doping concentration of the first heavily doped region is greater than the doping concentration of other regions of the first doped region.

According to some embodiments of the present disclosure, the isolation material layer includes a first curved portion, and the first curved portion and the dielectric layer are enclosed to form the air gap.

According to some embodiments of the present disclosure, the first curved portion is recessed toward a side away from the base in a direction perpendicular to the base.

According to some embodiments of the present disclosure, the dielectric layer includes a second curved portion that is recessed toward the substrate in a direction perpendicular to the substrate.

According to some embodiments of the present disclosure, the depth of the air gap extending to the first doped region is 10 to 100 nm.

According to some embodiments of the present disclosure, the first gate includes a first gate electrode and a first gate insulating layer, the second gate includes a second gate electrode and the second gate insulating layer, and the first The thickness of the gate insulating layer is smaller than the thickness of the second gate insulating layer.

According to some embodiments of the present disclosure, the antifuse structure further includes a third doped region located on a side of the first gate away from the first doped region.

A second aspect of the present disclosure provides an antifuse array. The antifuse array includes a plurality of antifuse structures as described above, and some of the antifuse structures in the plurality of antifuse structures are The first gate electrodes of the wire structures are electrically connected to each other, and/or the second gate electrodes of some of the anti-fuse structures in the plurality of anti-fuse structures are electrically connected to each other.

A third aspect of the present disclosure provides a method for manufacturing an antifuse structure. The method for manufacturing an antifuse structure includes:

providing a substrate in which a first doped region and a second doped region are formed;

A first gate and a second gate are formed on the substrate, the first gate and the second gate are located on both sides of the first doped region, and the second gate is located on the between the first doped region and the second doped region;

forming an isolation material layer on the substrate, the isolation material layer covering the first gate electrode, the second gate electrode and the substrate;

An air gap is formed between the isolation material layer and the first doped region, and the air gap extends toward the first doped region in a direction perpendicular to the substrate.

According to some embodiments of the present disclosure, before forming the air gap, the method of manufacturing the antifuse structure further includes:

The first doped region is etched to form a second curved portion; the second curved portion is recessed toward the substrate in a direction perpendicular to the substrate.

forming a dielectric layer on the third curved surface;

Wherein, the air gap is located above the dielectric layer.

High-concentration ion implantation is performed on the first doped region to form a first heavily doped region. The doping concentration of the first heavily doped region is greater than the doping concentration of other regions of the first doped region.

According to some embodiments of the present disclosure, forming the isolation material layer on the substrate includes: forming the isolation material layer through deposition, and adjusting the height of the air gap by controlling deposition parameters.

According to a fourth aspect of the present disclosure, a memory device is provided, the memory device including the antifuse array according to the above, wherein the antifuse array is a one-time programmable memory.

In the antifuse structure and its preparation method provided by the embodiments of the present disclosure, by forming an air gap between the first gate and the second gate, the voltage dividing distance is increased, the influence of coupling is reduced, and the parasitic capacitance is reduced. It can effectively prevent possible damage to the second gate-related device during the operation of the first gate-related device; therefore, even if the size of the anti-fuse is reduced, its performance can be ensured not to be affected.

Other aspects will be apparent after reading and understanding the drawings and detailed description.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain principles of the embodiments of the disclosure. In the drawings, similar reference numbers are used to identify similar elements. The drawings in the following description are of some, but not all, embodiments of the disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of the circuit principle of an antifuse structure in the related art;

Figure 2 is a schematic structural diagram of an antifuse structure in related art;

Figure 3 is a schematic cross-sectional structural diagram along the A-A direction in Figure 2;

Figure 4A is a schematic diagram of the current change of the antifuse structure in the related art before and after the first breakdown;

Figure 4B is a schematic diagram of the current change of the antifuse structure in the related art before and after being broken down again;

Figure 5 is a schematic structural diagram of an antifuse structure according to an exemplary embodiment;

Figure 6 is a schematic structural diagram of an antifuse structure according to an exemplary embodiment;

Figure 7 is a schematic structural diagram of an antifuse array according to an exemplary embodiment;

Figure 8 is a flow chart of a method of manufacturing an antifuse structure according to an exemplary embodiment;

Figure 9 is a schematic diagram of an antifuse structure after forming an isolation material layer according to an exemplary embodiment;

Figure 10 is a schematic diagram of an antifuse structure after forming a trench according to an exemplary embodiment;

FIG. 11 is a schematic diagram of an antifuse structure after forming a first heavily doped region according to an exemplary embodiment;

FIG. 12 is a schematic diagram of an antifuse structure after forming a third curved portion according to an exemplary embodiment;

Figure 13 is a schematic diagram of an antifuse structure after forming a dielectric layer according to an exemplary embodiment;

Figure 14 is a schematic diagram of an antifuse structure after forming an air gap according to an exemplary embodiment;

Figure 15 is a schematic diagram of the principle of using a slower deposition rate to deposit an isolation material layer;

Figure 16 is a schematic diagram of the principle of forming an isolation material layer by depositing at a higher deposition rate.

Reference signs:

101’, Bit Line; 120’, Anti-fuse; 130’, switching device;

100. Antifuse structure; 101. Bit line; 110. Substrate; 111. First doped region; 111a, first heavily doped region; 111b, third curved portion; 112, second doped region; 113. Third doped region; 120, first gate electrode; 121, first gate electrode; 122, first gate insulating layer; 130, second gate electrode; 131, second gate electrode; 132, second gate insulating layer; 140. Isolation material layer; 141. First curved surface; 150. Air gap; 151. Groove; 160. Dielectric layer; 161. Second curved surface;

200. Antifuse array.

Detailed ways

The technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the disclosed embodiments. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of this disclosure. It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments can be arbitrarily combined with each other.

With the miniaturization and increasing complexity of semiconductor processes, semiconductor chips have become more susceptible to various defects or impurities. The failure of any component (such as transistors, diodes, etc.) in the semiconductor structure often leads to the failure of the entire chip. defect. In order to solve this problem, antifuses are introduced into the integrated circuits of semiconductor chips to improve the yield of integrated circuits.

The antifuse structure is a protective structure in semiconductor circuits. It is used to open the backup circuit through breakdown fuse control after detecting circuit failure in the chip to repair the failed circuit or adjust some parameters. With the shrinkage design of the anti-fuse structure, the distance between the gate of the anti-fuse and the gate of the switching device becomes smaller, so that the large current generated when the anti-fuse is broken down does not have enough distance to disperse. Voltage will cause damage to the switching device and affect the identification of antifuse breakdown results. The current mainstream anti-fuse structure is mainly a dual-transistor structure. The Anti-fuse+ switching mode structure shown in Figures 1 to 3 includes a switching device 130' and an Anti-fuse anti-fuse 120'. For the sake of size reduction, the source and drain of the Anti-fuse 120' and the switching device 130' are shared.

Bit Line bit line 101' is connected to the source of the switching transistor, and reading or programming operations are performed to the antifuse structure through Bit Line bit line 101'. For example, applying different voltages to the gate of the switching device 130', the gate of the Anti-fuse anti-fuse 120' and the anti-fuse structure respectively can be achieved through the Bit Line bit line 101' and the Anti-fuse anti-fuse 120' The current between them determines the state of the antifuse structure.

When programming the Anti-fuse anti-fuse 120', the gate insulation layer of the Anti-fuse anti-fuse 120' needs to be broken down, that is, the Anti-fuse anti-fuse 120' is broken down, while ensuring that the switching device 130' normal operation, that is, not punctured or damaged.

When programming the Anti-fuse 120', the current anti-fuse structure is selected through the word line and bit line, and voltage U2' is applied to the switching device 130', so that the switching device 130' is turned on, and the switching device 130' The gate insulating layer works, in which U2' needs to be less than the breakdown voltage of the switching device 130'; then the voltage U1' is applied to the Anti-fuse antifuse 120' through the word line, and at the same time, by applying to the Bit Line bit line 101', for example The zero voltage causes the gate insulation layer of the Anti-fuse anti-fuse 120' to be broken down, that is, the Anti-fuse anti-fuse 120' is broken down, thereby realizing the programming operation.

When the Anti-fuse anti-fuse 120' is read, when the Anti-fuse anti-fuse 120' is broken down, the current path from the Anti-fuse anti-fuse 120' to the Bit Line bit line 101' can be detected. P' current, and determine the content of the Anti-fuse antifuse 120' according to the current detected on the Bit Line bit line 101'.

For example, during the read operation, the voltage U2' applied to the switching device 130' terminal is 1.1-3V, the voltage U1' applied to the Anti-fuse antifuse 120' is 1-1.5V, and the voltage U2' applied to the Bit Line bit line The applied voltage of 101' is 0V. In this case, when the current detected on the Bit Line bit line 101' flowing through the current path P' is an extremely weak current (for example, a current of the order of pA, it is regarded as zero current ), it means that the Anti-fuse anti-fuse 120' has not been broken down, and the content of the Anti-fuse anti-fuse 120' is "0"; when the current path P' flowing through the Bit Line bit line 101' is detected The current is a non-zero current (for example, a current of the order of μA), indicating that the Anti-fuse anti-fuse 120' has been broken down, and the content of the Anti-fuse anti-fuse 120' is "1".

When the size of the anti-fuse structure is further reduced, the distance between the Anti-fuse anti-fuse 120' and the switching device 130' is reduced, and the coupling between the two is intensified, which makes U1' during the programming operation It may cause damage to the switching device 130', for example, breakdown of the switching device 130', thereby affecting the performance and stability of the antifuse structure.

In actual applications, Anti-fuse may require multiple programming operations to ensure programming effects. Referring to Figure 4A, when the Anti-fuse is broken down for the first time, the current is maintained at the order of μA (for example, on the order of tens to hundreds of μA), as shown in the curve in Figure 4A; Referring to Figure 4B, when the Anti-fuse -fuse is broken down again. If the switching device is damaged, the current will suddenly decrease to the order of pA (for example, the order of tens of pA), as shown in the curve in Figure 4B.

The present disclosure provides an anti-fuse structure that forms an air gap between the Anti-fuse anti-fuse and the switching device to increase the voltage dividing distance and avoid the switching device from being damaged during the Anti-fuse anti-fuse breakdown process. It facilitates the identification of Anti-fuse antifuse breakdown results.

Figure 5 shows a schematic structural diagram of an antifuse structure in an exemplary embodiment. Referring to Figure 5, the antifuse structure 100 includes: a substrate 110, a first gate 120 located on the substrate 110 and a second gate 120. Gate 130, isolation material layer 140 and air gap 150. in,

The substrate 110 includes a first doped region 111 and a second doped region 112;

The first gate 120 and the second gate 130 are located on both sides of the first doped region 111, and the second gate 130 is located between the first doped region 111 and the second doped region 112;

The isolation material layer 140 is located on the substrate 110 and covers the first gate electrode 120, the second gate electrode 130 and the substrate 110;

The air gap 150 is located between the first doped region 111 and the isolation material layer 140 in a direction perpendicular to the substrate 110 , and the air gap 150 extends toward the first doped region 111 .

The material of the substrate 110 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon carbide and other materials; the material of the isolation material layer 140 can be insulating materials such as silicon nitride, silicon oxynitride, silicon dioxide, etc., to ensure its isolation properties. In the embodiment of the present disclosure, an air gap 150 is provided between the first gate 120 and the second gate 130 , and the air gap 150 extends toward the first doped region 111 , which can effectively increase the number of spaces between the first gate 120 and the second gate 130 . The voltage dividing distance between the electrodes 130 effectively prevents the components related to the first gate 120 from causing damage to the components related to the second gate 130 during operation, thereby improving the accuracy of identification of the operation results of the first gate 120 .

In this embodiment, by setting the air gap 150 , the current path P between the first gate 120 and the bit line 101 is extended. The path length of P > the path length of P′, which is equivalent to extending the first gate 120 The voltage dividing distance between the second gate electrode 130 and the second gate electrode 130 . When the linear distance between the first gate 120 and the second gate 130 is reduced, sufficient voltage division between the first gate 120 and the second gate 130 can still be ensured by setting the air gap 150 distance to prevent the second gate 130 from being damaged when the first gate 120 is read or penetrated.

Continuing to refer to Figure 5, taking the first gate 120 as an anti-fuse as an example, its U1 is 1-1.5V, and the voltage at the bit line 101 is 0V. By setting the air gap 150, the first gate 120 and The voltage dividing distance between the second gates 130 increases to ensure the voltage dividing effect of the second gate 130 on the first gate 120 and to ensure that the second gate 130 will not be damaged, so that the voltage of the second gate 130 U2 can be maintained between 1.1-3V to avoid breakdown of the second gate 130, accurately identify the operation accuracy of the anti-fuse Anti-fuse and ensure the operation stability of the anti-fuse Anti-fuse and the semiconductor circuit.

Referring to FIG. 5 , in some embodiments, the antifuse structure 100 further includes a dielectric layer 160 , the dielectric layer 160 is located above the first doped region 111 , and the air gap 150 is located above the dielectric layer 160 .

The dielectric layer 160 may be made of high temperature resistant polymer material.

In the embodiment of the present disclosure, the dielectric layer 160 is disposed between the first doped region 111 and the air gap 150 to enhance the dielectric strength of the air gap 150, thereby fully ensuring that the first gate 120 and the second gate The voltage division distance between the electrodes 130 increases the accuracy of result identification when performing a breakdown or reading operation on the first gate 120 .

Figure 6 is a schematic structural diagram of the antifuse structure 100 in an exemplary embodiment. Referring to Figure 6, in some embodiments, the first doped region 111 includes a first heavily doped region 111a. The doping concentration of the region 111a is greater than the doping concentration of other regions of the first doped region 111.

By arranging the first heavily doped region 111a so that the doping concentration of the first heavily doped region 111a is greater than the doping concentration of other regions of the first doped region 111, the induced current path P passes through the first heavily doped region. The area 111a can ensure that the voltage dividing distance between the first gate 120 and the second gate 130 is increased, thereby ensuring the operational stability of the second gate 130, preventing the second gate 130 from being damaged, and ensuring that the first gate 130 is protected from damage. Reliability of result identification when the gate 120 performs a breakdown or read operation.

As shown in FIG. 6 , in some embodiments, the isolation material layer 140 includes a first curved portion 141 , and the first curved portion 141 and the dielectric layer 160 form an air gap 150 .

The first curved surface portion 141 may have a regular curved surface shape or an irregular curved surface shape.

As shown in FIG. 6 , in some embodiments, the first curved portion 141 is recessed toward a side away from the base 110 in a direction perpendicular to the base 110 .

In some embodiments, the first curved portion 141 can also protrude toward the base 110 in a direction perpendicular to the base 110 or at a preset angle with the base 110 ; The structure protrudes in the direction of the base 110 and the structure is recessed in the direction away from the base 110 .

As shown in FIG. 6 , in some embodiments, the dielectric layer 160 includes a second curved portion 161 , and the second curved portion 161 is recessed toward the substrate 110 in a direction perpendicular to the substrate 110 .

The second curved portion 161 and the first curved portion 141 form an air gap 150 . The second curved portion 161 is recessed toward the substrate, so that at least part of the air gap 150 extends toward the substrate 110 , that is, at least part of the air gap 150 extends toward the first doping region 111 . For example, in the direction shown in FIG. 6 , at least part of the air gap 150 is disposed lower than the upper surface of the first doped region 110 , thereby increasing the separation between the first gate 120 and the second gate 130 . The effect of pressure distance.

The air gap 150 may be a regular-shaped structure or an irregular-shaped structure. The shape of the air gap 150 depends on the shape structures of the first curved portion 141 and the second curved portion 161 .

In some embodiments, the depth of the air gap 150 extending to the first doped region 111 is 10 nm to 100 nm. In the direction shown in FIG. 6 , the air gap 150 extends into the first doped region 111 to a depth of 10 nm to 100 nm. For example, the depth of the air gap 150 extending toward the substrate 110 may be 25 nm, 38 nm, 56 nm, 74 nm, or 83 nm, etc.

As shown in FIG. 6 , in some embodiments, the first gate 120 includes a first gate electrode 121 and a first gate insulating layer 122 , and the second gate 130 includes a second gate electrode 131 and a second gate insulating layer 132 . The thickness of the first gate insulating layer 122 is smaller than the thickness of the second gate insulating layer 132 .

The first gate electrode 121 is made of polysilicon, metal or other conductive materials, and the first gate insulating layer 122 is an oxide layer. Correspondingly, the second gate electrode 131 is made of polysilicon, metal or other conductive materials; the second gate insulating layer 132 is an oxide layer.

When the first gate 120 operates, it needs to break down the first gate insulating layer 122 . During the operation of the first gate 120, the second gate 130 divides the voltage of the first gate 120, and the thickness of the second gate insulating layer 132 is greater than the thickness of the first gate insulating layer 122, which can effectively ensure that the When the gate insulating layer 122 is broken down, the second gate insulating layer 132 will not be broken down, ensuring that the second gate 130 can operate normally. If the second gate insulating layer 132 is broken down, the second gate 130 will be destroyed, and it is difficult to ensure the accuracy of the first gate 120 being broken down as an anti-fuse or the result of the reading operation.

As shown in FIG. 6 , in some embodiments, the antifuse structure 100 further includes a third doped region 113 located on a side of the first gate 120 away from the first doped region 111 . The third doped region 113 can maintain the symmetry of the device, form a stable carrier injection concentration, and protect the first gate 120; at the same time, the uniform arrangement is also conducive to simplifying the process flow.

An exemplary embodiment of the present disclosure provides an antifuse array, and FIG. 7 shows a schematic structural diagram of an antifuse array 200 in an exemplary embodiment. Referring to FIG. 7 , the antifuse array 200 includes a plurality of the above-mentioned antifuse structures 100 , the first gates 120 of some of the antifuse structures 100 in the plurality of antifuse structures 100 are electrically connected to each other, and/ Or, the second gates 130 of some of the antifuse structures 100 in the plurality of antifuse structures 100 are electrically connected to each other. It can be understood that the first gate electrodes 120 of the partial anti-fuse structure 100 are electrically connected to each other, which means that the first gate electrodes 121 in the first gate electrodes 120 of the partial anti-fuse structure 100 are electrically connected to each other. For example, the The first gate electrode 121 in the first gate electrode 120 of the partial antifuse structure 100 is integrally formed, and the first gate insulating layer 122 in the first gate electrode 120 of the partial antifuse structure 100 may be separate. ;Similarly, the second gate electrodes 130 of the partial antifuse structure 100 are electrically connected to each other, which means that the second gate electrodes 131 in the second gate electrodes 130 of the partial antifuse structure 100 are electrically connected to each other. For example, this part The second gate electrode 131 in the second gate electrode 130 of the antifuse structure 100 is integrally formed, and the second gate insulating layer 132 in the second gate electrode 130 of the antifuse structure 100 may be separate.

An exemplary embodiment of the present disclosure provides a method of manufacturing an antifuse structure 100. FIG. 8 shows a flow chart of a method of manufacturing the antifuse structure 100 in an exemplary embodiment. Referring to Figures 5, 6 and 8, the production method includes:

Step S310, provide a substrate, and form a first doped region and a second doped region in the substrate;

Step S320: Form a first gate and a second gate on the substrate. The first gate and the second gate are located on both sides of the first doped region. The second gate is located between the first doped region and the second doped region. between miscellaneous areas;

Step S330: Form an isolation material layer on the substrate, and the isolation material layer covers the first gate, the second gate and the substrate;

Step S340: An air gap is formed between the isolation material layer and the first doped region, and the air gap extends toward the first doped region in a direction perpendicular to the substrate.

The embodiment of the present disclosure forms an air gap 150 between the isolation material layer 140 and the first doped region 111, and causes the air gap 150 to extend toward the first doped region 111 in a direction perpendicular to the substrate 110, so that the first The current path flowing from the gate 120 to the second gate 130 needs to bypass the area of the air gap 150 , thereby extending the current path between the first gate 120 and the second gate 130 , that is, increasing the number of first gate 120 The voltage dividing distance between the second gate 130 and the second gate 130 reduces the coupling effect and parasitic capacitance between the second gate 130 and the first gate 120, and improves the accuracy of the breakdown or reading operation of the first gate 120. performance and reliability.

In some exemplary embodiments, the air gap 150 may be directly formed during the process of forming the isolation material layer 140 , or may be formed during the formation of an isolation material layer that completely covers the substrate 110 , the first gate electrode 120 and the second gate electrode 130 . After 140, it was formed through an independent process.

Among them, the material of the substrate 110 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon carbide and other materials; the material of the isolation material layer 140 can be insulating materials such as silicon nitride, silicon oxynitride, silicon dioxide, etc. to ensure its isolation performance.

In the following, after the isolation material layer 140 that completely covers the substrate 110, the first gate electrode 120, and the second gate electrode 130 is formed, that is, after the isolation material layer 140 also completely covers the first doped region 111 and the second doped region 112, Using an independent process to form the air gap 150 is taken as an example to illustrate the manufacturing method of the antifuse structure provided by the present disclosure.

Referring to FIG. 9 , the isolation material layer 140 formed in step S330 not only covers the substrate 110 but also covers the first doping region 111 and the second doping region 112 . At this time, it is necessary to form the air gap 150 between the first doped region 111 and the isolation material layer 140 through processes such as etching and deposition.

As shown in FIG. 10 , between the first gate 120 and the second gate 130 , the isolation material layer 140 is etched to form a trench 151 , and the trench 151 extends toward the first gate in a direction perpendicular to the substrate 110 . Doped region 111 extends. For example, a dry etching process may be used to form the trench 151, and the depth of the trench 151 extending toward the first doped region 111 is 10 nm to 100 nm.

Then, the same material as the isolation material layer 140 is used to deposit into the trench 151 to form the space gap 150. At the same time, the deposited material is integrated with the isolation material layer 140 to ensure the function and performance of the isolation material layer 140.

According to some embodiments of the present disclosure, before forming the air gap 150, the method of manufacturing the antifuse structure 100 further includes:

As shown in FIG. 11 , high-concentration ions can be injected through the bottom of the trench 151 into various directions where the first doped region 111 contacts the trench 151 to form a first heavily doped region in the first doped region 111 111a.

Referring to FIGS. 5 and 11 , by setting the first heavily doped region 111 a so that the doping concentration of the first heavily doped region 111 a is greater than the doping concentration of other regions of the first doped region 111 , the formation of the first heavily doped region 111 is induced. The current path P passes through the first heavily doped region 111a, which can further ensure that the voltage dividing distance between the first gate 120 and the second gate 130 is increased, thereby ensuring the operation stability of the second gate 130 and avoiding The second gate 130 is damaged to ensure the reliability of result identification when performing a breakdown or reading operation on the first gate 120 .

In some embodiments, before forming the air gap 150, the manufacturing method further includes:

The first doped region is etched to form a third curved portion; the third curved portion is recessed toward the substrate in a direction perpendicular to the substrate.

In some embodiments, if the first heavily doped region 111a is not provided, the first doped region 111 can be directly etched to form a third curved surface.

In the embodiment shown in FIG. 12 , after the first heavily doped region 111 a is formed, the first doped region 111 is etched. At this time, the first heavily doped region 111a can be etched through the trench 151 to form a third curved portion 111b, and the third curved portion 111b is recessed toward the substrate 110, that is, the third curved portion 111b is toward the first doped region. 111 depression.

At this time, if silicon dioxide is directly deposited in the trench 151 to form the air gap 150, then the third curved portion 111b and the deposited silicon dioxide are surrounded to form the air gap 150.

In some embodiments, as shown in FIG. 13 , before forming the air gap 150 , the third curved portion 111 b can also be filled with a high-temperature resistant polymer material to form a dielectric layer 160 . As shown in FIG. 14 , material is then deposited in the trench 151 above the dielectric layer 160 to form an air gap 150 above the dielectric layer 160 .

By providing the dielectric layer 160, the dielectric strength of the air gap 150 can be enhanced, thereby fully ensuring that the voltage dividing distance between the first gate 120 and the second gate 130 is increased, and the operation of the first gate 120 is improved. The result identification accuracy and reliability.

In the embodiment of the present disclosure, to deposit material into the trench 151 to form the air gap 150, a CVD (Chemical Vapor Deposition) process may be used, using the same chemical material as the isolation material layer 140, such as silicon dioxide. The air gap 150 is formed while ensuring that the deposited material above the air gap 150 is integrated with the isolation material layer 140 .

According to some embodiments of the present disclosure, forming the isolation material layer 140 on the substrate 110 includes: forming the isolation material layer 140 through deposition, and adjusting the height of the air gap 150 by controlling deposition parameters.

Deposition parameters that need to be controlled may include deposition rate. For example, the deposition rate can be controlled by controlling parameters such as the equipment power of the deposition process, the vacuum degree of the working environment, and the deposition air flow.

Figures 15 and 16 respectively show two schematic diagrams of the deposition process at different deposition rates. In FIGS. 15 and 16 , the material used to form the air gap 150 is the same as the material of the isolation material layer 140 . In the embodiment shown in FIG. 15 , the deposition rate is slow and the particles sink more. The height of the air gap 150 formed by deposition using this deposition rate is relatively small. In the embodiment shown in FIG. 16 , the deposition rate is relatively high, the number of particles sinking is small, and the height of the air gap 150 formed by deposition using this deposition rate is relatively high.

In an exemplary embodiment, the process of forming the air gap 150 uses PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method) to deposit silicon dioxide, controls the temperature of the substrate 110 to 200-350°C, and uses radio frequency The power is 30-200W, the background vacuum parameter (that is, the vacuum parameter in the chamber before the reaction gas is injected) is 1×10 ^-3 Pa ~ 1×10 ^-1 Pa (for example, 5×10 ^-2 Pa), and the working environment The vacuum parameter (that is, the vacuum parameter in the chamber after the reaction gas is injected) is 30Pa-120Pa, and the control gas flow ratio is N ₂ O: SiH ₄ =1/10~1/5.

In some embodiments, the depth of the air gap 150 extending to the first doped region 111 is 10 to 100 nm, which can better match the device size and form an antifuse device and an antifuse array with better electrical performance.

An embodiment of the present disclosure also provides a memory device, which includes an antifuse array as described above, such as the antifuse array 200 shown in FIG. 7 .

In some embodiments, the antifuse array 200 may be a one-time programmable memory.

Each embodiment or implementation mode in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between various embodiments can be referred to each other.

In the description of this specification, reference to the description of the terms "embodiments," "exemplary embodiments," "some embodiments," "illustrative embodiments," "examples," etc. is intended to be described in connection with the embodiments or examples. A specific feature, structure, material, or characteristic is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description. It does not indicate or imply that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on the present disclosure.

It will be understood that the terms "first", "second", etc. used in this disclosure may be used to describe various structures in this disclosure, but these structures are not limited by these terms. These terms are used only to distinguish one structure from another.

In one or more of the figures, identical elements are designated with similar reference numbers. For the sake of clarity, various parts of the figures are not drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure are described below, such as device structures, materials, dimensions, processing processes and techniques, to provide a clearer understanding of the present disclosure. However, as one skilled in the art will appreciate, the present disclosure may be practiced without these specific details.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that it can still be used Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent substitutions are made to some or all of the technical features; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present disclosure.

Industrial applicability

In the antifuse structure and its manufacturing method, antifuse array, and memory device provided by the embodiments of the present disclosure, an air gap is formed between the first gate and the second gate to increase the voltage dividing distance and reduce the coupling effect. The effect of reducing the parasitic capacitance can effectively prevent possible damage to the second gate-related devices during the operation of the first gate-related devices.

Claims

An antifuse structure, the antifuse structure includes:

A substrate, including a first doped region and a second doped region;

The first gate electrode and the second gate electrode are located on the substrate, and the first gate electrode and the second gate electrode are located on both sides of the first doped region, and the second gate electrode is located on the between the first doped region and the second doped region;

A layer of isolation material, located on the substrate, covering the first gate, the second gate and the substrate;

An air gap is located between the first doped region and the isolation material layer in a direction perpendicular to the substrate, and the air gap extends toward the first doped region.
The antifuse structure according to claim 1, said antifuse structure further comprising:

A dielectric layer is located above the first doped region, and the air gap is located above the dielectric layer.
The antifuse structure according to claim 1, wherein the first doped region includes a first heavily doped region, and the doping concentration of the first heavily doped region is greater than other parts of the first doped region. doping concentration of the region.
The antifuse structure according to claim 2, wherein the isolation material layer includes a first curved portion, and the first curved portion and the dielectric layer form the air gap.
The antifuse structure according to claim 4, wherein the first curved portion is recessed toward a side away from the substrate in a direction perpendicular to the substrate.
The antifuse structure of claim 4, wherein the dielectric layer includes a second curved portion that is recessed toward the substrate in a direction perpendicular to the substrate.
The antifuse structure according to any one of claims 1 to 6, wherein a depth of the air gap extending to the first doped region is 10 to 100 nm.
The antifuse structure according to any one of claims 1 to 6, wherein the first gate electrode includes a first gate electrode and a first gate insulating layer, and the second gate electrode includes a second gate electrode and a first gate insulating layer. Two gate insulating layers, the thickness of the first gate insulating layer is smaller than the thickness of the second gate insulating layer.
The antifuse structure according to any one of claims 1 to 6, further comprising a third doped region located on a side of the first gate away from the first doped region.
An antifuse array, comprising a plurality of antifuse structures according to any one of claims 1 to 9, and the first gates of some of the antifuse structures in the plurality of antifuse structures The electrodes are electrically connected to each other, and/or the second gate electrodes of some of the anti-fuse structures in the plurality of anti-fuse structures are electrically connected to each other.
A method of making an antifuse structure. The method of making an antifuse structure includes:

providing a substrate in which a first doped region and a second doped region are formed;

A first gate and a second gate are formed on the substrate, the first gate and the second gate are located on both sides of the first doped region, and the second gate is located on the between the first doped region and the second doped region;

forming an isolation material layer on the substrate, the isolation material layer covering the first gate electrode, the second gate electrode and the substrate;

An air gap is formed between the isolation material layer and the first doped region, and the air gap extends toward the first doped region in a direction perpendicular to the substrate.
The method of making an anti-fuse structure according to claim 11, before forming the air gap, the method of making an anti-fuse structure further includes:

The first doped region is etched to form a third curved portion; the third curved portion is recessed toward the substrate in a direction perpendicular to the substrate.
The method of making an anti-fuse structure according to claim 12, before forming the air gap, the method of making an anti-fuse structure further includes:

forming a dielectric layer on the third curved surface;

Wherein, the air gap is located above the dielectric layer.
The method of making an anti-fuse structure according to claim 11, before forming the air gap, the method of making an anti-fuse structure further includes:

High-concentration ion implantation is performed on the first doped region to form a first heavily doped region. The doping concentration of the first heavily doped region is greater than the doping concentration of other regions of the first doped region.
The method of making an antifuse structure according to claim 11, wherein forming an isolation material layer on the substrate includes: forming the isolation material layer through deposition, and adjusting the air gap by controlling deposition parameters. the height of.
The method of manufacturing an antifuse structure according to claim 11, wherein a depth of the air gap extending to the first doped region is 10 to 100 nm.
A memory device, the memory device comprising the antifuse array according to claim 10, wherein the antifuse array is a one-time programmable memory.