TWI782628B - Memory structure - Google Patents

Abstract

A memory structure including a substrate and a one time programmable (OTP) memory device is provided. The OTP memory device includes a first buried gate structure, a first doped region, a second doped region, a first contact, an anti-fuse material layer, a first conductive line, and a second contact. The first buried gate structure is disposed in the substrate. The first doped region and the second doped region are located in the substrate on two sides of the first buried gate structure. The first contact is disposed on the first doped region. The anti-fuse material layer is disposed between the first contact and the first doped region. The first conductive line is disposed on the first contact. The second contact is disposed on the second doped region.

Description

memory structure

Embodiments of the present invention relate to a semiconductor structure, and more particularly to a memory structure.

One time programmable (OTP) memory is a kind of non-volatile memory (non-volatile memory, NVM). After programming OTP memory, the written data will be retained even if the power is removed. However, how to further reduce the area of OTP memory cells is the goal of ongoing efforts.

The invention provides a memory structure, which can have a smaller OTP memory cell area, and can be integrated with other semiconductor device manufacturing processes.

The invention proposes a memory structure, including a substrate and an OTP memory element. The OTP memory element includes a first buried gate structure, a first doped region, a second doped region, a first contact, an anti-fuse material layer, a first wire and a second doped region. Two contact windows. The first buried gate structure is disposed in the substrate. The first doped region and the second doped region are located in the substrates on both sides of the first buried gate structure. The first contact window is disposed on the first doped region. The antifuse material layer is disposed between the first contact window and the first doped region. The first wire is disposed on the first contact window. The second contact window is disposed on the second doped region.

According to an embodiment of the present invention, the above memory structure may further include a dynamic random access memory (DRAM) element. The DRAM device may include a second buried gate structure, a third doped region, a fourth doped region, a third contact window, a second wire, a fourth contact window and a capacitor. The second buried gate structure is disposed in the substrate. The third doped region and the fourth doped region are located in the substrates on both sides of the second buried gate structure. The third contact window is disposed on the third doped region. The second wire is disposed on the third contact window. The fourth contact window is disposed on the fourth doped region. The capacitor is electrically connected to the fourth doped region through the fourth contact window.

According to an embodiment of the present invention, in the above memory structure, the first buried gate structure and the second buried gate structure can be derived from the same material layer. The first contact and the third contact can be derived from the same material layer. The first wire and the second wire may originate from the same material layer. The second contact and the fourth contact may be derived from the same material layer.

The present invention proposes another memory structure, including a substrate and an OTP memory element. The OTP memory device includes a first buried gate structure, a first doped region, a second doped region, a first contact window, a first wire, a second contact window and an antifuse material layer. The first buried gate structure is disposed in the substrate. The first doped region and the second doped region are located in the substrates on both sides of the first buried gate structure. The first contact window is disposed on the first doped region. The first wire is disposed on the first contact window. The second contact window is disposed on the second doped region. The antifuse material layer is disposed between the second contact window and the second doped region.

According to another embodiment of the present invention, the above memory structure may further include a DRAM element. The DRAM device may include a second buried gate structure, a third doped region, a fourth doped region, a third contact window, a second wire, a fourth contact window and a capacitor. The second buried gate structure is disposed in the substrate. The third doped region and the fourth doped region are located in the substrates on both sides of the second buried gate structure. The third contact window is disposed on the third doped region. The second wire is disposed on the third contact window. The fourth contact window is disposed on the fourth doped region. The capacitor is electrically connected to the fourth doped region through the fourth contact window.

According to another embodiment of the present invention, in the above memory structure, the first buried gate structure and the second buried gate structure may be derived from the same material layer. The first contact and the third contact can be derived from the same material layer. The first wire and the second wire may originate from the same material layer. The second contact and the fourth contact may be derived from the same material layer.

The present invention proposes another memory structure, including a substrate and an OTP memory element. The OTP memory device includes a first buried gate structure, a first doped region, a second doped region, a first contact window, a first wire, a second contact window, a second wire and an antifuse material layer. The first buried gate structure is disposed in the substrate. The first doped region and the second doped region are located in the substrates on both sides of the first buried gate structure. The first contact window is disposed on the first doped region. The first wire is disposed on the first contact window. The second contact window is disposed on the second doped region. The second wire is arranged on one side of the first wire. The second contact window is disposed between the first wire and the second wire. The antifuse material layer is disposed between the second contact window and the second wire.

According to yet another embodiment of the present invention, the above memory structure may further include a DRAM element. The DRAM device may include a second buried gate structure, a third doped region, a fourth doped region, a third contact window, a third wire, a fourth contact window and a capacitor. The second buried gate structure is disposed in the substrate. The third doped region and the fourth doped region are located in the substrates on both sides of the second buried gate structure. The third contact window is disposed on the third doped region. The third wire is disposed on the third contact window. The fourth contact window is disposed on the fourth doped region. The capacitor is electrically connected to the fourth doped region through the fourth contact window.

According to yet another embodiment of the present invention, in the above memory structure, the first buried gate structure and the second buried gate structure may be derived from the same material layer. The first contact and the third contact can be derived from the same material layer. The first wire, the second wire and the third wire may originate from the same material layer. The second contact and the fourth contact may be derived from the same material layer.

According to still another embodiment of the present invention, in the above memory structure, the second wire does not pass above the active area.

Based on the above, in the memory structure proposed by an embodiment of the present invention, since the antifuse material layer is disposed between the first contact window and the first doped region, the OTP memory element can have smaller memory cells. area, and can be integrated with other semiconductor device manufacturing processes. In the memory structure proposed by another embodiment of the present invention, since the antifuse material layer is disposed between the second contact window and the second doped region, the OTP memory element can have a smaller memory cell area, And it can be integrated with the manufacturing process of other semiconductor elements. In the memory structure proposed in yet another embodiment of the present invention, since the antifuse material layer is disposed between the second contact window and the second wire, the OTP memory element can have a smaller memory cell area, and can Integrate with the process of other semiconductor components.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

FIG. 1A is a top view of an OTP memory device in a memory structure according to an embodiment of the present invention. FIG. 1B is a cross-sectional view of a memory structure according to an embodiment of the present invention. In FIG. 1B, the cross-sectional view of the OTP memory 100 is drawn along the line I-I' in FIG. 1A. In FIG. 1A , some components in FIG. 1B are omitted to clearly illustrate the positional relationship between the components in FIG. 1A . In the following drawings, in accordance with the standard practice in the industry, various features in the drawings are not drawn to scale. Additionally, features in the above views are not drawn to scale to those in the cross-sectional views. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Referring to FIGS. 1A and 1B , the memory structure 10 a includes a substrate 12 and an OTP memory device 100 . The substrate 12 can be a semiconductor substrate, such as a silicon substrate. In addition, an isolation structure 14 may be provided in the substrate 12, thereby defining an active area AA (FIG. 1A). The isolation structure 14 is, for example, a shallow trench isolation (STI) structure. The material of the isolation structure 14 is, for example, silicon oxide.

The OTP memory device 100 includes a buried gate structure 102 , a doped region 104 , a doped region 106 , a contact window 108 , an antifuse material layer 110 , a wire 112 and a contact window 114 . The buried gate structure 102 is disposed in the substrate 12 . The buried gate structure 102 may include a gate 102a and a dielectric layer 102b. The gate 102 a is disposed in the substrate 12 . In some embodiments, the gate 102 a can serve as a word line of the OTP memory device 100 . The material of the gate 102a is, for example, metal materials such as tungsten. The dielectric layer 102b is located between the gate 102a and the substrate 12 . The material of the dielectric layer 102a is, for example, a dielectric material such as silicon oxide. The doped region 104 and the doped region 106 are located in the substrate 12 on both sides of the buried gate structure 102 . According to the product design, the doped region 104 and the doped region 106 can be N-type conductivity or P-type conductivity.

In addition, a contact window 108 is disposed on the doped region 104 . The material of the contact window 108 is, for example, metal material such as tungsten or doped polysilicon. The antifuse material layer 110 is disposed between the contact window 108 and the doped region 104 . The material of the antifuse material layer 110 is, for example, a dielectric material such as silicon oxide. The wire 112 is disposed on the contact window 108 . In some embodiments, the wires 112 may serve as bit lines of the OTP memory device 100 . The material of the wire 112 is, for example, a metal material. The contact window 114 is disposed on the doped region 106 . The material of the contact window 114 is, for example, a conductive material.

In addition, the OTP memory device 100 may further include at least one of the dielectric layer 116 , the dielectric layer 118 , the dielectric layer 120 , the conductive layer 122 , the via 124 and the conductive layer 126 . The dielectric layer 116 is disposed between the wire 112 and the substrate 12 . A dielectric layer 118 is disposed on the dielectric layer 116 . A dielectric layer 120 is disposed on the dielectric layer 118 . The conductive layer 122 is disposed in the dielectric layer 120 and electrically connected to the contact window 114 . The via hole 124 is disposed in the dielectric layer 120 and electrically connected to the conductive layer 122 . The conductive layer 126 is disposed on the dielectric layer 120 and electrically connected to the via 124 . The materials of the dielectric layer 116 , the dielectric layer 118 and the dielectric layer 120 are respectively, for example, dielectric materials such as silicon oxide. The material of the through hole 124 is, for example, metal material such as tungsten. Materials of the conductive layer 122 and the conductive layer 126 are, for example, metal materials.

Hereinafter, the programming method of the OTP memory device 100 will be described. For example, a gate voltage (VG) is applied to the gate 102a, a working voltage (VDD) is applied to the conductive layer 122, and a reference voltage (VBB) is applied to the wire 112 or the wire 112 is grounded, so that the generated current can be This results in a breakdown of the antifuse material layer 110 . In this way, the antifuse material layer 110 can be changed from a high-resistance state to a low-resistance state, thereby programming the memory cell MC1 ( FIG. 1B ). In some embodiments, the memory cell MC1 can be programmed through the wire 112 and the gate 102 a and the conductive layer 122 on one side of the wire 112 . In some other embodiments, the memory cell MC1 can be programmed through the wire 112 and the gate 102 a and the conductive layer 122 on both sides of the wire 112 .

In addition, the memory structure 10a can further include a DRAM device 200 . The DRAM device 200 may include a buried gate structure 202 , a doped region 204 , a doped region 206 , a contact 208 , a wire 210 , a contact 212 and a capacitor 214 . The buried gate structure 202 is disposed in the substrate 12 . The buried gate structure 202 may include a gate 202a and a dielectric layer 202b. The gate 202 a is disposed in the substrate 12 . In some embodiments, the gate 202 a may serve as a word line of the DRAM device 200 . The material of the gate 202a is, for example, metal materials such as tungsten. The dielectric layer 202b is located between the gate 202a and the substrate 12 . The material of the dielectric layer 202a is, for example, a dielectric material such as silicon oxide. The doped region 204 and the doped region 206 are located in the substrate 12 on both sides of the buried gate structure 202 . According to product design, the doped region 204 and the doped region 206 can be of N-type conductivity or P-type conductivity.

In addition, a contact window 208 is disposed on the doped region 204 . The material of the contact window 208 is, for example, metal material such as tungsten or doped polysilicon. The wire 210 is disposed on the contact window 208 . In some embodiments, the wire 210 may serve as a bit line of the DRAM device 200 . The material of the wire 210 is, for example, a metal material. The contact window 212 is disposed on the doped region 206 . The material of the contact window 212 is, for example, a conductive material. The capacitor 214 is electrically connected to the doped region 206 through the contact window 212 . The capacitor 214 may include an electrode layer 216 , an electrode layer 218 and a dielectric layer 220 . The electrode layer 216 is electrically connected to the contact window 212 . The material of the electrode layer 216 is, for example, a conductive material, such as titanium, titanium nitride or a combination thereof. The electrode layer 218 is disposed on the electrode layer 216 . The electrode layer 218 can be a single-layer structure or a multi-layer structure. For example, the electrode layer 218 may include an electrode layer 218a and an electrode layer 218b. The electrode layer 218 a is disposed on the electrode layer 216 . The material of the electrode layer 218a is, for example, conductive material such as doped polysilicon. The electrode layer 218b is disposed on the electrode layer 218a. The material of the electrode layer 218b is, for example, metal materials such as tungsten. The dielectric layer 220 is disposed between the electrode layer 218 (eg, the electrode layer 218 a ) and the electrode layer 216 . The material of the dielectric layer 220 is, for example, a dielectric material such as a high dielectric constant material (high dielectric constant, high-k).

In addition, the DRAM device 200 may further include at least one of the dielectric layer 222 , the dielectric layer 224 , the dielectric layer 226 , the dielectric layer 228 , the contact window 230 and the conductive layer 232 . The dielectric layer 222 is disposed between the wire 212 and the substrate 12 . The dielectric layer 224 is disposed on the dielectric layer 222 . A dielectric layer 226 is disposed on the dielectric layer 224 . A dielectric layer 228 is disposed on the electrode layer 218 (eg, electrode layer 218b). The contact window 230 is disposed in the dielectric layer 228 and electrically connected to the electrode layer 218 (eg, the electrode layer 218 b ). The conductive layer 232 is disposed on the dielectric layer 228 and electrically connected to the contact window 230 . Materials of the dielectric layer 222 , the dielectric layer 224 , the dielectric layer 226 and the dielectric layer 228 are dielectric materials such as silicon oxide, respectively. The material of the contact window 230 is, for example, metal materials such as tungsten. The material of the conductive layer 232 is, for example, a metal material.

In addition, the main steps of the manufacturing method of the memory structure 10a may include the following steps. The buried gate structure 102 and the buried gate structure 202 are formed in the substrate 12 . The doped region 104 and the doped region 106 are formed in the substrate 12 on both sides of the buried gate structure 102, and the doped region 204 and the doped region are formed in the substrate 12 on both sides of the buried gate structure 202. District 206. A layer 110 of antifuse material is formed on the doped region 104 . A contact window 108 is formed on the antifuse material layer 110 , and a contact window 208 is formed on the doped region 204 . The wire 112 is formed on the contact 108 , and the wire 210 is formed on the contact 208 . A contact window 114 is formed on the doped region 106 , and a contact window 212 is formed on the doped region 206 . A capacitor 214 electrically connected to the contact 212 is formed.

In some embodiments, the manufacturing process of the OTP memory device 100 and the manufacturing process of the DRAM device 200 can be integrated. For example, the buried gate structure 102 and the buried gate structure 202 can be formed simultaneously by the same process. That is, buried gate structure 102 and buried gate structure 202 may be derived from the same material layer. The contact window 108 and the contact window 208 can be formed simultaneously by the same process. That is, the contact 108 and the contact 208 may be derived from the same material layer. The wires 112 and the wires 210 can be formed simultaneously by the same process. That is, the wires 112 and the wires 210 may be derived from the same material layer. The contact window 114 and the contact window 212 can be formed simultaneously by the same process. That is, the contact 114 and the contact 212 may be derived from the same material layer. The via hole 124 and the contact window 230 can be formed simultaneously by the same process. That is, the via 124 and the contact 230 may be derived from the same material layer. The conductive layer 126 and the conductive layer 232 can be formed simultaneously by the same process. That is, the conductive layer 126 and the conductive layer 232 may be derived from the same material layer.

Based on the above-mentioned embodiments, in the memory structure 10a, since the antifuse material layer 110 is disposed between the contact window 108 and the doped region 104, the OTP memory element 100 can have a smaller memory cell area, and can It is integrated with the manufacturing process of other semiconductor devices (eg, DRAM device 200 ).

FIG. 2A is a top view of an OTP memory device in a memory structure according to another embodiment of the present invention. FIG. 2B is a cross-sectional view of a memory structure according to another embodiment of the present invention. In FIG. 2B, the cross-sectional view of the OTP memory 300 is drawn along the line II-II' in FIG. 2A. In FIG. 2A , some components in FIG. 2B are omitted to clearly illustrate the positional relationship between the components in FIG. 2A .

Referring to FIG. 1A , FIG. 1B , FIG. 2A and FIG. 2B , the differences between the memory structure 10 b ( FIG. 2B ) and the memory structure 10 a ( FIG. 1B ) are as follows. In the memory structure 10b, the OTP memory 300 (FIG. 2B) does not include the antifuse material layer 110 between the contact window 108 and the doped region 104 in FIG. 1B. In addition, the OTP memory 300 ( FIG. 2B ) further includes an antifuse material layer 310 . The antifuse material layer 310 is disposed between the contact window 114 and the doped region 106 . The material of the antifuse material layer 310 is, for example, a dielectric material such as silicon oxide.

In addition, the manufacturing method of the memory structure 10b does not include the step of forming the fuse material layer 110 (FIG. 1B). The method of fabricating the memory structure 10b further includes forming an antifuse material layer 310 on the doped region 106 (FIG. 2B).

In addition, the same or similar components in the memory structure 10b and the memory structure 10a are denoted by the same or similar symbols, and their descriptions are omitted.

Hereinafter, the programming method of the OTP memory device 300 will be described. For example, a gate voltage (VG) is applied to the gate 102a, a reference voltage (VBB) is applied to the conductive layer 122 or the conductive layer 122 is grounded, and a working voltage (VDD) is applied to the wire 112, thereby generating a current The antifuse material layer 310 may be collapsed. In this way, the antifuse material layer 310 can be changed from a high-resistance state to a low-resistance state, thereby programming the memory cell MC2 ( FIG. 2B ). In some embodiments, two adjacent memory cells MC2 may share the doped region 104 , the contact window 108 and the wire 112 .

Based on the above-mentioned embodiments, in the memory structure 10b, since the antifuse material layer 310 is disposed between the contact window 114 and the doped region 106, the OTP memory element 300 can have a smaller memory cell area, and can It is integrated with the manufacturing process of other semiconductor devices (eg, DRAM device 200 ).

FIG. 3A is a top view of an OTP memory device in a memory structure according to another embodiment of the present invention. FIG. 3B is a cross-sectional view of a memory structure according to another embodiment of the present invention. In FIG. 3B, the cross-sectional view of the OTP memory 300 is drawn along the line III-III' in FIG. 3A. In FIG. 3A , some components in FIG. 3B are omitted to clearly illustrate the positional relationship between the components in FIG. 3A .

Referring to FIG. 1A , FIG. 1B , FIG. 3A and FIG. 3B , the differences between the memory structure 10c ( FIG. 3B ) and the memory structure 10a ( FIG. 1B ) are as follows. In the memory structure 10c, the OTP memory 400 (FIG. 3B) does not include the antifuse material layer 110 between the contact window 108 and the doped region 104 in FIG. 1B. As shown in FIG. 3A , the OTP memory 400 further includes a wire 412 and an antifuse material layer 410 a. The wire 412 is disposed on one side of the wire 112 . In some embodiments, the wire 412 does not pass over the active area AA. The material of the wire 412 is, for example, a metal material. The contact window 114 is disposed between the wire 112 and the wire 412 . The antifuse material layer 410 a is disposed between the contact window 114 and the wire 412 . The material of the antifuse material layer 410 a is, for example, a dielectric material such as silicon oxide. In addition, the OTP memory 400 may further include an antifuse material layer 410b. The antifuse material layer 410 b is disposed between the contact window 114 and the wire 112 . The material of the antifuse material layer 410b is, for example, a dielectric material such as silicon oxide. In some embodiments, the OTP memory 400 ( FIG. 3B ) may not include the conductive layer 122 , the via 124 and the conductive layer 126 in FIG. 1B .

In addition, the method of fabricating the memory structure 10c does not include the step of forming the fuse material layer 110 (FIG. 1B). Please refer to FIG. 3A , the manufacturing method of the memory structure 10c further includes the following steps. A wire 412 is formed on one side of the wire 112 . An antifuse material layer 410 a is formed between the contact window 114 and the wire 412 . An antifuse material layer 410 b is formed between the contact window 114 and the wire 112 . In some embodiments, please refer to FIG. 3A and FIG. 3B , the wire 112 , the wire 412 and the wire 210 can be formed simultaneously by the same process. That is, the wire 112 , the wire 412 and the wire 210 may be derived from the same material layer.

In addition, the same or similar components in the memory structure 10c and the memory structure 10a are denoted by the same or similar symbols, and description thereof will be omitted.

Hereinafter, the programming method of the OTP memory device 400 will be described. For example, a gate voltage (VG) is applied to the gate 102a, a working voltage (VDD) is applied to the wire 112, and a reference voltage (VBB) is applied to the wire 412 or the wire 412 is grounded, whereby the generated current can make The antifuse material layer 410a collapses. In this way, the antifuse material layer 410a can be changed from a high-resistance state to a low-resistance state, thereby programming the memory cell MC3 ( FIG. 3A ). In some embodiments, two adjacent memory cells MC3 may share the doped region 104 , the contact window 108 and the wire 112 .

Based on the foregoing embodiments, it can be seen that in the memory structure 10c, since the antifuse material layer 410a is disposed between the contact window 114 and the wire 412, the OTP memory element 400 can have a smaller memory cell area, and can be combined with other The manufacturing process of the semiconductor device (eg, the DRAM device 200 ) is integrated.

To sum up, with the memory structure of the above embodiment, the area of the OTP memory cell can be further reduced to improve the area utilization rate. In addition, because the OTP memory device can be integrated with the manufacturing process of other semiconductor devices, the complexity of the manufacturing process can be reduced.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10a, 10b, 10c: base

12: Base

14: Isolation structure

100,300,400: OTP memory

102,202: Buried gate structure

102a, 202a: gate

102b, 116, 118, 120, 202b, 220, 222, 224, 226, 228: dielectric layer

104, 106, 204, 206: doped regions

108,114,208,212,230: contact window

110, 310, 410a, 410b: layers of antifuse material

112,210,412: wire

122, 126, 232: conductive layer

124: Through hole

200: DRAM components

214: Capacitor

216, 218, 218a, 218b: electrode layer

MC1, MC2, MC3: memory cells

FIG. 1A is a top view of an OTP memory device in a memory structure according to an embodiment of the present invention. FIG. 1B is a cross-sectional view of a memory structure according to an embodiment of the present invention. FIG. 2A is a top view of an OTP memory device in a memory structure according to another embodiment of the present invention. FIG. 2B is a cross-sectional view of a memory structure according to another embodiment of the present invention. FIG. 3A is a top view of an OTP memory device in a memory structure according to another embodiment of the present invention. FIG. 3B is a cross-sectional view of a memory structure according to another embodiment of the present invention.

10a: Base

12: Base

14: Isolation structure

100: OTP memory

102,202: Buried gate structure

102a, 202a: gate

102b, 116, 118, 120, 202b, 220, 222, 224, 226, 228: dielectric layer

104, 106, 204, 206: doped regions

108,114,208,212,230: contact window

110: antifuse material layer

112,210: Wire

122, 126, 232: conductive layer

124: Through hole

200: DRAM components

214: Capacitor

216, 218, 218a, 218b: electrode layer

MC1: memory cell

Claims (4)

A memory structure, including: a substrate; and a one-time programmable memory element, including: a first buried gate structure disposed in the substrate; a first doped region and a second doped region located in the In the substrate on both sides of the first buried gate structure; the first contact window is arranged on the first doped region; the first wire is arranged on the first contact window; the second A contact window is arranged on the second doped region; a second wire is arranged on one side of the first wire, wherein the second contact window is arranged between the first wire and the second wire and an antifuse material layer disposed between the second contact window and the second wire. The memory structure according to claim 1, further comprising: a dynamic random access memory element, including: a second buried gate structure disposed in the substrate; a third doped region and a fourth doped region, located in the substrate on both sides of the second buried gate structure; a third contact window, disposed on the third doped region; a third wire, disposed on the third contact on the window; a fourth contact window disposed on the fourth doped region; and The capacitor is electrically connected to the fourth doped region through the fourth contact window. The memory structure according to claim 2, wherein the first buried gate structure and the second buried gate structure are derived from the same material layer, the first contact window and the first buried gate structure The three contacts originate from the same material layer, the first wire, the second wire and the third wire originate from the same material layer, and the second contact and the fourth contact originate from the same material layer. on the same material layer. The memory structure according to claim 1, wherein the second wire does not pass over the active area.

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