CN115642143A - Memory structure - Google Patents
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- CN115642143A CN115642143A CN202110966714.8A CN202110966714A CN115642143A CN 115642143 A CN115642143 A CN 115642143A CN 202110966714 A CN202110966714 A CN 202110966714A CN 115642143 A CN115642143 A CN 115642143A
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Abstract
The invention discloses a memory structure, which comprises a substrate and a one-time programmable memory element. The one-time programmable memory element comprises a first embedded gate structure, a first doped region, a second doped region, a first contact window, an anti-fuse material layer, a first lead and a second contact window. The first buried gate structure is disposed in the substrate. The first doped region and the second doped region are located in the substrate at two sides of the first buried gate structure. The first contact window is arranged on the first doping area. The anti-fuse material layer is arranged between the first contact window and the first doping region. The first conductive line is disposed on the first contact window. The second contact window is arranged on the second doping area.
Description
Technical Field
The present invention relates generally to semiconductor structures, and more particularly to memory structures.
Background
One-time programmable (OTP) memory is a non-volatile memory (NVM). After programming the OTP memory, the written data is retained even if power is removed. However, how to further reduce the OTP memory cell area is a goal of continuous effort.
Disclosure of Invention
The invention provides a memory structure which can have a smaller OTP memory cell area and can be integrated with the process of other semiconductor elements.
The invention provides a memory structure, which comprises a substrate and an OTP memory element. The OTP memory device includes a first buried gate structure, a first doped region, a second doped region, a first contact (contact), an anti-fuse (anti-fuse) material layer, a first conductive line and a second contact. The first buried gate structure is disposed in the substrate. The first doped region and the second doped region are located in the substrate at two sides of the first buried gate structure. The first contact window is arranged on the first doping area. The anti-fuse material layer is disposed between the first contact window and the first doped region. The first wire is arranged on the first contact window. The second contact window is arranged on the second doping area.
According to an embodiment of the invention, the memory structure may further include a Dynamic Random Access Memory (DRAM) element. The DRAM device may include a second buried gate structure, a third doped region, a fourth doped region, a third contact, a second conductive line, a fourth contact, and a capacitor. The second buried gate structure is disposed in the substrate. The third doped region and the fourth doped region are located in the substrate at two sides of the second embedded gate structure. The third contact window is disposed on the third doped region. The second conductive line is disposed on the third contact window. The fourth contact window is arranged on the fourth doping area. The capacitor is electrically connected to the fourth doped region through the fourth contact window.
According to an embodiment of the present invention, in the memory structure, the first buried gate structure and the second buried gate structure may be derived from the same material layer. The first contact window and the third contact window may be derived from the same material layer. The first conductive line and the second conductive line may be derived from the same material layer. The second contact window and the fourth contact window may be derived from the same material layer.
The invention provides another memory structure, which comprises a substrate and an OTP memory element. The OTP memory device includes a first buried gate structure, a first doped region, a second doped region, a first contact, a first conductive line, a second contact and an anti-fuse material layer. The first buried gate structure is disposed in the substrate. The first doped region and the second doped region are located in the substrate at two sides of the first buried gate structure. The first contact window is arranged on the first doping area. The first conductive line is disposed on the first contact window. The second contact window is arranged on the second doping area. The anti-fuse material layer is arranged between the second contact window and the second doping region.
According to another embodiment of the present invention, the memory structure may further include a DRAM device. The DRAM device may include a second buried gate structure, a third doped region, a fourth doped region, a third contact, a second conductive line, a fourth contact, and a capacitor. The second buried gate structure is disposed in the substrate. The third doped region and the fourth doped region are located in the substrate at two sides of the second embedded gate structure. The third contact window is arranged on the third doped region. The second conductive line is disposed on the third contact window. The fourth contact window is arranged on the fourth doping area. The capacitor is electrically connected to the fourth doped region through the fourth contact window.
According to another embodiment of the present invention, in the memory structure, the first buried gate structure and the second buried gate structure may be derived from the same material layer. The first contact window and the third contact window may be derived from the same material layer. The first conductive line and the second conductive line may be derived from the same material layer. The second contact window and the fourth contact window may be derived from the same material layer.
The invention provides a memory structure including a substrate and an OTP memory device. The OTP memory device includes a first buried gate structure, a first doped region, a second doped region, a first contact, a first conductive line, a second contact, a second conductive line and an anti-fuse material layer. The first buried gate structure is disposed in the substrate. The first doped region and the second doped region are located in the substrate at two sides of the first buried gate structure. The first contact window is arranged on the first doping area. The first conductive line is disposed on the first contact window. The second contact window is arranged on the second doping area. The second conductive line is disposed at one side of the first conductive line. The second contact window is arranged between the first conducting wire and the second conducting wire. The anti-fuse material layer is arranged between the second contact window and the second conducting wire.
According to still another embodiment of the present invention, the memory structure may further include a DRAM device. The DRAM device may include a second buried gate structure, a third doped region, a fourth doped region, a third contact, a third conductive line, a fourth contact, and a capacitor. The second buried gate structure is disposed in the substrate. The third doped region and the fourth doped region are located in the substrate at two sides of the second embedded gate structure. The third contact window is disposed on the third doped region. The third wire is arranged on the third contact window. The fourth contact window is arranged on the fourth doping area. The capacitor is electrically connected to the fourth doped region through the fourth contact window.
According to another embodiment of the present invention, in the memory structure, the first buried gate structure and the second buried gate structure may be derived from the same material layer. The first contact window and the third contact window may be derived from the same material layer. The first conductive lines, the second conductive lines and the third conductive lines may be derived from the same material layer. The second contact window and the fourth contact window may be derived from the same material layer.
According to still another embodiment of the present invention, in the memory structure, the second conductive line does not pass over the active region.
In view of the above, in the memory structure provided in the embodiment of the invention, since the anti-fuse material layer is disposed between the first contact and the first doped region, the OTP memory device has a smaller memory cell area and can be integrated with the processes of other semiconductor devices. In another embodiment of the present invention, the anti-fuse material layer is disposed between the second contact and the second doped region, so that the OTP memory device has a smaller memory cell area and can be integrated with other semiconductor device processes. In the memory structure according to still another embodiment of the present invention, since the anti-fuse material layer is disposed between the second contact and the second conductive line, the OTP memory device can have a smaller memory cell area and can be integrated with other semiconductor device processes.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1A is a top view of an OTP memory element in a memory structure according to an embodiment of the invention;
FIG. 1B is a cross-sectional view of a memory structure according to one embodiment of the invention;
FIG. 2A is a top view of an OTP memory element in a memory structure according to another embodiment of the invention;
FIG. 2B is a cross-sectional view of a memory structure according to another embodiment of the invention;
FIG. 3A is a top view of an OTP memory element in a memory structure of another embodiment of the invention;
fig. 3B is a cross-sectional view of a memory structure according to another embodiment of the invention.
Description of the symbols
10a,10b,10c, substrate
12 base
14 isolation structure
100,300,400
102,202 buried gate structure
102a,202a Gate
102b,116,118,120,202b,220,222,224,226,228 dielectric layer
104,106,204,206 doped region
108,114,208,212,230 contact window
110,310,410a,410b anti-fuse material layer
112,210,412 conducting wire
122,126,232 conductive layer
124 through hole
200
214 capacitor
216,218,218a,218b electrode layers
MC1, MC2, MC3 memory cell
Detailed Description
FIG. 1A is a top view of an OTP memory element in a memory structure according to an embodiment of the invention. Fig. 1B is a cross-sectional view of a memory structure according to an embodiment of the invention. In FIG. 1B, a cross-sectional view of OTP memory 100 is depicted along section line I-I' in FIG. 1A. In fig. 1A, some components in fig. 1B are omitted to clearly explain the positional relationship between the components in fig. 1A. In the following drawings, various features in the drawings are not drawn to scale in accordance with standard practice in the industry. Furthermore, features in the top view and features in the cross-sectional view are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Referring to fig. 1A and 1B, a memory structure 10a includes a substrate 12 and an OTP memory device 100. The substrate 12 may be a semiconductor substrate, such as a silicon substrate. In addition, an isolation structure 14 may be formed in the substrate 12, thereby defining an active area AA (fig. 1A). The isolation structure 14 is, for example, a Shallow Trench Isolation (STI) structure. The material of the isolation structure 14 is, for example, silicon oxide.
The OTP memory device 100 includes a buried gate structure 102, a doped region 104, a doped region 106, a contact 108, an anti-fuse material layer 110, a conductive line 112 and a contact 114. The buried gate structure 102 is disposed in the substrate 12. The buried gate structure 102 may include a gate 102a and a dielectric layer 102b. The gate 102a is disposed in the substrate 12. In some embodiments, the gate 102a may serve as a word line for the OTP memory element 100. The material of the gate 102a is, for example, a metal material such as tungsten. The dielectric layer 102b is located between the gate 102a and the substrate 12. The dielectric layer 102a is made of a dielectric material such as silicon oxide. The doped regions 104 and 106 are located in the substrate 12 at two sides of the buried gate structure 102. The doped regions 104 and 106 can be of N-type conductivity or P-type conductivity depending on the product design.
In addition, a contact 108 is disposed on the doped region 104. The material of the contact window 108 is, for example, a metal material such as tungsten or doped polysilicon. A layer of anti-fuse material 110 is disposed between the contact window 108 and the doped region 104. The material of the anti-fuse material layer 110 is, for example, a dielectric material such as silicon oxide. The conductive line 112 is disposed on the contact window 108. In some embodiments, conductive line 112 may serve as a bit line for OTP memory element 100. The material of the conductive line 112 is, for example, a metal material. A contact 114 is disposed over the doped region 106. The material of the contact window 114 is, for example, a conductive material.
In addition, OTP memory element 100 can also include at least one of dielectric layer 116, dielectric layer 118, dielectric layer 120, conductive layer 122, via (via) 124, and conductive layer 126. Dielectric layer 116 is disposed between conductive line 112 and substrate 12. Dielectric layer 118 is disposed on dielectric layer 116. Dielectric layer 120 is disposed on dielectric layer 118. The conductive layer 122 is disposed in the dielectric layer 120 and electrically connected to the contact window 114. Vias 124 are disposed in dielectric layer 120 and electrically connected to conductive layer 122. A conductive layer 126 is disposed on the dielectric layer 120 and is electrically connected to the vias 124. The dielectric layers 116,118 and 120 are made of dielectric materials such as silicon oxide, for example. The material of the via 124 is, for example, a metal material such as tungsten. The conductive layers 122 and 126 are made of metal materials, for example.
The method of programming the OTP memory element 100 is explained below. For example, a gate Voltage (VG) is applied to the gate 102a, a working Voltage (VDD) is applied to the conductive layer 122, and a reference Voltage (VBB) is applied to the conductive line 112 or the conductive line 112 is grounded, so that the generated current can cause the anti-fuse material layer 110 to break down (breakdown). As such, the anti-fuse material layer 110 changes from a high resistance state to a low resistance state, thereby programming the memory cell MC1 (fig. 1B). In some embodiments, memory cell MC1 can be programmed through conductive line 112 and gate 102a and conductive layer 122 on one side of conductive line 112. In other embodiments, memory cell MC1 can be programmed through conductive line 112 and gate 102a and conductive layer 122 on both sides of conductive line 112.
In addition, the memory structure 10a may also include a DRAM element 200. The DRAM device 200 may include a buried gate structure 202, a doped region 204, a doped region 206, a contact 208, a conductive line 210, a contact 212, and a capacitor 214. The buried gate structure 202 is disposed in the substrate 12. The buried gate structure 202 may include a gate 202a and a dielectric layer 202b. Gate 202a is disposed in substrate 12. In some embodiments, the gate 202a may serve as a word line for the DRAM device 200. The material of the gate 202a is, for example, a metal material such as tungsten. The dielectric layer 202b is located between the gate 202a and the substrate 12. The dielectric layer 202a is made of a dielectric material such as silicon oxide. The doped regions 204 and 206 are located in the substrate 12 at two sides of the buried gate structure 202. The doped regions 204 and 206 may be of N-type conductivity or P-type conductivity, depending on the product design.
In addition, a contact window 208 is disposed on the doped region 204. The material of the contact window 208 is, for example, a metal material such as tungsten or doped polysilicon. The conductive line 210 is disposed on the contact window 208. In some embodiments, conductive line 210 may serve as a bit line for DRAM device 200. The material of the conductive line 210 is, for example, a metal material. Contact windows 212 are disposed over the doped regions 206. The material of the contact window 212 is, for example, a conductive material. The capacitor 214 is electrically connected to the doped region 206 through the contact window 212. Capacitor 214 may include electrode layer 216, electrode layer 218, and dielectric layer 220. The electrode layer 216 is electrically connected to the contact window 212. The material of the electrode layer 216 is, for example, a conductive material such as titanium, titanium nitride, or a combination thereof. Electrode layer 218 is disposed on electrode layer 216. The electrode layer 218 may have a single-layer structure or a multi-layer structure. For example, the electrode layer 218 may include an electrode layer 218a and an electrode layer 218b. The electrode layer 218a is provided over the electrode layer 216. The material of the electrode layer 218a is, for example, a conductive material such as doped polysilicon. The electrode layer 218b is provided over the electrode layer 218 a. The material of the electrode layer 218b is, for example, a metal material such as tungsten. Dielectric layer 220 is disposed between electrode layer 218 (e.g., electrode layer 218 a) and electrode layer 216. The dielectric layer 220 is made of a dielectric material such as a high dielectric constant (high-k) material.
In addition, the DRAM device 200 may further include at least one of a dielectric layer 222, a dielectric layer 224, a dielectric layer 226, a dielectric layer 228, a contact 230, and a conductive layer 232. A dielectric layer 222 is disposed between the conductive lines 212 and the substrate 12. Dielectric layer 224 is disposed on dielectric layer 222. Dielectric layer 226 is disposed on dielectric layer 224. Dielectric layer 228 is disposed on electrode layer 218 (e.g., electrode layer 218 b). Contact window 230 is disposed in dielectric layer 228 and electrically connected to electrode layer 218 (e.g., electrode layer 218 b). The conductive layer 232 is disposed on the dielectric layer 228 and electrically connected to the contact 230. The dielectric layers 222,224,226 and 228 are made of dielectric materials such as silicon oxide, respectively. The contact 230 is made of a metal material such as tungsten. The material of the conductive layer 232 is, for example, a metal material.
In addition, the main steps of the manufacturing method of the memory structure 10a may include the following steps. The buried gate structure 102 and the buried gate structure 202 are formed in the substrate 12. The doped regions 104 and 106 are formed in the substrate 12 on both sides of the buried gate structure 102, and the doped regions 204 and 206 are formed in the substrate 12 on both sides of the buried gate structure 202. A layer of anti-fuse material 110 is formed over the doped region 104. A contact 108 is formed over the layer of antifuse material 110 and a contact 208 is formed over the doped region 204. Conductive line 112 is formed over contact 108 and conductive line 210 is formed over contact 208. Contact windows 114 are formed on doped regions 106 and contact windows 212 are formed on doped regions 206. A capacitor 214 is formed electrically connected to the contact 212.
In some embodiments, the process of the OTP memory device 100 may be integrated with the process of the DRAM device 200. For example, the buried gate structure 102 and the buried gate structure 202 may be formed simultaneously by the same process. That is, the buried gate structure 102 and the buried gate structure 202 may be derived from the same material layer. The contact 108 and the contact 208 may be formed simultaneously by the same process. That is, the contact 108 and the contact 208 may be derived from the same material layer. The conductive lines 112 and 210 may be formed simultaneously by the same process. That is, the conductive lines 112 and 210 may be derived from the same material layer. The contact windows 114 and 212 may be formed simultaneously by the same process. That is, the contact windows 114 and 212 may be derived from the same material layer. The via 124 and the contact 230 may be formed simultaneously by the same process. That is, the via 124 and the contact 230 may be derived from the same material layer. Conductive layer 126 and conductive layer 232 can be formed simultaneously by the same process. That is, the conductive layer 126 and the conductive layer 232 may be derived from the same material layer.
Based on the above embodiments, in the memory structure 10a, since the anti-fuse material layer 110 is disposed between the contact 108 and the doped region 104, the OTP memory device 100 can have a smaller memory cell area and can be integrated with the process of other semiconductor devices (e.g., the DRAM device 200).
FIG. 2A is a top view of an OTP memory element in a memory structure according to another embodiment of the invention. Fig. 2B is a cross-sectional view of a memory structure according to another embodiment of the invention. In FIG. 2B, a cross-sectional view of OTP memory 300 is depicted along section line II-II' in FIG. 2A. In fig. 2A, some components in fig. 2B are omitted to clearly explain the positional relationship between the components in fig. 2A.
Referring to fig. 1A, 1B, 2A and 2B, the difference between the memory structure 10B (fig. 2B) and the memory structure 10a (fig. 1B) is as follows. In memory structure 10B, OTP memory 300 (fig. 2B) does not include antifuse material layer 110 between contact window 108 and doped region 104 in fig. 1B. In addition, OTP memory 300 (FIG. 2B) further includes a layer 310 of antifuse material. The layer of antifuse material 310 is disposed between the contact window 114 and the doped region 106. The material of the anti-fuse material layer 310 is a dielectric material such as silicon oxide.
In addition, the manufacturing method of the memory structure 10B does not include the step of forming the fuse material layer 110 (fig. 1B). The method of fabricating the memory structure 10B further includes forming a layer 310 of anti-fuse material on the doped region 106 (fig. 2B).
In addition, the same or similar components in the memory structure 10b and the memory structure 10a are denoted by the same or similar symbols, and the description thereof is omitted.
The method of programming the OTP memory element 300 is described below. For example, a gate Voltage (VG) is applied to the gate 102a, a reference Voltage (VBB) is applied to the conductive layer 122 or the conductive layer 122 is grounded, and an operating Voltage (VDD) is applied to the conductive line 112, so that the generated current can cause the anti-fuse material layer 310 to break down. As such, the anti-fuse material layer 310 may change from a high resistance state to a low resistance state, thereby programming the memory cell MC2 (fig. 2B). In some embodiments, two adjacent memory cells MC2 may share the doped region 104, the contact window 108 and the conductive line 112.
Based on the above embodiments, in the memory structure 10b, since the anti-fuse material layer 310 is disposed between the contact window 114 and the doped region 106, the OTP memory device 300 can have a smaller memory cell area and can be integrated with the processes of other semiconductor devices (e.g., the DRAM device 200).
FIG. 3A is a top view of an OTP memory element in a memory structure according to another embodiment of the invention. Fig. 3B is a cross-sectional view of a memory structure according to another embodiment of the invention. In FIG. 3B, a cross-sectional view of OTP memory 300 is depicted along cross-sectional line III-III' in FIG. 3A. In fig. 3A, some components in fig. 3B are omitted to clearly explain the positional relationship between the components in fig. 3A.
Referring to fig. 1A, 1B, 3A, and 3B, the difference between the memory structure 10c (fig. 3B) and the memory structure 10a (fig. 1B) is as follows. In memory structure 10c, OTP memory 400 (fig. 3B) does not include antifuse material layer 110 of fig. 1B between contact window 108 and doped region 104. As shown in fig. 3A, the OTP memory 400 further includes a conductive line 412 and an anti-fuse material layer 410a. The conductive line 412 is disposed at one side of the conductive line 112. In some embodiments, the conductive line 412 does not pass over the active area AA. The material of the conductive line 412 is, for example, a metal material. The contact window 114 is disposed between the conductive line 112 and the conductive line 412. The anti-fuse material layer 410a is disposed between the contact window 114 and the conductive line 412. The material of the anti-fuse material layer 410a is a dielectric material such as silicon oxide. In addition, the OTP memory 400 may further include an antifuse material layer 410b. The anti-fuse material layer 410b is disposed between the contact window 114 and the conductive line 112. The material of the antifuse material layer 410b is a dielectric material such as silicon oxide. In some embodiments, OTP memory 400 (fig. 3B) may not include conductive layer 122, via (via) 124, and conductive layer 126 of fig. 1B.
In addition, the method of fabricating the memory structure 10c does not include the step of forming the fuse material layer 110 (fig. 1B). Referring to fig. 3A, the method for manufacturing the memory structure 10c further includes the following steps. A conductive line 412 is formed on one side of the conductive line 112. An anti-fuse material layer 410a is formed between the contact window 114 and the conductive line 412. An anti-fuse material layer 410b is formed between the contact window 114 and the conductive line 112. In some embodiments, referring to fig. 3A and 3B, the conductive lines 112, 412 and 210 can be formed simultaneously by the same process. That is, the conductive lines 112, 412 and 210 may be derived from the same material layer.
In addition, the same or similar components in the memory structure 10c and the memory structure 10a are denoted by the same or similar symbols, and the description thereof is omitted.
The method of programming the OTP memory element 400 is explained below. For example, a gate Voltage (VG) is applied to the gate 102a, a working Voltage (VDD) is applied to the conductive line 112, and a reference Voltage (VBB) is applied to the conductive line 412 or the conductive line 412 is grounded, so that the generated current can cause the anti-fuse material layer 410a to break down. As such, the anti-fuse material layer 410a changes from a high resistance state to a low resistance state, thereby programming the memory cell MC3 (fig. 3A). In some embodiments, two adjacent memory cells MC3 may share the doped region 104, the contact window 108 and the conductive line 112.
Based on the above embodiments, in the memory structure 10c, since the anti-fuse material layer 410a is disposed between the contact window 114 and the conductive line 412, the OTP memory device 400 can have a smaller memory cell area and can be integrated with the processes of other semiconductor devices (e.g., the DRAM device 200).
In summary, the memory structure of the above embodiments can further reduce the area of the OTP memory cell, so as to improve the area utilization. In addition, the OTP memory device can be integrated with other semiconductor devices, thereby reducing the process complexity.
Although the present invention has been described in conjunction with the above embodiments, it is not intended to limit the present invention, and those skilled in the art may make modifications and alterations without departing from the spirit and scope of the present invention.
Claims (10)
1. A memory structure, comprising:
a substrate; and
a one-time programmable memory element comprising:
a first buried gate structure disposed in the substrate;
a first doped region and a second doped region in the substrate at two sides of the first buried gate structure;
the first contact window is arranged on the first doping region;
the anti-fuse material layer is arranged between the first contact window and the first doping region;
a first conductive line disposed on the first contact window; and
and the second contact window is arranged on the second doping region.
2. The memory structure of claim 1, further comprising:
a dynamic random access memory device, comprising:
a second buried gate structure disposed in the substrate;
a third doped region and a fourth doped region in the substrate at two sides of the second buried gate structure;
a third contact window disposed on the third doped region;
the second conducting wire is arranged on the third contact window;
the fourth contact window is arranged on the fourth doping area; and
a capacitor electrically connected to the fourth doped region through the fourth contact window.
3. The memory structure of claim 2, wherein
The first buried gate structure and the second buried gate structure are derived from the same material layer,
the first contact window and the third contact window are originated from the same material layer,
the first conductive line and the second conductive line are derived from the same material layer, and
the second contact window and the fourth contact window are derived from the same material layer.
4. A memory structure, comprising:
a substrate; and
a one-time programmable memory element comprising:
a first buried gate structure disposed in the substrate;
a first doped region and a second doped region in the substrate at two sides of the first buried gate structure;
the first contact window is arranged on the first doping region;
a first conductive line disposed on the first contact window;
the second contact window is arranged on the second doping area; and
and the anti-fuse material layer is arranged between the second contact window and the second doped region.
5. The memory structure of claim 4, further comprising:
a dynamic random access memory device, comprising:
a second buried gate structure disposed in the substrate;
a third doped region and a fourth doped region in the substrate at two sides of the second buried gate structure;
a third contact window disposed on the third doped region;
the second conducting wire is arranged on the third contact window;
the fourth contact window is arranged on the fourth doping area; and
a capacitor electrically connected to the fourth doped region through the fourth contact window.
6. The memory structure of claim 5, wherein
The first buried gate structure and the second buried gate structure are derived from the same material layer,
the first contact window and the third contact window are derived from the same material layer,
the first conductive line and the second conductive line are derived from the same material layer, and
the second contact window and the fourth contact window are derived from the same material layer.
7. A memory structure, comprising:
a substrate; and
a one-time programmable memory element comprising:
a first buried gate structure disposed in the substrate;
a first doped region and a second doped region in the substrate at two sides of the first buried gate structure;
the first contact window is arranged on the first doping region;
a first conductive line disposed on the first contact window;
the second contact window is arranged on the second doping area;
a second conductive line disposed at one side of the first conductive line, wherein the second contact window is disposed between the first conductive line and the second conductive line; and
and the anti-fuse material layer is arranged between the second contact window and the second conducting wire.
8. The memory structure of claim 7, further comprising:
a dynamic random access memory device, comprising:
a second buried gate structure disposed in the substrate;
a third doped region and a fourth doped region in the substrate at two sides of the second buried gate structure;
a third contact window disposed on the third doped region;
a third conductive line disposed on the third contact window;
the fourth contact window is arranged on the fourth doping area; and
a capacitor electrically connected to the fourth doped region through the fourth contact window.
9. The memory structure of claim 8, wherein
The first buried gate structure and the second buried gate structure are derived from the same material layer,
the first contact window and the third contact window are originated from the same material layer,
the first, second and third conductive lines are derived from the same material layer, and
the second contact window and the fourth contact window are derived from the same material layer.
10. The memory structure of claim 7, wherein the second conductive line does not pass over an active region.
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| Application Number | Priority Date | Filing Date | Title |
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| TW110126347A TWI782628B (en) | 2021-07-19 | 2021-07-19 | Memory structure |
| TW110126347 | 2021-07-19 |
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| CN115642143A true CN115642143A (en) | 2023-01-24 |
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| US11456303B2 (en) * | 2018-12-27 | 2022-09-27 | Nanya Technology Corporation | Fuse array structure |
| US10825823B1 (en) * | 2019-04-29 | 2020-11-03 | Nanya Technology Corporation | Semiconductor memory device including decoupling capacitor array arranged overlying one-time programmable device |
| US10818592B1 (en) * | 2019-04-29 | 2020-10-27 | Nanya Technology Corporation | Semiconductor memory device including decoupling capacitor array arranged overlying one-time programmable device |
| US11121081B2 (en) * | 2019-10-18 | 2021-09-14 | Nanya Technology Corporation | Antifuse element |
| US11527541B2 (en) * | 2019-12-31 | 2022-12-13 | Taiwan Semiconductoh Manufactuhing Company Limited | System and method for reducing resistance in anti-fuse cell |
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| TWI782628B (en) | 2022-11-01 |
| TW202306128A (en) | 2023-02-01 |
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