CN210575939U - Anti-fuse structure and programmable memory - Google Patents
Anti-fuse structure and programmable memory Download PDFInfo
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- CN210575939U CN210575939U CN201922075776.0U CN201922075776U CN210575939U CN 210575939 U CN210575939 U CN 210575939U CN 201922075776 U CN201922075776 U CN 201922075776U CN 210575939 U CN210575939 U CN 210575939U
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Abstract
The application relates to an antifuse structure and an editable memory comprising the same. The antifuse structure includes: a first doped region and a second doped region formed at least partially within the first doped region; the isolation layer is formed on the first doping area and part of the second doping area and is provided with a window exposing the second doping area; the grid structure comprises a fuse medium layer and a grid conducting layer which are overlapped, and the fuse medium layer is contacted with the second doped region through the window; a first electrode in contact with the gate conductive layer; and the second electrode sequentially penetrates through the grid structure and the isolation layer and is contacted with the second doping region, and the second electrode is electrically isolated from the grid structure through an isolation gasket. By arranging the second doped region below the gate structure and making the second electrode penetrate through the gate structure to contact with the second doped region, the occupied area of the anti-fuse structure can be reduced, and the integration level of the device can be improved.
Description
Technical Field
The utility model relates to a semiconductor field especially relates to an antifuse structure and a programmable memory.
Background
OTP (One Time Programmable) memories are classified into a fuse type and an antifuse type, in which a Programmable cell of the antifuse type memory is an antifuse structure. The anti-fuse structure specifically comprises a fuse medium layer and two electrodes respectively connected with two sides of the fuse medium layer, when programming is not performed, the voltage applied to the fuse medium layer is small, the fuse medium layer is not broken down, and the anti-fuse structure is equivalent to a capacitor and is in a high-resistance state; when programming, the voltage is increased to make the fuse dielectric layer breakdown, and the anti-fuse structure is equivalent to resistance and is in a low-resistance state.
At present, a gate dielectric layer in a transistor gate structure is usually used as a fuse dielectric layer, a gate is used as a first electrode, a second electrode is led out from an active region, and whether the fuse dielectric layer is broken down or not can be controlled by controlling a voltage difference between the first electrode and the second electrode. The gate structure and the active region respectively occupy a certain area, so that the area of the anti-fuse structure is large, which is not beneficial to the integration of devices.
SUMMERY OF THE UTILITY MODEL
Based on this, the application provides an anti-fuse structure and a programmable memory, wherein the anti-fuse structure has a smaller area and can improve the device integration level.
In order to solve the above technical problem, a first technical solution proposed by the present application is:
an antifuse structure, comprising:
a first doped region having a first conductivity type formed in the semiconductor substrate;
a second doped region having a second conductivity type formed at least partially within the first doped region;
an isolation layer formed on the first doped region and the second doped region, the isolation layer having a window exposing the second doped region;
the grid structure comprises a fuse medium layer and a grid conducting layer overlapped on the fuse medium layer, and the fuse medium layer is contacted with the second doped region through the window;
a first electrode in contact with the gate conductive layer; and
and the second electrode sequentially penetrates through the grid structure and the isolation layer and is in contact with the second doping region, and the second electrode is electrically isolated from the grid structure through an isolation gasket.
In one embodiment, the second doped region includes a bottom arm formed in the first doped region and a protruding arm extending upward from the bottom arm, the isolation layer covers the first doped region and the bottom arm on both sides of the protruding arm, the window exposes the protruding arm, and the fuse dielectric layer contacts the protruding arm.
In one embodiment, the second doped region has an L-shaped lateral cross-section.
In one embodiment, isolation spacers are further formed on two sides of the gate structure.
In one embodiment, the method further comprises the following steps:
the passivation layer covers the grid structure; the first electrode penetrates through the passivation layer and is in contact with the gate conductive layer, and the second electrode penetrates through the passivation layer, the gate structure and the isolation layer in sequence and is in contact with the second doped region.
In one embodiment, the isolation pad penetrates through the passivation layer and the gate conductive layer in sequence, and the bottom of the isolation pad is in contact with the fuse dielectric layer.
In one embodiment, the isolation spacer penetrates the passivation layer and the gate structure in sequence and the bottom of the isolation spacer contacts the isolation layer.
In one embodiment, the fuse dielectric layer is an oxide layer.
In one embodiment, the gate conductive layer includes a polysilicon layer and a metal layer sequentially stacked on the fuse dielectric layer, and the bottom of the first electrode is in contact with the metal layer.
In order to solve the above technical problem, a second technical solution proposed by the present application is:
a programmable memory comprising the antifuse structure of any preceding claim.
According to the structure, the grid is used as the first electrode, the second electrode is led out from the second doping region, the second doping region is arranged at the bottom of the grid structure, the overlapping region of the second doping region and the grid structure is enlarged, and the second electrode penetrates through the grid structure and is electrically connected with the second doping region at the bottom of the grid structure, so that the area occupied by the whole anti-fuse structure is reduced, and the integration level of a device is improved.
Drawings
FIG. 1a is a cross-sectional side view of an anti-fuse structure according to the prior art;
FIG. 1b is a diagram illustrating a relationship between the second doped region and the gate structure of FIG. 1 a;
FIG. 2a is a cross-sectional side view of an antifuse structure according to an embodiment of the present application;
FIG. 2b is a diagram of a position relationship between the second doped region and the gate structure in FIG. 2 a;
FIG. 3 is a cross-sectional side view of an antifuse structure according to another embodiment of the present application.
Description of the reference symbols
100 a first doped region; 110 a second doped region; 111 a bottom arm; 112 convex arm; 200 an isolation layer; 300 a gate structure; 310 a fuse dielectric layer; 320 a gate conductive layer; 321 a polysilicon layer; 322 a metal layer; 400 passivation layer; 500 spacer pads; 601 a first opening; 602 a second opening; 610 a first electrode; 620 a second electrode; 700 isolating the side walls; 710 a first sidewall; 720 second side walls; 730 a third side wall; and (A) a breakdown region.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 1a and 1b show an anti-fuse structure in the prior art, wherein fig. 1a is a cross-sectional side view of the anti-fuse structure, and fig. 1b is a positional relationship diagram of a second doped region and a gate structure.
As shown in fig. 1a, in the conventional technology, a second doped region 110 ' is formed in a first doped region 100 ', a gate dielectric layer in a gate structure 300 ' is used as a fuse dielectric layer 310 ', a breakdown region a of the fuse dielectric layer 310 ' is defined by an isolation layer 200 ', meanwhile, one end of the second doped region 110 ' is in contact with the breakdown region a, the other end extends out of a projection region of the gate structure 300 ', a first electrode 610 ' penetrates through a passivation layer 400 ' and is in contact with a gate conductive layer 320 ', and a second electrode 620 ' is staggered from the gate structure 300 ' and is in contact with the second doped region 110 ' at a position different from the gate structure 300 '. The second doping region 110 ' and the gate structure 300 ' are located in a relationship as shown in fig. 1b, and the length L ' of the antifuse structure is longer, which results in a larger area occupied by the antifuse structure.
To this end, the present application proposes a new antifuse structure.
As shown in fig. 2a, the anti-fuse structure at least comprises the following structures:
a first doped region 100, having a first conductivity type, is formed in the semiconductor substrate. Specifically, the first doped region 100 may be a well region having the first conductivity type formed in the semiconductor substrate.
The second doped region 110, having the second conductivity type, is at least partially formed in the first doped region 100, and the second doped region 110 is used for leading out the second electrode. The first conductivity type and the second conductivity type have opposite conductivity, wherein when the first conductivity type is N-type, the second conductivity type is P-type, and when the first conductivity type is P-type, the second conductivity type is N-type.
The isolation layer 200 is formed on the first doped region 100 and the second doped region 110, and the isolation layer 200 has a window exposing the second doped region 110.
The gate structure 300 is formed on the isolation layer 200, and includes a gate dielectric layer and a gate conductive layer 320, which are stacked, wherein the gate dielectric layer forms the fuse dielectric layer 310 in this application, the fuse dielectric layer 310 contacts the second doped region 110 through the window, and a breakdown area a of the fuse dielectric layer 310 can be defined by using the window, that is, the breakdown area a of the fuse dielectric layer 310 is an area where the fuse dielectric layer 310 contacts the second doped region 110 through the window.
A first electrode 610 and a second electrode 620, wherein the first electrode 610 contacts the gate conductive layer 320 to provide a voltage signal to one side of the fuse dielectric layer 310. The second electrode 620 sequentially penetrates the gate structure 300 and the isolation layer 200 and contacts the second doped region 110 to provide a voltage signal to the other side of the fuse dielectric layer 310. Meanwhile, the second electrode 620 is electrically isolated from the gate structure 300 by the isolation spacer 500. Further, the structure may further include a passivation layer 400 covering the gate structure 300, and the passivation layer 400 protects the structure, in which the first electrode 610 penetrates through the passivation layer 400 and contacts the gate conductive layer 320, and the second electrode 620 penetrates through the passivation layer 400, the gate structure 300, and the isolation layer 200 in sequence and contacts the second doped region 110.
In the anti-fuse structure, one side of the fuse dielectric layer 310 is electrically connected to the first electrode 610, and the other side is connected to the second electrode 620, so that the breakdown state of the fuse dielectric layer 310 can be controlled by controlling the voltage difference between the two electrodes. Before programming, the fuse dielectric layer 310 is not broken down and is in a high-resistance state, and when programming is needed, the fuse dielectric layer 310 is broken down and is in a low-resistance state. Meanwhile, in the present application, as shown in fig. 2b, the second doped region 110 is disposed below the gate structure 300, and the area of the breakdown region a is defined by the isolation layer 200, and the second electrode 620 penetrates through the gate structure 300 and the isolation layer 200 to contact the second doped region 110 directly below the gate structure 300, so as to increase the overlapping area of the gate structure 300 and the second doped region 110, and reduce the area occupied by the anti-fuse structure. As shown in fig. 2b, the length of the antifuse structure is L, and compared with the conventional antifuse structure, under the condition that the second doping region 110 and the gate structure 300 have the same topography, the length L of the antifuse structure in the present application is smaller than the length L' of the conventional antifuse structure, that is, the area occupied by the antifuse structure in the present application is reduced, which is beneficial to improving the integration level of the device. Meanwhile, in the present application, the second doped region 110 is disposed below the gate structure 300, and the area of the breakdown region a is defined by the isolation layer 200, so that the area of the breakdown region a can be increased, and the boundary of the breakdown region a is increased, thereby obtaining an obvious boundary effect; accordingly, the second electrode 620 penetrates through the gate structure 300 and contacts the second doped region 110, which can reduce the distance between the second electrode 620 and the breakdown region a, and reduce the resistance between the second electrode 620 and the breakdown region a, thereby effectively improving the anti-fuse repair effect.
There are various ways for the fuse dielectric layer 310 to contact the second doped region 110 through the window, which is not limited herein. For example, the second doped region 110 has a flat upper surface, and the lower surface of the fuse dielectric layer 310 has a protrusion matching with the window, i.e. the fuse dielectric layer 310 is deposited in the window to make contact with the second doped region 110. In the present embodiment, the second doped region 110 includes a bottom arm 111 formed in the first doped region 100 and a protruding arm 112 extending upward from the bottom arm 110, and an upper surface of the protruding arm 112 is higher than an upper surface of the bottom arm 111 and an upper surface of the first doped region 100. The isolation layer 200 covers the first doped region 100 and the bottom arm 111 on both sides of the protruding arm 112, but does not cover the protruding arm 112, so as to form a window exposing the protruding arm 112 at the protruding arm 112, and at this time, the second doped region 110 is in contact with the fuse dielectric layer 310 through the protruding arm 112. Further, the upper surface of the protruding arm 112 is flush with the upper surface of the isolation layer 200, and the fuse dielectric layer 310 has a flat lower surface. Further, when the second doped region 110 has a bottom arm 111 and a protruding arm 112, the bottom arm 111 and the protruding arm 112 are L-shaped in the side cross-section shown in fig. 2a, that is, the protruding arm 112 extends upward from the end of the bottom arm 111.
In an embodiment, as shown in fig. 2a, isolation spacers 700 are further formed on both sides of the gate structure 300, it can be understood that the isolation spacers 700 should comprise an insulating material having an isolation effect, for example, the isolation spacers 700 may be made of one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and the like, and when the isolation spacers 700 have a multilayer structure, an air gap may be formed in the middle to further improve the isolation effect. In the present embodiment, the isolation sidewall spacer 700 is composed of a first sidewall 710, a second sidewall 720 and a third sidewall 730 stacked together, and the first sidewall 710, the second sidewall 720 and the third sidewall 730 are made of different materials, for example, the first sidewall 710 may be silicon nitride, the second sidewall 720 may be silicon oxide, and the third sidewall 730 may be silicon nitride.
Specifically, the isolation pad 500 may be disposed in various ways, as long as it can electrically isolate the second electrode 620 from the gate structure 300, which is not limited herein. In one embodiment, as shown in fig. 2a, the isolation pad 500 penetrates the passivation layer 400, the gate conductive layer 320 and extends to the fuse dielectric layer 310 in sequence, i.e. the bottom of the isolation pad 500 contacts the fuse dielectric layer 310. In another embodiment, referring to fig. 3, the isolation pad 500 sequentially penetrates the passivation layer 400 and the gate structure 300 and extends to the isolation layer 200, i.e., the bottom of the isolation pad 500 contacts the isolation layer 200. In other embodiments, the isolation pad 500 may also sequentially penetrate the passivation layer 400, the gate structure 300 and the isolation layer 200 and directly contact the second doped region 110. It is understood that the isolation pad 500 should also comprise an insulating material having an isolation function, for example, the isolation pad 500 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc., and when the isolation pad 500 has a multi-layer structure, an air gap may be formed therebetween to further improve the isolation effect.
Specifically, the fuse dielectric layer 310 may be an oxide layer, and specifically may be a silicon oxide layer. The gate conductive layer 320 may be a polysilicon layer, a metal layer, or a stacked polysilicon layer and metal layer. In the embodiment, the fuse dielectric layer 310 is a silicon oxide layer, the gate conductive layer 320 includes a polysilicon layer 321 and a metal layer 322 sequentially stacked on the fuse dielectric layer 310, and the first electrode 610 is in contact with the metal layer 322. Further, the metal layer 322 may be metal tungsten.
The present application further relates to a programmable memory, which includes the above antifuse structure, wherein the specific structure of the antifuse structure has been described above and is not described herein again. As described above, the area occupied by the antifuse structure in the programmable memory is small, and thus the programmable memory has a high integration level.
The above examples only represent some embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. An antifuse structure, comprising:
a first doped region having a first conductivity type formed in the semiconductor substrate;
a second doped region having a second conductivity type formed at least partially within the first doped region;
an isolation layer formed on the first doped region and the second doped region, the isolation layer having a window exposing the second doped region;
the grid structure comprises a fuse medium layer and a grid conducting layer overlapped on the fuse medium layer, and the fuse medium layer is contacted with the second doped region through the window;
a first electrode in contact with the gate conductive layer; and
and the second electrode sequentially penetrates through the grid structure and the isolation layer and is in contact with the second doping region, and the second electrode is electrically isolated from the grid structure through an isolation gasket.
2. The antifuse structure of claim 1, wherein the second doped region comprises a bottom arm formed in the first doped region and a protruding arm extending upward from the bottom arm, the isolation layer covers the first doped region and the bottom arm on both sides of the protruding arm, the window exposes the protruding arm, and the fuse dielectric layer contacts the protruding arm.
3. The antifuse structure of claim 2, wherein the second doped region is L-shaped in side cross-section.
4. The antifuse structure of claim 1, wherein isolation spacers are further formed on both sides of the gate structure.
5. The antifuse structure of claim 1, further comprising:
the passivation layer covers the grid structure; the first electrode penetrates through the passivation layer and is in contact with the gate conductive layer, and the second electrode penetrates through the passivation layer, the gate structure and the isolation layer in sequence and is in contact with the second doped region.
6. The antifuse structure of claim 5, wherein the isolation pad penetrates the passivation layer, the gate conductive layer, and a bottom of the isolation pad is in contact with the fuse dielectric layer in that order.
7. The antifuse structure of claim 5, wherein the isolation pad penetrates the passivation layer and the gate structure in sequence and a bottom of the isolation pad is in contact with the isolation layer.
8. The antifuse structure of any one of claims 1 to 7, wherein the fuse dielectric layer is an oxide layer.
9. The antifuse structure of claim 8, wherein the gate conductive layer comprises a polysilicon layer and a metal layer sequentially stacked on the fuse dielectric layer, and a bottom of the first electrode is in contact with the metal layer.
10. A programmable memory comprising the antifuse structure of any one of claims 1 to 9.
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| CN201922075776.0U CN210575939U (en) | 2019-11-25 | 2019-11-25 | Anti-fuse structure and programmable memory |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113192828A (en) * | 2021-04-29 | 2021-07-30 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN113658909A (en) * | 2021-08-12 | 2021-11-16 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| WO2023213014A1 (en) * | 2022-05-05 | 2023-11-09 | 长鑫存储技术有限公司 | Anti-fuse structure and manufacturing method therefor, anti-fuse array and storage device |
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2019
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113192828A (en) * | 2021-04-29 | 2021-07-30 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN113658909A (en) * | 2021-08-12 | 2021-11-16 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN113658909B (en) * | 2021-08-12 | 2023-10-27 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
| WO2023213014A1 (en) * | 2022-05-05 | 2023-11-09 | 长鑫存储技术有限公司 | Anti-fuse structure and manufacturing method therefor, anti-fuse array and storage device |
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