CN113658909B - Method for manufacturing semiconductor structure and semiconductor structure - Google Patents

Method for manufacturing semiconductor structure and semiconductor structure Download PDF

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Publication number
CN113658909B
CN113658909B CN202110926931.4A CN202110926931A CN113658909B CN 113658909 B CN113658909 B CN 113658909B CN 202110926931 A CN202110926931 A CN 202110926931A CN 113658909 B CN113658909 B CN 113658909B
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air gap
carbon
layer
semiconductor structure
oxide
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CN113658909A (en
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郗宁
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Abstract

The application provides a manufacturing method of a semiconductor structure and the semiconductor structure, relates to the technical field of semiconductors, and is used for solving the technical problem of high parasitic capacitance value of the semiconductor structure. The semiconductor structure comprises a bit line and an air gap positioned on at least one side of the bit line, wherein the material of the side wall of the air gap comprises a silicon-containing compound, the side wall of the air gap is subjected to carburizing treatment, and a carbon-containing layer is formed on the inner side surface of the air gap; and (3) oxidizing the area of the carbon-containing layer close to the opening of the air gap to generate oxide to block the opening of the air gap. The generated oxide is used for blocking the air gap, the oxide grows on the side wall of the air gap to realize self-sealing of the air gap, and the probability that the oxide falls into the air gap is reduced, so that the effect of the air gap on reducing the parasitic capacitance value is ensured, and the parasitic capacitance value of the semiconductor structure is reduced.

Description

Method for manufacturing semiconductor structure and semiconductor structure
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
With the development of semiconductor technology, the integration level of semiconductor structures on a chip is continuously improved, and the space between each semiconductor structure is continuously reduced, so that the space between adjacent conductive devices (such as bit lines) in the semiconductor structure is continuously reduced, and the parasitic capacitance value between the adjacent conductive devices is increased. With the increase of the parasitic capacitance value, the capacitive coupling between adjacent conductive devices increases, which results in delay of the electrical signal on the chip (capacitive resistance delay), not only affecting the operating frequency of the chip, but also affecting the reliability of the chip.
In the related art, by providing an air gap between conductive devices, the dielectric constant of air is utilized to be low to reduce the parasitic capacitance value between conductive devices. However, when the air gap opening is closed, the sealing material is easy to fall into the air gap, so that the effect of reducing the parasitic capacitance value of the air gap is reduced, and the parasitic capacitance value of the semiconductor structure is higher.
Disclosure of Invention
In view of the foregoing, embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure for reducing parasitic capacitance of the semiconductor structure.
A first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, where the semiconductor structure includes a bit line and an air gap located on at least one side of the bit line, and a material of a sidewall of the air gap includes a silicon-containing compound, and the method for manufacturing the semiconductor structure includes:
carburizing the side wall of the air gap, wherein a carbon-containing layer is formed on the inner side surface of the air gap;
and oxidizing the area of the carbon-containing layer close to the opening of the air gap to form oxide which is blocked at the opening of the air gap.
The manufacturing method of the semiconductor structure provided by the embodiment of the application has at least the following advantages:
in the manufacturing method of the semiconductor structure provided by the embodiment of the application, the carbon-containing layer is formed on the inner side surface of the air gap, and the area, close to the opening of the air gap, of the carbon-containing layer is subjected to oxidation treatment, the side wall of the air gap grows oxide to self-seal the air gap, so that the probability that the oxide falls into the air gap is reduced, the effect of the air gap on reducing the parasitic capacitance value is ensured, and the parasitic capacitance value of the semiconductor structure is reduced.
In the method for manufacturing the semiconductor structure, the first temperature is 70-200 ℃, the first pressure is 10mTorr-500mTorr, the first radio frequency power is 1000W-10000W, and the first bias voltage is 50W-500W during carburizing treatment.
In the method for manufacturing the semiconductor structure, when the side wall of the air gap is carburized, a first plasma is utilized to react with the side wall of the air gap, and the first plasma comprises one or more of methane, ethylene or acetylene.
In the method for manufacturing the semiconductor structure, the first plasma is methane, and the flow rate of the methane is 10sccm-500sccm.
In the above method for manufacturing a semiconductor structure, the sidewall of the air gap is made of silicon nitride, and the carbon-containing layer is made of silicon carbide nitride.
In the method for manufacturing the semiconductor structure, the first plasma uses nitrogen or argon as a carrier, and the flow rate of the nitrogen or argon is 10sccm-500sccm.
In the method for manufacturing the semiconductor structure, the second temperature is 10-80 ℃, the second pressure is 1000mTorr-20000mTorr, the second radio frequency power is 1000W-10000W, and the second bias voltage is 0W-50W during the oxidation treatment.
In the method for manufacturing the semiconductor structure, when the region of the carbon-containing layer close to the opening of the air gap is subjected to oxidation treatment, the second plasma is utilized to react with the region of the carbon-containing layer close to the opening of the air gap; the second plasma includes an oxidizing gas including one or more of carbon monoxide or carbon dioxide and an assist gas including one or more of silane or disilane.
In the method for manufacturing the semiconductor structure, the flow rate of the oxidizing gas is 500sccm-5000sccm; the auxiliary gas is silane, and the flow rate of the silane is 500sccm-5000sccm.
In the method for manufacturing the semiconductor structure, the second plasma uses nitrogen or argon as a carrier, and the flow rate of the nitrogen or argon is 10sccm-500sccm.
In the above method for manufacturing a semiconductor structure, the carbon-containing layer is made of silicon carbide nitride, and the oxide material includes one or more of silicon oxide, silicon oxycarbide or silicon oxynitride.
According to the manufacturing method of the semiconductor structure, the width of the air gap is smaller than or equal to 5nm and larger than or equal to 1nm, and the thickness of the carbon-containing layer is smaller than 1.5nm.
The method for manufacturing the semiconductor structure, before the step of carburizing the side wall of the air gap to form the carbon-containing layer, further comprises: forming a plurality of bit lines arranged at intervals on a substrate, and a first insulating layer covering the bit lines, wherein the first insulating layer between adjacent bit lines surrounds a containing groove; forming a sacrificial layer on a sidewall of the accommodating groove, and a second insulating layer covering the sacrificial layer; removing the second insulating layer on the surface of the sacrificial layer facing away from the substrate to expose the sacrificial layer; and removing the sacrificial layer to form the air gap, wherein the first insulating layer and the second insulating layer form side walls of the air gap.
A second aspect of embodiments of the present application provides a semiconductor structure including a bit line, and an air gap disposed on at least one side of the bit line; the inner side surface of the air gap is provided with a carbon-containing layer, an oxide is formed in the area, close to the opening of the air gap, of the carbon-containing layer, and the opening of the air gap is plugged by the oxide.
The semiconductor structure provided by the embodiment of the application has at least the following advantages:
in the semiconductor structure provided by the embodiment of the application, the carbon-containing layer is formed on the inner side surface of the air gap, and the air gap is self-sealed by forming the oxide on the carbon-containing layer, so that the probability that the oxide falls into the air gap is reduced, the effect of the air gap on reducing the parasitic capacitance value is ensured, and the parasitic capacitance value of the semiconductor structure is reduced.
In the semiconductor structure described above, the material of the carbon-containing layer includes silicon carbide nitride, and the material of the oxide includes one or more of silicon oxide, silicon oxycarbide, or silicon oxycarbonitride.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a related art semiconductor structure;
FIG. 2 is a schematic diagram of a structure of the prior art after exposing a sacrificial layer;
FIG. 3 is a schematic diagram of a structure after forming an air gap in the related art;
FIG. 4 is a schematic view of a structure of a support layer according to the related art;
FIG. 5 is a flow chart of forming an air gap in an embodiment of the application;
FIG. 6 is a schematic view of a part of the structure of an embodiment of the present application;
FIG. 7 is a schematic diagram of an embodiment of the present application after forming an air gap;
FIG. 8 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 9 is a schematic view of a structure of a preliminary carbon-containing layer according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a structure after forming a carbon-containing layer according to an embodiment of the present application;
FIG. 11 is a schematic view of the structure of an oxide formed initially in an embodiment of the present application;
fig. 12 is a schematic diagram of an oxide structure for blocking an air gap in an embodiment of the present application.
Reference numerals illustrate:
10-bit lines; 11-a first insulating layer;
12-a sacrificial layer; 13-a second insulating layer;
14-bit line contacts; 15-a support layer;
20-air gap; 21-sidewalls;
22-a carbon-containing layer; 23-oxide.
Detailed Description
Referring to fig. 1 to 4, when the air gap 20 is formed, a first insulating layer 11, a sacrificial layer 12 and a second insulating layer 13 are sequentially formed on the sidewall of the conductive device, the sacrificial layer 12 is removed, and then a supporting layer 15 is formed on the top surface of the first insulating layer 11 and the top surface of the second insulating layer 13, and the supporting layer 15 blocks the air gap 20. However, when the supporting layer 15 is formed, the supporting layer 15 is easily filled into the air gap 20, so that the effect of reducing the parasitic capacitance value of the air gap 20 is reduced, and the parasitic capacitance value of the semiconductor structure is high.
In order to reduce the parasitic capacitance value of the semiconductor structure, in the manufacturing method of the semiconductor structure provided by the embodiment of the application, the carbon-containing layer is formed on the inner side surface of the air gap, and the opening of the air gap is blocked by the generated oxide through oxidation treatment of the carbon-containing layer, so that the probability that the oxide falls into the air gap is reduced, the effect of the air gap on reducing the parasitic capacitance value is ensured, and the parasitic capacitance value of the semiconductor structure is reduced.
In order to make the above objects, features and advantages of the embodiments of the present application more comprehensible, the technical solutions of the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The embodiment of the application provides a manufacturing method of a semiconductor structure, which can be a part of a dynamic random access memory. As shown in fig. 3, the semiconductor structure includes a plurality of Bit lines 10 (BL) arranged at intervals, and the plurality of Bit lines 10 extend in a first direction. The first direction is a direction perpendicular to the paper surface in fig. 1.
It will be appreciated that a plurality of bit lines 10 are provided on a substrate (not shown) which is supported by the substrate. The substrate is typically a semiconductor substrate, such as a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, or the like. For example, the substrate in the embodiment of the present application is a silicon substrate, where the silicon substrate may be an N-type doped silicon substrate or a P-type doped silicon substrate. Of course, the silicon substrate may be an undoped silicon substrate.
The bit line 10 is disposed on the substrate and extends in a first direction. The bit line 10 is electrically connected to the substrate, for example, the bit line 10 is electrically connected to the substrate through a bit line contact 14 located in the substrate, and the bit line contact 14 may be made of polysilicon (polysilicon). The bit line 10 may include a plurality of conductive layers including one or more of a tungsten layer, a titanium layer, a nickel layer, an aluminum layer, a titanium oxide layer, and a titanium nitride layer, which are sequentially stacked. Illustratively, the bit line 10 includes a titanium nitride layer and a tungsten layer disposed on the titanium nitride layer.
The side and top surfaces of the bit line 10 are covered with a first insulating layer 11, wherein the top surface refers to the surface facing away from the substrate, i.e. the upper surface shown in fig. 3. The first insulating layer 11 is made of insulating material to protect the bit line 10 and isolate electrical appliances. Illustratively, the material of the first insulating layer 11 may include a silicon-containing compound, such as silicon nitride.
The second insulating layer 13 is provided beside the first insulating layer 11, for example, one second insulating layer 13 is provided on each side of the first insulating layer 11. An air gap 20 is formed between the first insulating layer 11 and the second insulating layer 13, and the first insulating layer 11 and the second insulating layer 13 are sidewalls 21 of the air gap 20, respectively.
The material of the second insulating layer 13 is an insulating material, and the material of the first insulating layer 11 may include a silicon-containing compound, for example. Specifically, the material of the second insulating layer 13 is the same as that of the first insulating layer 11, so that the material of the sidewall of the air gap 20 is consistent.
The first insulating layer 11 located between two adjacent bit lines 10 encloses a receiving groove, and the extending direction of the receiving groove is the same as the extending direction of the bit lines 10. Two second insulating layers 13 are provided in the accommodating groove. The two second insulating layers 13 form an air gap 20 with their corresponding first insulating layers 11, respectively. As shown in fig. 3, in the same accommodating groove, the second insulating layer 13 on the left side forms an air gap 20 with the first insulating layer 11 on the left side wall of the accommodating groove, and the second insulating layer 13 on the right side forms an air gap 20 with the first insulating layer 11 on the right side wall of the accommodating groove.
Referring to fig. 5, in some possible embodiments of the present application, the formation of the air gap 20 may include the steps of:
step a: a plurality of bit lines are formed on a substrate at intervals, and first insulating layers are covered on the bit lines, and the first insulating layers between adjacent bit lines are surrounded to form accommodating grooves.
Illustratively, a plurality of bit lines 10 are formed on a substrate through a deposition process, each bit line 10 being disposed at intervals; a first insulating layer 11 is then deposited over the plurality of bit lines 10 and the substrate. The first insulating layer 11 covers the top and side surfaces of the bit lines 10, and the top surface of the substrate, and the first insulating layer 11 between adjacent bit lines 10 is enclosed to form a receiving groove.
Step b: a sacrificial layer is formed on a sidewall of the accommodating groove, and a second insulating layer covering the sacrificial layer.
Illustratively, the sacrificial layer 12 is formed by a deposition process, the sacrificial layer 12 covering the top surface of the first insulating layer 11, the side walls and the bottom surface of the accommodating groove; removing the sacrificial layer 12 on the top surface of the first insulating layer 11 and the sacrificial layer 12 on the bottom surface of the accommodating groove, and reserving the sacrificial layer 12 on the side wall of the accommodating groove; then, a second insulating layer 13 is formed by a deposition process, and the second insulating layer 13 covers the top and side surfaces of the sacrificial layer 12.
The material of the sacrificial layer 12 is different from the material of the first insulating layer 11 and the material of the second insulating layer 13, for example, the material of the sacrificial layer 12 is silicon oxide. The sacrificial layer 12 and the first insulating layer 11, and the sacrificial layer 12 and the second insulating layer 13 may have a larger selection ratio, and damage to the first insulating layer 11 and the second insulating layer 13 is smaller when the sacrificial layer 12 is subsequently removed. For example, the material of the first insulating layer 11 is the same as that of the second insulating layer 13, so that the second insulating layer 13 and the first insulating layer 11 form an integrated structure, and separation among the second insulating layer 13, the sacrificial layer 12 and the first insulating layer 11 is reduced or avoided. It will be appreciated that the nitride, oxide, nitride (Nitride Oxide Nitride, simply NON) structures are in sequence along a direction perpendicular to the sides of the conductive layer and away from the conductive layer (i.e., the X direction shown in FIG. 2).
Step c: the second insulating layer is removed at a surface of the sacrificial layer facing away from the substrate to expose the sacrificial layer.
The second insulating layer 13 on the top surface of the sacrificial layer 12 is removed by an etching process to expose the sacrificial layer 12, for example. In the same accommodating groove, the second insulating layer 13 on the top surface of the sacrificial layer 12 on the left side is removed, and the second insulating layer 13 on the top surface of the sacrificial layer 12 on the right side is covered with other structures, such as a capacitor contact, and the second insulating layer 13 not covered by the capacitor contact is also removed, thereby exposing the sacrificial layers 12 on both the left and right sides.
Step d: the sacrificial layer is removed to form an air gap, and the first insulating layer and the second insulating layer form sidewalls of the air gap.
Illustratively, the sacrificial layer 12 is removed by an etching process to form the air gap 20. When the second insulating layer 13 is etched away, portions of the first insulating layer 11 and the second insulating layer 13 are also etched away. That is, the width of the air gap 20 is greater than the thickness of the sacrificial layer 12, wherein the width direction of the air gap 20 and the thickness direction of the sacrificial layer 12 are perpendicular to the side direction of the conductive layer.
For example, referring to fig. 6 and 7, the height H of the sacrificial layer 12 may be 120nm, the thickness L1 of the first insulating layer 11 may be 2nm, the thickness L2 of the sacrificial layer 12 may be 2nm, and the thickness L3 of the second insulating layer 13 may be 3nm. The depth of the air gap 20 formed after the sacrificial layer 12 is removed is 120nm, the width D of the air gap 20 may be less than or equal to 5nm and greater than or equal to 1nm, for example, the width of the air gap 20 is 3nm, the thickness L1 of the first insulating layer 11 may be 1.5nm, and the thickness L3 of the second insulating layer 13 may be 2.5nm.
Referring to fig. 8, in the embodiments of the present application and the following embodiments, taking the sidewall 21 of the air gap 20 as silicon nitride as an example, the method for manufacturing the semiconductor structure may include the following steps:
step S101, carburizing the side wall of the air gap, wherein a carbon-containing layer is formed on the inner side surface of the air gap.
Referring to fig. 9, the side wall 21 of the air gap 20 is carburized by the first plasma, specifically, the side wall 21 of the air gap 20 is bombarded with the first plasma, and carbon element (C-radial) in the first plasma diffuses in the side wall 21 of the air gap 20 and reacts with the side wall 21 of the air gap 20, so that the inner side surface of the air gap 20 forms the carbon-containing layer 22.
Specifically, the first temperature is 70-200 ℃ to increase the carbon flow at the bottom of the air gap 20. The first pressure is 10mTorr-500mTorr, the first Radio Frequency (RF) Power is 1000W-10000W, and the first Bias voltage (Bias Power) is 50W-500W. The first rf power is used to generate a first plasma and the first bias voltage is used to accelerate the first plasma so that the first plasma may accelerate to the bottom of the air gap 20 so that a carbon-containing layer 22 may be formed along the entire inner side of the air gap 20.
In some possible examples, the first plasma includes methane (CH 4 ) Ethylene (C) 2 H 2 ) Or acetylene (C) 2 H 4 ) One or more of the following. The sidewall 21 of the air gap 20 is made of silicon nitride (e.g., si 3 N 4 ) The carbon-containing layer 22 is silicon carbide nitride (SiCN). By forming the carbon-containing layer 22 with a dielectric constant smaller than that of the sidewall 21 of the air gap 20, the parasitic capacitance of the semiconductor structure can be further reduced.
The sidewall 21 of the air gap 20 is made of silicon nitride (e.g., si 3 N 4 ) When the carbon-containing layer 22 is silicon carbide nitride (SiCN), the reaction process in the carburizing treatment is as follows:
Si 3 N 4 +C * →SiCN
for example, the first plasma is methane, and the flow rate of methane may be 10sccm-500sccm (Standard-state Cubic Centimeter per Minute, standard milliliters per minute) during the carburization process. The first plasma uses inert gases such as nitrogen (N2) or argon (Ar) as a carrier, and the flow rate of the nitrogen or the argon is 10sccm-500sccm. The first plasma is fed into the reaction chamber by nitrogen or argon, and the reaction chamber is purged with nitrogen or argon to remove by-products and the like.
Referring to fig. 9 and 10, the diffusion degree of carbon element is limited at the time of carburizing treatment, and the thickness of the carbon-containing layer 22 may be less than 1.5nm, i.e., the thickness of the carbon-containing layer 22 is less than the thickness of the side wall 21 of the air gap 20. Of course, the thickness of the carbon-containing layer 22 may also be equal to the thickness of the side walls 21 of the air gap 20.
Step S102, oxidizing the area of the carbon-containing layer close to the opening of the air gap, and blocking the opening of the air gap by the generated oxide.
Referring to fig. 10 to 12, the carbonaceous layer 22 is subjected to oxidation treatment by the second plasma, and oxide 23 is produced in a region of the carbonaceous layer 22 near the opening of the air gap 20, and the oxide 23 blocks the opening of the air gap 20 so that the air gap 20 is closed. The self-sealing of the air gap 20 by the accumulation of the oxide 23 can reduce or prevent the deposited material from falling into the air gap 20 in the related art, thereby ensuring the effect of reducing the parasitic capacitance value of the air gap 20 and fully playing the effect of reducing the parasitic capacitance value of the air gap 20.
Specifically, the second temperature is 10-80 ℃ to increase the carbon flow at the top of the air gap 20. The second pressure is 1000mTorr-20000mTorr to reduce the flow of the second plasma to the bottom of the air gap 20. The second radio frequency power is 1000W-10000W, and the second bias voltage is 0W-50W. The second rf power is used to generate a second plasma, the second bias is used to accelerate the first plasma, and the second bias is 0W-50W to reduce the flow of the first plasma to the bottom of the air gap 20 so that the oxide 23 is formed mainly near the opening of the air gap 20.
In some possible examples, the second plasma includes an oxidizing gas and an auxiliary gas, the oxidizing gas and the sidewall 21 of the air space 20, and the oxidizing gas and the auxiliary gas can react to form the oxide 23, and the oxide 23 formed is at least partially the same to increase the content of the oxide 23, so as to facilitate sealing the air space 20. The second plasma takes nitrogen or argon as a carrier, and the flow rate of the nitrogen or the argon is 10sccm-500sccm. The second plasma is fed into the reaction chamber by nitrogen or argon, and the reaction chamber is purged with nitrogen or argon to remove by-products and the like.
The oxidizing gas comprises one or more of carbon monoxide or carbon dioxide, for example, the oxidizing gas may also comprise oxygen. The oxidizing gas reacts with the carbon-containing layer 22 to form an oxide 23, and the flow rate of the oxidizing gas may be 500sccm to 5000sccm. The material of the carbon-containing layer 22 is silicon carbide nitride, the material of the oxide 23 comprises one or more of silicon oxide, silicon oxycarbide or silicon oxynitride, and the reaction process during the oxidation treatment is as follows:
SICN+O * →SiO 2 +SiCO+SiCNO
the assist gas includes Silane (SiH) 4 ) Or disilane (SiH) 6 ) The auxiliary gas reacts with the oxidizing gas to form an oxide, which oxide 23 is partially identical to the oxide formed by the carbon-containing layer 22, so that the oxide is deposited on the oxide formed by the carbon-containing layer 22. At the same time, this oxide increases the total amount of oxide 23 and also facilitates sealing the air gap 20.
The auxiliary gas is silane, the flow rate of the silane is 500sccm-5000sccm, and the reaction process of the auxiliary gas and the oxidizing gas is as follows:
SiH 4 +O * →H 2 O+Si x O y
SiH 4 +O * +C * →SiCO
as shown in fig. 11 and 12, the oxidizing gas reacts with the side wall 21 of the air space 20 and the oxidizing gas reacts with the assist gas to form oxide 23, which gradually accumulates in the opening of the air space 20 until the opening of the air space 20 is closed. In the embodiment of the present application, after the oxide 23 seals the opening of the air gap 20, no other film layer is required to be formed on the oxide 23 or the sidewall 21 of the air gap 20.
In the method for manufacturing the semiconductor structure provided by the embodiment of the application, the carbon-containing layer 22 is formed on the inner side surface of the air gap 20, and the area, close to the opening of the air gap 20, of the carbon-containing layer 22 is subjected to oxidation treatment, the oxide 23 grows on the side wall 21 of the air gap 20 to self-seal the air gap 20, so that the probability that the oxide 23 falls into the air gap 20 is reduced, the effect of the air gap 20 on reducing the parasitic capacitance value is ensured, and the parasitic capacitance value of the semiconductor structure is reduced.
The embodiment of the application also provides a semiconductor structure which comprises bit lines and air gaps positioned on at least one side of the bit lines, and parasitic capacitance values between the bit lines and/or between the bit lines and other structures (such as capacitor plugs) are reduced by arranging the air gaps.
A plurality of bit lines are disposed on a substrate (not shown) and are supported by the substrate. The substrate is typically a semiconductor substrate, such as a silicon substrate, which may be an N-doped silicon substrate or a P-doped silicon substrate. Of course, the silicon substrate may be an undoped silicon substrate.
The bit line may include a plurality of conductive layers sequentially stacked, and the conductive layers include one or more of a tungsten layer, a titanium layer, a nickel layer, an aluminum layer, a titanium oxide layer, and a titanium nitride layer. Illustratively, the bit line includes a titanium nitride layer and a tungsten layer disposed on the titanium nitride layer. The side and top surfaces of the bit line are covered with a first insulating layer, wherein the top surface refers to the surface facing away from the substrate. The first insulating layer is made of insulating materials so as to protect the bit line and isolate electrical appliances. Illustratively, the material of the first insulating layer may include a silicon-containing compound, such as silicon nitride.
The second insulating layer is disposed beside the first insulating layer, for example, two sides of the first insulating layer are respectively provided with a second insulating layer. An air gap is formed between the first insulating layer and the second insulating layer, and the first insulating layer and the second insulating layer are respectively the side walls of the air gap. The material of the second insulating layer is an insulating material, and exemplary materials of the first insulating layer may include a silicon-containing compound. Specifically, the material of the second insulating layer is the same as that of the first insulating layer, so that the material of the side wall of the air gap is consistent.
It is understood that the first insulating layer between two adjacent bit lines encloses a receiving groove, and the extending direction of the receiving groove is the same as the extending direction of the bit lines. Two second insulating layers are arranged in the accommodating groove, and the two second insulating layers and the first insulating layers opposite to the two second insulating layers form an air gap.
The inner side surface of the air gap is provided with a carbon-containing layer, and the area of the carbon-containing layer close to the opening of the air gap is provided with an oxide which seals the opening of the air gap. The carbon-containing layer is formed by carburizing the first insulating layer and the second insulating layer, and the oxide is formed by oxidizing a region of the carbon-containing layer adjacent to an opening of the air gap. The material of the first insulating layer and the second insulating layer comprises silicon nitride, the material of the carbon-containing layer comprises silicon carbide nitride, and the material of the oxide comprises one or more of silicon oxide, silicon oxycarbide or silicon oxycarbonitride. The dielectric constant of the carbon-containing layer is lower than that of the first insulating layer and the second insulating layer, and the parasitic capacitance value of the semiconductor structure can be further reduced by arranging the carbon-containing layer.
In the oxidation treatment of the region of the carbonaceous layer near the opening of the air gap, the oxidizing gas reacts not only with the carbonaceous layer to form an oxide, but also with the assist gas to form an oxide, which is partially the same as the oxide formed by the carbonaceous layer, so that the oxide is deposited on the oxide formed by the carbonaceous layer. At the same time, the oxide increases the total amount of oxide, and is convenient for sealing the air gap.
In the semiconductor structure provided by the embodiment of the application, the carbon-containing layer is formed on the inner side surface of the air gap, and the air gap is self-sealed by forming the oxide on the carbon-containing layer, so that the probability that the oxide falls into the air gap is reduced, the effect of the air gap on reducing the parasitic capacitance value is ensured, and the parasitic capacitance value of the semiconductor structure is reduced.
In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
In the description of the present specification, reference is made to "one embodiment," "some embodiments," "an exemplary embodiment," "an example," "a particular instance," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims (15)

1. A method for fabricating a semiconductor structure, wherein the semiconductor structure includes a bit line and an air gap located on at least one side of the bit line, and a sidewall of the air gap includes a silicon-containing compound, the method comprising:
carburizing the side wall of the air gap, wherein a carbon-containing layer is formed on the inner side surface of the air gap;
and oxidizing the area of the carbon-containing layer close to the opening of the air gap to form oxide which is blocked at the opening of the air gap.
2. The method of claim 1, wherein the first temperature during the carburizing process is 70 ℃ to 200 ℃, the first pressure is 10mTorr to 500mTorr, the first rf power is 1000W to 10000W, and the first bias voltage is 50W to 500W.
3. The method of claim 2, wherein the carburizing of the sidewalls of the air gap is performed by reacting a first plasma with the sidewalls of the air gap, the first plasma comprising one or more of methane, ethylene, or acetylene.
4. The method of claim 3, wherein the first plasma is methane, and the flow rate of the methane is 10sccm-500sccm.
5. The method of claim 4, wherein the sidewall of the air gap is silicon nitride and the carbon-containing layer is silicon carbide nitride.
6. The method of claim 3, wherein the first plasma uses nitrogen or argon as a carrier, and the flow rate of the nitrogen or argon is 10sccm-500sccm.
7. The method of any one of claims 1-6, wherein the second temperature during the oxidation process is between 10 ℃ and 80 ℃, the second pressure is between 1000mTorr and 20000mTorr, the second rf power is between 1000W and 10000W, and the second bias voltage is between 0W and 50W.
8. The method according to any one of claims 1 to 6, wherein the region of the carbon-containing layer adjacent to the opening of the air gap is subjected to oxidation treatment, and the region of the carbon-containing layer adjacent to the opening of the air gap is reacted with a second plasma;
the second plasma includes an oxidizing gas including one or more of carbon monoxide or carbon dioxide and an assist gas including one or more of silane or disilane.
9. The method of fabricating a semiconductor structure according to claim 8, wherein a flow rate of the oxidizing gas is 500sccm to 5000sccm;
the auxiliary gas is silane, and the flow rate of the silane is 500sccm-5000sccm.
10. The method of claim 8, wherein the second plasma is nitrogen or argon as a carrier, and the flow rate of the nitrogen or argon is 10sccm-500sccm.
11. The method of claim 8, wherein the carbon-containing layer is silicon carbide nitride, and the oxide material comprises one or more of silicon oxide, silicon oxycarbide, and silicon oxynitride.
12. The method of any one of claims 1-6, wherein the air gap has a width of less than or equal to 5nm and greater than or equal to 1nm, and the carbon-containing layer has a thickness of less than 1.5nm.
13. The method of fabricating a semiconductor structure according to any one of claims 1 to 6, wherein the step of carburizing the sidewall of the air gap, before the step of forming the carbon-containing layer on the inner side surface of the air gap, further comprises:
forming a plurality of bit lines arranged at intervals on a substrate, and a first insulating layer covering the bit lines, wherein the first insulating layer between adjacent bit lines surrounds a containing groove;
forming a sacrificial layer on a sidewall of the accommodating groove, and a second insulating layer covering the sacrificial layer;
removing the second insulating layer on the surface of the sacrificial layer facing away from the substrate to expose the sacrificial layer;
and removing the sacrificial layer to form the air gap, wherein the first insulating layer and the second insulating layer form side walls of the air gap.
14. A semiconductor structure comprising a bit line and an air gap disposed on at least one side of the bit line;
the inner side surface of the air gap is provided with a carbon-containing layer, an oxide is formed in the area, close to the opening of the air gap, of the carbon-containing layer, and the oxide is formed by oxidizing the carbon-containing layer and plugs the opening of the air gap.
15. The semiconductor structure of claim 14, wherein the carbon-containing layer comprises silicon carbide nitride and the oxide comprises one or more of silicon oxide, silicon oxycarbide, or silicon oxycarbonitride.
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