CN209785927U - Chip and method for manufacturing the same - Google Patents
Chip and method for manufacturing the same Download PDFInfo
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- CN209785927U CN209785927U CN201920527670.7U CN201920527670U CN209785927U CN 209785927 U CN209785927 U CN 209785927U CN 201920527670 U CN201920527670 U CN 201920527670U CN 209785927 U CN209785927 U CN 209785927U
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Abstract
The utility model relates to a chip, chip includes: a substrate including a storage region and a peripheral region; a memory array formed in the memory region; at least one antifuse device formed in the peripheral region, the antifuse device for repairing memory defects caused by failed memory cells within the memory array; the antifuse device includes: the grid structure is positioned on the surface of the substrate and comprises a grid dielectric layer positioned on the surface of the substrate and a grid positioned on the surface of the grid dielectric layer; and the doped region is arranged in the substrate on one side of the grid structure parallel to the surface direction of the substrate, and at least part of the edge of the doped region is aligned with the edge of the grid or positioned below the grid. The antifuse device is more susceptible to breakdown.
Description
Technical Field
The utility model relates to a storage technology field especially relates to a chip.
Background
The DRAM chip manufactured by adopting a semiconductor process inevitably generates a defective memory unit, and a redundant memory unit is usually formed on the DRAM chip, and the DRAM chip can be repaired by using the redundant memory unit to permanently replace the defective memory unit.
In repairing a DRAM chip, a One Time Programming (OTP) device such as a fuse or an antifuse is required. As the feature size of semiconductor processes has decreased, the thickness of the gate dielectric layer of MOS transistor structures has become very thin, so that MOS structures can be utilized as anti-fuse devices.
In the prior art, the forming process of an anti-fuse device is complex, the resistance in the breakdown process is large, large breakdown current is not easy to realize, and the repair efficiency of a chip is influenced.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that through the breakdown current who improves anti-fuse device, improve the repair efficiency of chip.
In order to solve the above problem, the utility model provides a chip, include: a substrate including a storage region and a peripheral region; a memory array formed in the memory region; an antifuse device formed in the peripheral region, the antifuse device for repairing memory defects caused by failed memory cells within the memory array; the antifuse device is connected to the memory array; the antifuse device includes: the grid structure is positioned on the surface of the substrate and comprises a grid dielectric layer positioned on the surface of the substrate and a grid positioned on the surface of the grid dielectric layer; and the doped region is arranged in the substrate on one side of the grid structure parallel to the surface direction of the substrate, and at least part of the edge of the doped region is aligned with the edge of the grid or positioned below the grid.
Optionally, the storage array includes: the storage device comprises a main storage array and a redundant storage array, wherein redundant storage units in the redundant storage array are used for replacing failed storage units in the main storage array for data storage.
Optionally, the at least one antifuse device constitutes a programmable module for recording information of failed memory cells in the main memory array or/and redundant memory cells in the redundant memory array.
Optionally, the substrate of the peripheral region includes an active region and an isolation region surrounding the active region; the grid structure covers part of the active region and part of the isolation region, and only part of the active region on one side of the grid is exposed.
Optionally, a doped well is formed in the substrate below the gate structure of the antifuse device, and the doping type of the doped well is opposite to that of the doped region.
Optionally, the thickness of the gate dielectric layer is 2nm to 4 nm.
optionally, the chip is a memory chip, and the memory includes any one of an SRAM memory, a DRAM memory, or an MRAM memory.
Optionally, a peripheral circuit transistor is further formed in the peripheral region.
Optionally, the gates of the antifuse devices, the gates of the peripheral circuit transistors, and the bit lines of the memory array are located in the same layer.
Optionally, the sidewalls of the two sides of the gate of the peripheral circuit transistor are covered with sidewalls.
the utility model discloses a peripheral region of chip includes the antifuse device, the antifuse device adopts the MOS structure, directly uses the grid to form the doping region as the mask for doping region aligns or is located the grid below with the grid edge, thereby shortens the current path between doping region and the grid, thereby reduces the resistance on the current path, is favorable to improving breakdown current.
Drawings
Fig. 1 to 4 are schematic structural diagrams illustrating a process of forming an antifuse device according to an embodiment of the present invention;
Fig. 5 to 9 are schematic structural diagrams illustrating a forming process of a memory according to an embodiment of the present invention.
Detailed Description
The following describes in detail embodiments of an antifuse device and a method of forming the same, and a memory and a method of forming the same according to the present invention with reference to the accompanying drawings.
Please refer to fig. 1 to 4, which are schematic structural diagrams illustrating a process of forming an antifuse device according to an embodiment of the present invention.
Referring to fig. 1 and fig. 2, fig. 2 is a schematic cross-sectional view along the cut line AA' in fig. 1.
Providing a substrate 100, and forming a gate structure on the surface of the substrate 100, wherein the gate structure comprises a gate dielectric layer 103 located on the surface of the substrate 100 and a gate 104 located on the surface of the gate dielectric layer 103.
The substrate 100 may be a semiconductor substrate, such as a monocrystalline silicon substrate, a monocrystalline germanium substrate, or the like. The substrate 100 may also be an N-type or P-type semiconductor substrate.
The substrate 100 includes an active region 102 and an isolation region 101 surrounding the active region 102. The isolation region 101 may be a shallow trench isolation structure formed in the substrate 100. A doped well may be formed in the active region 102, and the doped well may be a doped portion of the substrate 100 itself, or may be a doped well formed by ion implantation or diffusion performed on the substrate 100.
The method for forming the gate structure on the surface of the substrate 100 comprises the following steps: and sequentially forming a gate dielectric material layer covering the surface of the substrate 100 and a gate material layer covering the surface of the gate dielectric material layer, forming a patterned mask layer on the surface of the gate material layer, and etching the gate material layer and the gate dielectric material layer to the surface of the substrate 100 by using the patterned mask layer as a mask to form the gate 104 and the gate dielectric layer 103.
The gate dielectric layer 103 can be made of one or a combination of high-K dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, and the like; the gate layer 104 may be at least one of polysilicon, titanium, copper, tungsten, metal silicide, and other conductive materials.
The gate structure covers a portion of the active region 102, and may cover an end of the active region 102. In this embodiment, the width of one end of the active region 102 is smaller than that of the other end, and the gate structure covers the end of the active region 102 with smaller width and is partially located on the surface of the isolation region 101.
As an antifuse device, the thickness and dielectric constant of the gate dielectric layer 103 determine the breakdown voltage of the antifuse device. In the embodiment of the present invention, in order to facilitate process compatibility with other MOS transistors in the circuit, the gate dielectric layer 103 may be formed simultaneously with the gate dielectric layer 103 of a part of the transistors formed in other regions on the substrate 100, and the same material and thickness are used, for example, substantially the same as the gate dielectric layer of the low voltage transistor in the peripheral region. Since the channel regions under the gate dielectric layers in different regions have different gate dielectric layer growth environments such as doping concentration, even if the gate dielectric layers are formed in the same forming process, the thicknesses of the gate dielectric layers in different regions may have slight differences, and thus are "substantially the same". In this embodiment, the gate dielectric layer 103 is made of silicon oxide, and the thickness range may be 2nm to 4 nm.
Referring to fig. 3 and 4, a doped region 105 is formed in the substrate 100 along a side of the gate structure in a direction parallel to the surface of the substrate 100, and at least a portion of an edge of the doped region 105 is aligned with an edge of the gate 104 or is located below the gate 104.
The doped region 105 may be formed by ion implantation, and the substrate 100 is ion implanted using the gate 104 as a mask to form the doped region 105 in the partially or completely uncovered active region 102. The doping type of the doped region 105 is opposite to that of the doped well in the active region 102, in this embodiment, the active region 102 has a P-type doped well therein, and the doped region 105 is doped N-type.
The doped region 105 serves as a conductive contact region, and has a higher doping concentration to reduce resistance. In this embodiment, the doped region 105 is formed in a region with a larger width of the active region 102, which can increase the contact area of the doped region 105, thereby increasing the size of an electrical contact formed on the surface of the doped region 105, and reducing the contact resistance between the electrical contact and the doped region 105. In one embodiment, the doping concentration of the doped region 105 ranges from 1e20 to 5e21cm-3As doping can be used, the ion implantation energy can be 20keV to 50keV, and the implantation dosage can be 1e15 to 5e15cm-2Higher doping concentrations may further reduce the resistance of the doped region 105.
since the periphery of the active region 102 is the isolation region 101, the isolation region 101 is also implanted during ion implantation, but no conductive doped region is formed.
Since the ion implantation is masked by the gate 104, the edge of the doped region 105 is formed to be aligned with the edge of the gate 104, or may be partially located under the gate 104. When breakdown voltage is applied to the gate 104, the current flows from the gate 104 to the doped region 105, and the distance between the doped region 105 and the gate 104 is short, so that the resistance on a carrier moving path can be reduced, the breakdown current is increased, and the breakdown efficiency of the anti-fuse device is improved. No additional ion implantation is required for the active region under the gate 104 to reduce the resistance.
In the method for forming the anti-fuse device in the above embodiment, the MOS structure is adopted, and the gate is directly used as a mask to form the doped region, so that the doped region is aligned with the edge of the gate or is located below the gate, thereby shortening a current path between the doped region and the gate, reducing resistance on the current path, and facilitating improvement of breakdown current.
The utility model discloses a specific embodiment still provides an antifuse device that adopts above-mentioned method to form.
Referring to fig. 3 and 4, an anti-fuse device according to an embodiment of the present invention is shown.
the antifuse device includes: a substrate 100; the gate structure is positioned on the surface of the substrate 100 and comprises a gate dielectric layer 103 positioned on the surface of the substrate 100 and a gate 104 positioned on the surface of the gate dielectric layer 103; a doped region 105 located in the substrate on one side of the gate structure, at least a portion of an edge of the doped region 105 being aligned with or located below an edge of the gate structure.
The substrate 100 includes an active region 102 and an isolation region 101 surrounding the active region 102. The isolation region 101 may be a shallow trench isolation structure formed in the substrate 100. A doped well may be formed in the active region 102, and the doped well may be a doped portion of the substrate 100 itself, or may be a doped well formed by ion implantation or diffusion performed on the substrate 100.
The gate dielectric layer 103 can be made of one or a combination of high-K dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, and the like; the gate layer 104 may be at least one of polysilicon, titanium, copper, tungsten, metal silicide, and other conductive materials. The gate structure covers a portion of the active region 102, and may cover an end of the active region 102. In this embodiment, the width of one end of the active region 102 is smaller than that of the other end, and the gate structure covers the end of the active region 102 with smaller width and is partially located on the surface of the isolation region 101.
As an antifuse device, the thickness and dielectric constant of the gate dielectric layer 103 determine the breakdown voltage of the antifuse device. In the embodiment of the present invention, in order to facilitate process compatibility with other MOS transistors in the circuit, the gate dielectric layer 103 may be made of the same material and thickness as the gate dielectric layer 103 of some transistors formed in other regions on the substrate 100, such as the gate dielectric layer of the low voltage transistor in the peripheral region. Since the channel regions under the gate dielectric layers in different regions have different gate dielectric layer growth environments such as doping concentration, even if the gate dielectric layers are formed in the same forming process, the thicknesses of the gate dielectric layers in different regions may have slight differences, and thus are "substantially the same". In this embodiment, the gate dielectric layer 103 is made of silicon oxide, and the thickness range may be 2nm to 4 nm.
The doping type of the doped region 105 is opposite to the doping type of the doped well in the active region 102, in this embodiment, the active region 102 has a P-type doped well therein, and the doped region 105 is doped N-type.
The heavy doping 105 is used as a conductive contact area, and the doping concentration is higher so as to reduce the resistance. In this embodiment, the doped region 105 is formed in a region with a larger width of the active region 102, which can increase the doped region 105, thereby increasing the size of an electrical contact formed on the surface of the doped region 105 later and reducing the contact resistance between the electrical contact and the doped region 105. The doping concentration range of the doping region 105 is 1e 20-5 e21cm-3Higher doping concentrations may further reduce the resistance of the doped region 105.
The edge of the doped region 105 is aligned with the edge of the gate 104, or may be partially under the gate 104. When a breakdown voltage is applied to the gate 104, the current flows from the gate 104 to the doped region 105, and since the distance between the doped region 105 and the gate 104 is short, the resistance on a carrier moving path can be reduced, so that the breakdown current is increased, and the anti-fuse device is more easily broken down.
Embodiments of the present invention also provide a chip having the antifuse device described in the above embodiments. The chip comprises a storage area and a peripheral area; a memory array formed in the memory region; at least one antifuse device formed within the peripheral region. The storage area is internally provided with a storage array, the storage array comprises a main storage array and a redundant storage array, a storage unit in the main storage array is used for storing data, and when one storage unit in the storage array fails, the failed storage unit cannot store the data or the stored data is wrong, so that the storage defect of the storage occurs. The redundant memory cells in the redundant memory array are used for replacing the failed memory cells in the main memory array for data storage.
The at least one antifuse device constitutes a non-volatile programmable module that can be programmed by performing a breakdown operation on the fuse device to change the state of the corresponding antifuse device. By programming the programmable module, the related information of the failed memory cell in the main memory array can be recorded, for example, the related information of the address of the failed memory cell can be recorded; information on a redundant memory cell for storing data in place of the failed memory cell may be recorded, and may be information on an address of the redundant memory cell, for example. After the chip is powered on, the information recorded in the programmable module can be read firstly, the related information of the failed storage unit and the redundant storage unit is obtained, and then data storage or reading operation is carried out, so that the storage defect caused by the failed storage unit is repaired.
The utility model discloses a specific embodiment's anti-fuse device is at the in-process that carries out the programming, and resistance when puncturing the gate dielectric layer is less, under the condition of same programming voltage, can form bigger programming current, consequently can suitably reduce programming voltage, reduces the consumption, improves programming efficiency.
Please refer to fig. 5 to 8, which are schematic structural diagrams illustrating a chip forming process according to an embodiment of the present invention.
Referring to fig. 5, a substrate 200 is provided, the substrate 200 includes a memory region II and a peripheral region I.
The chip can be a memory chip, and the memory can be various types of memories such as an SRAM memory, a DRAM memory or an MRAM memory. In this embodiment, the memory chip is a DRAM memory chip.
The storage region II of the substrate 200 is used to form a storage array, which includes a main storage array and a redundant storage array, and a redundant storage unit in the redundant storage array is used to replace a failed storage unit for data storage when the storage unit in the main storage array fails.
The peripheral region I is used to form a peripheral control circuit. In this particular embodiment, the peripheral region I is used to form an antifuse device, which is used to repair a memory. And other peripheral transistors of a peripheral control circuit are formed on the peripheral area I.
Shallow trench isolation structures 201 are also formed in the substrate 200 as isolation structures between active regions. The anti-fuse device, the peripheral circuit transistor and the memory array are all formed on the active region.
In this embodiment, two word lines 211 of the memory cell and a gate dielectric layer 212 between the word lines and the substrate 200 are formed in the active region of the memory region II of the substrate 200. The word line 211 is buried in the active region of the memory region II, crossing the active region. The memory region II also has a drain 214 located between adjacent word lines 211 and two source 213 located at the other side of the word lines 211.
In other specific embodiments, memory cells with other structures may also be formed in the memory region II. The memory region II may also be formed with other semiconductor device structures before forming the bit lines of the memory array.
Referring to fig. 6, a gate 222 of the antifuse device and a gate 232 of the peripheral transistor are formed in a peripheral region I, and a bit line 215 of the memory array is formed in a memory region II.
Before the specific formation of the gate electrode 232 and the gate electrode 222, a gate dielectric material layer covering the surface of the peripheral region I is further formed.
In this embodiment, the forming of the gate 232, the gate 222 and the bit line 215 simultaneously includes: a gate material layer is formed on the peripheral region I and the memory region II, and the gate 232, the gate 222, and the bit line 215 are respectively formed by patterning the gate material layer. And etching the gate dielectric material layer while forming the gate electrode 232 and the gate electrode 222, and forming a gate dielectric layer 231 below the gate electrode 232 and a gate dielectric layer 221 below the gate electrode 222. The bit line 215 is located at the surface of the drain 214.
The gate dielectric layer 221 and the gate electrode 222 cover a part of the active region and a part of the isolation region 201, and only one side of the gate electrode 222 is exposed out of a part of the active region for forming the anti-fuse device.
In other embodiments, the gate on the peripheral region I and the bit line on the storage region II can be formed separately.
After the gate 232 and the gate 222 are formed, lightly doped ion implantation may be performed on the peripheral region I by using the gate 232 and the gate 222 as masks to form a lightly doped region 233 of the peripheral circuit transistor, and a lightly doped region 223 is also formed on one side of the gate 222. In the process of performing the lightly doped ion implantation, a protective layer may also be formed on the storage region II to avoid performing the ion implantation on the active region of the storage region II.
Referring to fig. 7, spacers 224 are formed on both sides of the gate 222 of the antifuse device, spacers 234 are formed on both sides of the gate 232 of the peripheral circuit transistor, and spacers 216 are formed on both sides of the bit line 215.
The side walls 234, 224 and 216 are formed simultaneously, and the specific method includes: forming a side wall material layer covering the peripheral region I and the storage region II, wherein the side wall material layer covers the top and the side wall of the gate 222, the gate 232 and the bit line 215; and etching the side wall material layer by using a maskless etching process, removing the side wall material layer positioned on the tops of the gate 222, the gate 232 and the bit line 215 and on the surface of the substrate 200, and forming a side wall 224 covering the side wall of the gate 222, a side wall 234 covering the side wall of the gate 232 and a side wall 215 covering the side wall of the bit line 215 respectively. And meanwhile, each side wall is formed, so that the process steps are reduced.
Referring to fig. 8, the sidewalls 216 and 224 (see fig. 7) on both sides of the bit line 215 and the gate 222 of the antifuse device are removed.
Since a capacitor connected to the source 213 needs to be formed above the storage region II, and an electrical connection portion needs to be formed on the surface of the source 213 to connect to a lower electrode of the capacitor, a sufficient lateral space needs to be left on the surface of the source 213, and therefore, the sidewalls on both sides of the bit line 215 need to be removed. In this embodiment, the spacers 224 on both sides of the gate 222 of the antifuse device are removed at the same time as the spacers 216 on both sides of the bit line 215 are removed, and no additional process step is required.
The method for removing the side walls 216 and 224 includes: covering a mask layer on the storage region II and the peripheral region I, and patterning the mask layer on the storage region II and the peripheral region I by using the same mask plate to expose a grid 222 of the anti-fuse device and side walls 224 at two sides of the grid, a bit line 215 of the storage region and side walls 216 at two sides of the bit line; the spacers 216 and 224 are then removed simultaneously using an anisotropic or isotropic etch process.
Referring to fig. 9, the gate 232, the sidewalls 234 on the two sides thereof, and the gate 222 are used as masks to perform heavy doping ion implantation on the peripheral region I, so as to form the source/drain 235 of the peripheral circuit transistor and the doped region 225 of the antifuse device. At least a portion of the edge of the doped region 225 is aligned with the edge of the gate 222 or is located under the gate 222.
Because the side walls on the two sides of the gate 222 of the antifuse device are removed before the heavily doped ion implantation, the formed doped region 225 completely replaces the lightly doped region 233 formed in the previous step, so that the distance between the doped region 225 and the gate 222 is shortened, the resistance on a breakdown current path is reduced, and the formed antifuse device is more easily broken down.
In the formation process of the memory, the side walls on both sides of the gate 222 of the antifuse device and the side walls 216 on both sides of the bit line 215 are removed at the same time, so that no additional process step is required to be added, and no additional ion implantation is required to be performed on the active region below the gate 222 of the antifuse device to reduce the resistance on the breakdown circuit path, so that the process step can be saved, and the antifuse device is more easily broken down.
In another embodiment, after forming the gate of the antifuse device, the gate of the peripheral circuit transistor, and the bit line of the memory array, lightly doping ions are implanted into the substrate on both sides of the gate of the peripheral region; then, forming side walls only on two sides of the peripheral circuit transistor; and then carrying out heavy doping ion implantation on the substrate of the peripheral region by taking the grid electrode of the peripheral circuit transistor, the side walls on two sides and the grid electrode of the anti-fuse device as masks to form the doped regions of the source/drain electrode and the anti-fuse device. Because the side walls are only formed on the two sides of the grid electrode of the peripheral circuit transistor, the step of removing the grid electrode of the anti-fuse device and the side walls on the two sides of the bit line is not needed, and the process steps can be further saved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A chip, comprising:
A substrate including a storage region and a peripheral region;
A memory array formed in the memory region;
At least one antifuse device formed in the peripheral region, the antifuse device for repairing memory defects caused by failed memory cells within the memory array;
the antifuse device includes:
The grid structure is positioned on the surface of the substrate and comprises a grid dielectric layer positioned on the surface of the substrate and a grid positioned on the surface of the grid dielectric layer;
And the doped region is arranged in the substrate on one side of the grid structure parallel to the surface direction of the substrate, and at least part of the edge of the doped region is aligned with the edge of the grid or positioned below the grid.
2. The chip of claim 1, wherein the memory array comprises: the storage device comprises a main storage array and a redundant storage array, wherein redundant storage units in the redundant storage array are used for replacing failed storage units in the main storage array for data storage.
3. The chip of claim 2, wherein the at least one antifuse device constitutes a programmable block for recording information about failed memory cells in the main memory array and/or redundant memory cells in a redundant memory array.
4. The chip of claim 1, wherein the substrate of the peripheral region comprises an active region and an isolation region surrounding the active region; the grid structure covers part of the active region and part of the isolation region, and only part of the active region on one side of the grid is exposed.
5. the chip of claim 1, wherein a doped well is formed in the substrate under the gate structure of the antifuse device, and the doped well is of an opposite doping type to the doped region.
6. The chip of claim 1, wherein the gate dielectric layer has a thickness of 2nm to 4 nm.
7. The chip of claim 1, wherein the chip is a memory chip, and the memory comprises any one of an SRAM memory, a DRAM memory, or an MRAM memory.
8. The chip of claim 1, wherein peripheral circuit transistors are further formed in the peripheral region.
9. The chip of claim 8, wherein the gates of the antifuse devices, the gates of the peripheral circuit transistors, and the bit lines of the memory array are at the same level.
10. The chip of claim 8, wherein sidewalls of both sides of the gate of the peripheral circuit transistor are covered with a sidewall.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113497043A (en) * | 2020-04-08 | 2021-10-12 | 长鑫存储技术有限公司 | Anti-fuse unit |
| CN113496989A (en) * | 2020-04-08 | 2021-10-12 | 长鑫存储技术有限公司 | Anti-fuse unit and anti-fuse array |
| CN114582835A (en) * | 2022-05-05 | 2022-06-03 | 长鑫存储技术有限公司 | Anti-fuse structure and manufacturing method thereof, anti-fuse array and storage device |
| WO2023245728A1 (en) * | 2022-06-24 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor, memory and operation method therefor |
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2019
- 2019-04-18 CN CN201920527670.7U patent/CN209785927U/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113497043A (en) * | 2020-04-08 | 2021-10-12 | 长鑫存储技术有限公司 | Anti-fuse unit |
| CN113496989A (en) * | 2020-04-08 | 2021-10-12 | 长鑫存储技术有限公司 | Anti-fuse unit and anti-fuse array |
| WO2021203907A1 (en) * | 2020-04-08 | 2021-10-14 | 长鑫存储技术有限公司 | Anti-fuse unit and anti-fuse array |
| WO2021203898A1 (en) * | 2020-04-08 | 2021-10-14 | 长鑫存储技术有限公司 | Anti-fuse unit |
| CN113497043B (en) * | 2020-04-08 | 2023-12-12 | 长鑫存储技术有限公司 | antifuse unit |
| US11869608B2 (en) | 2020-04-08 | 2024-01-09 | Changxin Memory Technologies, Inc. | Anti-fuse unit and anti-fuse array |
| CN113496989B (en) * | 2020-04-08 | 2024-02-09 | 长鑫存储技术有限公司 | Antifuse cell and antifuse array |
| CN114582835A (en) * | 2022-05-05 | 2022-06-03 | 长鑫存储技术有限公司 | Anti-fuse structure and manufacturing method thereof, anti-fuse array and storage device |
| CN114582835B (en) * | 2022-05-05 | 2022-07-29 | 长鑫存储技术有限公司 | Anti-fuse structure and manufacturing method thereof, anti-fuse array and storage device |
| WO2023245728A1 (en) * | 2022-06-24 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor, memory and operation method therefor |
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