WO2023209960A1 - Procédé de conception, programme de conception et procédé de production de carte de circuit imprimé - Google Patents

Procédé de conception, programme de conception et procédé de production de carte de circuit imprimé Download PDF

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Publication number
WO2023209960A1
WO2023209960A1 PCT/JP2022/019309 JP2022019309W WO2023209960A1 WO 2023209960 A1 WO2023209960 A1 WO 2023209960A1 JP 2022019309 W JP2022019309 W JP 2022019309W WO 2023209960 A1 WO2023209960 A1 WO 2023209960A1
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WO
WIPO (PCT)
Prior art keywords
resin
wiring
layer
resin laminate
image data
Prior art date
Application number
PCT/JP2022/019309
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English (en)
Japanese (ja)
Inventor
慎二 瀧川
亮二郎 富永
Original Assignee
株式会社Fuji
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社Fuji filed Critical 株式会社Fuji
Priority to PCT/JP2022/019309 priority Critical patent/WO2023209960A1/fr
Publication of WO2023209960A1 publication Critical patent/WO2023209960A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern

Definitions

  • the present invention relates to a method for designing a plurality of resin layers of a circuit board manufactured by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers. Regarding.
  • the following patent document describes a technique for manufacturing a circuit board by forming wiring on the upper surface of a resin layer.
  • An object of the present invention is to appropriately produce a circuit board by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers.
  • the present specification provides a circuit board that is manufactured by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers.
  • a method for designing the plurality of resin layers the method of designing the plurality of resin layers by generating image data showing at least the plurality of resin layers at locations that support and cover wiring.
  • the present specification is produced by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers.
  • a design program for designing the plurality of resin layers of a circuit board is disclosed, the design program generating image data showing at least the plurality of resin layers at locations that support and cover wiring.
  • the present specification provides a circuit board by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers.
  • a circuit board manufacturing method in which the plurality of resin layers are formed at locations that support and cover wiring.
  • image data is generated that shows at least a plurality of resin layers that support and cover the wiring.
  • a plurality of resin layers are formed at locations that support and cover the wiring. This makes it possible to appropriately manufacture the circuit board.
  • FIG. 2 is a block diagram showing a control device.
  • FIG. 2 is a cross-sectional view showing a circuit in a state where a first layer of resin laminate is formed.
  • FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on the first layer of the resin laminate.
  • FIG. 3 is a cross-sectional view showing the circuit in a state where a second layer of resin laminate is formed.
  • FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on a second layer of resin laminate.
  • FIG. 7 is a cross-sectional view showing the circuit in a state where a third layer of resin laminate is formed.
  • FIG. 1 is a block diagram showing a control device.
  • FIG. 2 is a cross-sectional view showing a circuit in a state where a first layer of resin laminate is formed.
  • FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on the first layer of the resin laminate.
  • FIG. 3
  • FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on a third layer of resin laminate.
  • FIG. 7 is a cross-sectional view showing the circuit in a state where a fourth layer of resin laminate is formed.
  • FIG. 7 is a cross-sectional view showing a circuit in which wiring is formed on a fourth layer of the resin laminate.
  • FIG. 7 is a cross-sectional view showing a circuit in a state where a fifth layer of resin laminate is formed.
  • FIG. 2 is a cross-sectional view showing a circuit in which a conductive resin paste is applied to the ends of the wiring.
  • FIG. 7 is a cross-sectional view showing a circuit in which electronic components are mounted in cavities of a fifth layer of resin laminate.
  • FIG. 3 is a diagram showing a circuit pattern and electronic components. It is a figure which shows the resin laminated body designed based on the circuit pattern of the lowest layer. It is a figure which shows the resin laminated body designed based on the circuit pattern of the second layer from the bottom. It is a figure which shows the resin laminated body designed based on the circuit pattern of the third layer from the bottom. It is a figure which shows the resin laminated body designed based on the circuit pattern of an uppermost layer.
  • FIG. 3 is a diagram showing a circuit board including a resin laminate designed by a first design program. It is a figure which shows the flowchart of a 2nd design program.
  • FIG. 7 is a diagram showing a circuit board including a resin laminate designed by a second design program.
  • FIG. 1 shows a circuit forming apparatus 10.
  • the circuit forming apparatus 10 includes a transport device 20, a first modeling unit 22, a second modeling unit 24, a third modeling unit 25, a mounting unit 27, and a control device (see FIG. 2) 28.
  • the transport device 20 , the first modeling unit 22 , the second modeling unit 24 , the third modeling unit 25 , and the mounting unit 27 are arranged on the base 29 of the circuit forming apparatus 10 .
  • the base 29 has a generally rectangular shape, and in the following description, the longitudinal direction of the base 29 is the X-axis direction, the short direction of the base 29 is the Y-axis direction, and it is perpendicular to both the X-axis direction and the Y-axis direction. The direction will be described as the Z-axis direction.
  • the transport device 20 includes an X-axis slide mechanism 30 and a Y-axis slide mechanism 32.
  • the X-axis slide mechanism 30 includes an X-axis slide rail 34 and an X-axis slider 36.
  • the X-axis slide rail 34 is arranged on the base 29 so as to extend in the X-axis direction.
  • the X-axis slider 36 is held by the X-axis slide rail 34 so as to be slidable in the X-axis direction.
  • the X-axis slide mechanism 30 includes an electromagnetic motor (see FIG. 2) 38, and the X-axis slider 36 is moved to any position in the X-axis direction by driving the electromagnetic motor 38.
  • the Y-axis slide mechanism 32 includes a Y-axis slide rail 50 and a stage 52.
  • the Y-axis slide rail 50 is disposed on the base 29 so as to extend in the Y-axis direction, and is movable in the X-axis direction.
  • One end of the Y-axis slide rail 50 is connected to the X-axis slider 36.
  • a stage 52 is held on the Y-axis slide rail 50 so as to be slidable in the Y-axis direction.
  • the Y-axis slide mechanism 32 includes an electromagnetic motor (see FIG. 2) 56, and the stage 52 is moved to an arbitrary position in the Y-axis direction by driving the electromagnetic motor 56. Thereby, the stage 52 is moved to an arbitrary position on the base 29 by driving the X-axis slide mechanism 30 and the Y-axis slide mechanism 32.
  • the stage 52 has a base 60, a holding device 62, and a lifting device 64.
  • the base 60 is formed into a flat plate shape, and a substrate is placed on the top surface.
  • the holding device 62 is provided on both sides of the base 60 in the X-axis direction. Then, both edges of the substrate placed on the base 60 in the X-axis direction are held between the holding devices 62, so that the substrate is fixedly held. Further, the lifting device 64 is disposed below the base 60 and raises and lowers the base 60.
  • the first modeling unit 22 is a unit that models wiring on a substrate placed on the base 60 of the stage 52, and includes a first printing section 72 and a firing section 74.
  • the first printing section 72 has an inkjet head (see FIG. 2) 76, and the inkjet head 76 discharges metal ink in a linear manner.
  • Metal ink is made by dispersing nanometer-sized metal particles, such as silver, in a solvent. Note that the surface of the metal fine particles is coated with a dispersant to prevent agglomeration in the solvent. Further, the inkjet head 76 ejects metal ink from a plurality of nozzles using a piezo system using piezoelectric elements, for example.
  • the baking section 74 has an infrared irradiation device (see FIG. 2) 78.
  • the infrared irradiation device 78 is a device that irradiates the ejected metal ink with infrared rays.
  • the metal ink irradiated with infrared rays is fired and wiring is formed.
  • firing metal ink means that energy is applied to vaporize the solvent and decompose the protective film of the metal particles, that is, the dispersant, etc., and the metal particles contact or fuse to form a conductive layer. This is a phenomenon where the rate increases.
  • metal wiring is formed by firing the metal ink.
  • the second modeling unit 24 is a unit that models a resin layer on the substrate placed on the base 60 of the stage 52, and includes a second printing section 84 and a curing section 86.
  • the second printing section 84 has an inkjet head (see FIG. 2) 88, and the inkjet head 88 discharges ultraviolet curing resin.
  • Ultraviolet curable resin is a resin that is cured by irradiation with ultraviolet rays.
  • the inkjet head 88 may be of a piezo type using a piezoelectric element, for example, or may be a thermal type of heating resin to generate bubbles and ejecting the bubbles from a plurality of nozzles.
  • the curing section 86 includes a flattening device (see FIG. 2) 90 and an irradiation device (see FIG. 2) 92.
  • the flattening device 90 flattens the upper surface of the ultraviolet curable resin discharged by the inkjet head 88, and for example, scrapes off excess resin with a roller or blade while leveling the surface of the ultraviolet curable resin. to make the thickness of the ultraviolet curing resin uniform.
  • the irradiation device 92 includes a mercury lamp or an LED as a light source, and irradiates the discharged ultraviolet curing resin with ultraviolet rays. As a result, the discharged ultraviolet curing resin is cured and a resin layer is formed.
  • the third molding unit 25 is a unit that molds connection parts between electrodes and wiring of electronic components on a substrate placed on a base 60 of the stage 52, and includes a third printing part 100 and a first heating part. 102.
  • the third printing unit 100 has a dispenser (see FIG. 2) 106, and the dispenser 106 dispenses a conductive resin paste.
  • the conductive resin paste is made by dispersing micrometer-sized metal particles in a resin that hardens by heating at a relatively low temperature. Incidentally, the metal particles are in the form of flakes, and the viscosity of the conductive resin paste is relatively high compared to the metal ink.
  • the first heating section 102 has a heater (see FIG. 2) 108.
  • the heater 108 is a device that heats the conductive resin paste applied by the dispenser 106. In the heated conductive resin paste, the resin hardens. At this time, in the conductive resin paste, the resin hardens and contracts, and the flaky metal particles dispersed in the resin come into contact with each other. Thereby, the conductive resin paste exhibits conductivity. Further, the resin of the conductive resin paste is an organic adhesive, and exhibits adhesive strength by being cured by heating.
  • the mounting section 122 includes a mounting head (see FIG. 2) 126 and a moving device (see FIG. 2) 128.
  • the mounting head 126 has a suction nozzle (not shown) for suctioning and holding the electronic component.
  • the suction nozzle is supplied with negative pressure from a positive and negative pressure supply device (not shown), and suctions and holds the electronic component by suctioning air. Then, by supplying a slight positive pressure from the positive/negative pressure supply device, the electronic component is detached.
  • the moving device 128 moves the mounting head 126 between the position where the electronic components are supplied by the tape feeder 124 and the substrate placed on the base 60. Thereby, in the mounting section 122, the electronic component supplied from the tape feeder 124 is held by the suction nozzle, and the electronic component held by the suction nozzle is mounted on the board.
  • control device 28 includes a controller 130 and a plurality of drive circuits 132, as shown in FIG.
  • the plurality of drive circuits 132 include the electromagnetic motors 38 and 56, a holding device 62, a lifting device 64, an inkjet head 76, an infrared irradiation device 78, an inkjet head 88, a flattening device 90, an irradiation device 92, a dispenser 106, a heater 108, It is connected to a tape feeder 124, a mounting head 126, and a moving device 128.
  • the controller 130 is mainly a computer, including a CPU, ROM, RAM, etc., and is connected to a plurality of drive circuits 132. As a result, the operations of the transport device 20 , the first modeling unit 22 , the second modeling unit 24 , the third modeling unit 25 , and the mounting unit 27 are controlled by the controller 130 .
  • circuit forming apparatus 10 With the above-described configuration, a plurality of resin laminates are stacked on the base 60, and wiring is formed on the upper surface of each resin laminate. Then, the electrodes of the electronic component are electrically connected to the wiring via the conductive resin paste, thereby forming a circuit board.
  • the stage 52 is moved below the second modeling unit 24. Then, in the second modeling unit 24, as shown in FIG. 3, a resin laminate 150 is formed on the base 60 of the stage 52.
  • the resin laminate 150 is formed by repeatedly ejecting the ultraviolet curable resin from the inkjet head 88 and irradiating the ejected ultraviolet curable resin with ultraviolet rays by the irradiation device 92.
  • the inkjet head 88 discharges ultraviolet curing resin in a thin film onto the upper surface of the base 60. Subsequently, when the ultraviolet curable resin is discharged in the form of a thin film, the ultraviolet curable resin is flattened by a flattening device 90 in the curing section 86 so that the thickness of the ultraviolet curable resin becomes uniform. Then, the irradiation device 92 irradiates the thin film of ultraviolet curing resin with ultraviolet rays. As a result, a thin film-like resin layer 152 is formed on the base 60.
  • the inkjet head 88 discharges a thin film of ultraviolet curing resin onto the thin film resin layer 152.
  • the thin film-like ultraviolet curable resin is flattened by the flattening device 90, and the irradiation device 92 irradiates the ultraviolet rays onto the thin film-like ultraviolet curable resin, thereby forming a layer on the thin film-like resin layer 152.
  • a thin film-like resin layer 152 is laminated.
  • the resin laminate 150 is formed by repeating the discharging of the ultraviolet curable resin onto the thin film-like resin layer 152 and the irradiation of ultraviolet rays, and by stacking a plurality of resin layers 152.
  • the stage 52 is moved below the first modeling unit 22. Then, in the first printing section 72 of the first modeling unit 22, the inkjet head 76 discharges the metal ink 154 linearly onto the upper surface of the resin laminate 150 according to the circuit pattern, as shown in FIG. Subsequently, in the firing section 74 of the first modeling unit 22, the infrared ray irradiation device 78 irradiates the metal ink 154 ejected according to the circuit pattern with infrared rays. As a result, the metal ink 154 is fired, and the wiring 156 is formed on the resin laminate 150.
  • a second layer resin laminate 160 is formed on the resin laminate 150.
  • the resin laminate 160 is formed to cover the wiring 156 formed on the upper surface of the resin laminate 150.
  • the resin laminate 160 is formed by repeatedly discharging an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92. Further, the outer dimensions of the resin laminate 160 are the same as the outer dimensions of the resin laminate 150.
  • the stage 52 is moved below the first modeling unit 22.
  • the inkjet head 76 discharges the metal ink 162 linearly onto the upper surface of the resin laminate 160 according to the circuit pattern, as shown in FIG.
  • the infrared rays irradiation device 78 irradiates the metal ink 162 with infrared rays in the baking section 74 of the first modeling unit 22, thereby baking the metal ink 162 and forming the wiring 164 on the resin laminate 160.
  • the stage 52 is moved below the second modeling unit 24.
  • a third layer resin laminate 170 is formed on the resin laminate 160, as shown in FIG.
  • the resin laminate 170 is formed to cover the wiring 164 formed on the upper surface of the resin laminate 160.
  • the resin laminate 170 is also formed by repeatedly discharging an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92.
  • the outer dimensions of the resin laminate 170 are also the same as the outer dimensions of the resin laminate 150.
  • the stage 52 is moved below the first modeling unit 22.
  • the inkjet head 76 discharges the metal ink 172 linearly onto the upper surface of the resin laminate 170 according to the circuit pattern, as shown in FIG.
  • the infrared irradiation device 78 irradiates the metal ink 172 with infrared rays in the baking section 74 of the first modeling unit 22, thereby baking the metal ink 172 and forming the wiring 174 on the resin laminate 170. Ru. Note that two wirings 174 are formed on the resin laminate 170.
  • a fourth resin laminate 180 is formed on the resin laminate 170.
  • the resin laminate 180 is formed to cover the two wirings 174 formed on the upper surface of the resin laminate 170.
  • the resin laminate 180 is also formed by repeatedly ejecting an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92.
  • the outer dimensions of the resin laminate 180 are also the same as the outer dimensions of the resin laminate 150.
  • the stage 52 is moved below the first modeling unit 22.
  • the inkjet head 76 discharges the metal ink 182 linearly onto the upper surface of the resin laminate 180 according to the circuit pattern, as shown in FIG.
  • the infrared irradiation device 78 irradiates the metal ink 182 with infrared rays in the baking section 74 of the first modeling unit 22, thereby baking the metal ink 182 and forming the wiring 184 on the resin laminate 180. Ru. Note that three wirings 184 are formed on the resin laminate 180.
  • a fifth layer resin laminate 190 is formed on the resin laminate 180.
  • the resin laminate 190 is formed so as to cover the three wirings 184 formed on the upper surface of the resin laminate 180.
  • a cavity 192 is formed in which mutually opposing ends of are exposed.
  • the resin laminate 190 is also formed by repeatedly ejecting an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92.
  • the outer dimensions of the resin laminate 190 are also the same as the outer dimensions of the resin laminate 150.
  • the stage 52 is moved below the third modeling unit 25.
  • the dispenser 106 applies a conductive resin paste 196 onto the ends of the two wirings 184 exposed inside the cavity 192, as shown in FIG. Exhale.
  • the conductive resin paste 196 is heated by the heater 108, so that the conductive resin paste 196 exhibits conductivity.
  • the stage 52 is moved below the mounting unit 27.
  • an electronic component (see FIG. 13) is supplied by a tape feeder 124, and the electronic component 200 is held by a suction nozzle of a mounting head 126.
  • the electronic component 200 includes a component body 202 and two leads 204 extending downward from a pair of opposing side surfaces of the component body 202.
  • the mounting head 126 is moved by the moving device 128, and the electronic component 200 held by the suction nozzle is mounted on the upper surface of the resin laminate 180 inside the cavity 192, as shown in FIG.
  • the electronic component 200 is mounted so that the leads 204 of the electronic component 200 come into contact with the conductive resin paste 196 discharged onto the wiring 184.
  • the circuit board 210 is made up of five layers of resin laminates 150, 160, 170, 180, and 190 having the same dimensions, but in recent years, it has been desired to reduce the weight of the circuit board. That is, for example, when a circuit board is disposed on a robot hand, it is desired to reduce the weight of the circuit board from the viewpoint of improving the moving speed of the robot hand and controlling vibration damping.
  • circuit board when a circuit board is installed in a drone, a radio control device, etc., it is desired that the circuit board be made lighter so that it can operate for a long time with a single charge.
  • the circuit forming apparatus 10 it is possible to form a resin laminate having an arbitrary shape by discharging the ultraviolet curing resin at an arbitrary position.
  • a plurality of resin laminates are formed only at locations that support and cover the wiring, rather than stacking a plurality of resin laminates having the same dimensions.
  • the controller 130 of the control device 28 stores a first design program 220 and a second design program 222. Then, each of the first design program 220 and the second design program 222 designs a plurality of resin laminates for locations that support and cover the wiring and locations that support electronic components connected to the wiring.
  • a plurality of resin laminates are designed sequentially from the lower resin laminate to the upper resin laminate.
  • the first design program 220 adds a resin laminate to a location that supports the wiring and a location that covers the wiring, and also adds a resin laminate to a location that supports the electronic component connected to the wiring. Image data showing a plurality of resin laminates is generated.
  • a design of a circuit pattern and a design of a mounting position of an electronic component are performed (S10).
  • the design of the circuit pattern and the design of the mounting position of the electronic components are performed according to the functions of the circuit board, etc., and are designed in the same manner as in the conventional method.
  • a four-layer circuit pattern is designed as shown in FIG. A placement position for the component 200 is designed.
  • a plurality of resin laminates 150, 160, 170, 180, and 190 having the same dimensions are stacked to support all the wiring, as in the circuit board 210 shown in FIG. Image data of the covering resin laminate was also generated.
  • the first design program 220 a plurality of resin laminates are designed sequentially from the lower resin laminate to the upper resin laminate. Image data of the resin laminate is generated such that the resin laminate is added to the area covering the wiring. Further, when an electronic component is connected to the wiring, image data of the resin laminate is generated so that the resin laminate is also added to a location that supports the electronic component.
  • the image data of the resin laminate is created by adding the necessary resin laminate based on the lowest circuit pattern of the four-layer circuit pattern designed in S10 and the mounting position of the electronic component. is generated (S12). Note that no electronic component is connected to the wiring 156 corresponding to the circuit pattern in the lowest layer among the four layers of circuit patterns, that is, the circuit pattern in the first layer from the bottom. For this reason, image data is created such that the resin laminate is added to a location that supports the wiring 156 and a location that covers the wiring 156 according to the first layer circuit pattern. Specifically, as shown in FIG. 16, image data of the resin laminate at a location 230a that supports the wiring 156 and a location 230b that covers the wiring 156 is generated.
  • image data when image data is generated, not only the area directly below the wiring that supports the wiring and the area directly above the wiring that covers the wiring, but also the part that supports and covers the area that is a preset dimension and away from the end of the wiring. Image data of the resin laminate including the location is generated.
  • the first design program 220 it is determined whether the image data of the resin laminate has been generated based on the circuit pattern of the uppermost layer in the process in S12 (S14). That is, it is determined whether the image data of the resin laminate has been generated based on the circuit patterns of all the layers.
  • S14 since the image data of the resin laminate is generated based on the circuit pattern of the first layer, it is determined that the image data of the resin laminate is not generated based on the circuit pattern of the top layer. (S14: NO). Then, image data of the resin laminate is generated by adding the necessary resin laminate based on the circuit pattern on the upper layer and the placement position of the electronic component (S16).
  • image data of the resin laminate is generated by adding the necessary resin laminate based on the circuit pattern of the second layer and the mounting position of the electronic component.
  • image data is created such that the resin laminate is added to a location that supports the wiring 164 and a location that covers the wiring 164 according to the second layer circuit pattern.
  • image data of the resin laminate of the portion 232a that supports the wiring 164 and the portion 232b that covers the wiring 164 is generated.
  • the image data of the resin laminate at the portion 232a that supports the wiring 164 is the image data of the resin laminate only at a portion that is different from the previously generated image data of the resin laminate. That is, image data of the resin laminate at the location 232a that supports the wiring 164 is generated, excluding the resin laminate at the location 230 that is generated based on the wiring 156.
  • image data is created such that the resin laminate is added to a location that supports the wiring 174 and a location that covers the wiring 174 according to the third layer circuit pattern.
  • image data of the resin laminate of the portion 234a that supports the wiring 174 and the portion 234b that covers the wiring 174 is generated.
  • the image data of the resin laminate at the portion 234a that supports the wiring 174 is the image data of the resin laminate only at a portion that is different from the previously generated image data of the resin laminate. That is, image data of the resin laminate at the location 234a that supports the wiring 174 is generated, excluding the resin laminate at the location 232 that is generated based on the wiring 164.
  • image data is created such that the resin laminate is added to a location that supports the wiring 184 according to the fourth layer circuit pattern, a location that covers the wiring 184, and a location that supports the electronic component 200.
  • image data of the resin laminate of a portion 236a that supports the wiring 184 and the electronic component 200 and a portion 236b that covers the wiring 184 is generated.
  • the image data of the resin laminate at the portion 236a that supports the wiring 184 and the electronic component 200 is the image data of the resin laminate only at a portion that is different from the previously generated image data of the resin laminate.
  • image data of the resin laminate at the location 236a that supports the wiring 184 and the electronic component 200 is generated, excluding the resin laminate at the location 234 that is generated based on the wiring 174. Further, the image data of the resin laminate at the portion 236b covering the wiring 184 is generated excluding the cavity 192 for mounting the electronic component 200.
  • image data of the resin laminate at locations 230, 232, 234, and 236 is generated based on the wiring according to the circuit pattern of each layer and the electronic components connected to the wiring. Then, when a resin laminate is formed based on the generated image data, a circuit board 260 made up of the five layers of resin laminates 250 to 254 is formed, as shown in FIG. In other words, when the resin laminate is formed based on the image data generated by the first design program 220, the circuit board 260 has the resin laminate formed only in areas that support wiring and electronic components and areas that cover the wiring. is formed.
  • the second design program 222 a plurality of resin laminates are designed sequentially from the upper resin laminate to the lower resin laminate.
  • the second design program 222 identifies parts unnecessary for supporting and covering the wiring from virtual images (hereinafter referred to as "virtual images") of the plurality of resin laminates designed using the conventional method.
  • Image data showing a plurality of resin laminates is generated by deleting portions unnecessary for supporting electronic components.
  • the virtual image is an image of a plurality of resin laminates designed using a conventional method, and is an image of five resin laminates 150, 160, 170, 180, and 190 that constitute the circuit board 210 in FIG. be.
  • the virtual image shows a resin laminate that supports and covers all the wiring 156, 164, 174, 184 of the circuit board 210 by laminating five resin laminates of the same size, and supports all the electronic components 200. It is an image of the body.
  • a design of a circuit pattern and a design of a mounting position of an electronic component are performed (S20).
  • the design of the circuit pattern and the design of the mounting position of the electronic component in the second design program 222 are the same as the design of the circuit pattern and the design of the mounting position of the electronic component in the first design program 220. For this reason, for example, when designing the circuit pattern of a circuit board with the same functions as the circuit board 210 in FIG. 13 and the mounting position of electronic components, a four-layer circuit pattern is designed as shown in FIG. A placement position for electronic component 200 is designed.
  • the virtual image is an image of the five layers of resin laminates 150, 160, 170, 180, and 190 that constitute the circuit board 210, so as shown in FIG. Designed. Note that when distinguishing each of the five layers of virtual images 270, in order from the upper virtual image, the first layer virtual image 270a, the second layer virtual image 270b, the third layer virtual image 270c, and the fourth layer virtual image A virtual image 270d of the fifth layer and a virtual image 270e of the fifth layer.
  • a portion 280 that is unnecessary for covering the wiring 184 is identified from the range of the uppermost layer virtual image 270a.
  • the unnecessary portions for covering the wiring are the portions where the wiring is not covered, and are not only the portions where the wiring is not covered but also the portions which are separated by a predetermined dimension from the end of the wiring. Then, when a portion 280 unnecessary for covering the wiring 184 is identified, the portion 280 unnecessary for covering the wiring 184 is deleted from the virtual image 270a of the uppermost layer, and as shown in FIG. Image data of the body 300 is generated.
  • the second design program 222 it is determined whether the image data of the resin laminate has been generated based on the virtual image 270e of the lowest layer in the process in S24 (S26). That is, it is determined whether image data of the resin laminate has been generated based on the virtual images 270 of all layers.
  • the image data of the resin laminate is generated based on the virtual image 270a of the top layer, that is, the first layer, the image data of the resin laminate is generated based on the virtual image 270e of the bottom layer. is determined to have not been generated (S26: NO).
  • the image data of the resin laminate is created by deleting parts unnecessary for supporting and covering the wiring and parts unnecessary for supporting the electronic components from the lower virtual image 270, that is, the second layer virtual image 270b. is generated (S28).
  • the virtual image 270b of the second layer based on the circuit pattern of the top layer and the wirings 174, 184 and the electronic component 200 according to the circuit pattern of the second layer, parts unnecessary for supporting and covering the wiring and electronic parts are removed. Locations that are unnecessary for supporting the component are identified. Specifically, as shown in FIG. 24, a location 282 that is unnecessary for supporting the wiring 184 and the electronic component 200 and unnecessary for covering the wiring 174 is identified from the range of the second layer virtual image 270b.
  • a location unnecessary for supporting the wiring is a location that does not support the wiring, but is also a location that does not support not only the wiring but also a location that is a predetermined distance away from the end of the wiring.
  • locations that are unnecessary for supporting electronic components are locations other than directly below the electronic components, but are not limited to locations that are not just directly below the electronic components, but also locations that are a preset distance from the edge of the electronic components, excluding locations directly below the electronic components. It is. Then, when a portion 282 that is unnecessary for supporting the wiring 184 and the electronic component 200 and is unnecessary for covering the wiring 174 is specified, the unnecessary portion 282 is deleted from the second layer virtual image 270b and shown in FIG. As shown, image data of the second layer resin laminate 302 is generated.
  • the third layer virtual image 270c wiring is performed based on the wiring 164, 174, 184 and the electronic component 200 according to the circuit patterns of three layers from the top layer circuit pattern to the third layer circuit pattern. Areas unnecessary for supporting and covering electronic components and areas unnecessary for supporting electronic components are identified. Specifically, as shown in FIG. 25, a portion 284 that is unnecessary for supporting the wirings 174, 184 and the electronic component 200 and unnecessary for covering the wiring 164 is identified from the range of the third layer virtual image 270c. .
  • the fourth layer virtual image 270d based on the wirings 156, 164, 174, 184 and the electronic component 200 according to the circuit patterns for four layers from the top layer circuit pattern to the fourth layer circuit pattern. , locations unnecessary for supporting and covering wiring and locations unnecessary for supporting electronic components are identified. Specifically, locations that are unnecessary for supporting the wirings 164, 174, 184 and the electronic component 200, and unnecessary for covering the wiring 156 are identified from the range of the fourth layer virtual image 270d. However, within the range of the fourth layer virtual image 270d, there are no locations that are unnecessary for supporting the wirings 164, 174, 184 and the electronic component 200, and are unnecessary for covering the wiring 156. Therefore, no portion is deleted from the fourth layer virtual image 270d, and image data of the fourth layer resin laminate 306 is generated at the same position as the fourth layer virtual image 270d.
  • the virtual image 270e of the fifth layer based on the wirings 156, 164, 174, 184 and the electronic component 200 according to the circuit patterns of four layers from the circuit pattern of the top layer to the circuit pattern of the fourth layer. , locations unnecessary for supporting and covering wiring and locations unnecessary for supporting electronic components are identified. Specifically, locations unnecessary for supporting the wirings 156, 164, 174, 184 and the electronic component 200 are identified from the range of the fifth layer virtual image 270e. However, within the range of the fifth layer virtual image 270e, there are no locations unnecessary for supporting the wirings 156, 164, 174, 184 and the electronic component 200. Therefore, no portion is deleted from the fifth layer virtual image 270e, and image data of the fifth layer resin laminate 308 is generated at the same position as the fifth layer virtual image 270e.
  • image data of a plurality of resin laminates are generated by deleting portions unnecessary for supporting and covering wiring and portions unnecessary for supporting electronic components from the virtual image 270 of each layer. Then, when a resin laminate is formed based on the generated image data, a circuit board 310 made up of the five layers of resin laminates 300 to 308 is formed, as shown in FIG. In other words, when a resin laminate is formed based on the image data generated by the second design program 222, the resin laminate is formed in areas unnecessary for supporting wiring and electronic components and areas unnecessary for covering wiring from the virtual image. is removed, and a circuit board 310 is formed in which the resin laminate is formed only at locations that support the wiring and electronic components and locations that cover the wiring. Note that the circuit board 260 and the circuit board 310 have substantially the same shape. In other words, the image data of the resin laminate generated by the first design program 220 and the image data of the resin laminate generated by the second design program 222 are approximately the same.
  • the time required to form resin laminates can be shortened, and the material of resin laminates can be reduced. It is also possible to reduce the amount of water used. Furthermore, since the image data of the resin laminate is generated by the first design program 220 or the second design program 222, it is possible to reduce the time required to design the circuit board.
  • the wirings 156, 164, 174, and 184 are examples of wirings.
  • Electronic component 200 is an example of an electronic component.
  • the first design program 220 is an example of a design program.
  • the second design program 222 is an example of a design program.
  • the resin laminates 250, 251, 252, 253, and 254 are examples of resin layers.
  • Circuit board 260 is an example of a circuit board.
  • Virtual image 270 is an example of a virtual image.
  • the resin laminates 300, 302, 304, 306, and 308 are examples of resin layers.
  • Circuit board 310 is an example of a circuit board.
  • the present invention is not limited to the above-mentioned embodiments, but can be implemented in various forms with various modifications and improvements based on the knowledge of those skilled in the art.
  • the first design program 220 and the second design program 222 are stored in the control device 28 of the circuit forming apparatus 10, but the The first design program 220 and the second design program 222 may be stored in the information processing device.
  • an ultraviolet curable resin is used as the curable resin for forming the resin laminate, but it is possible to use various resins such as thermosetting resins and two-component mixed resins. It is.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

La présente invention concerne un procédé de conception pour une pluralité de couches de résine d'une carte de circuit imprimé formée par l'empilement d'une pluralité de couches de résine et la formation d'une ligne de câblage sur la surface supérieure d'au moins une couche de résine parmi la pluralité de couches de résine. Ce procédé de conception permet de concevoir la pluralité de couches de résine en produisant des données d'image qui montrent au moins la pluralité de couches de résine dans des positions où la ligne de câblage est supportée et recouverte.
PCT/JP2022/019309 2022-04-28 2022-04-28 Procédé de conception, programme de conception et procédé de production de carte de circuit imprimé WO2023209960A1 (fr)

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PCT/JP2022/019309 WO2023209960A1 (fr) 2022-04-28 2022-04-28 Procédé de conception, programme de conception et procédé de production de carte de circuit imprimé

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PCT/JP2022/019309 WO2023209960A1 (fr) 2022-04-28 2022-04-28 Procédé de conception, programme de conception et procédé de production de carte de circuit imprimé

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004064039A (ja) * 2002-06-07 2004-02-26 Fuji Photo Film Co Ltd パターン形成方法及びパターン形成装置
JP2006024768A (ja) * 2004-07-08 2006-01-26 Seiko Epson Corp 配線基板、配線基板の製造方法および電子機器
WO2019171531A1 (fr) * 2018-03-08 2019-09-12 株式会社Ｆｕｊｉ Dispositif de traitement d'informations

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004064039A (ja) * 2002-06-07 2004-02-26 Fuji Photo Film Co Ltd パターン形成方法及びパターン形成装置
JP2006024768A (ja) * 2004-07-08 2006-01-26 Seiko Epson Corp 配線基板、配線基板の製造方法および電子機器
WO2019171531A1 (fr) * 2018-03-08 2019-09-12 株式会社Ｆｕｊｉ Dispositif de traitement d'informations

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