WO2021214813A1 - Procédé de formation de circuit et dispositif de formation de circuit - Google Patents

Procédé de formation de circuit et dispositif de formation de circuit Download PDF

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Publication number
WO2021214813A1
WO2021214813A1 PCT/JP2020/017010 JP2020017010W WO2021214813A1 WO 2021214813 A1 WO2021214813 A1 WO 2021214813A1 JP 2020017010 W JP2020017010 W JP 2020017010W WO 2021214813 A1 WO2021214813 A1 WO 2021214813A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic component
resin
base material
wiring
cavity
Prior art date
Application number
PCT/JP2020/017010
Other languages
English (en)
Japanese (ja)
Inventor
亮二郎 富永
Original Assignee
株式会社Fuji
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社Fuji filed Critical 株式会社Fuji
Priority to JP2022516470A priority Critical patent/JPWO2021214813A1/ja
Priority to PCT/JP2020/017010 priority patent/WO2021214813A1/fr
Publication of WO2021214813A1 publication Critical patent/WO2021214813A1/fr

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits

Definitions

  • the mounting unit 112 has a mounting head (see FIG. 2) 116 and a moving device (see FIG. 2) 118.
  • the mounting head 116 has a suction nozzle (not shown) for sucking and holding an electronic component (see FIG. 11) 119.
  • the suction nozzle sucks and holds electronic components by sucking air by supplying negative pressure from a positive / negative pressure supply device (not shown). Then, when a slight positive pressure is supplied from the positive / negative pressure supply device, the electronic component is separated. Further, the moving device 118 moves the mounting head 116 between the supply position of the electronic component by the tape feeder 114 and the base 60. As a result, in the mounting unit 112, the electronic component supplied from the tape feeder 114 is held by the suction nozzle, and the electronic component held by the suction nozzle is mounted on the circuit board.
  • Circuit forming device 76 Inkjet head (forming device) 78: Heater (forming device) 88: Inkjet head (sealing device) 89: Dispens head (sealing device) 92: Irradiation device (sealing device) 93: Heater ( Encapsulation device) 116: Mounting head (mounting device) 118: Moving device (mounting device) 130: Resin laminate (base material) 140: Resin laminate (base material) 142: Cavity 150: Electronic parts 154: Electrodes 172: Wiring 180: Metal paste (conductive fluid) 200: Thermosetting resin 220: Forming part (forming process) 222: Coating part (coating process) 224: Mounting part (mounting process) 226: Encapsulation part (encapsulation process) 228: Sealing Stop (sealing process) 230: Flattening part (flattening process)

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

La présente invention concerne un procédé de formation de circuit qui comprend : une étape de formation destinée à former un câblage sur un substrat ; une étape de montage destinée à monter un composant électronique sur le substrat de sorte qu'une électrode soit connectée électriquement au câblage tandis que l'électrode est tournée vers le bas ; une étape de remplissage destinée à introduire une résine thermodurcissable entre le substrat et le composant électronique monté sur le substrat ; et une étape de scellement destinée à sceller le composant électronique monté sur le substrat avec une résine durcissable aux ultraviolets.
PCT/JP2020/017010 2020-04-20 2020-04-20 Procédé de formation de circuit et dispositif de formation de circuit WO2021214813A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2022516470A JPWO2021214813A1 (fr) 2020-04-20 2020-04-20
PCT/JP2020/017010 WO2021214813A1 (fr) 2020-04-20 2020-04-20 Procédé de formation de circuit et dispositif de formation de circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/017010 WO2021214813A1 (fr) 2020-04-20 2020-04-20 Procédé de formation de circuit et dispositif de formation de circuit

Publications (1)

Publication Number Publication Date
WO2021214813A1 true WO2021214813A1 (fr) 2021-10-28

Family

ID=78270903

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/017010 WO2021214813A1 (fr) 2020-04-20 2020-04-20 Procédé de formation de circuit et dispositif de formation de circuit

Country Status (2)

Country Link
JP (1) JPWO2021214813A1 (fr)
WO (1) WO2021214813A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023148888A1 (fr) * 2022-02-03 2023-08-10 株式会社Fuji Procédé de formation de circuit électrique et appareil de formation de circuit électrique

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10209217A (ja) * 1997-01-24 1998-08-07 Matsushita Electric Ind Co Ltd バンプ付きワークの実装方法
JP2010199621A (ja) * 2010-05-31 2010-09-09 Murata Mfg Co Ltd 多層セラミック基板
WO2016147284A1 (fr) * 2015-03-16 2016-09-22 富士機械製造株式会社 Procédé de formation et dispositif de formation
WO2019193644A1 (fr) * 2018-04-03 2019-10-10 株式会社Fuji Procédé et dispositif de formation de structure tridimensionnelle

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10209217A (ja) * 1997-01-24 1998-08-07 Matsushita Electric Ind Co Ltd バンプ付きワークの実装方法
JP2010199621A (ja) * 2010-05-31 2010-09-09 Murata Mfg Co Ltd 多層セラミック基板
WO2016147284A1 (fr) * 2015-03-16 2016-09-22 富士機械製造株式会社 Procédé de formation et dispositif de formation
WO2019193644A1 (fr) * 2018-04-03 2019-10-10 株式会社Fuji Procédé et dispositif de formation de structure tridimensionnelle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023148888A1 (fr) * 2022-02-03 2023-08-10 株式会社Fuji Procédé de formation de circuit électrique et appareil de formation de circuit électrique

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Publication number Publication date
JPWO2021214813A1 (fr) 2021-10-28

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