WO2023209960A1 - Design method, design program and method for producing circuit board - Google Patents

Design method, design program and method for producing circuit board Download PDF

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Publication number
WO2023209960A1
WO2023209960A1 PCT/JP2022/019309 JP2022019309W WO2023209960A1 WO 2023209960 A1 WO2023209960 A1 WO 2023209960A1 JP 2022019309 W JP2022019309 W JP 2022019309W WO 2023209960 A1 WO2023209960 A1 WO 2023209960A1
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WO
WIPO (PCT)
Prior art keywords
resin
wiring
layer
resin laminate
image data
Prior art date
Application number
PCT/JP2022/019309
Other languages
French (fr)
Japanese (ja)
Inventor
慎二 瀧川
亮二郎 富永
Original Assignee
株式会社Fuji
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社Fuji filed Critical 株式会社Fuji
Priority to PCT/JP2022/019309 priority Critical patent/WO2023209960A1/en
Publication of WO2023209960A1 publication Critical patent/WO2023209960A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern

Definitions

  • the present invention relates to a method for designing a plurality of resin layers of a circuit board manufactured by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers. Regarding.
  • the following patent document describes a technique for manufacturing a circuit board by forming wiring on the upper surface of a resin layer.
  • An object of the present invention is to appropriately produce a circuit board by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers.
  • the present specification provides a circuit board that is manufactured by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers.
  • a method for designing the plurality of resin layers the method of designing the plurality of resin layers by generating image data showing at least the plurality of resin layers at locations that support and cover wiring.
  • the present specification is produced by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers.
  • a design program for designing the plurality of resin layers of a circuit board is disclosed, the design program generating image data showing at least the plurality of resin layers at locations that support and cover wiring.
  • the present specification provides a circuit board by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers.
  • a circuit board manufacturing method in which the plurality of resin layers are formed at locations that support and cover wiring.
  • image data is generated that shows at least a plurality of resin layers that support and cover the wiring.
  • a plurality of resin layers are formed at locations that support and cover the wiring. This makes it possible to appropriately manufacture the circuit board.
  • FIG. 2 is a block diagram showing a control device.
  • FIG. 2 is a cross-sectional view showing a circuit in a state where a first layer of resin laminate is formed.
  • FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on the first layer of the resin laminate.
  • FIG. 3 is a cross-sectional view showing the circuit in a state where a second layer of resin laminate is formed.
  • FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on a second layer of resin laminate.
  • FIG. 7 is a cross-sectional view showing the circuit in a state where a third layer of resin laminate is formed.
  • FIG. 1 is a block diagram showing a control device.
  • FIG. 2 is a cross-sectional view showing a circuit in a state where a first layer of resin laminate is formed.
  • FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on the first layer of the resin laminate.
  • FIG. 3
  • FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on a third layer of resin laminate.
  • FIG. 7 is a cross-sectional view showing the circuit in a state where a fourth layer of resin laminate is formed.
  • FIG. 7 is a cross-sectional view showing a circuit in which wiring is formed on a fourth layer of the resin laminate.
  • FIG. 7 is a cross-sectional view showing a circuit in a state where a fifth layer of resin laminate is formed.
  • FIG. 2 is a cross-sectional view showing a circuit in which a conductive resin paste is applied to the ends of the wiring.
  • FIG. 7 is a cross-sectional view showing a circuit in which electronic components are mounted in cavities of a fifth layer of resin laminate.
  • FIG. 3 is a diagram showing a circuit pattern and electronic components. It is a figure which shows the resin laminated body designed based on the circuit pattern of the lowest layer. It is a figure which shows the resin laminated body designed based on the circuit pattern of the second layer from the bottom. It is a figure which shows the resin laminated body designed based on the circuit pattern of the third layer from the bottom. It is a figure which shows the resin laminated body designed based on the circuit pattern of an uppermost layer.
  • FIG. 3 is a diagram showing a circuit board including a resin laminate designed by a first design program. It is a figure which shows the flowchart of a 2nd design program.
  • FIG. 7 is a diagram showing a circuit board including a resin laminate designed by a second design program.
  • FIG. 1 shows a circuit forming apparatus 10.
  • the circuit forming apparatus 10 includes a transport device 20, a first modeling unit 22, a second modeling unit 24, a third modeling unit 25, a mounting unit 27, and a control device (see FIG. 2) 28.
  • the transport device 20 , the first modeling unit 22 , the second modeling unit 24 , the third modeling unit 25 , and the mounting unit 27 are arranged on the base 29 of the circuit forming apparatus 10 .
  • the base 29 has a generally rectangular shape, and in the following description, the longitudinal direction of the base 29 is the X-axis direction, the short direction of the base 29 is the Y-axis direction, and it is perpendicular to both the X-axis direction and the Y-axis direction. The direction will be described as the Z-axis direction.
  • the transport device 20 includes an X-axis slide mechanism 30 and a Y-axis slide mechanism 32.
  • the X-axis slide mechanism 30 includes an X-axis slide rail 34 and an X-axis slider 36.
  • the X-axis slide rail 34 is arranged on the base 29 so as to extend in the X-axis direction.
  • the X-axis slider 36 is held by the X-axis slide rail 34 so as to be slidable in the X-axis direction.
  • the X-axis slide mechanism 30 includes an electromagnetic motor (see FIG. 2) 38, and the X-axis slider 36 is moved to any position in the X-axis direction by driving the electromagnetic motor 38.
  • the Y-axis slide mechanism 32 includes a Y-axis slide rail 50 and a stage 52.
  • the Y-axis slide rail 50 is disposed on the base 29 so as to extend in the Y-axis direction, and is movable in the X-axis direction.
  • One end of the Y-axis slide rail 50 is connected to the X-axis slider 36.
  • a stage 52 is held on the Y-axis slide rail 50 so as to be slidable in the Y-axis direction.
  • the Y-axis slide mechanism 32 includes an electromagnetic motor (see FIG. 2) 56, and the stage 52 is moved to an arbitrary position in the Y-axis direction by driving the electromagnetic motor 56. Thereby, the stage 52 is moved to an arbitrary position on the base 29 by driving the X-axis slide mechanism 30 and the Y-axis slide mechanism 32.
  • the stage 52 has a base 60, a holding device 62, and a lifting device 64.
  • the base 60 is formed into a flat plate shape, and a substrate is placed on the top surface.
  • the holding device 62 is provided on both sides of the base 60 in the X-axis direction. Then, both edges of the substrate placed on the base 60 in the X-axis direction are held between the holding devices 62, so that the substrate is fixedly held. Further, the lifting device 64 is disposed below the base 60 and raises and lowers the base 60.
  • the first modeling unit 22 is a unit that models wiring on a substrate placed on the base 60 of the stage 52, and includes a first printing section 72 and a firing section 74.
  • the first printing section 72 has an inkjet head (see FIG. 2) 76, and the inkjet head 76 discharges metal ink in a linear manner.
  • Metal ink is made by dispersing nanometer-sized metal particles, such as silver, in a solvent. Note that the surface of the metal fine particles is coated with a dispersant to prevent agglomeration in the solvent. Further, the inkjet head 76 ejects metal ink from a plurality of nozzles using a piezo system using piezoelectric elements, for example.
  • the baking section 74 has an infrared irradiation device (see FIG. 2) 78.
  • the infrared irradiation device 78 is a device that irradiates the ejected metal ink with infrared rays.
  • the metal ink irradiated with infrared rays is fired and wiring is formed.
  • firing metal ink means that energy is applied to vaporize the solvent and decompose the protective film of the metal particles, that is, the dispersant, etc., and the metal particles contact or fuse to form a conductive layer. This is a phenomenon where the rate increases.
  • metal wiring is formed by firing the metal ink.
  • the second modeling unit 24 is a unit that models a resin layer on the substrate placed on the base 60 of the stage 52, and includes a second printing section 84 and a curing section 86.
  • the second printing section 84 has an inkjet head (see FIG. 2) 88, and the inkjet head 88 discharges ultraviolet curing resin.
  • Ultraviolet curable resin is a resin that is cured by irradiation with ultraviolet rays.
  • the inkjet head 88 may be of a piezo type using a piezoelectric element, for example, or may be a thermal type of heating resin to generate bubbles and ejecting the bubbles from a plurality of nozzles.
  • the curing section 86 includes a flattening device (see FIG. 2) 90 and an irradiation device (see FIG. 2) 92.
  • the flattening device 90 flattens the upper surface of the ultraviolet curable resin discharged by the inkjet head 88, and for example, scrapes off excess resin with a roller or blade while leveling the surface of the ultraviolet curable resin. to make the thickness of the ultraviolet curing resin uniform.
  • the irradiation device 92 includes a mercury lamp or an LED as a light source, and irradiates the discharged ultraviolet curing resin with ultraviolet rays. As a result, the discharged ultraviolet curing resin is cured and a resin layer is formed.
  • the third molding unit 25 is a unit that molds connection parts between electrodes and wiring of electronic components on a substrate placed on a base 60 of the stage 52, and includes a third printing part 100 and a first heating part. 102.
  • the third printing unit 100 has a dispenser (see FIG. 2) 106, and the dispenser 106 dispenses a conductive resin paste.
  • the conductive resin paste is made by dispersing micrometer-sized metal particles in a resin that hardens by heating at a relatively low temperature. Incidentally, the metal particles are in the form of flakes, and the viscosity of the conductive resin paste is relatively high compared to the metal ink.
  • the first heating section 102 has a heater (see FIG. 2) 108.
  • the heater 108 is a device that heats the conductive resin paste applied by the dispenser 106. In the heated conductive resin paste, the resin hardens. At this time, in the conductive resin paste, the resin hardens and contracts, and the flaky metal particles dispersed in the resin come into contact with each other. Thereby, the conductive resin paste exhibits conductivity. Further, the resin of the conductive resin paste is an organic adhesive, and exhibits adhesive strength by being cured by heating.
  • the mounting section 122 includes a mounting head (see FIG. 2) 126 and a moving device (see FIG. 2) 128.
  • the mounting head 126 has a suction nozzle (not shown) for suctioning and holding the electronic component.
  • the suction nozzle is supplied with negative pressure from a positive and negative pressure supply device (not shown), and suctions and holds the electronic component by suctioning air. Then, by supplying a slight positive pressure from the positive/negative pressure supply device, the electronic component is detached.
  • the moving device 128 moves the mounting head 126 between the position where the electronic components are supplied by the tape feeder 124 and the substrate placed on the base 60. Thereby, in the mounting section 122, the electronic component supplied from the tape feeder 124 is held by the suction nozzle, and the electronic component held by the suction nozzle is mounted on the board.
  • control device 28 includes a controller 130 and a plurality of drive circuits 132, as shown in FIG.
  • the plurality of drive circuits 132 include the electromagnetic motors 38 and 56, a holding device 62, a lifting device 64, an inkjet head 76, an infrared irradiation device 78, an inkjet head 88, a flattening device 90, an irradiation device 92, a dispenser 106, a heater 108, It is connected to a tape feeder 124, a mounting head 126, and a moving device 128.
  • the controller 130 is mainly a computer, including a CPU, ROM, RAM, etc., and is connected to a plurality of drive circuits 132. As a result, the operations of the transport device 20 , the first modeling unit 22 , the second modeling unit 24 , the third modeling unit 25 , and the mounting unit 27 are controlled by the controller 130 .
  • circuit forming apparatus 10 With the above-described configuration, a plurality of resin laminates are stacked on the base 60, and wiring is formed on the upper surface of each resin laminate. Then, the electrodes of the electronic component are electrically connected to the wiring via the conductive resin paste, thereby forming a circuit board.
  • the stage 52 is moved below the second modeling unit 24. Then, in the second modeling unit 24, as shown in FIG. 3, a resin laminate 150 is formed on the base 60 of the stage 52.
  • the resin laminate 150 is formed by repeatedly ejecting the ultraviolet curable resin from the inkjet head 88 and irradiating the ejected ultraviolet curable resin with ultraviolet rays by the irradiation device 92.
  • the inkjet head 88 discharges ultraviolet curing resin in a thin film onto the upper surface of the base 60. Subsequently, when the ultraviolet curable resin is discharged in the form of a thin film, the ultraviolet curable resin is flattened by a flattening device 90 in the curing section 86 so that the thickness of the ultraviolet curable resin becomes uniform. Then, the irradiation device 92 irradiates the thin film of ultraviolet curing resin with ultraviolet rays. As a result, a thin film-like resin layer 152 is formed on the base 60.
  • the inkjet head 88 discharges a thin film of ultraviolet curing resin onto the thin film resin layer 152.
  • the thin film-like ultraviolet curable resin is flattened by the flattening device 90, and the irradiation device 92 irradiates the ultraviolet rays onto the thin film-like ultraviolet curable resin, thereby forming a layer on the thin film-like resin layer 152.
  • a thin film-like resin layer 152 is laminated.
  • the resin laminate 150 is formed by repeating the discharging of the ultraviolet curable resin onto the thin film-like resin layer 152 and the irradiation of ultraviolet rays, and by stacking a plurality of resin layers 152.
  • the stage 52 is moved below the first modeling unit 22. Then, in the first printing section 72 of the first modeling unit 22, the inkjet head 76 discharges the metal ink 154 linearly onto the upper surface of the resin laminate 150 according to the circuit pattern, as shown in FIG. Subsequently, in the firing section 74 of the first modeling unit 22, the infrared ray irradiation device 78 irradiates the metal ink 154 ejected according to the circuit pattern with infrared rays. As a result, the metal ink 154 is fired, and the wiring 156 is formed on the resin laminate 150.
  • a second layer resin laminate 160 is formed on the resin laminate 150.
  • the resin laminate 160 is formed to cover the wiring 156 formed on the upper surface of the resin laminate 150.
  • the resin laminate 160 is formed by repeatedly discharging an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92. Further, the outer dimensions of the resin laminate 160 are the same as the outer dimensions of the resin laminate 150.
  • the stage 52 is moved below the first modeling unit 22.
  • the inkjet head 76 discharges the metal ink 162 linearly onto the upper surface of the resin laminate 160 according to the circuit pattern, as shown in FIG.
  • the infrared rays irradiation device 78 irradiates the metal ink 162 with infrared rays in the baking section 74 of the first modeling unit 22, thereby baking the metal ink 162 and forming the wiring 164 on the resin laminate 160.
  • the stage 52 is moved below the second modeling unit 24.
  • a third layer resin laminate 170 is formed on the resin laminate 160, as shown in FIG.
  • the resin laminate 170 is formed to cover the wiring 164 formed on the upper surface of the resin laminate 160.
  • the resin laminate 170 is also formed by repeatedly discharging an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92.
  • the outer dimensions of the resin laminate 170 are also the same as the outer dimensions of the resin laminate 150.
  • the stage 52 is moved below the first modeling unit 22.
  • the inkjet head 76 discharges the metal ink 172 linearly onto the upper surface of the resin laminate 170 according to the circuit pattern, as shown in FIG.
  • the infrared irradiation device 78 irradiates the metal ink 172 with infrared rays in the baking section 74 of the first modeling unit 22, thereby baking the metal ink 172 and forming the wiring 174 on the resin laminate 170. Ru. Note that two wirings 174 are formed on the resin laminate 170.
  • a fourth resin laminate 180 is formed on the resin laminate 170.
  • the resin laminate 180 is formed to cover the two wirings 174 formed on the upper surface of the resin laminate 170.
  • the resin laminate 180 is also formed by repeatedly ejecting an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92.
  • the outer dimensions of the resin laminate 180 are also the same as the outer dimensions of the resin laminate 150.
  • the stage 52 is moved below the first modeling unit 22.
  • the inkjet head 76 discharges the metal ink 182 linearly onto the upper surface of the resin laminate 180 according to the circuit pattern, as shown in FIG.
  • the infrared irradiation device 78 irradiates the metal ink 182 with infrared rays in the baking section 74 of the first modeling unit 22, thereby baking the metal ink 182 and forming the wiring 184 on the resin laminate 180. Ru. Note that three wirings 184 are formed on the resin laminate 180.
  • a fifth layer resin laminate 190 is formed on the resin laminate 180.
  • the resin laminate 190 is formed so as to cover the three wirings 184 formed on the upper surface of the resin laminate 180.
  • a cavity 192 is formed in which mutually opposing ends of are exposed.
  • the resin laminate 190 is also formed by repeatedly ejecting an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92.
  • the outer dimensions of the resin laminate 190 are also the same as the outer dimensions of the resin laminate 150.
  • the stage 52 is moved below the third modeling unit 25.
  • the dispenser 106 applies a conductive resin paste 196 onto the ends of the two wirings 184 exposed inside the cavity 192, as shown in FIG. Exhale.
  • the conductive resin paste 196 is heated by the heater 108, so that the conductive resin paste 196 exhibits conductivity.
  • the stage 52 is moved below the mounting unit 27.
  • an electronic component (see FIG. 13) is supplied by a tape feeder 124, and the electronic component 200 is held by a suction nozzle of a mounting head 126.
  • the electronic component 200 includes a component body 202 and two leads 204 extending downward from a pair of opposing side surfaces of the component body 202.
  • the mounting head 126 is moved by the moving device 128, and the electronic component 200 held by the suction nozzle is mounted on the upper surface of the resin laminate 180 inside the cavity 192, as shown in FIG.
  • the electronic component 200 is mounted so that the leads 204 of the electronic component 200 come into contact with the conductive resin paste 196 discharged onto the wiring 184.
  • the circuit board 210 is made up of five layers of resin laminates 150, 160, 170, 180, and 190 having the same dimensions, but in recent years, it has been desired to reduce the weight of the circuit board. That is, for example, when a circuit board is disposed on a robot hand, it is desired to reduce the weight of the circuit board from the viewpoint of improving the moving speed of the robot hand and controlling vibration damping.
  • circuit board when a circuit board is installed in a drone, a radio control device, etc., it is desired that the circuit board be made lighter so that it can operate for a long time with a single charge.
  • the circuit forming apparatus 10 it is possible to form a resin laminate having an arbitrary shape by discharging the ultraviolet curing resin at an arbitrary position.
  • a plurality of resin laminates are formed only at locations that support and cover the wiring, rather than stacking a plurality of resin laminates having the same dimensions.
  • the controller 130 of the control device 28 stores a first design program 220 and a second design program 222. Then, each of the first design program 220 and the second design program 222 designs a plurality of resin laminates for locations that support and cover the wiring and locations that support electronic components connected to the wiring.
  • a plurality of resin laminates are designed sequentially from the lower resin laminate to the upper resin laminate.
  • the first design program 220 adds a resin laminate to a location that supports the wiring and a location that covers the wiring, and also adds a resin laminate to a location that supports the electronic component connected to the wiring. Image data showing a plurality of resin laminates is generated.
  • a design of a circuit pattern and a design of a mounting position of an electronic component are performed (S10).
  • the design of the circuit pattern and the design of the mounting position of the electronic components are performed according to the functions of the circuit board, etc., and are designed in the same manner as in the conventional method.
  • a four-layer circuit pattern is designed as shown in FIG. A placement position for the component 200 is designed.
  • a plurality of resin laminates 150, 160, 170, 180, and 190 having the same dimensions are stacked to support all the wiring, as in the circuit board 210 shown in FIG. Image data of the covering resin laminate was also generated.
  • the first design program 220 a plurality of resin laminates are designed sequentially from the lower resin laminate to the upper resin laminate. Image data of the resin laminate is generated such that the resin laminate is added to the area covering the wiring. Further, when an electronic component is connected to the wiring, image data of the resin laminate is generated so that the resin laminate is also added to a location that supports the electronic component.
  • the image data of the resin laminate is created by adding the necessary resin laminate based on the lowest circuit pattern of the four-layer circuit pattern designed in S10 and the mounting position of the electronic component. is generated (S12). Note that no electronic component is connected to the wiring 156 corresponding to the circuit pattern in the lowest layer among the four layers of circuit patterns, that is, the circuit pattern in the first layer from the bottom. For this reason, image data is created such that the resin laminate is added to a location that supports the wiring 156 and a location that covers the wiring 156 according to the first layer circuit pattern. Specifically, as shown in FIG. 16, image data of the resin laminate at a location 230a that supports the wiring 156 and a location 230b that covers the wiring 156 is generated.
  • image data when image data is generated, not only the area directly below the wiring that supports the wiring and the area directly above the wiring that covers the wiring, but also the part that supports and covers the area that is a preset dimension and away from the end of the wiring. Image data of the resin laminate including the location is generated.
  • the first design program 220 it is determined whether the image data of the resin laminate has been generated based on the circuit pattern of the uppermost layer in the process in S12 (S14). That is, it is determined whether the image data of the resin laminate has been generated based on the circuit patterns of all the layers.
  • S14 since the image data of the resin laminate is generated based on the circuit pattern of the first layer, it is determined that the image data of the resin laminate is not generated based on the circuit pattern of the top layer. (S14: NO). Then, image data of the resin laminate is generated by adding the necessary resin laminate based on the circuit pattern on the upper layer and the placement position of the electronic component (S16).
  • image data of the resin laminate is generated by adding the necessary resin laminate based on the circuit pattern of the second layer and the mounting position of the electronic component.
  • image data is created such that the resin laminate is added to a location that supports the wiring 164 and a location that covers the wiring 164 according to the second layer circuit pattern.
  • image data of the resin laminate of the portion 232a that supports the wiring 164 and the portion 232b that covers the wiring 164 is generated.
  • the image data of the resin laminate at the portion 232a that supports the wiring 164 is the image data of the resin laminate only at a portion that is different from the previously generated image data of the resin laminate. That is, image data of the resin laminate at the location 232a that supports the wiring 164 is generated, excluding the resin laminate at the location 230 that is generated based on the wiring 156.
  • image data is created such that the resin laminate is added to a location that supports the wiring 174 and a location that covers the wiring 174 according to the third layer circuit pattern.
  • image data of the resin laminate of the portion 234a that supports the wiring 174 and the portion 234b that covers the wiring 174 is generated.
  • the image data of the resin laminate at the portion 234a that supports the wiring 174 is the image data of the resin laminate only at a portion that is different from the previously generated image data of the resin laminate. That is, image data of the resin laminate at the location 234a that supports the wiring 174 is generated, excluding the resin laminate at the location 232 that is generated based on the wiring 164.
  • image data is created such that the resin laminate is added to a location that supports the wiring 184 according to the fourth layer circuit pattern, a location that covers the wiring 184, and a location that supports the electronic component 200.
  • image data of the resin laminate of a portion 236a that supports the wiring 184 and the electronic component 200 and a portion 236b that covers the wiring 184 is generated.
  • the image data of the resin laminate at the portion 236a that supports the wiring 184 and the electronic component 200 is the image data of the resin laminate only at a portion that is different from the previously generated image data of the resin laminate.
  • image data of the resin laminate at the location 236a that supports the wiring 184 and the electronic component 200 is generated, excluding the resin laminate at the location 234 that is generated based on the wiring 174. Further, the image data of the resin laminate at the portion 236b covering the wiring 184 is generated excluding the cavity 192 for mounting the electronic component 200.
  • image data of the resin laminate at locations 230, 232, 234, and 236 is generated based on the wiring according to the circuit pattern of each layer and the electronic components connected to the wiring. Then, when a resin laminate is formed based on the generated image data, a circuit board 260 made up of the five layers of resin laminates 250 to 254 is formed, as shown in FIG. In other words, when the resin laminate is formed based on the image data generated by the first design program 220, the circuit board 260 has the resin laminate formed only in areas that support wiring and electronic components and areas that cover the wiring. is formed.
  • the second design program 222 a plurality of resin laminates are designed sequentially from the upper resin laminate to the lower resin laminate.
  • the second design program 222 identifies parts unnecessary for supporting and covering the wiring from virtual images (hereinafter referred to as "virtual images") of the plurality of resin laminates designed using the conventional method.
  • Image data showing a plurality of resin laminates is generated by deleting portions unnecessary for supporting electronic components.
  • the virtual image is an image of a plurality of resin laminates designed using a conventional method, and is an image of five resin laminates 150, 160, 170, 180, and 190 that constitute the circuit board 210 in FIG. be.
  • the virtual image shows a resin laminate that supports and covers all the wiring 156, 164, 174, 184 of the circuit board 210 by laminating five resin laminates of the same size, and supports all the electronic components 200. It is an image of the body.
  • a design of a circuit pattern and a design of a mounting position of an electronic component are performed (S20).
  • the design of the circuit pattern and the design of the mounting position of the electronic component in the second design program 222 are the same as the design of the circuit pattern and the design of the mounting position of the electronic component in the first design program 220. For this reason, for example, when designing the circuit pattern of a circuit board with the same functions as the circuit board 210 in FIG. 13 and the mounting position of electronic components, a four-layer circuit pattern is designed as shown in FIG. A placement position for electronic component 200 is designed.
  • the virtual image is an image of the five layers of resin laminates 150, 160, 170, 180, and 190 that constitute the circuit board 210, so as shown in FIG. Designed. Note that when distinguishing each of the five layers of virtual images 270, in order from the upper virtual image, the first layer virtual image 270a, the second layer virtual image 270b, the third layer virtual image 270c, and the fourth layer virtual image A virtual image 270d of the fifth layer and a virtual image 270e of the fifth layer.
  • a portion 280 that is unnecessary for covering the wiring 184 is identified from the range of the uppermost layer virtual image 270a.
  • the unnecessary portions for covering the wiring are the portions where the wiring is not covered, and are not only the portions where the wiring is not covered but also the portions which are separated by a predetermined dimension from the end of the wiring. Then, when a portion 280 unnecessary for covering the wiring 184 is identified, the portion 280 unnecessary for covering the wiring 184 is deleted from the virtual image 270a of the uppermost layer, and as shown in FIG. Image data of the body 300 is generated.
  • the second design program 222 it is determined whether the image data of the resin laminate has been generated based on the virtual image 270e of the lowest layer in the process in S24 (S26). That is, it is determined whether image data of the resin laminate has been generated based on the virtual images 270 of all layers.
  • the image data of the resin laminate is generated based on the virtual image 270a of the top layer, that is, the first layer, the image data of the resin laminate is generated based on the virtual image 270e of the bottom layer. is determined to have not been generated (S26: NO).
  • the image data of the resin laminate is created by deleting parts unnecessary for supporting and covering the wiring and parts unnecessary for supporting the electronic components from the lower virtual image 270, that is, the second layer virtual image 270b. is generated (S28).
  • the virtual image 270b of the second layer based on the circuit pattern of the top layer and the wirings 174, 184 and the electronic component 200 according to the circuit pattern of the second layer, parts unnecessary for supporting and covering the wiring and electronic parts are removed. Locations that are unnecessary for supporting the component are identified. Specifically, as shown in FIG. 24, a location 282 that is unnecessary for supporting the wiring 184 and the electronic component 200 and unnecessary for covering the wiring 174 is identified from the range of the second layer virtual image 270b.
  • a location unnecessary for supporting the wiring is a location that does not support the wiring, but is also a location that does not support not only the wiring but also a location that is a predetermined distance away from the end of the wiring.
  • locations that are unnecessary for supporting electronic components are locations other than directly below the electronic components, but are not limited to locations that are not just directly below the electronic components, but also locations that are a preset distance from the edge of the electronic components, excluding locations directly below the electronic components. It is. Then, when a portion 282 that is unnecessary for supporting the wiring 184 and the electronic component 200 and is unnecessary for covering the wiring 174 is specified, the unnecessary portion 282 is deleted from the second layer virtual image 270b and shown in FIG. As shown, image data of the second layer resin laminate 302 is generated.
  • the third layer virtual image 270c wiring is performed based on the wiring 164, 174, 184 and the electronic component 200 according to the circuit patterns of three layers from the top layer circuit pattern to the third layer circuit pattern. Areas unnecessary for supporting and covering electronic components and areas unnecessary for supporting electronic components are identified. Specifically, as shown in FIG. 25, a portion 284 that is unnecessary for supporting the wirings 174, 184 and the electronic component 200 and unnecessary for covering the wiring 164 is identified from the range of the third layer virtual image 270c. .
  • the fourth layer virtual image 270d based on the wirings 156, 164, 174, 184 and the electronic component 200 according to the circuit patterns for four layers from the top layer circuit pattern to the fourth layer circuit pattern. , locations unnecessary for supporting and covering wiring and locations unnecessary for supporting electronic components are identified. Specifically, locations that are unnecessary for supporting the wirings 164, 174, 184 and the electronic component 200, and unnecessary for covering the wiring 156 are identified from the range of the fourth layer virtual image 270d. However, within the range of the fourth layer virtual image 270d, there are no locations that are unnecessary for supporting the wirings 164, 174, 184 and the electronic component 200, and are unnecessary for covering the wiring 156. Therefore, no portion is deleted from the fourth layer virtual image 270d, and image data of the fourth layer resin laminate 306 is generated at the same position as the fourth layer virtual image 270d.
  • the virtual image 270e of the fifth layer based on the wirings 156, 164, 174, 184 and the electronic component 200 according to the circuit patterns of four layers from the circuit pattern of the top layer to the circuit pattern of the fourth layer. , locations unnecessary for supporting and covering wiring and locations unnecessary for supporting electronic components are identified. Specifically, locations unnecessary for supporting the wirings 156, 164, 174, 184 and the electronic component 200 are identified from the range of the fifth layer virtual image 270e. However, within the range of the fifth layer virtual image 270e, there are no locations unnecessary for supporting the wirings 156, 164, 174, 184 and the electronic component 200. Therefore, no portion is deleted from the fifth layer virtual image 270e, and image data of the fifth layer resin laminate 308 is generated at the same position as the fifth layer virtual image 270e.
  • image data of a plurality of resin laminates are generated by deleting portions unnecessary for supporting and covering wiring and portions unnecessary for supporting electronic components from the virtual image 270 of each layer. Then, when a resin laminate is formed based on the generated image data, a circuit board 310 made up of the five layers of resin laminates 300 to 308 is formed, as shown in FIG. In other words, when a resin laminate is formed based on the image data generated by the second design program 222, the resin laminate is formed in areas unnecessary for supporting wiring and electronic components and areas unnecessary for covering wiring from the virtual image. is removed, and a circuit board 310 is formed in which the resin laminate is formed only at locations that support the wiring and electronic components and locations that cover the wiring. Note that the circuit board 260 and the circuit board 310 have substantially the same shape. In other words, the image data of the resin laminate generated by the first design program 220 and the image data of the resin laminate generated by the second design program 222 are approximately the same.
  • the time required to form resin laminates can be shortened, and the material of resin laminates can be reduced. It is also possible to reduce the amount of water used. Furthermore, since the image data of the resin laminate is generated by the first design program 220 or the second design program 222, it is possible to reduce the time required to design the circuit board.
  • the wirings 156, 164, 174, and 184 are examples of wirings.
  • Electronic component 200 is an example of an electronic component.
  • the first design program 220 is an example of a design program.
  • the second design program 222 is an example of a design program.
  • the resin laminates 250, 251, 252, 253, and 254 are examples of resin layers.
  • Circuit board 260 is an example of a circuit board.
  • Virtual image 270 is an example of a virtual image.
  • the resin laminates 300, 302, 304, 306, and 308 are examples of resin layers.
  • Circuit board 310 is an example of a circuit board.
  • the present invention is not limited to the above-mentioned embodiments, but can be implemented in various forms with various modifications and improvements based on the knowledge of those skilled in the art.
  • the first design program 220 and the second design program 222 are stored in the control device 28 of the circuit forming apparatus 10, but the The first design program 220 and the second design program 222 may be stored in the information processing device.
  • an ultraviolet curable resin is used as the curable resin for forming the resin laminate, but it is possible to use various resins such as thermosetting resins and two-component mixed resins. It is.

Abstract

The present invention discloses a design method for a plurality of resin layers of a circuit board that is formed by stacking a plurality of resin layers and forming a wiring line on the upper surface of at least one resin layer among the plurality of resin layers. This design method designs the plurality of resin layers by producing image data that show at least the plurality of resin layers in positions where the wiring line is supported and covered.

Description

設計方法、設計プログラム、および回路基板作製方法Design method, design program, and circuit board manufacturing method
　本発明は、複数の樹脂層を積層させるとともに、それら複数の樹脂層のうちの少なくとも１層の樹脂層の上面に配線を形成することで作製される回路基板の複数の樹脂層の設計方法などに関する。 The present invention relates to a method for designing a plurality of resin layers of a circuit board manufactured by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers. Regarding.
　下記特許文献には、樹脂層の上面に配線を形成することで回路基板を作製する技術が記載されている。 The following patent document describes a technique for manufacturing a circuit board by forming wiring on the upper surface of a resin layer.
国際公開第２０１６／１２５２７５号明細書International Publication No. 2016/125275
　本発明は、複数の樹脂層を積層させるとともに、それら複数の樹脂層のうちの少なくとも１層の樹脂層の上面に配線を形成することで回路基板を適切に作製することを課題とする。 An object of the present invention is to appropriately produce a circuit board by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers.
　上記課題を解決するために、本明細書は、複数の樹脂層を積層させるとともに、前記複数の樹脂層のうちの少なくとも１層の樹脂層の上面に配線を形成することで作製される回路基板の前記複数の樹脂層の設計方法であって、配線を支持するとともに覆う箇所の前記複数の樹脂層を少なくとも示す画像データを生成することで前記複数の樹脂層を設計する設計方法を開示する。 In order to solve the above problems, the present specification provides a circuit board that is manufactured by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers. Disclosed is a method for designing the plurality of resin layers, the method of designing the plurality of resin layers by generating image data showing at least the plurality of resin layers at locations that support and cover wiring.
　また、上記課題を解決するために、本明細書は、複数の樹脂層を積層させるとともに、前記複数の樹脂層のうちの少なくとも１層の樹脂層の上面に配線を形成することで作製される回路基板の前記複数の樹脂層を設計する設計プログラムであって、配線を支持するとともに覆う箇所の前記複数の樹脂層を少なくとも示す画像データを生成する設計プログラムを開示する。 Moreover, in order to solve the above-mentioned problem, the present specification is produced by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers. A design program for designing the plurality of resin layers of a circuit board is disclosed, the design program generating image data showing at least the plurality of resin layers at locations that support and cover wiring.
　また、上記課題を解決するために、本明細書は、複数の樹脂層を積層させるとともに、前記複数の樹脂層のうちの少なくとも１層の樹脂層の上面に配線を形成することで回路基板を作製する回路基板作製方法であって、配線を支持するとともに覆う箇所に前記複数の樹脂層を形成する回路基板作製方法を開示する。 Further, in order to solve the above problems, the present specification provides a circuit board by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers. Disclosed is a circuit board manufacturing method in which the plurality of resin layers are formed at locations that support and cover wiring.
　本開示では、配線を支持するとともに覆う箇所の複数の樹脂層を少なくとも示す画像データが生成される。若しくは、配線を支持するとともに覆う箇所に複数の樹脂層が形成される。これにより、回路基板を適切に作製することが可能となる。 In the present disclosure, image data is generated that shows at least a plurality of resin layers that support and cover the wiring. Alternatively, a plurality of resin layers are formed at locations that support and cover the wiring. This makes it possible to appropriately manufacture the circuit board.
回路形成装置を示す図である。It is a figure showing a circuit formation device. 制御装置を示すブロック図である。FIG. 2 is a block diagram showing a control device. １層目の樹脂積層体が形成された状態の回路を示す断面図である。FIG. 2 is a cross-sectional view showing a circuit in a state where a first layer of resin laminate is formed. １層目の樹脂積層体の上に配線が形成された状態の回路を示す断面図である。FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on the first layer of the resin laminate. ２層目の樹脂積層体が形成された状態の回路を示す断面図である。FIG. 3 is a cross-sectional view showing the circuit in a state where a second layer of resin laminate is formed. ２層目の樹脂積層体の上に配線が形成された状態の回路を示す断面図である。FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on a second layer of resin laminate. ３層目の樹脂積層体が形成された状態の回路を示す断面図である。FIG. 7 is a cross-sectional view showing the circuit in a state where a third layer of resin laminate is formed. ３層目の樹脂積層体の上に配線が形成された状態の回路を示す断面図である。FIG. 3 is a cross-sectional view showing a circuit in which wiring is formed on a third layer of resin laminate. ４層目の樹脂積層体が形成された状態の回路を示す断面図である。FIG. 7 is a cross-sectional view showing the circuit in a state where a fourth layer of resin laminate is formed. ４層目の樹脂積層体の上に配線が形成された状態の回路を示す断面図である。FIG. 7 is a cross-sectional view showing a circuit in which wiring is formed on a fourth layer of the resin laminate. ５層目の樹脂積層体が形成された状態の回路を示す断面図である。FIG. 7 is a cross-sectional view showing a circuit in a state where a fifth layer of resin laminate is formed. 配線の端部に導電性樹脂ペーストが塗布された状態の回路を示す断面図である。FIG. 2 is a cross-sectional view showing a circuit in which a conductive resin paste is applied to the ends of the wiring. ５層目の樹脂積層体のキャビティに電子部品が装着された状態の回路を示す断面図である。FIG. 7 is a cross-sectional view showing a circuit in which electronic components are mounted in cavities of a fifth layer of resin laminate. 第１設計プログラムのフローチャートを示す図である。It is a figure which shows the flowchart of a 1st design program. 回路パターン及び電子部品を示す図である。FIG. 3 is a diagram showing a circuit pattern and electronic components. 最下層の回路パターンに基づいて設計される樹脂積層体を示す図である。It is a figure which shows the resin laminated body designed based on the circuit pattern of the lowest layer. 下から２層目の回路パターンに基づいて設計される樹脂積層体を示す図である。It is a figure which shows the resin laminated body designed based on the circuit pattern of the second layer from the bottom. 下から３層目の回路パターンに基づいて設計される樹脂積層体を示す図である。It is a figure which shows the resin laminated body designed based on the circuit pattern of the third layer from the bottom. 最上層の回路パターンに基づいて設計される樹脂積層体を示す図である。It is a figure which shows the resin laminated body designed based on the circuit pattern of an uppermost layer. 第１設計プログラムにより設計された樹脂積層体を含む回路基板を示す図である。FIG. 3 is a diagram showing a circuit board including a resin laminate designed by a first design program. 第２設計プログラムのフローチャートを示す図である。It is a figure which shows the flowchart of a 2nd design program. 複数の樹脂積層体の仮想画像を示す図である。It is a figure showing a virtual image of a plurality of resin laminates. 最上層の仮想画像に基づいて設計される樹脂積層体を示す図である。It is a figure which shows the resin laminated body designed based on the virtual image of an uppermost layer. 上から２層目の仮想画像に基づいて設計される樹脂積層体を示す図である。It is a figure which shows the resin laminated body designed based on the virtual image of the second layer from the top. 上から３層目の仮想画像に基づいて設計される樹脂積層体を示す図である。It is a figure which shows the resin laminated body designed based on the virtual image of the third layer from the top. 上から４層目及び最下層の仮想画像に基づいて設計される樹脂積層体を示す図である。It is a figure which shows the resin laminated body designed based on the virtual image of the 4th layer from the top, and the lowest layer. 第２設計プログラムにより設計された樹脂積層体を含む回路基板を示す図である。FIG. 7 is a diagram showing a circuit board including a resin laminate designed by a second design program.
　図１に回路形成装置１０を示す。回路形成装置１０は、搬送装置２０と、第１造形ユニット２２と、第２造形ユニット２４と、第３造形ユニット２５と、装着ユニット２７と、制御装置（図２参照）２８とを備える。それら搬送装置２０と第１造形ユニット２２と第２造形ユニット２４と第３造形ユニット２５と装着ユニット２７とは、回路形成装置１０のベース２９の上に配置されている。ベース２９は、概して長方形状をなしており、以下の説明では、ベース２９の長手方向をＸ軸方向、ベース２９の短手方向をＹ軸方向、Ｘ軸方向及びＹ軸方向の両方に直交する方向をＺ軸方向と称して説明する。 FIG. 1 shows a circuit forming apparatus 10. The circuit forming apparatus 10 includes a transport device 20, a first modeling unit 22, a second modeling unit 24, a third modeling unit 25, a mounting unit 27, and a control device (see FIG. 2) 28. The transport device 20 , the first modeling unit 22 , the second modeling unit 24 , the third modeling unit 25 , and the mounting unit 27 are arranged on the base 29 of the circuit forming apparatus 10 . The base 29 has a generally rectangular shape, and in the following description, the longitudinal direction of the base 29 is the X-axis direction, the short direction of the base 29 is the Y-axis direction, and it is perpendicular to both the X-axis direction and the Y-axis direction. The direction will be described as the Z-axis direction.
　搬送装置２０は、Ｘ軸スライド機構３０と、Ｙ軸スライド機構３２とを備えている。そのＸ軸スライド機構３０は、Ｘ軸スライドレール３４とＸ軸スライダ３６とを有している。Ｘ軸スライドレール３４は、Ｘ軸方向に延びるように、ベース２９の上に配設されている。Ｘ軸スライダ３６は、Ｘ軸スライドレール３４によって、Ｘ軸方向にスライド可能に保持されている。さらに、Ｘ軸スライド機構３０は、電磁モータ（図２参照）３８を有しており、電磁モータ３８の駆動により、Ｘ軸スライダ３６がＸ軸方向の任意の位置に移動する。また、Ｙ軸スライド機構３２は、Ｙ軸スライドレール５０とステージ５２とを有している。Ｙ軸スライドレール５０は、Ｙ軸方向に延びるように、ベース２９の上に配設されており、Ｘ軸方向に移動可能とされている。そして、Ｙ軸スライドレール５０の一端部が、Ｘ軸スライダ３６に連結されている。そのＹ軸スライドレール５０には、ステージ５２が、Ｙ軸方向にスライド可能に保持されている。さらに、Ｙ軸スライド機構３２は、電磁モータ（図２参照）５６を有しており、電磁モータ５６の駆動により、ステージ５２がＹ軸方向の任意の位置に移動する。これにより、ステージ５２は、Ｘ軸スライド機構３０及びＹ軸スライド機構３２の駆動により、ベース２９上の任意の位置に移動する。 The transport device 20 includes an X-axis slide mechanism 30 and a Y-axis slide mechanism 32. The X-axis slide mechanism 30 includes an X-axis slide rail 34 and an X-axis slider 36. The X-axis slide rail 34 is arranged on the base 29 so as to extend in the X-axis direction. The X-axis slider 36 is held by the X-axis slide rail 34 so as to be slidable in the X-axis direction. Further, the X-axis slide mechanism 30 includes an electromagnetic motor (see FIG. 2) 38, and the X-axis slider 36 is moved to any position in the X-axis direction by driving the electromagnetic motor 38. Further, the Y-axis slide mechanism 32 includes a Y-axis slide rail 50 and a stage 52. The Y-axis slide rail 50 is disposed on the base 29 so as to extend in the Y-axis direction, and is movable in the X-axis direction. One end of the Y-axis slide rail 50 is connected to the X-axis slider 36. A stage 52 is held on the Y-axis slide rail 50 so as to be slidable in the Y-axis direction. Further, the Y-axis slide mechanism 32 includes an electromagnetic motor (see FIG. 2) 56, and the stage 52 is moved to an arbitrary position in the Y-axis direction by driving the electromagnetic motor 56. Thereby, the stage 52 is moved to an arbitrary position on the base 29 by driving the X-axis slide mechanism 30 and the Y-axis slide mechanism 32.
　ステージ５２は、基台６０と、保持装置６２と、昇降装置６４とを有している。基台６０は、平板状に形成され、上面に基板が載置される。保持装置６２は、基台６０のＸ軸方向の両側部に設けられている。そして、基台６０に載置された基板のＸ軸方向の両縁部が、保持装置６２によって挟まれることで、基板が固定的に保持される。また、昇降装置６４は、基台６０の下方に配設されており、基台６０を昇降させる。 The stage 52 has a base 60, a holding device 62, and a lifting device 64. The base 60 is formed into a flat plate shape, and a substrate is placed on the top surface. The holding device 62 is provided on both sides of the base 60 in the X-axis direction. Then, both edges of the substrate placed on the base 60 in the X-axis direction are held between the holding devices 62, so that the substrate is fixedly held. Further, the lifting device 64 is disposed below the base 60 and raises and lowers the base 60.
　第１造形ユニット２２は、ステージ５２の基台６０に載置された基板の上に配線を造形するユニットであり、第１印刷部７２と、焼成部７４とを有している。第１印刷部７２は、インクジェットヘッド（図２参照）７６を有しており、インクジェットヘッド７６が金属インクを線状に吐出する。金属インクは、ナノメートルサイズの金属、例えば銀の微粒子が溶剤中に分散されたものである。なお、金属微粒子の表面は分散剤によりコーティングされており、溶剤中での凝集が防止されている。また、インクジェットヘッド７６は、例えば、圧電素子を用いたピエゾ方式によって複数のノズルから金属インクを吐出する。 The first modeling unit 22 is a unit that models wiring on a substrate placed on the base 60 of the stage 52, and includes a first printing section 72 and a firing section 74. The first printing section 72 has an inkjet head (see FIG. 2) 76, and the inkjet head 76 discharges metal ink in a linear manner. Metal ink is made by dispersing nanometer-sized metal particles, such as silver, in a solvent. Note that the surface of the metal fine particles is coated with a dispersant to prevent agglomeration in the solvent. Further, the inkjet head 76 ejects metal ink from a plurality of nozzles using a piezo system using piezoelectric elements, for example.
　焼成部７４は、赤外線照射装置（図２参照）７８を有している。赤外線照射装置７８は、吐出された金属インクに赤外線を照射する装置である。赤外線が照射された金属インクは焼成し、配線が形成される。なお、金属インクの焼成とは、エネルギーを付与することによって、溶媒の気化や金属微粒子の保護膜、つまり、分散剤の分解等が行われ、金属微粒子が接触または融着をすることで、導電率が高くなる現象である。そして、金属インクが焼成することで、金属製の配線が形成される。 The baking section 74 has an infrared irradiation device (see FIG. 2) 78. The infrared irradiation device 78 is a device that irradiates the ejected metal ink with infrared rays. The metal ink irradiated with infrared rays is fired and wiring is formed. Incidentally, firing metal ink means that energy is applied to vaporize the solvent and decompose the protective film of the metal particles, that is, the dispersant, etc., and the metal particles contact or fuse to form a conductive layer. This is a phenomenon where the rate increases. Then, metal wiring is formed by firing the metal ink.
　また、第２造形ユニット２４は、ステージ５２の基台６０に載置された基板の上に樹脂層を造形するユニットであり、第２印刷部８４と、硬化部８６とを有している。第２印刷部８４は、インクジェットヘッド（図２参照）８８を有しており、インクジェットヘッド８８は紫外線硬化樹脂を吐出する。紫外線硬化樹脂は、紫外線の照射により硬化する樹脂である。なお、インクジェットヘッド８８は、例えば、圧電素子を用いたピエゾ方式でもよく、樹脂を加熱して気泡を発生させ複数のノズルから吐出するサーマル方式でもよい。 Further, the second modeling unit 24 is a unit that models a resin layer on the substrate placed on the base 60 of the stage 52, and includes a second printing section 84 and a curing section 86. The second printing section 84 has an inkjet head (see FIG. 2) 88, and the inkjet head 88 discharges ultraviolet curing resin. Ultraviolet curable resin is a resin that is cured by irradiation with ultraviolet rays. Note that the inkjet head 88 may be of a piezo type using a piezoelectric element, for example, or may be a thermal type of heating resin to generate bubbles and ejecting the bubbles from a plurality of nozzles.
　硬化部８６は、平坦化装置（図２参照）９０と照射装置（図２参照）９２とを有している。平坦化装置９０は、インクジェットヘッド８８によって吐出された紫外線硬化樹脂の上面を平坦化するものであり、例えば、紫外線硬化樹脂の表面を均しながら余剰分の樹脂を、ローラもしくはブレードによって掻き取ることで、紫外線硬化樹脂の厚みを均一させる。また、照射装置９２は、光源として水銀ランプもしくはＬＥＤを備えており、吐出された紫外線硬化樹脂に紫外線を照射する。これにより、吐出された紫外線硬化樹脂が硬化し、樹脂層が形成される。 The curing section 86 includes a flattening device (see FIG. 2) 90 and an irradiation device (see FIG. 2) 92. The flattening device 90 flattens the upper surface of the ultraviolet curable resin discharged by the inkjet head 88, and for example, scrapes off excess resin with a roller or blade while leveling the surface of the ultraviolet curable resin. to make the thickness of the ultraviolet curing resin uniform. Further, the irradiation device 92 includes a mercury lamp or an LED as a light source, and irradiates the discharged ultraviolet curing resin with ultraviolet rays. As a result, the discharged ultraviolet curing resin is cured and a resin layer is formed.
　第３造形ユニット２５は、ステージ５２の基台６０に載置された基板の上に電子部品の電極と配線との接続部を造形するユニットであり、第３印刷部１００と、第１加熱部１０２とを有している。第３印刷部１００は、ディスペンサ（図２参照）１０６を有しており、ディスペンサ１０６は導電性樹脂ペーストを吐出する。導電性樹脂ペーストは、比較的低温の加熱により硬化する樹脂に、マイクロメートルサイズの金属粒子が分散されたものである。ちなみに、金属粒子は、フレーク状とされており、導電性樹脂ペーストの粘度は、金属インクと比較して比較的高い。 The third molding unit 25 is a unit that molds connection parts between electrodes and wiring of electronic components on a substrate placed on a base 60 of the stage 52, and includes a third printing part 100 and a first heating part. 102. The third printing unit 100 has a dispenser (see FIG. 2) 106, and the dispenser 106 dispenses a conductive resin paste. The conductive resin paste is made by dispersing micrometer-sized metal particles in a resin that hardens by heating at a relatively low temperature. Incidentally, the metal particles are in the form of flakes, and the viscosity of the conductive resin paste is relatively high compared to the metal ink.
　第１加熱部１０２は、ヒータ（図２参照）１０８を有している。ヒータ１０８は、ディスペンサ１０６により塗布された導電性樹脂ペーストを加熱する装置である。加熱された導電性樹脂ペーストでは、樹脂が硬化する。この際、導電性樹脂ペーストでは、樹脂が硬化して収縮し、その樹脂に分散されたフレーク状の金属粒子が接触する。これにより、導電性樹脂ペーストが導電性を発揮する。また、導電性樹脂ペーストの樹脂は、有機系の接着剤であり、加熱により硬化することで接着力を発揮する。 The first heating section 102 has a heater (see FIG. 2) 108. The heater 108 is a device that heats the conductive resin paste applied by the dispenser 106. In the heated conductive resin paste, the resin hardens. At this time, in the conductive resin paste, the resin hardens and contracts, and the flaky metal particles dispersed in the resin come into contact with each other. Thereby, the conductive resin paste exhibits conductivity. Further, the resin of the conductive resin paste is an organic adhesive, and exhibits adhesive strength by being cured by heating.
　装着部１２２は、装着ヘッド（図２参照）１２６と、移動装置（図２参照）１２８とを有している。装着ヘッド１２６は、電子部品を吸着保持するための吸着ノズル（図示省略）を有する。吸着ノズルは、正負圧供給装置（図示省略）から負圧が供給されることで、エアの吸引により電子部品を吸着保持する。そして、正負圧供給装置から僅かな正圧が供給されることで、電子部品を離脱する。また、移動装置１２８は、テープフィーダ１２４による電子部品の供給位置と、基台６０に載置された基板との間で、装着ヘッド１２６を移動させる。これにより、装着部１２２では、テープフィーダ１２４から供給された電子部品が、吸着ノズルにより保持され、その吸着ノズルによって保持された電子部品が、基板に装着される。 The mounting section 122 includes a mounting head (see FIG. 2) 126 and a moving device (see FIG. 2) 128. The mounting head 126 has a suction nozzle (not shown) for suctioning and holding the electronic component. The suction nozzle is supplied with negative pressure from a positive and negative pressure supply device (not shown), and suctions and holds the electronic component by suctioning air. Then, by supplying a slight positive pressure from the positive/negative pressure supply device, the electronic component is detached. Furthermore, the moving device 128 moves the mounting head 126 between the position where the electronic components are supplied by the tape feeder 124 and the substrate placed on the base 60. Thereby, in the mounting section 122, the electronic component supplied from the tape feeder 124 is held by the suction nozzle, and the electronic component held by the suction nozzle is mounted on the board.
　また、制御装置２８は、図２に示すように、コントローラ１３０と、複数の駆動回路１３２とを備えている。複数の駆動回路１３２は、上記電磁モータ３８，５６、保持装置６２、昇降装置６４、インクジェットヘッド７６、赤外線照射装置７８、インクジェットヘッド８８、平坦化装置９０、照射装置９２、ディスペンサ１０６、ヒータ１０８、テープフィーダ１２４、装着ヘッド１２６、移動装置１２８に接続されている。コントローラ１３０は、ＣＰＵ，ＲＯＭ，ＲＡＭ等を備え、コンピュータを主体とするものであり、複数の駆動回路１３２に接続されている。これにより、搬送装置２０、第１造形ユニット２２、第２造形ユニット２４、第３造形ユニット２５、装着ユニット２７の作動が、コントローラ１３０によって制御される。 Further, the control device 28 includes a controller 130 and a plurality of drive circuits 132, as shown in FIG. The plurality of drive circuits 132 include the electromagnetic motors 38 and 56, a holding device 62, a lifting device 64, an inkjet head 76, an infrared irradiation device 78, an inkjet head 88, a flattening device 90, an irradiation device 92, a dispenser 106, a heater 108, It is connected to a tape feeder 124, a mounting head 126, and a moving device 128. The controller 130 is mainly a computer, including a CPU, ROM, RAM, etc., and is connected to a plurality of drive circuits 132. As a result, the operations of the transport device 20 , the first modeling unit 22 , the second modeling unit 24 , the third modeling unit 25 , and the mounting unit 27 are controlled by the controller 130 .
　回路形成装置１０では、上述した構成によって、基台６０の上に複数の樹脂積層体が積層され、各樹脂積層体の上面に配線が形成される。そして、導電性樹脂ペーストを介して、電子部品の電極が配線に電気的に接続されることで、回路基板が形成される。 In the circuit forming apparatus 10, with the above-described configuration, a plurality of resin laminates are stacked on the base 60, and wiring is formed on the upper surface of each resin laminate. Then, the electrodes of the electronic component are electrically connected to the wiring via the conductive resin paste, thereby forming a circuit board.
　具体的には、ステージ５２が、第２造形ユニット２４の下方に移動される。そして、第２造形ユニット２４において、図３に示すように、ステージ５２の基台６０の上に樹脂積層体１５０が形成される。樹脂積層体１５０は、インクジェットヘッド８８からの紫外線硬化樹脂の吐出と、吐出された紫外線硬化樹脂への照射装置９２による紫外線の照射とが繰り返されることにより形成される。 Specifically, the stage 52 is moved below the second modeling unit 24. Then, in the second modeling unit 24, as shown in FIG. 3, a resin laminate 150 is formed on the base 60 of the stage 52. The resin laminate 150 is formed by repeatedly ejecting the ultraviolet curable resin from the inkjet head 88 and irradiating the ejected ultraviolet curable resin with ultraviolet rays by the irradiation device 92.
　詳しくは、第２造形ユニット２４の第２印刷部８４において、インクジェットヘッド８８が、基台６０の上面に紫外線硬化樹脂を薄膜状に吐出する。続いて、紫外線硬化樹脂が薄膜状に吐出されると、硬化部８６において、紫外線硬化樹脂の膜厚が均一となるように、紫外線硬化樹脂が平坦化装置９０によって平坦化される。そして、照射装置９２が、その薄膜状の紫外線硬化樹脂に紫外線を照射する。これにより、基台６０の上に薄膜状の樹脂層１５２が形成される。 Specifically, in the second printing section 84 of the second modeling unit 24, the inkjet head 88 discharges ultraviolet curing resin in a thin film onto the upper surface of the base 60. Subsequently, when the ultraviolet curable resin is discharged in the form of a thin film, the ultraviolet curable resin is flattened by a flattening device 90 in the curing section 86 so that the thickness of the ultraviolet curable resin becomes uniform. Then, the irradiation device 92 irradiates the thin film of ultraviolet curing resin with ultraviolet rays. As a result, a thin film-like resin layer 152 is formed on the base 60.
　続いて、インクジェットヘッド８８が、その薄膜状の樹脂層１５２の上に紫外線硬化樹脂を薄膜状に吐出する。そして、平坦化装置９０によって薄膜状の紫外線硬化樹脂が平坦化され、照射装置９２が、その薄膜状に吐出された紫外線硬化樹脂に紫外線を照射することで、薄膜状の樹脂層１５２の上に薄膜状の樹脂層１５２が積層される。このように、薄膜状の樹脂層１５２の上への紫外線硬化樹脂の吐出と、紫外線の照射とが繰り返され、複数の樹脂層１５２が積層されることで、樹脂積層体１５０が形成される。 Subsequently, the inkjet head 88 discharges a thin film of ultraviolet curing resin onto the thin film resin layer 152. Then, the thin film-like ultraviolet curable resin is flattened by the flattening device 90, and the irradiation device 92 irradiates the ultraviolet rays onto the thin film-like ultraviolet curable resin, thereby forming a layer on the thin film-like resin layer 152. A thin film-like resin layer 152 is laminated. In this way, the resin laminate 150 is formed by repeating the discharging of the ultraviolet curable resin onto the thin film-like resin layer 152 and the irradiation of ultraviolet rays, and by stacking a plurality of resin layers 152.
　上述した手順により樹脂積層体１５０が形成されると、ステージ５２が第１造形ユニット２２の下方に移動される。そして、第１造形ユニット２２の第１印刷部７２において、インクジェットヘッド７６が、図４に示すように、樹脂積層体１５０の上面に金属インク１５４を、回路パターンに応じて線状に吐出する。続いて、回路パターンに応じて吐出された金属インク１５４に、第１造形ユニット２２の焼成部７４において、赤外線照射装置７８が赤外線を照射する。これにより、金属インク１５４が焼成し、樹脂積層体１５０の上に配線１５６が形成される。 After the resin laminate 150 is formed by the above-described procedure, the stage 52 is moved below the first modeling unit 22. Then, in the first printing section 72 of the first modeling unit 22, the inkjet head 76 discharges the metal ink 154 linearly onto the upper surface of the resin laminate 150 according to the circuit pattern, as shown in FIG. Subsequently, in the firing section 74 of the first modeling unit 22, the infrared ray irradiation device 78 irradiates the metal ink 154 ejected according to the circuit pattern with infrared rays. As a result, the metal ink 154 is fired, and the wiring 156 is formed on the resin laminate 150.
　次に、ステージ５２が、第２造形ユニット２４の下方に移動される。そして、第２造形ユニット２４において、図５に示すように、樹脂積層体１５０の上に２層目の樹脂積層体１６０が形成される。樹脂積層体１６０は、樹脂積層体１５０の上面に形成された配線１５６を覆うように形成される。なお、樹脂積層体１６０は、樹脂積層体１５０と同様に、インクジェットヘッド８８による紫外線硬化樹脂の吐出と、照射装置９２による紫外線の照射とが繰り返されることで、形成される。また、樹脂積層体１６０の外寸は樹脂積層体１５０の外寸と同じとされている。 Next, the stage 52 is moved below the second modeling unit 24. Then, in the second modeling unit 24, as shown in FIG. 5, a second layer resin laminate 160 is formed on the resin laminate 150. The resin laminate 160 is formed to cover the wiring 156 formed on the upper surface of the resin laminate 150. Note that, like the resin laminate 150, the resin laminate 160 is formed by repeatedly discharging an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92. Further, the outer dimensions of the resin laminate 160 are the same as the outer dimensions of the resin laminate 150.
　次に、ステージ５２が第１造形ユニット２２の下方に移動される。そして、第１造形ユニット２２の第１印刷部７２において、インクジェットヘッド７６が、図６に示すように、樹脂積層体１６０の上面に金属インク１６２を、回路パターンに応じて線状に吐出する。続いて、金属インク１６２に、第１造形ユニット２２の焼成部７４において、赤外線照射装置７８が赤外線を照射することで、金属インク１６２が焼成し、樹脂積層体１６０の上に配線１６４が形成される。 Next, the stage 52 is moved below the first modeling unit 22. Then, in the first printing section 72 of the first modeling unit 22, the inkjet head 76 discharges the metal ink 162 linearly onto the upper surface of the resin laminate 160 according to the circuit pattern, as shown in FIG. Subsequently, the infrared rays irradiation device 78 irradiates the metal ink 162 with infrared rays in the baking section 74 of the first modeling unit 22, thereby baking the metal ink 162 and forming the wiring 164 on the resin laminate 160. Ru.
　続いて、ステージ５２が、第２造形ユニット２４の下方に移動される。そして、第２造形ユニット２４において、図７に示すように、樹脂積層体１６０の上に３層目の樹脂積層体１７０が形成される。樹脂積層体１７０は、樹脂積層体１６０の上面に形成された配線１６４を覆うように形成される。なお、樹脂積層体１７０も、樹脂積層体１５０と同様に、インクジェットヘッド８８による紫外線硬化樹脂の吐出と、照射装置９２による紫外線の照射とが繰り返されることで、形成される。また、樹脂積層体１７０の外寸も樹脂積層体１５０の外寸と同じとされている。 Subsequently, the stage 52 is moved below the second modeling unit 24. Then, in the second modeling unit 24, a third layer resin laminate 170 is formed on the resin laminate 160, as shown in FIG. The resin laminate 170 is formed to cover the wiring 164 formed on the upper surface of the resin laminate 160. Note that, similarly to the resin laminate 150, the resin laminate 170 is also formed by repeatedly discharging an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92. Furthermore, the outer dimensions of the resin laminate 170 are also the same as the outer dimensions of the resin laminate 150.
　次に、ステージ５２が第１造形ユニット２２の下方に移動される。そして、第１造形ユニット２２の第１印刷部７２において、インクジェットヘッド７６が、図８に示すように、樹脂積層体１７０の上面に金属インク１７２を、回路パターンに応じて線状に吐出する。続いて、金属インク１７２に、第１造形ユニット２２の焼成部７４において、赤外線照射装置７８が赤外線を照射することで、金属インク１７２が焼成し、樹脂積層体１７０の上に配線１７４が形成される。なお、樹脂積層体１７０の上には２本の配線１７４が形成される。 Next, the stage 52 is moved below the first modeling unit 22. Then, in the first printing section 72 of the first modeling unit 22, the inkjet head 76 discharges the metal ink 172 linearly onto the upper surface of the resin laminate 170 according to the circuit pattern, as shown in FIG. Next, the infrared irradiation device 78 irradiates the metal ink 172 with infrared rays in the baking section 74 of the first modeling unit 22, thereby baking the metal ink 172 and forming the wiring 174 on the resin laminate 170. Ru. Note that two wirings 174 are formed on the resin laminate 170.
　続いて、ステージ５２が、第２造形ユニット２４の下方に移動される。そして、第２造形ユニット２４において、図９に示すように、樹脂積層体１７０の上に４層目の樹脂積層体１８０が形成される。樹脂積層体１８０は、樹脂積層体１７０の上面に形成された２本の配線１７４を覆うように形成される。なお、樹脂積層体１８０も、樹脂積層体１５０と同様に、インクジェットヘッド８８による紫外線硬化樹脂の吐出と、照射装置９２による紫外線の照射とが繰り返されることで、形成される。また、樹脂積層体１８０の外寸も樹脂積層体１５０の外寸と同じとされている。 Subsequently, the stage 52 is moved below the second modeling unit 24. Then, in the second modeling unit 24, as shown in FIG. 9, a fourth resin laminate 180 is formed on the resin laminate 170. The resin laminate 180 is formed to cover the two wirings 174 formed on the upper surface of the resin laminate 170. Note that, like the resin laminate 150, the resin laminate 180 is also formed by repeatedly ejecting an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92. Furthermore, the outer dimensions of the resin laminate 180 are also the same as the outer dimensions of the resin laminate 150.
　次に、ステージ５２が第１造形ユニット２２の下方に移動される。そして、第１造形ユニット２２の第１印刷部７２において、インクジェットヘッド７６が、図１０に示すように、樹脂積層体１８０の上面に金属インク１８２を、回路パターンに応じて線状に吐出する。続いて、金属インク１８２に、第１造形ユニット２２の焼成部７４において、赤外線照射装置７８が赤外線を照射することで、金属インク１８２が焼成し、樹脂積層体１８０の上に配線１８４が形成される。なお、樹脂積層体１８０の上には３本の配線１８４が形成される。 Next, the stage 52 is moved below the first modeling unit 22. Then, in the first printing section 72 of the first modeling unit 22, the inkjet head 76 discharges the metal ink 182 linearly onto the upper surface of the resin laminate 180 according to the circuit pattern, as shown in FIG. Subsequently, the infrared irradiation device 78 irradiates the metal ink 182 with infrared rays in the baking section 74 of the first modeling unit 22, thereby baking the metal ink 182 and forming the wiring 184 on the resin laminate 180. Ru. Note that three wirings 184 are formed on the resin laminate 180.
　続いて、ステージ５２が、第２造形ユニット２４の下方に移動される。そして、第２造形ユニット２４において、図１１に示すように、樹脂積層体１８０の上に５層目の樹脂積層体１９０が形成される。樹脂積層体１９０は、樹脂積層体１８０の上面に形成された３本の配線１８４を覆うように形成されるが、樹脂積層体１９０には、３本の配線１８４のうちの２本の配線１８４の互いに対向する端部が露出するキャビティ１９２が形成されている。なお、樹脂積層体１９０も、樹脂積層体１５０と同様に、インクジェットヘッド８８による紫外線硬化樹脂の吐出と、照射装置９２による紫外線の照射とが繰り返されることで、形成される。また、樹脂積層体１９０の外寸も樹脂積層体１５０の外寸と同じとされている。 Subsequently, the stage 52 is moved below the second modeling unit 24. Then, in the second modeling unit 24, as shown in FIG. 11, a fifth layer resin laminate 190 is formed on the resin laminate 180. The resin laminate 190 is formed so as to cover the three wirings 184 formed on the upper surface of the resin laminate 180. A cavity 192 is formed in which mutually opposing ends of are exposed. Note that, like the resin laminate 150, the resin laminate 190 is also formed by repeatedly ejecting an ultraviolet curable resin by the inkjet head 88 and irradiating ultraviolet rays by the irradiation device 92. Furthermore, the outer dimensions of the resin laminate 190 are also the same as the outer dimensions of the resin laminate 150.
　このように、キャビティ１９２を有する樹脂積層体１９０が形成されると、ステージ５２が第３造形ユニット２５の下方に移動される。そして、第３造形ユニット２５の第３印刷部１００において、ディスペンサ１０６が、図１２に示すように、キャビティ１９２の内部で露出する２本の配線１８４の端部の上に導電性樹脂ペースト１９６を吐出する。そして、第３造形ユニット２５の第１加熱部１０２において、導電性樹脂ペースト１９６が、ヒータ１０８により加熱されることで、導電性樹脂ペースト１９６が導電性を発揮する。 After the resin laminate 190 having the cavity 192 is formed in this way, the stage 52 is moved below the third modeling unit 25. Then, in the third printing section 100 of the third modeling unit 25, the dispenser 106 applies a conductive resin paste 196 onto the ends of the two wirings 184 exposed inside the cavity 192, as shown in FIG. Exhale. Then, in the first heating section 102 of the third modeling unit 25, the conductive resin paste 196 is heated by the heater 108, so that the conductive resin paste 196 exhibits conductivity.
　続いて、ステージ５２が装着ユニット２７の下方に移動される。装着ユニット２７では、テープフィーダ１２４により電子部品（図１３参照）２００が供給され、その電子部品２００が装着ヘッド１２６の吸着ノズルによって、保持される。なお、電子部品２００は、部品本体２０２と、部品本体２０２の対向する１対の側面から下方に延び出す２本のリード２０４とにより構成されている。そして、装着ヘッド１２６が、移動装置１２８によって移動され、吸着ノズルにより保持された電子部品２００が、図１３に示すように、キャビティ１９２の内部において樹脂積層体１８０の上面に装着される。この際、電子部品２００のリード２０４が、配線１８４の上に吐出された導電性樹脂ペースト１９６に接触するように、電子部品２００は装着される。 Subsequently, the stage 52 is moved below the mounting unit 27. In the mounting unit 27, an electronic component (see FIG. 13) is supplied by a tape feeder 124, and the electronic component 200 is held by a suction nozzle of a mounting head 126. Note that the electronic component 200 includes a component body 202 and two leads 204 extending downward from a pair of opposing side surfaces of the component body 202. Then, the mounting head 126 is moved by the moving device 128, and the electronic component 200 held by the suction nozzle is mounted on the upper surface of the resin laminate 180 inside the cavity 192, as shown in FIG. At this time, the electronic component 200 is mounted so that the leads 204 of the electronic component 200 come into contact with the conductive resin paste 196 discharged onto the wiring 184.
　このように、回路形成装置１０では、５層の樹脂積層体１５０，１６０，１７０，１８０，１９０が積層され、各樹脂積層体の上面に配線が形成される。そして、導電性樹脂ペースト１９６を介して、電子部品２００のリード２０４が配線に電気的に接続されることで、回路基板２１０が形成される。なお、回路基板２１０では、同じ寸法の５層の樹脂積層体１５０，１６０，１７０，１８０，１９０が積層されているが、近年では、回路基板の軽量化が望まれている。つまり、例えば、ロボットハンドに回路基板が配設される場合には、ロボットハンドの移動速度の向上，制振制御の面から回路基板の軽量化が望まれている。また、例えば、ドローン，ラジコン等に回路基板が配設される場合には、１回の充電で長い時間稼働することができるように、回路基板の軽量化が望まれている。そして、回路形成装置１０では、任意の位置に紫外線硬化樹脂を吐出することで、任意の形状の樹脂積層体を形成することが可能である。このようなことに鑑みて、回路形成装置１０では、同じ寸法の複数の樹脂積層体を積層させるのではなく、配線を支持するとともに覆う箇所にのみ複数の樹脂積層体が形成される。 In this manner, in the circuit forming apparatus 10, five resin laminates 150, 160, 170, 180, and 190 are stacked, and wiring is formed on the top surface of each resin laminate. Then, the leads 204 of the electronic component 200 are electrically connected to the wiring via the conductive resin paste 196, thereby forming the circuit board 210. Note that the circuit board 210 is made up of five layers of resin laminates 150, 160, 170, 180, and 190 having the same dimensions, but in recent years, it has been desired to reduce the weight of the circuit board. That is, for example, when a circuit board is disposed on a robot hand, it is desired to reduce the weight of the circuit board from the viewpoint of improving the moving speed of the robot hand and controlling vibration damping. Furthermore, for example, when a circuit board is installed in a drone, a radio control device, etc., it is desired that the circuit board be made lighter so that it can operate for a long time with a single charge. In the circuit forming apparatus 10, it is possible to form a resin laminate having an arbitrary shape by discharging the ultraviolet curing resin at an arbitrary position. In view of this, in the circuit forming apparatus 10, a plurality of resin laminates are formed only at locations that support and cover the wiring, rather than stacking a plurality of resin laminates having the same dimensions.
　詳しくは、図２に示すように、制御装置２８のコントローラ１３０には、第１設計プログラム２２０と第２設計プログラム２２２とが記憶されている。そして、第１設計プログラム２２０と第２設計プログラム２２２との各々により、配線を支持するとともに覆う箇所及び配線に接続される電子部品を支持する箇所の複数の樹脂積層体が設計される。まず、第１設計プログラム２２０では、複数の樹脂積層体の下方の樹脂積層体から順次、上方の樹脂積層体に向って複数の樹脂積層体が設計される。この際、第１設計プログラム２２０は、配線を支持する箇所と当該配線を覆う箇所に樹脂積層体を加算するとともに、当該配線に接続される電子部品を支持する箇所に樹脂積層体を加算するように複数の樹脂積層体を示す画像データを生成する。 Specifically, as shown in FIG. 2, the controller 130 of the control device 28 stores a first design program 220 and a second design program 222. Then, each of the first design program 220 and the second design program 222 designs a plurality of resin laminates for locations that support and cover the wiring and locations that support electronic components connected to the wiring. First, in the first design program 220, a plurality of resin laminates are designed sequentially from the lower resin laminate to the upper resin laminate. At this time, the first design program 220 adds a resin laminate to a location that supports the wiring and a location that covers the wiring, and also adds a resin laminate to a location that supports the electronic component connected to the wiring. Image data showing a plurality of resin laminates is generated.
　具体的には、まず、第１設計プログラム２２０において、図１４に示すように、回路パターンの設計及び、電子部品の載置位置の設計が行われる（Ｓ１０）。回路パターンの設計及び、電子部品の載置位置の設計は、回路基板の機能等に応じて行われるものであり、従来の手法と同様に設計される。つまり、例えば、図１３の回路基板２１０と同じ機能等を備える回路基板の回路パターン及び、電子部品の載置位置の設計では、図１５に示すように、４層の回路パターンが設計され、電子部品２００の載置位置が設計される。 Specifically, first, in the first design program 220, as shown in FIG. 14, a design of a circuit pattern and a design of a mounting position of an electronic component are performed (S10). The design of the circuit pattern and the design of the mounting position of the electronic components are performed according to the functions of the circuit board, etc., and are designed in the same manner as in the conventional method. In other words, for example, when designing the circuit pattern of a circuit board with the same functions as the circuit board 210 in FIG. 13 and the mounting position of electronic components, a four-layer circuit pattern is designed as shown in FIG. A placement position for the component 200 is designed.
　そして、従来の樹脂積層体の設計では、図１３に示す回路基板２１０のように、同じ寸法の複数の樹脂積層体１５０，１６０，１７０，１８０，１９０が積層されて、全ての配線を支持するとともに覆う樹脂積層体の画像データが生成されていた。一方、第１設計プログラム２２０では、複数の樹脂積層体の下方の樹脂積層体から順次、上方の樹脂積層体に向って複数の樹脂積層体が設計され、この際、配線を支持する箇所と当該配線を覆う箇所に樹脂積層体を加算するように樹脂積層体の画像データが生成される。また、当該配線に電子部品が接続される場合には、その電子部品を支持する箇所にも樹脂積層体を加算するように樹脂積層体の画像データが生成される。このため、まず、Ｓ１０で設計された４層の回路パターンのうちの最下層の回路パターン及び電子部品の載置位置に基づいて、必要な樹脂積層体を加算して樹脂積層体の画像データが生成される（Ｓ１２）。なお、４層の回路パターンのうちの最下層の回路パターン、つまり、下層から１層目の回路パターンに応じた配線１５６に電子部品は接続されない。このため、１層目の回路パターンに応じた配線１５６を支持する箇所と当該配線１５６を覆う箇所に樹脂積層体を加算するように画像データが作成される。具体的には、図１６に示すように、配線１５６を支持する箇所２３０ａと当該配線１５６を覆う箇所２３０ｂの樹脂積層体の画像データが生成される。なお、画像データが生成される際に、配線を支持する配線の真下及び配線を覆う配線の真上だけでなく、配線の端から予め設定された寸法、離れた箇所をも支持する箇所と覆う箇所も含む樹脂積層体の画像データが生成される。 In the conventional resin laminate design, a plurality of resin laminates 150, 160, 170, 180, and 190 having the same dimensions are stacked to support all the wiring, as in the circuit board 210 shown in FIG. Image data of the covering resin laminate was also generated. On the other hand, in the first design program 220, a plurality of resin laminates are designed sequentially from the lower resin laminate to the upper resin laminate. Image data of the resin laminate is generated such that the resin laminate is added to the area covering the wiring. Further, when an electronic component is connected to the wiring, image data of the resin laminate is generated so that the resin laminate is also added to a location that supports the electronic component. For this reason, first, the image data of the resin laminate is created by adding the necessary resin laminate based on the lowest circuit pattern of the four-layer circuit pattern designed in S10 and the mounting position of the electronic component. is generated (S12). Note that no electronic component is connected to the wiring 156 corresponding to the circuit pattern in the lowest layer among the four layers of circuit patterns, that is, the circuit pattern in the first layer from the bottom. For this reason, image data is created such that the resin laminate is added to a location that supports the wiring 156 and a location that covers the wiring 156 according to the first layer circuit pattern. Specifically, as shown in FIG. 16, image data of the resin laminate at a location 230a that supports the wiring 156 and a location 230b that covers the wiring 156 is generated. Note that when image data is generated, not only the area directly below the wiring that supports the wiring and the area directly above the wiring that covers the wiring, but also the part that supports and covers the area that is a preset dimension and away from the end of the wiring. Image data of the resin laminate including the location is generated.
　次に、第１設計プログラム２２０において、Ｓ１２での処理が最上層の回路パターンに基づいて樹脂積層体の画像データが生成された否かが判断される（Ｓ１４）。つまり、全ての層の回路パターンに基づいて樹脂積層体の画像データが生成された否かが判断される。この際、上記説明では、１層目の回路パターンに基づいて樹脂積層体の画像データが生成されているため、最上層の回路パターンに基づいて樹脂積層体の画像データは生成されていないと判断される（Ｓ１４：ＮＯ）。そして、一層上の回路パターン及び電子部品の載置位置に基づいて、必要な樹脂積層体を加算して樹脂積層体の画像データが生成される（Ｓ１６）。つまり、２層目の回路パターン及び電子部品の載置位置に基づいて、必要な樹脂積層体を加算して樹脂積層体の画像データが生成される。なお、図１７に示すように、２層目の回路パターンに応じた配線１６４に電子部品は接続されない。このため、２層目の回路パターンに応じた配線１６４を支持する箇所と当該配線１６４を覆う箇所に樹脂積層体を加算するように画像データが作成される。つまり、配線１６４を支持する箇所２３２ａと当該配線１６４を覆う箇所２３２ｂの樹脂積層体の画像データが生成される。なお、配線１６４を支持する箇所２３２ａの樹脂積層体の画像データは、先に生成されている樹脂積層体の画像データと異なる箇所のみの樹脂積層体の画像データである。つまり、配線１５６に基づいて生成された箇所２３０の樹脂積層体を除いて、配線１６４を支持する箇所２３２ａの樹脂積層体の画像データが生成される。 Next, in the first design program 220, it is determined whether the image data of the resin laminate has been generated based on the circuit pattern of the uppermost layer in the process in S12 (S14). That is, it is determined whether the image data of the resin laminate has been generated based on the circuit patterns of all the layers. At this time, in the above explanation, since the image data of the resin laminate is generated based on the circuit pattern of the first layer, it is determined that the image data of the resin laminate is not generated based on the circuit pattern of the top layer. (S14: NO). Then, image data of the resin laminate is generated by adding the necessary resin laminate based on the circuit pattern on the upper layer and the placement position of the electronic component (S16). That is, image data of the resin laminate is generated by adding the necessary resin laminate based on the circuit pattern of the second layer and the mounting position of the electronic component. Note that, as shown in FIG. 17, no electronic component is connected to the wiring 164 according to the second layer circuit pattern. For this reason, image data is created such that the resin laminate is added to a location that supports the wiring 164 and a location that covers the wiring 164 according to the second layer circuit pattern. In other words, image data of the resin laminate of the portion 232a that supports the wiring 164 and the portion 232b that covers the wiring 164 is generated. Note that the image data of the resin laminate at the portion 232a that supports the wiring 164 is the image data of the resin laminate only at a portion that is different from the previously generated image data of the resin laminate. That is, image data of the resin laminate at the location 232a that supports the wiring 164 is generated, excluding the resin laminate at the location 230 that is generated based on the wiring 156.
　次に、再度、Ｓ１４において、最上層の回路パターンに基づいて樹脂積層体の画像データが生成された否かが判断される（Ｓ１４）。この際、上記説明では、２層目の回路パターンに基づいて樹脂積層体の画像データが生成されているため、最上層の回路パターンに基づいて樹脂積層体の画像データは生成されていないと判断される（Ｓ１４：ＮＯ）。そして、一層上の回路パターン、つまり、３層目の回路パターン及び電子部品の載置位置に基づいて、必要な樹脂積層体を加算して樹脂積層体の画像データが生成される（Ｓ１６）。なお、図１８に示すように、３層目の回路パターンに応じた配線１７４に電子部品は接続されない。このため、３層目の回路パターンに応じた配線１７４を支持する箇所と当該配線１７４を覆う箇所に樹脂積層体を加算するように画像データが作成される。つまり、配線１７４を支持する箇所２３４ａと当該配線１７４を覆う箇所２３４ｂの樹脂積層体の画像データが生成される。なお、配線１７４を支持する箇所２３４ａの樹脂積層体の画像データは、先に生成されている樹脂積層体の画像データと異なる箇所のみの樹脂積層体の画像データである。つまり、配線１６４に基づいて生成された箇所２３２の樹脂積層体を除いて、配線１７４を支持する箇所２３４ａの樹脂積層体の画像データが生成される。 Next, in S14 again, it is determined whether image data of the resin laminate has been generated based on the circuit pattern of the uppermost layer (S14). At this time, in the above explanation, since the image data of the resin laminate is generated based on the circuit pattern of the second layer, it is determined that the image data of the resin laminate is not generated based on the circuit pattern of the top layer. (S14: NO). Then, the image data of the resin laminate is generated by adding the necessary resin laminate based on the circuit pattern on the upper layer, that is, the third layer circuit pattern and the placement position of the electronic component (S16). Note that, as shown in FIG. 18, no electronic component is connected to the wiring 174 according to the third layer circuit pattern. For this reason, image data is created such that the resin laminate is added to a location that supports the wiring 174 and a location that covers the wiring 174 according to the third layer circuit pattern. In other words, image data of the resin laminate of the portion 234a that supports the wiring 174 and the portion 234b that covers the wiring 174 is generated. Note that the image data of the resin laminate at the portion 234a that supports the wiring 174 is the image data of the resin laminate only at a portion that is different from the previously generated image data of the resin laminate. That is, image data of the resin laminate at the location 234a that supports the wiring 174 is generated, excluding the resin laminate at the location 232 that is generated based on the wiring 164.
　次に、再度、Ｓ１４において、最上層の回路パターンに基づいて樹脂積層体の画像データが生成された否かが判断される（Ｓ１４）。この際、上記説明では、３層目の回路パターンに基づいて樹脂積層体の画像データが生成されているため、最上層の回路パターンに基づいて樹脂積層体の画像データは生成されていないと判断される（Ｓ１４：ＮＯ）。そして、一層上の回路パターン、つまり、４層目の回路パターン及び電子部品の載置位置に基づいて、必要な樹脂積層体を加算して樹脂積層体の画像データが生成される（Ｓ１６）。なお、図１９に示すように、４層目の回路パターンに応じた配線１８４には電子部品２００が接続される。このため、４層目の回路パターンに応じた配線１８４を支持する箇所と当該配線１８４を覆う箇所及び、電子部品２００を支持する箇所に樹脂積層体を加算するように画像データが作成される。つまり、配線１８４及び電子部品２００を支持する箇所２３６ａと当該配線１８４を覆う箇所２３６ｂの樹脂積層体の画像データが生成される。なお、配線１８４及び電子部品２００を支持する箇所２３６ａの樹脂積層体の画像データは、先に生成されている樹脂積層体の画像データと異なる箇所のみの樹脂積層体の画像データである。つまり、配線１７４に基づいて生成された箇所２３４の樹脂積層体を除いて、配線１８４及び電子部品２００を支持する箇所２３６ａの樹脂積層体の画像データが生成される。また、配線１８４を覆う箇所２３６ｂの樹脂積層体の画像データは、電子部品２００を装着するためのキャビティ１９２を除いて生成される。 Next, in S14 again, it is determined whether image data of the resin laminate has been generated based on the circuit pattern of the uppermost layer (S14). At this time, in the above explanation, since the image data of the resin laminate is generated based on the circuit pattern of the third layer, it is determined that the image data of the resin laminate is not generated based on the circuit pattern of the top layer. (S14: NO). Then, the image data of the resin laminate is generated by adding the necessary resin laminate based on the circuit pattern on the upper layer, that is, the fourth layer circuit pattern and the placement position of the electronic component (S16). Note that, as shown in FIG. 19, an electronic component 200 is connected to the wiring 184 according to the fourth layer circuit pattern. For this reason, image data is created such that the resin laminate is added to a location that supports the wiring 184 according to the fourth layer circuit pattern, a location that covers the wiring 184, and a location that supports the electronic component 200. In other words, image data of the resin laminate of a portion 236a that supports the wiring 184 and the electronic component 200 and a portion 236b that covers the wiring 184 is generated. Note that the image data of the resin laminate at the portion 236a that supports the wiring 184 and the electronic component 200 is the image data of the resin laminate only at a portion that is different from the previously generated image data of the resin laminate. That is, image data of the resin laminate at the location 236a that supports the wiring 184 and the electronic component 200 is generated, excluding the resin laminate at the location 234 that is generated based on the wiring 174. Further, the image data of the resin laminate at the portion 236b covering the wiring 184 is generated excluding the cavity 192 for mounting the electronic component 200.
　続いて、再度、Ｓ１４において、最上層の回路パターンに基づいて樹脂積層体の画像データが生成された否かが判断される（Ｓ１４）。この際、上記説明では、４層目の回路パターンに基づいて樹脂積層体の画像データが生成されているため、最上層の回路パターンに基づいて樹脂積層体の画像データが生成されたと判断される（Ｓ１４：ＹＥＳ）。つまり、全ての層の回路パターンに基づいて樹脂積層体の画像データが生成されたと判断される。これにより、全ての樹脂積層体の画像データの生成が完了する（Ｓ１８）。つまり、各層の回路パターンに応じた配線及び配線に接続される電子部品に基づいて生成された箇所２３０，２３２，２３４，２３６の樹脂積層体の画像データが生成される。そして、生成された画像データに基づいて樹脂積層体が形成されると、図２０に示すように、積層された５層の樹脂積層体２５０～２５４により構成される回路基板２６０が形成される。つまり、第１設計プログラム２２０により生成された画像データに基づいて樹脂積層体が形成されると、配線及び電子部品を支持する箇所及び配線を覆う箇所のみに樹脂積層体が形成された回路基板２６０が形成される。 Subsequently, in S14 again, it is determined whether image data of the resin laminate has been generated based on the circuit pattern of the uppermost layer (S14). At this time, in the above explanation, since the image data of the resin laminate is generated based on the circuit pattern of the fourth layer, it is determined that the image data of the resin laminate is generated based on the circuit pattern of the top layer. (S14: YES). In other words, it is determined that the image data of the resin laminate has been generated based on the circuit patterns of all the layers. This completes the generation of image data for all resin laminates (S18). That is, image data of the resin laminate at locations 230, 232, 234, and 236 is generated based on the wiring according to the circuit pattern of each layer and the electronic components connected to the wiring. Then, when a resin laminate is formed based on the generated image data, a circuit board 260 made up of the five layers of resin laminates 250 to 254 is formed, as shown in FIG. In other words, when the resin laminate is formed based on the image data generated by the first design program 220, the circuit board 260 has the resin laminate formed only in areas that support wiring and electronic components and areas that cover the wiring. is formed.
　また、第２設計プログラム２２２では、複数の樹脂積層体の上方の樹脂積層体から順次、下方の樹脂積層体に向って複数の樹脂積層体が設計される。この際、第２設計プログラム２２２は、従来の手法で設計された複数の樹脂積層体の仮想の画像（以下、「仮想画像」と記載する）から、配線の支持及び被覆に不要な箇所と、電子部品の支持に不要な箇所とを削除することで複数の樹脂積層体を示す画像データを生成する。なお、仮想画像は、従来の手法で設計された複数の樹脂積層体の画像であり、図１３の回路基板２１０を構成する５層の樹脂積層体１５０，１６０，１７０，１８０，１９０の画像である。つまり、仮想画像は、同じ寸法の樹脂積層体を５層積層させて、回路基板２１０の全ての配線１５６，１６４，１７４，１８４を支持するとともに覆って、全ての電子部品２００を支持する樹脂積層体の画像である。 Furthermore, in the second design program 222, a plurality of resin laminates are designed sequentially from the upper resin laminate to the lower resin laminate. At this time, the second design program 222 identifies parts unnecessary for supporting and covering the wiring from virtual images (hereinafter referred to as "virtual images") of the plurality of resin laminates designed using the conventional method. Image data showing a plurality of resin laminates is generated by deleting portions unnecessary for supporting electronic components. The virtual image is an image of a plurality of resin laminates designed using a conventional method, and is an image of five resin laminates 150, 160, 170, 180, and 190 that constitute the circuit board 210 in FIG. be. In other words, the virtual image shows a resin laminate that supports and covers all the wiring 156, 164, 174, 184 of the circuit board 210 by laminating five resin laminates of the same size, and supports all the electronic components 200. It is an image of the body.
　具体的に、第２設計プログラム２２２では、図２１に示すように、回路パターンの設計及び、電子部品の載置位置の設計が行われる（Ｓ２０）。第２設計プログラム２２２での回路パターンの設計及び、電子部品の載置位置の設計は、第１設計プログラム２２０での回路パターンの設計及び、電子部品の載置位置の設計と同じである。このため、例えば、図１３の回路基板２１０と同じ機能等を備える回路基板の回路パターン及び、電子部品の載置位置の設計では、図１５に示すように、４層の回路パターンが設計され、電子部品２００の載置位置が設計される。 Specifically, in the second design program 222, as shown in FIG. 21, a design of a circuit pattern and a design of a mounting position of an electronic component are performed (S20). The design of the circuit pattern and the design of the mounting position of the electronic component in the second design program 222 are the same as the design of the circuit pattern and the design of the mounting position of the electronic component in the first design program 220. For this reason, for example, when designing the circuit pattern of a circuit board with the same functions as the circuit board 210 in FIG. 13 and the mounting position of electronic components, a four-layer circuit pattern is designed as shown in FIG. A placement position for electronic component 200 is designed.
　次に、仮想画像が設計される（Ｓ２２）。仮想画像は、上述したように、回路基板２１０を構成する５層の樹脂積層体１５０，１６０，１７０，１８０，１９０の画像であるため、図２２に示すように、５層の仮想画像２７０が設計される。なお、５層の仮想画像２７０の各々を区別する場合に、上方の仮想画像から順に、１層目の仮想画像２７０ａ，２層目の仮想画像２７０ｂ，３層目の仮想画像２７０ｃ，４層目の仮想画像２７０ｄ，５層目の仮想画像２７０ｅと記載する。 Next, a virtual image is designed (S22). As described above, the virtual image is an image of the five layers of resin laminates 150, 160, 170, 180, and 190 that constitute the circuit board 210, so as shown in FIG. Designed. Note that when distinguishing each of the five layers of virtual images 270, in order from the upper virtual image, the first layer virtual image 270a, the second layer virtual image 270b, the third layer virtual image 270c, and the fourth layer virtual image A virtual image 270d of the fifth layer and a virtual image 270e of the fifth layer.
　そして、第２設計プログラム２２２では、１層目の仮想画像２７０ａから５層目の仮想画像２７０ｅまで順次、各層の仮想画像２７０から配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とを削除することで樹脂積層体の画像データが生成される。このため、まず、Ｓ２２で設計された５層の仮想画像２７０のうちの最上層の仮想画像２７０ａから配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とを削除することで樹脂積層体の画像データが生成される（Ｓ２４）。なお、最上層の仮想画像２７０ａでは、最上層の回路パターンに応じた配線１８４に基づいて、配線の被覆に不要な箇所が特定される。具体的には、図２３に示すように、最上層の仮想画像２７０ａの範囲から配線１８４の被覆に不要な箇所２８０が特定される。なお、配線の被覆に不要な箇所は、配線を被覆しない箇所であるが、配線だけでなく、配線の端から予め設定された寸法、離れた箇所も被覆しない箇所である。そして、配線１８４の被覆に不要な箇所２８０が特定されると、最上層の仮想画像２７０ａから配線１８４の被覆に不要な箇所２８０が削除されて、図２４に示すように、最上層の樹脂積層体３００の画像データが生成される。 Then, in the second design program 222, from the virtual image 270a of the first layer to the virtual image 270e of the fifth layer, from the virtual image 270 of each layer, areas unnecessary for supporting and covering wiring and areas unnecessary for supporting electronic components are Image data of the resin laminate is generated by deleting the locations. For this reason, first, parts unnecessary for supporting and covering the wiring and parts unnecessary for supporting the electronic components are deleted from the virtual image 270a of the top layer of the five-layer virtual image 270 designed in S22. Image data of the resin laminate is generated (S24). In addition, in the virtual image 270a of the top layer, unnecessary portions of the wiring are identified based on the wiring 184 according to the circuit pattern of the top layer. Specifically, as shown in FIG. 23, a portion 280 that is unnecessary for covering the wiring 184 is identified from the range of the uppermost layer virtual image 270a. Incidentally, the unnecessary portions for covering the wiring are the portions where the wiring is not covered, and are not only the portions where the wiring is not covered but also the portions which are separated by a predetermined dimension from the end of the wiring. Then, when a portion 280 unnecessary for covering the wiring 184 is identified, the portion 280 unnecessary for covering the wiring 184 is deleted from the virtual image 270a of the uppermost layer, and as shown in FIG. Image data of the body 300 is generated.
　次に、第２設計プログラム２２２において、Ｓ２４での処理が最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データが生成された否かが判断される（Ｓ２６）。つまり、全ての層の仮想画像２７０に基づいて樹脂積層体の画像データが生成された否かが判断される。この際、上記説明では、最上層、つまり、１層目の仮想画像２７０ａに基づいて樹脂積層体の画像データが生成されているため、最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データは生成されていないと判断される（Ｓ２６：ＮＯ）。そして、一層下の仮想画像２７０、つまり、２層目の仮想画像２７０ｂから配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とを削除することで樹脂積層体の画像データが生成される（Ｓ２８）。なお、２層目の仮想画像２７０ｂでは、最上層の回路パターン及び２層目の回路パターンに応じた配線１７４，１８４と電子部品２００とに基づいて、配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とが特定される。具体的には、図２４に示すように、２層目の仮想画像２７０ｂの範囲から配線１８４及び電子部品２００の支持に不要であり、配線１７４の被覆に不要な箇所２８２が特定される。なお、配線の支持に不要な箇所は、配線を支持しない箇所であるが、配線だけでなく、配線の端から予め設定された寸法、離れた箇所も支持しない箇所である。また、電子部品の支持に不要な箇所は、電子部品の真下を除く箇所であるが、電子部品の真下だけでなく、電子部品の端から予め設定された寸法、離れた箇所の真下も除く箇所である。そして、配線１８４及び電子部品２００の支持に不要であり、配線１７４の被覆に不要な箇所２８２が特定されると、２層目の仮想画像２７０ｂから不要な箇所２８２が削除されて、図２５に示すように、２層目の樹脂積層体３０２の画像データが生成される。 Next, in the second design program 222, it is determined whether the image data of the resin laminate has been generated based on the virtual image 270e of the lowest layer in the process in S24 (S26). That is, it is determined whether image data of the resin laminate has been generated based on the virtual images 270 of all layers. At this time, in the above description, since the image data of the resin laminate is generated based on the virtual image 270a of the top layer, that is, the first layer, the image data of the resin laminate is generated based on the virtual image 270e of the bottom layer. is determined to have not been generated (S26: NO). Then, the image data of the resin laminate is created by deleting parts unnecessary for supporting and covering the wiring and parts unnecessary for supporting the electronic components from the lower virtual image 270, that is, the second layer virtual image 270b. is generated (S28). In addition, in the virtual image 270b of the second layer, based on the circuit pattern of the top layer and the wirings 174, 184 and the electronic component 200 according to the circuit pattern of the second layer, parts unnecessary for supporting and covering the wiring and electronic parts are removed. Locations that are unnecessary for supporting the component are identified. Specifically, as shown in FIG. 24, a location 282 that is unnecessary for supporting the wiring 184 and the electronic component 200 and unnecessary for covering the wiring 174 is identified from the range of the second layer virtual image 270b. Incidentally, a location unnecessary for supporting the wiring is a location that does not support the wiring, but is also a location that does not support not only the wiring but also a location that is a predetermined distance away from the end of the wiring. In addition, locations that are unnecessary for supporting electronic components are locations other than directly below the electronic components, but are not limited to locations that are not just directly below the electronic components, but also locations that are a preset distance from the edge of the electronic components, excluding locations directly below the electronic components. It is. Then, when a portion 282 that is unnecessary for supporting the wiring 184 and the electronic component 200 and is unnecessary for covering the wiring 174 is specified, the unnecessary portion 282 is deleted from the second layer virtual image 270b and shown in FIG. As shown, image data of the second layer resin laminate 302 is generated.
　続いて、再度、Ｓ２６において、Ｓ２８での処理が最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データが生成された否かが判断される（Ｓ２６）。この際、上記説明では、２層目の仮想画像２７０ｂに基づいて樹脂積層体の画像データが生成されているため、最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データは生成されていないと判断される（Ｓ２６：ＮＯ）。そして、一層下の仮想画像２７０、つまり、３層目の仮想画像２７０ｃから配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とを削除することで樹脂積層体の画像データが生成される（Ｓ２８）。なお、３層目の仮想画像２７０ｃでは、最上層の回路パターンから３層目の回路パターンまでの３層分の回路パターンに応じた配線１６４，１７４，１８４と電子部品２００とに基づいて、配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とが特定される。具体的には、図２５に示すように、３層目の仮想画像２７０ｃの範囲から配線１７４，１８４及び電子部品２００の支持に不要であり、配線１６４の被覆に不要な箇所２８４が特定される。そして、配線１７４，１８４及び電子部品２００の支持に不要であり、配線１６４の被覆に不要な箇所２８４が特定されると、３層目の仮想画像２７０ｃから不要な箇所２８４が削除されて、図２６に示すように、３層目の樹脂積層体３０４の画像データが生成される。 Subsequently, in S26, it is determined again whether the image data of the resin laminate has been generated based on the virtual image 270e of the lowest layer in the process in S28 (S26). At this time, in the above description, since the image data of the resin laminate is generated based on the second layer virtual image 270b, the image data of the resin laminate is not generated based on the bottom layer virtual image 270e. It is determined that (S26: NO). Then, the image data of the resin laminate is created by deleting the parts unnecessary for supporting and covering the wiring and the parts unnecessary for supporting the electronic components from the virtual image 270 on the lower layer, that is, the virtual image 270c of the third layer. is generated (S28). Note that in the third layer virtual image 270c, wiring is performed based on the wiring 164, 174, 184 and the electronic component 200 according to the circuit patterns of three layers from the top layer circuit pattern to the third layer circuit pattern. Areas unnecessary for supporting and covering electronic components and areas unnecessary for supporting electronic components are identified. Specifically, as shown in FIG. 25, a portion 284 that is unnecessary for supporting the wirings 174, 184 and the electronic component 200 and unnecessary for covering the wiring 164 is identified from the range of the third layer virtual image 270c. . Then, when a location 284 that is unnecessary for supporting the wirings 174, 184 and the electronic component 200 and unnecessary for covering the wiring 164 is identified, the unnecessary location 284 is deleted from the third layer virtual image 270c, and the unnecessary location 284 is deleted from the third layer virtual image 270c. As shown in 26, image data of the third layer resin laminate 304 is generated.
　続いて、再度、Ｓ２６において、Ｓ２８での処理が最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データが生成された否かが判断される（Ｓ２６）。この際、上記説明では、３層目の仮想画像２７０ｃに基づいて樹脂積層体の画像データが生成されているため、最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データは生成されていないと判断される（Ｓ２６：ＮＯ）。そして、一層下の仮想画像２７０、つまり、４層目の仮想画像２７０ｄから配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とを削除することで樹脂積層体の画像データが生成される（Ｓ２８）。なお、４層目の仮想画像２７０ｄでは、最上層の回路パターンから４層目の回路パターンまでの４層分の回路パターンに応じた配線１５６，１６４，１７４，１８４と電子部品２００とに基づいて、配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とが特定される。具体的には、４層目の仮想画像２７０ｄの範囲から配線１６４，１７４，１８４及び電子部品２００の支持に不要であり、配線１５６の被覆に不要な箇所が特定される。ただし、４層目の仮想画像２７０ｄの範囲内に、配線１６４，１７４，１８４及び電子部品２００の支持に不要であり、配線１５６の被覆に不要な箇所はない。このため、４層目の仮想画像２７０ｄから削除される箇所はなく、４層目の仮想画像２７０ｄと同じ位置に４層目の樹脂積層体３０６の画像データが生成される。 Subsequently, in S26, it is determined again whether the image data of the resin laminate has been generated based on the virtual image 270e of the lowest layer in the process in S28 (S26). At this time, in the above description, since the image data of the resin laminate is generated based on the virtual image 270c of the third layer, the image data of the resin laminate is not generated based on the virtual image 270e of the lowest layer. It is determined that (S26: NO). Then, the image data of the resin laminate is created by deleting parts unnecessary for supporting and covering the wiring and parts unnecessary for supporting the electronic components from the virtual image 270 on the lower layer, that is, the virtual image 270d of the fourth layer. is generated (S28). In addition, in the fourth layer virtual image 270d, based on the wirings 156, 164, 174, 184 and the electronic component 200 according to the circuit patterns for four layers from the top layer circuit pattern to the fourth layer circuit pattern. , locations unnecessary for supporting and covering wiring and locations unnecessary for supporting electronic components are identified. Specifically, locations that are unnecessary for supporting the wirings 164, 174, 184 and the electronic component 200, and unnecessary for covering the wiring 156 are identified from the range of the fourth layer virtual image 270d. However, within the range of the fourth layer virtual image 270d, there are no locations that are unnecessary for supporting the wirings 164, 174, 184 and the electronic component 200, and are unnecessary for covering the wiring 156. Therefore, no portion is deleted from the fourth layer virtual image 270d, and image data of the fourth layer resin laminate 306 is generated at the same position as the fourth layer virtual image 270d.
　続いて、再度、Ｓ２６において、Ｓ２８での処理が最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データが生成された否かが判断される（Ｓ２６）。この際、上記説明では、４層目の仮想画像２７０ｄに基づいて樹脂積層体の画像データが生成されているため、最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データは生成されていないと判断される（Ｓ２６：ＮＯ）。そして、一層下の仮想画像２７０、つまり、５層目の仮想画像２７０ｅから配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とを削除することで樹脂積層体の画像データが生成される（Ｓ２８）。なお、５層目の仮想画像２７０ｅでは、最上層の回路パターンから４層目の回路パターンまでの４層分の回路パターンに応じた配線１５６，１６４，１７４，１８４と電子部品２００とに基づいて、配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とが特定される。具体的には、５層目の仮想画像２７０ｅの範囲から配線１５６，１６４，１７４，１８４及び電子部品２００の支持に不要な箇所が特定される。ただし、５層目の仮想画像２７０ｅの範囲内に、配線１５６，１６４，１７４，１８４及び電子部品２００の支持に不要な箇所はない。このため、５層目の仮想画像２７０ｅから削除される箇所はなく、５層目の仮想画像２７０ｅと同じ位置に５層目の樹脂積層体３０８の画像データが生成される。 Subsequently, in S26, it is determined again whether the image data of the resin laminate has been generated based on the virtual image 270e of the lowest layer in the process in S28 (S26). At this time, in the above description, since the image data of the resin laminate is generated based on the virtual image 270d of the fourth layer, the image data of the resin laminate is not generated based on the virtual image 270e of the lowest layer. It is determined that (S26: NO). Then, the image data of the resin laminate is created by deleting parts unnecessary for supporting and covering the wiring and parts unnecessary for supporting the electronic components from the virtual image 270 on the lower layer, that is, the virtual image 270e of the fifth layer. is generated (S28). In addition, in the virtual image 270e of the fifth layer, based on the wirings 156, 164, 174, 184 and the electronic component 200 according to the circuit patterns of four layers from the circuit pattern of the top layer to the circuit pattern of the fourth layer. , locations unnecessary for supporting and covering wiring and locations unnecessary for supporting electronic components are identified. Specifically, locations unnecessary for supporting the wirings 156, 164, 174, 184 and the electronic component 200 are identified from the range of the fifth layer virtual image 270e. However, within the range of the fifth layer virtual image 270e, there are no locations unnecessary for supporting the wirings 156, 164, 174, 184 and the electronic component 200. Therefore, no portion is deleted from the fifth layer virtual image 270e, and image data of the fifth layer resin laminate 308 is generated at the same position as the fifth layer virtual image 270e.
　続いて、再度、Ｓ２６において、最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データが生成された否かが判断される（Ｓ２６）。この際、上記説明では、５層目の仮想画像２７０ｅに基づいて樹脂積層体の画像データが生成されているため、最下層の仮想画像２７０ｅに基づいて樹脂積層体の画像データが生成されたと判断される（Ｓ２６：ＹＥＳ）。つまり、全ての層の仮想画像２７０に基づいて樹脂積層体の画像データが生成されたと判断される。これにより、全ての樹脂積層体の画像データの生成が完了する（Ｓ３０）。つまり、各層の仮想画像２７０から配線の支持及び被覆に不要な箇所と電子部品の支持に不要な箇所とが削除されることで複数の樹脂積層体の画像データが生成される。そして、生成された画像データに基づいて樹脂積層体が形成されると、図２７に示すように、積層された５層の樹脂積層体３００～３０８により構成される回路基板３１０が形成される。つまり、第２設計プログラム２２２により生成された画像データに基づいて樹脂積層体が形成されると、仮想画像から配線及び電子部品の支持に不要な箇所及び配線の被覆に不要な箇所の樹脂積層体が削除されて、配線及び電子部品を支持する箇所及び配線を覆う箇所のみに樹脂積層体が形成された回路基板３１０が形成される。なお、回路基板２６０及び回路基板３１０は略同じ形状である。つまり、第１設計プログラム２２０より生成される樹脂積層体の画像データと、第２設計プログラム２２２により生成される樹脂積層体の画像データとは略同じものとなる。 Subsequently, in S26, it is determined again whether image data of the resin laminate has been generated based on the virtual image 270e of the lowest layer (S26). At this time, in the above explanation, since the image data of the resin laminate is generated based on the virtual image 270e of the fifth layer, it is determined that the image data of the resin laminate is generated based on the virtual image 270e of the lowest layer. (S26: YES). In other words, it is determined that the image data of the resin laminate has been generated based on the virtual images 270 of all the layers. This completes the generation of image data for all resin laminates (S30). That is, image data of a plurality of resin laminates are generated by deleting portions unnecessary for supporting and covering wiring and portions unnecessary for supporting electronic components from the virtual image 270 of each layer. Then, when a resin laminate is formed based on the generated image data, a circuit board 310 made up of the five layers of resin laminates 300 to 308 is formed, as shown in FIG. In other words, when a resin laminate is formed based on the image data generated by the second design program 222, the resin laminate is formed in areas unnecessary for supporting wiring and electronic components and areas unnecessary for covering wiring from the virtual image. is removed, and a circuit board 310 is formed in which the resin laminate is formed only at locations that support the wiring and electronic components and locations that cover the wiring. Note that the circuit board 260 and the circuit board 310 have substantially the same shape. In other words, the image data of the resin laminate generated by the first design program 220 and the image data of the resin laminate generated by the second design program 222 are approximately the same.
　このように、第１設計プログラム２２０、若しくは第２設計プログラム２２２により樹脂積層体の画像データを作成することで、回路基板２６０，３１０では、配線及び電子部品を支持する箇所及び配線を覆う箇所のみに樹脂積層体が形成される。つまり、第１設計プログラム２２０、若しくは第２設計プログラム２２２を用いることで、回路基板２６０，３１０では、回路基板２１０と比較して判るように、配線及び電子部品の支持に不要な箇所及び配線の被覆に不要な箇所の樹脂積層体が削除されている。これにより、回路基板の軽量化を図ることが可能となる。また、配線及び電子部品の支持に不要な箇所及び配線の被覆に不要な箇所の樹脂積層体を形成する必要がなくなるため、樹脂積層体の形成に要する時間の短縮及び、樹脂積層体の材料の削減をも図ることが可能となる。さらに言えば、第１設計プログラム２２０、若しくは第２設計プログラム２２２により樹脂積層体の画像データが生成されるため、回路基板の設計に要する時間の短縮をも図ることが可能となる。 In this way, by creating the image data of the resin laminate using the first design program 220 or the second design program 222, on the circuit boards 260, 310, only the parts that support wiring and electronic components and the parts that cover the wiring can be created. A resin laminate is formed. In other words, by using the first design program 220 or the second design program 222, the circuit boards 260 and 310 are free of unnecessary parts and wiring for supporting wiring and electronic components, as can be seen from the comparison with the circuit board 210. The resin laminate in areas unnecessary for coating has been removed. This makes it possible to reduce the weight of the circuit board. In addition, since it is no longer necessary to form resin laminates in areas unnecessary for supporting wiring and electronic components and areas unnecessary for covering wiring, the time required to form resin laminates can be shortened, and the material of resin laminates can be reduced. It is also possible to reduce the amount of water used. Furthermore, since the image data of the resin laminate is generated by the first design program 220 or the second design program 222, it is possible to reduce the time required to design the circuit board.
　なお、上記実施例において、配線１５６，１６４，１７４，１８４は、配線の一例である。電子部品２００は、電子部品の一例である。第１設計プログラム２２０は、設計プログラムの一例である。第２設計プログラム２２２は、設計プログラムの一例である。樹脂積層体２５０，２５１，２５２，２５３，２５４は、樹脂層の一例である。回路基板２６０は、回路基板の一例である。仮想画像２７０は、仮想画像の一例である。樹脂積層体３００，３０２，３０４，３０６，３０８は、樹脂層の一例である。回路基板３１０は、回路基板の一例である。 Note that in the above embodiment, the wirings 156, 164, 174, and 184 are examples of wirings. Electronic component 200 is an example of an electronic component. The first design program 220 is an example of a design program. The second design program 222 is an example of a design program. The resin laminates 250, 251, 252, 253, and 254 are examples of resin layers. Circuit board 260 is an example of a circuit board. Virtual image 270 is an example of a virtual image. The resin laminates 300, 302, 304, 306, and 308 are examples of resin layers. Circuit board 310 is an example of a circuit board.
　なお、本発明は、上記実施例に限定されるものではなく、当業者の知識に基づいて種々の変更、改良を施した種々の態様で実施することが可能である。例えば、上記実施例では、回路形成装置１０の制御装置２８に第１設計プログラム２２０及び第２設計プログラム２２２が記憶されているが、回路形成装置１０と異なる装置、例えば、回路基板の設計に用いられる情報処理装置に、第１設計プログラム２２０及び第２設計プログラム２２２が記憶されていてもよい。 Note that the present invention is not limited to the above-mentioned embodiments, but can be implemented in various forms with various modifications and improvements based on the knowledge of those skilled in the art. For example, in the above embodiment, the first design program 220 and the second design program 222 are stored in the control device 28 of the circuit forming apparatus 10, but the The first design program 220 and the second design program 222 may be stored in the information processing device.
　また、上記実施例では、樹脂積層体を形成するための硬化性樹脂として紫外線硬化樹脂が採用されているが、熱硬化性樹脂，２液混合型樹脂など、種々の樹脂を採用することが可能である。 Furthermore, in the above example, an ultraviolet curable resin is used as the curable resin for forming the resin laminate, but it is possible to use various resins such as thermosetting resins and two-component mixed resins. It is.
　１５６：配線　　１６４：配線　　１７４：配線　　１８４：配線　　２００：電子部品　　２２０：第１設計プログラム（設計プログラム）　　２２２：第２設計プログラム（設計プログラム）　　２５０：樹脂積層体（樹脂層）　　２５１：樹脂積層体（樹脂層）　　２５２：樹脂積層体（樹脂層）　　２５３：樹脂積層体（樹脂層）　　２５４：樹脂積層体（樹脂層）　　２６０：回路基板　　２７０：仮想画像　　３００：樹脂積層体（樹脂層）　　３０２：樹脂積層体（樹脂層）　　３０４：樹脂積層体（樹脂層）　　３０６：樹脂積層体（樹脂層）　　３０８：樹脂積層体（樹脂層）　　３１０：回路基板 156: Wiring 164: Wiring 174: Wiring 184: Wiring 200: Electronic components 220: First design program (design program) 222: Second design program (design program) 250: Resin laminate (resin layer) 251: Resin laminate (Resin layer) 252: Resin laminate (resin layer) 253: Resin laminate (resin layer) 254: Resin laminate (resin layer) 260: Circuit board 270: Virtual image 300: Resin laminate (resin layer) 302: Resin laminate (resin layer) 304: Resin laminate (resin layer) 306: Resin laminate (resin layer) 308: Resin laminate (resin layer) 310: Circuit board

Claims (6)

  1. 　複数の樹脂層を積層させるとともに、前記複数の樹脂層のうちの少なくとも１層の樹脂層の上面に配線を形成することで作製される回路基板の前記複数の樹脂層の設計方法であって、
    　配線を支持するとともに覆う箇所の前記複数の樹脂層を少なくとも示す画像データを生成することで前記複数の樹脂層を設計する設計方法。     A method for designing the plurality of resin layers of a circuit board produced by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers, the method comprising:
    A design method for designing the plurality of resin layers by generating image data showing at least the plurality of resin layers at locations that support and cover wiring.
  2. 　配線に接続される電子部品を支持する箇所の前記複数の樹脂層を少なくとも示す画像データを生成する請求項１に記載の設計方法。 The design method according to claim 1, wherein image data is generated that shows at least the plurality of resin layers at locations that support electronic components connected to wiring.
  3. 　前記複数の樹脂層の下方の樹脂層から順次、上方の樹脂層に向って前記複数の樹脂層を設計する設計方法であって、
    　配線を支持する箇所と当該配線を覆う箇所に樹脂層を加算するように前記複数の樹脂層を少なくとも示す画像データを生成する請求項１または請求項２に記載の設計方法。     A design method in which the plurality of resin layers are designed sequentially from the lower resin layer to the upper resin layer of the plurality of resin layers,
    3. The design method according to claim 1, wherein image data showing at least the plurality of resin layers is generated such that resin layers are added to locations that support the wiring and locations that cover the wiring.
  4. 　前記複数の樹脂層の上方の樹脂層から順次、下方の樹脂層に向って前記複数の樹脂層を設計する設計方法であって、
    　同じ寸法の樹脂層を前記複数の樹脂層と同数仮想的に積層させて、前記回路基板の全ての配線を支持するとともに覆う樹脂層を示す画像である仮想画像から、配線の支持及び被覆に不要な箇所を削除することで、前記複数の樹脂層を少なくとも示す画像データを生成する請求項１または請求項２に記載の設計方法。     A design method in which the plurality of resin layers are designed sequentially from the upper resin layer to the lower resin layer,
    From a virtual image that is an image showing a resin layer that supports and covers all the wiring on the circuit board by virtually laminating the same number of resin layers of the same size as the plurality of resin layers, it is possible to determine whether the resin layer is unnecessary for supporting and covering the wiring. 3. The design method according to claim 1 or 2, wherein image data showing at least the plurality of resin layers is generated by deleting portions that are similar to those of the plurality of resin layers.
  5. 　複数の樹脂層を積層させるとともに、前記複数の樹脂層のうちの少なくとも１層の樹脂層の上面に配線を形成することで作製される回路基板の前記複数の樹脂層を設計する設計プログラムであって、
    　配線を支持するとともに覆う箇所の前記複数の樹脂層を少なくとも示す画像データを生成する設計プログラム。     A design program for designing the plurality of resin layers of a circuit board produced by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers. hand,
    A design program that generates image data showing at least the plurality of resin layers at locations that support and cover wiring.
  6. 　複数の樹脂層を積層させるとともに、前記複数の樹脂層のうちの少なくとも１層の樹脂層の上面に配線を形成することで回路基板を作製する回路基板作製方法であって、
    　配線を支持するとともに覆う箇所に前記複数の樹脂層を形成する回路基板作製方法。     A circuit board manufacturing method for manufacturing a circuit board by laminating a plurality of resin layers and forming wiring on the upper surface of at least one resin layer among the plurality of resin layers, the method comprising:
    A method for manufacturing a circuit board, comprising forming the plurality of resin layers at locations that support and cover wiring.
PCT/JP2022/019309 2022-04-28 2022-04-28 Design method, design program and method for producing circuit board WO2023209960A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004064039A (en) * 2002-06-07 2004-02-26 Fuji Photo Film Co Ltd Pattern forming method and pattern forming apparatus
JP2006024768A (en) * 2004-07-08 2006-01-26 Seiko Epson Corp Wiring board, manufacturing method thereof, and electronic appliance
WO2019171531A1 (en) * 2018-03-08 2019-09-12 株式会社Ｆｕｊｉ Information processing device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004064039A (en) * 2002-06-07 2004-02-26 Fuji Photo Film Co Ltd Pattern forming method and pattern forming apparatus
JP2006024768A (en) * 2004-07-08 2006-01-26 Seiko Epson Corp Wiring board, manufacturing method thereof, and electronic appliance
WO2019171531A1 (en) * 2018-03-08 2019-09-12 株式会社Ｆｕｊｉ Information processing device

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