WO2023209486A1 - 半導体装置、及び記憶装置 - Google Patents

半導体装置、及び記憶装置 Download PDF

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Publication number
WO2023209486A1
WO2023209486A1 PCT/IB2023/053823 IB2023053823W WO2023209486A1 WO 2023209486 A1 WO2023209486 A1 WO 2023209486A1 IB 2023053823 W IB2023053823 W IB 2023053823W WO 2023209486 A1 WO2023209486 A1 WO 2023209486A1
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Prior art keywords
insulator
conductor
oxide
film
transistor
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Ceased
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PCT/IB2023/053823
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English (en)
French (fr)
Japanese (ja)
Inventor
遠藤俊弥
方堂涼太
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to US18/855,764 priority Critical patent/US20250241009A1/en
Priority to KR1020247037280A priority patent/KR20250003743A/ko
Priority to CN202380034188.9A priority patent/CN119013792A/zh
Priority to JP2024517599A priority patent/JPWO2023209486A1/ja
Publication of WO2023209486A1 publication Critical patent/WO2023209486A1/ja
Anticipated expiration legal-status Critical
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D64/00—Electrodes of devices having potential barriers
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device using an oxide semiconductor. Further, one embodiment of the present invention relates to a method for manufacturing the above semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (for example, touch sensors), input/output devices (for example, touch panels), An example of such a driving method or a manufacturing method thereof can be mentioned.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and storage devices are examples of semiconductor devices.
  • Display devices liquid crystal display devices, light emitting display devices, etc.
  • projection devices lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic equipment, and the like may be said to include semiconductor devices.
  • a CPU is an assembly of semiconductor elements, including a semiconductor integrated circuit (at least a transistor and a memory) formed into a chip by processing a semiconductor wafer, and on which electrodes serving as connection terminals are formed.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.
  • a technology that constructs a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention.
  • the transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.
  • Patent Document 1 discloses a CPU with low power consumption that takes advantage of the low leakage current of a transistor using an oxide semiconductor.
  • Patent Document 2 discloses a memory device that can retain stored content for a long period of time by applying the characteristic of a transistor using an oxide semiconductor that the leakage current is small.
  • Patent Document 3 discloses a transistor with a fine structure in which a source electrode layer and a drain electrode layer are provided in contact with the upper surface of an oxide semiconductor.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device in which the electrical characteristics of transistors have little variation. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.
  • an object of one embodiment of the present invention is to provide a novel semiconductor device.
  • an object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.
  • Another object of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device.
  • an object of one embodiment of the present invention is to provide a storage device with a large storage capacity.
  • an object of one embodiment of the present invention is to provide a storage device that operates at high speed.
  • an object of one embodiment of the present invention is to provide a storage device with low power consumption.
  • an object of one aspect of the present invention is to provide a novel storage device.
  • One embodiment of the present invention includes an oxide on a substrate, a first conductor and a second conductor on the oxide that are spaced apart from each other, and a third conductor in contact with an upper surface of the first conductor. a fourth conductor in contact with the upper surface of the second conductor; a third conductor; a first insulator having an opening on the fourth conductor; and an opening in the first insulator.
  • a second insulator disposed within the conductor and in contact with the top surface of the first conductor, the top surface of the second conductor, the side surface of the third conductor, and the side surface of the fourth conductor; a third insulator on the insulator and a fifth conductor on the third insulator, and the opening is in a region between the third conductor and the fourth conductor.
  • the fifth conductor has a region that overlaps with the oxide through the third insulator, and the third insulator has a region between the first conductor and the second conductor. In the region, the semiconductor device is in contact with the top surface of the oxide, and the distance between the first conductor and the second conductor is smaller than the distance between the third conductor and the fourth conductor.
  • the first conductor and the second conductor include metal nitride. Moreover, in the above, it is preferable that the first conductor and the second conductor include tantalum nitride. Moreover, in the above, it is preferable that the first conductor and the second conductor include tantalum nitride, and the third conductor and the fourth conductor include tungsten.
  • the second insulator includes nitride. Moreover, in the above, it is preferable that the second insulator includes silicon nitride.
  • the third insulator has an aluminum oxide film and a silicon nitride film on the aluminum oxide film.
  • the third insulator includes an aluminum oxide film, a silicon oxide film on the aluminum oxide film, and a silicon nitride film on the silicon oxide film.
  • the third insulator includes an aluminum oxide film, a silicon oxide film on the aluminum oxide film, a hafnium oxide film on the silicon oxide film, and a silicon nitride film on the hafnium oxide film, It is preferable.
  • the second insulator is in contact with the side surface of the first insulator.
  • the third insulator is in contact with the top surface and side surface of the second insulator, the side surface of the first conductor, and the side surface of the second conductor.
  • Another embodiment of the present invention includes the above-described semiconductor device and a capacitor, wherein one electrode of the capacitor is electrically connected to a third conductor of the semiconductor device. It is a device.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device that operates at high speed can be provided.
  • a semiconductor device having good electrical characteristics can be provided.
  • a semiconductor device with less variation in the electrical characteristics of transistors can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with a large on-state current can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a novel semiconductor device can be provided.
  • a method for manufacturing a semiconductor device with high productivity can be provided.
  • a novel method for manufacturing a semiconductor device can be provided.
  • a storage device with a large storage capacity can be provided.
  • a storage device with high operating speed can be provided.
  • a storage device with low power consumption can be provided.
  • a novel storage device can be provided.
  • FIG. 1A is a plan view showing an example of a semiconductor device.
  • FIGS. 1B to 1D are cross-sectional views showing an example of a semiconductor device.
  • 2A to 2C are cross-sectional views showing an example of a semiconductor device.
  • 3A to 3C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 4A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • 4B to 4D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 5A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • 5B to 5D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 1A is a plan view showing an example of a semiconductor device.
  • FIGS. 1B to 1D are cross-sectional views showing an example of a semiconductor device.
  • 2A to 2C are cross-sectional views showing an example of
  • FIG. 6A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • 6B to 6D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 7A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • 7B to 7D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 8A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • 8B to 8D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 9A to 9D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 10A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • FIG. 10B to 10D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 11A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • 11B to 11D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 12A to 12D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 13A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • 13B to 13D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 14A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • FIG. 14B to 14D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 15A is a plan view showing an example of a method for manufacturing a semiconductor device.
  • 15B to 15D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 16 is a block diagram showing an example of a storage device.
  • 17A and 17B are a schematic diagram and a circuit diagram showing an example of a storage device.
  • 18A and 18B are schematic diagrams showing an example of a storage device.
  • FIG. 19 is a circuit diagram showing an example of a storage device.
  • FIG. 20 is a cross-sectional view showing an example of a storage device.
  • FIG. 21 is a cross-sectional view showing an example of a storage device.
  • 22A to 22C are circuit diagrams showing an example of a storage device.
  • 23A and 23B are diagrams showing an example of a semiconductor device.
  • 24A and 24B are diagrams showing an example of an electronic component.
  • 25A and 25B are diagrams showing an example of an electronic device
  • FIGS. 25C to 25E are diagrams showing an example of a large-sized computer.
  • FIG. 26 is a diagram showing an example of space equipment.
  • FIG. 27 is a diagram illustrating an example of a storage system applicable to a data center.
  • 28A and 28B are graphs according to the example.
  • FIG. 29 is a cross-sectional STEM image according to the example.
  • 30A to 30C are cross-sectional STEM images according to the example.
  • 31A and 31B are cross-sectional STEM images according to the example.
  • 32A and 32B are graphs of electrical characteristics according to the example.
  • 33A and 33B are graphs of electrical characteristics according to the example.
  • 34A and 34B are graph
  • ordinal numbers such as “first” and “second” are used for convenience, and do not limit the number of components or the order of the components (for example, the order of steps or the order of lamination). It's not something you do. Further, the ordinal number attached to a constituent element in a certain part of this specification may not match the ordinal number attached to the constituent element in another part of this specification or in the claims.
  • film and “layer” can be interchanged depending on the situation or circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • conductor can be interchanged with the term “conductive layer” or the term “conductive film” depending on the case or the situation.
  • insulator can be interchanged with the term “insulating layer” or the term “insulating film” depending on the case or the situation.
  • the opening includes, for example, a groove, a slit, etc. Further, a region in which an opening is formed may be referred to as an opening.
  • drawings used in this embodiment show a case where the sidewall of the insulator in the opening of the insulator is approximately perpendicular to the substrate surface or the surface to be formed, it may have a tapered shape.
  • a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • a taper angle a region where the angle between the inclined side surface and the substrate surface or the surface to be formed (hereinafter sometimes referred to as a taper angle) is less than 90°.
  • the side surfaces of the structure and the substrate surface do not necessarily have to be completely flat, and may be substantially planar with minute curvatures or substantially planar with minute irregularities.
  • FIGS. 1 to 3 are a plan view and a cross-sectional view of a semiconductor device (transistor 200).
  • FIG. 1A is a plan view of the semiconductor device.
  • FIGS. 1B to 1D are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 1C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG.
  • FIG. 1A is also a cross-sectional view of the transistor 200 in the channel width direction.
  • FIG. 1D is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that in the plan view of FIG. 1A, some elements are omitted for clarity. Further, FIGS. 2A to 3C show enlarged cross-sectional views of the transistor 200 in the channel length direction.
  • the transistor 200 includes an insulator 216 over an insulator 215, a conductor 205 (a conductor 205a and a conductor 205b) embedded in the insulator 216, and an insulator over the insulator 216 and the conductor 205. 222, an insulator 224 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 224, and a conductor 242a (conductor 242a1 and conductor 242a2) on the oxide 230.
  • a conductor 260 (a conductor 260a and a conductor 260b).
  • An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. Further, an insulator 255 is provided between the conductor 242a1, the conductor 242b1, the conductor 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, and the insulator 280, and the insulator 250. There is. Insulator 255, insulator 250, and conductor 260 are embedded in openings provided in insulator 280 and insulator 275. Further, an insulator 282 is provided on the insulator 280 and the conductor 260. Further, an insulator 283 is provided on the insulator 282.
  • the oxide 230 has a region that functions as a channel formation region of the transistor 200.
  • the conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200.
  • Insulator 250 has a region that functions as a first gate insulator of transistor 200.
  • the conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200.
  • Insulator 224 and insulator 222 each have a region that functions as a second gate insulator of transistor 200.
  • the conductor 242a has a region that functions as either a source electrode or a drain electrode of the transistor 200.
  • the conductor 242b has a region that functions as the other of the source electrode and the drain electrode of the transistor 200.
  • the conductor 242a has a laminated structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a
  • the conductor 242b has a laminated structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1.
  • the conductor 242a1 and the conductor 242b1 in contact with the oxide 230b are preferably conductors that are difficult to oxidize, such as metal nitride. This can prevent the conductor 242a and the conductor 242b from being excessively oxidized by oxygen contained in the oxide 230b.
  • the conductor 242a2 and the conductor 242b2 are preferably conductors such as metal layers that have higher conductivity than the conductor 242a1 and the conductor 242b1.
  • the conductor 242a and the conductor 242b can function as highly conductive wiring or electrodes.
  • a semiconductor device can be provided in which the conductor 242a and the conductor 242b, which function as wiring or electrodes, are provided in contact with the upper surface of the oxide 230, which functions as an active layer.
  • the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2.
  • the insulator 255 is preferably an insulator that is difficult to oxidize, such as nitride.
  • the insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and has a function of protecting the conductor 242a2 and the conductor 242b2.
  • heat treatment is preferably performed in an atmosphere containing oxygen after the conductor 242a1 and the conductor 242b1 are separated and before the insulator 250 is formed.
  • the oxide 230 preferably includes an oxide 230a on the insulator 224 and an oxide 230b on the oxide 230a. By having the oxide 230a below the oxide 230b, diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b can be suppressed.
  • the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b
  • the structure is not limited thereto.
  • the oxide 230 may have a single layer structure of the oxide 230b, or may have a stacked structure of three or more layers.
  • a channel formation region and a source region and a drain region provided to sandwich the channel formation region in the transistor 200 are formed in the oxide 230b. At least a portion of the channel forming region overlaps with the conductor 260.
  • the source region overlaps the conductor 242a, and the drain region overlaps the conductor 242b. Note that the source region and the drain region can be replaced with each other.
  • the channel forming region has fewer oxygen vacancies or has a lower impurity concentration than the source and drain regions, so it is a high resistance region with a lower carrier concentration. Therefore, the channel forming region can be said to be i-type (intrinsic) or substantially i-type.
  • the source region and the drain region are low resistance regions with a high carrier concentration because they have many oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. That is, the source region and the drain region are n-type regions (low resistance regions) that have a higher carrier concentration than the channel forming region.
  • the carrier concentration of the channel forming region is 1 ⁇ 10 18 cm ⁇ 3 or less, less than 1 ⁇ 10 17 cm ⁇ 3 , less than 1 ⁇ 10 16 cm ⁇ 3 , less than 1 ⁇ 10 15 cm ⁇ 3 , or 1 ⁇ 10 14 It is preferably less than cm ⁇ 3 , less than 1 ⁇ 10 13 cm ⁇ 3 , less than 1 ⁇ 10 12 cm ⁇ 3 , less than 1 ⁇ 10 11 cm ⁇ 3 , or less than 1 ⁇ 10 10 cm ⁇ 3 . Further, the lower limit of the carrier concentration in the channel forming region is not particularly limited, but can be set to, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the impurity concentration in the oxide 230b is lowered to lower the defect level density.
  • the term "high purity intrinsic” or “substantially high purity intrinsic” means that the impurity concentration is low and the defect level density is low.
  • an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).
  • the impurity concentration in the oxide 230b In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. Further, in order to reduce the impurity concentration of the oxide 230b, it is preferable to also reduce the impurity concentration in the adjacent film.
  • impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide 230b refer to, for example, substances other than the main components that constitute the oxide 230b. For example, an element having a concentration of less than 0.1 atomic % can be considered an impurity.
  • the channel formation region, the source region, and the drain region may each be formed not only with the oxide 230b but also with the oxide 230a.
  • the concentration of metal elements and impurity elements such as hydrogen and nitrogen detected in each region is not limited to a stepwise change from region to region, and may be continuously changed within each region. In other words, the closer the region is to the channel formation region, the lower the concentration of metal elements and impurity elements such as hydrogen and nitrogen may be.
  • oxide 230 oxide 230a and oxide 230b.
  • the band gap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more.
  • the off-state current of the transistor can be reduced.
  • a transistor having a metal oxide in a channel formation region in this way is called an OS transistor. Since the OS transistor has a small off-state current, the power consumption of the semiconductor device can be sufficiently reduced. Further, since the frequency characteristics of the OS transistor are high, the semiconductor device can be operated at high speed.
  • the oxide 230 preferably includes a metal oxide (oxide semiconductor).
  • metal oxides that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide contains at least indium (In) or zinc (Zn).
  • the metal oxide has two or three selected from indium, element M, and zinc.
  • the element M is a metal element or a metalloid element that has a high bonding energy with oxygen, for example, a metal element or a metalloid element that has a higher bonding energy with oxygen than indium.
  • the element M includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, and calcium. , strontium, barium, boron, silicon, germanium, and antimony.
  • the element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further gallium. preferable. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include semimetal elements.
  • the oxide 230 is, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In- Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO) , aluminum zinc oxide (aluminum zinc oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO) ), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may contain one or more metal elements with a large number of periods instead of or in addition to indium.
  • metal elements having a large number of periods include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • Specific examples of the metal element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more types of nonmetallic elements.
  • the metal oxide contains a nonmetal element, the field effect mobility of the transistor can be increased in some cases.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. . Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the oxide 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.
  • the oxide 230 has a stacked structure of a plurality of oxide layers having different chemical compositions.
  • the atomic ratio of the element M to the metal element that is the main component is the same as the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. It is preferable that it be larger.
  • the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the oxide 230a and the oxide 230b have a common element other than oxygen as a main component, the density of defect levels at the interface between the oxide 230a and the oxide 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the element M it is preferable to use gallium.
  • a metal oxide that can be used for the oxide 230a may be used as the oxide 230b.
  • the compositions of the metal oxides that can be used for the oxide 230a and the oxide 230b are not limited to the above.
  • a metal oxide composition that can be used for oxide 230a may be applied to oxide 230b.
  • the composition of metal oxides that can be used for oxide 230b may also be applied to oxide 230a.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but also the atomic ratio of the sputtering target used for forming the metal oxide film. It may be.
  • the oxide 230b has crystallinity.
  • CAAC-OS c-axis aligned crystalline oxide semiconductor
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (for example, oxygen vacancies).
  • heat treatment at a temperature that does not polycrystallize the metal oxide (e.g., 400°C or higher and 600°C or lower) allows CAAC-OS to have a more highly crystalline and dense structure. It can be done. In this way, by further increasing the density of the CAAC-OS, it is possible to further reduce diffusion of impurities or oxygen in the CAAC-OS.
  • CAAC-OS it is difficult to confirm clear grain boundaries, so it can be said that reduction in electron mobility due to grain boundaries is less likely to occur. Therefore, the metal oxide with CAAC-OS has stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and have high reliability.
  • the oxide 230b Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, even if heat treatment is performed, extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against high temperatures (so-called thermal budget) during the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the channel formation region in the oxide semiconductor preferably has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.
  • the insulator can be converted to an oxide semiconductor. Oxygen can be supplied, and oxygen vacancies and V OH can be reduced.
  • excess oxygen oxygen can be supplied to the source region or the drain region, there is a possibility that the on-state current of the transistor 200 or the field effect mobility of the transistor 200 will decrease.
  • the amount of oxygen supplied to the source region or the drain region varies within the substrate plane, resulting in variations in the characteristics of a semiconductor device including a transistor.
  • the channel formation region has a reduced carrier concentration and is preferably i-type or substantially i-type, whereas the source and drain regions have a high carrier concentration and are n-type. It is preferable. In other words, it is preferable to reduce oxygen vacancies and V OH in the channel formation region of the oxide semiconductor. Further, it is preferable that an excessive amount of oxygen is not supplied to the source region and the drain region, and that the amount of V OH in the source region and the drain region is not excessively reduced. Further, it is preferable to adopt a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like.
  • a semiconductor device in which the hydrogen concentration in the channel formation region is reduced, the oxidation of the conductor 242a, the conductor 242b, and the conductor 260 is suppressed, and the hydrogen concentration in the source region and the drain region is suppressed.
  • the configuration is such that the hydrogen concentration of the hydrogen concentration is suppressed from decreasing.
  • the insulator 250 in contact with the channel forming region in the oxide 230b preferably has the function of capturing and fixing hydrogen. Thereby, the hydrogen concentration in the channel formation region of the oxide 230b can be reduced. Therefore, V O H in the channel formation region can be reduced and the channel formation region can be made into i-type or substantially i-type.
  • the insulator 250 may have a laminated structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.
  • the insulator 250a has the function of capturing and fixing hydrogen.
  • Examples of insulators that have the function of capturing and fixing hydrogen include metal oxides with an amorphous structure.
  • the insulator 250a it is preferable to use, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium.
  • metal oxides having such an amorphous structure oxygen atoms have dangling bonds, and the dangling bonds may capture or fix hydrogen.
  • metal oxides having an amorphous structure have a high ability to capture or fix hydrogen.
  • a high dielectric constant (high-k) material for the insulator 250a.
  • a high-k material is an oxide containing one or both of aluminum and hafnium.
  • an oxide containing one or both of aluminum and hafnium as the insulator 250a, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. It is further preferable to use aluminum oxide having a structure.
  • an aluminum oxide film is used as the insulator 250a.
  • the insulator 250a is an insulator containing at least oxygen and aluminum.
  • the aluminum oxide has an amorphous structure.
  • the insulator 250a has an amorphous structure.
  • an insulator having a stable structure against heat such as silicon oxide or silicon oxynitride.
  • oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • nitrided oxide refers to a material whose composition contains more nitrogen than oxygen.
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. shows.
  • an insulator 250d may be provided on the insulator 250b.
  • an insulator that can be used for the insulator 250a can be provided as the insulator 250d.
  • hafnium oxide can be used as the insulator 250d.
  • the insulators are, for example, an insulator 250a, an insulator 250c, an insulator 250d, an insulator 255, and an insulator 275.
  • barrier insulator refers to an insulator that has barrier properties.
  • barrier property is defined as a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability).
  • the function is to capture and fix (also referred to as gettering) the corresponding substance.
  • barrier insulators against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).
  • the insulator 250a, the insulator 250c, the insulator 250d, the insulator 255, and the insulator 275 each preferably have a single layer structure or a laminated structure of the above oxygen barrier insulator.
  • the insulator 250a and the insulator 255 have barrier properties against oxygen. It is preferable that the insulator 250a and the insulator 255 are at least less permeable to oxygen than the insulator 280.
  • the insulator 250a has a region in contact with a side surface of the conductor 242a1 and a side surface of the conductor 242b1.
  • the insulator 255 has a region in contact with the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. Further, the insulator 250a is in contact with the top and side surfaces of the insulator 255.
  • the insulator 250a and the insulator 255 have barrier properties against oxygen, the side surfaces of the conductor 242a and the conductor 242b can be prevented from being oxidized and formation of an oxide film on the side surfaces. Thereby, it is possible to suppress a decrease in the on-state current of the transistor 200 or a decrease in field effect mobility.
  • the insulator 250a is provided in contact with the top and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. Since the insulator 250a has barrier properties against oxygen, desorption of oxygen from the channel formation region of the oxide 230b can be suppressed when heat treatment or the like is performed. Therefore, formation of oxygen vacancies in the oxide 230a and the oxide 230b can be reduced.
  • the insulator 250a and the insulator 255 even if the insulator 280 contains an excessive amount of oxygen, it is possible to suppress the oxygen from being excessively supplied to the oxide 230a and the oxide 230b. , an appropriate amount of oxygen can be supplied to the oxide 230a and the oxide 230b. Therefore, excessive oxidation of the source region and the drain region, resulting in a decrease in the on-state current or a decrease in field-effect mobility of the transistor 200, can be suppressed.
  • an oxide containing one or both of aluminum and hafnium has barrier properties against oxygen, it can be suitably used as the insulator 250a.
  • silicon nitride can also be suitably used as the insulator 255 because it has barrier properties against oxygen.
  • the insulator 250c preferably has barrier properties against oxygen.
  • the insulator 250c is provided between the channel forming region of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260.
  • oxygen contained in the channel formation region of the oxide 230 can be prevented from diffusing into the conductor 260, and oxygen vacancies can be prevented from being formed in the channel formation region of the oxide 230.
  • oxygen contained in the oxide 230 and oxygen contained in the insulator 280 can be prevented from diffusing into the conductor 260 and oxidizing the conductor 260.
  • the insulator 250c is at least less permeable to oxygen than the insulator 280.
  • the insulator 250c is an insulator containing at least nitrogen and silicon.
  • the insulator 250c has barrier properties against hydrogen. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.
  • the insulator 275 preferably has barrier properties against oxygen.
  • the insulator 275 is provided between the insulator 280 and the conductor 242a and between the insulator 280 and the conductor 242b. With this configuration, it is possible to suppress oxygen contained in the insulator 280 from diffusing into the conductor 242a and the conductor 242b. Therefore, it is possible to suppress the conductor 242a and the conductor 242b from being oxidized by the oxygen contained in the insulator 280, increasing the resistivity, and reducing the on-current.
  • the insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.
  • the barrier insulator against hydrogen is, for example, the insulator 275.
  • barrier insulators against hydrogen examples include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride.
  • oxides such as aluminum oxide, hafnium oxide, and tantalum oxide
  • nitrides such as silicon nitride.
  • the insulator 275 has a single layer structure or a multilayer structure of the hydrogen barrier insulator.
  • the source region and the drain region can be n-type.
  • the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, and a semiconductor device with good electrical characteristics can be provided.
  • the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics.
  • miniaturizing the transistor 200 high frequency characteristics can be improved. Specifically, the cutoff frequency can be improved.
  • the insulators 250a to 250d function as part of the first gate insulator.
  • the insulators 250a to 250d are provided in openings formed in the insulator 280 along with the insulator 255 and the conductor 260.
  • each of the insulators 250a to 250d be thin.
  • the thickness of each of the insulators 250a to 250d is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, and 1.0 nm or more.
  • each of the insulators 250a to 250d only needs to have a region with the thickness described above in at least a portion thereof.
  • the films In order to reduce the film thickness of the insulators 250a to 250d as described above, it is preferable to form the films using an atomic layer deposition (ALD) method.
  • ALD atomic layer deposition
  • the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, and a PEALD method in which a plasma-excited reactant is used.
  • PEALD method by using plasma, it is possible to form a film at a lower temperature, which may be preferable.
  • the ALD method can deposit atoms one layer at a time, it is possible to form extremely thin films, to form structures with high aspect ratios, to form films with few defects such as pinholes, and to improve coverage. It has the advantage of being able to form excellent films and being able to form films at low temperatures. Therefore, the insulator 255 and the insulator 250 are formed with a thin film thickness as described above with good coverage on the side surfaces of the opening formed in the insulator 280 and the side edges of the conductors 242a and 242b. be able to.
  • a film formed by the ALD method may contain more impurities such as carbon than a film formed by other film forming methods.
  • the impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES). Auger Electron Spectroscopy) It can be done using
  • the present invention is not limited to this. isn't it.
  • the insulator 250 can be configured to include at least one of insulators 250a to 250d. By forming the insulator 250 with one layer, two layers, or three layers among the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.
  • the insulator 250 may have a two-layer structure.
  • the insulator 250 has a laminated structure of an insulator 250a and an insulator 250c on the insulator 250a.
  • a high-k material can be used for at least one of the insulator 250a and the insulator 250c. This makes it possible to reduce the equivalent oxide thickness (EOT) while maintaining the thickness of the insulator 250a and the insulator 250c to the extent that leakage current is suppressed.
  • EOT equivalent oxide thickness
  • the oxide 230b includes a region that overlaps with the insulator 250 that is in contact with the side surface of the conductor 242b1, and a region that overlaps with the insulator 250 that is in contact with the side surface of the conductor 242b1.
  • a region overlapping with 250 (hereinafter referred to as Loff region) is formed.
  • the Loff region does not overlap with the conductor 242a1 and the conductor 242b1, and does not properly overlap with the conductor 260 via the insulator 250, so it functions like a resistor.
  • the insulator 250 is composed of only the insulator 250a and the insulator 250c, and the thickness of the insulator 250a and the insulator 250c can be made thin as described above.
  • the insulator 250a can be made of aluminum oxide to a thickness of 2.0 nm
  • the insulator 250c can be made of silicon nitride to a thickness of 1.5 nm
  • the insulator 250 can have a thickness of 3.5 nm.
  • an insulator 255 is provided between the insulator 250 and the conductor 242a and between the insulator 250 and the conductor 242b.
  • the semiconductor device preferably has a configuration that suppresses hydrogen from entering the transistor 200 and the like.
  • the semiconductor device described in this embodiment the insulators are, for example, the insulator 282 and the insulator 283.
  • the insulator 215 provided under the transistor 200 may have the same structure as one or both of the insulator 282 and the insulator 283.
  • the insulator 215 may have a laminated structure of the insulator 282 and the insulator 283, the insulator 282 may be on the bottom and the insulator 283 on the top, or the insulator 282 may be on the top. , the insulator 283 may be placed at the bottom.
  • One or more of the insulator 282 and the insulator 283 serves as a barrier insulator that suppresses impurities such as water and hydrogen from diffusing into the transistor 200 etc. from the substrate side or from above the transistor 200 etc.
  • one or more of the insulator 282 and the insulator 283 are hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( N2O , NO, NO2 , etc.), copper atoms.
  • the insulator 282 and the insulator 283 each have an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, such as aluminum oxide, magnesium oxide, hafnium oxide, and gallium oxide.
  • oxygen such as aluminum oxide, magnesium oxide, hafnium oxide, and gallium oxide.
  • indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like can be used.
  • the insulator 283 it is preferable to use silicon nitride, which has a higher hydrogen barrier property.
  • the insulator 282 includes aluminum oxide, magnesium oxide, or the like, which have a high function of capturing and fixing hydrogen, respectively.
  • impurities such as water and hydrogen can be suppressed from diffusing into the transistor 200 and the like from an interlayer insulating film and the like disposed outside the insulator 283. Further, oxygen contained in the insulator 280 and the like can be suppressed from diffusing upward from the transistor 200 and the like via the insulator 282 and the like. Furthermore, by using the same structure as the insulator 215 as one or both of the insulator 282 and the insulator 283, impurities such as water and hydrogen can be diffused from the substrate side to the transistor 200 and the like via the insulator 215. can be suppressed. Furthermore, oxygen contained in the insulator 224 and the like can be suppressed from diffusing toward the substrate side. In this way, it is preferable to have a structure in which the upper and lower sides of the transistor 200 and the like are surrounded by an insulator that has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.
  • the conductor 205 is arranged to overlap the oxide 230 and the conductor 260.
  • the conductor 205 is preferably embedded in an opening formed in the insulator 216.
  • the conductor 205 is preferably provided extending in the channel width direction, as shown in FIGS. 1A and 1C. With this structure, the conductor 205 functions as a wiring when a plurality of transistors are provided.
  • the conductor 205 may have a single layer structure or a laminated structure.
  • the conductor 205 includes a conductor 205a and a conductor 205b.
  • the conductor 205a is provided in contact with the bottom and side walls of the opening.
  • the conductor 205b is provided so as to fill the recess of the conductor 205a formed along the opening.
  • the height of the top surface of the conductor 205 approximately matches the height of the top surface of the insulator 216.
  • the conductor 205a has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( N2O , NO, NO2 , etc.), and copper atoms.
  • the conductive material has a conductive material having the following properties.
  • the conductor 205a By using a conductive material that has a function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 216 or the like. It can be prevented. Further, by using a conductive material that has a function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the decrease in conductivity due to oxidation of the conductor 205b. Examples of the conductive material having the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.
  • the conductor 205a can have a single layer structure or a laminated structure of the above-mentioned conductive materials.
  • the conductor 205a preferably includes titanium nitride.
  • the conductor 205b preferably includes tungsten.
  • the conductor 205 can function as a second gate electrode.
  • the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with the potential applied to the conductor 260.
  • Vth threshold voltage
  • the electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. Furthermore, the thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable that the film thicknesses of the conductor 205 and the insulator 216 be made as thin as the design of the conductor 205 allows. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that diffusion of the impurities into the oxide 230 can be reduced. .
  • the insulator 222 and the insulator 224 function as a second gate insulator.
  • the insulator 222 has a function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule). Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen more than the insulator 224.
  • the insulator 222 preferably includes an oxide of one or both of aluminum and hafnium, which are insulating materials.
  • the insulator it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.
  • an oxide containing hafnium and zirconium, such as hafnium zirconium oxide is preferable to use.
  • the insulator 222 prevents the release of oxygen from the oxide 230 to the substrate side and the release of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Functions as a layer that suppresses diffusion.
  • the insulator 222 impurities such as hydrogen can be suppressed from diffusing inside the transistor 200, and generation of oxygen vacancies in the oxide 230 can be suppressed. Further, it is possible to suppress the conductor 205 from reacting with the oxygen contained in the insulator 224 and the oxide 230.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulator.
  • these insulators may be nitrided.
  • the insulator 222 may be used by stacking silicon oxide, silicon oxynitride, or silicon nitride on the above insulator.
  • the insulator 222 may have a single layer structure or a multilayer structure of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
  • a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
  • a material with a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba,Sr)TiO 3 (BST) may be used in some cases.
  • the insulator 224 in contact with the oxide 230 preferably includes, for example, silicon oxide or silicon oxynitride. Thereby, oxygen can be supplied from the insulator 224 to the oxide 230, and oxygen vacancies can be reduced.
  • the insulator 224 is preferably processed into an island shape.
  • insulators 224 of approximately the same size are provided for one transistor 200.
  • the amount of oxygen supplied from the insulator 224 to the oxide 230 becomes approximately the same. Therefore, variations in the electrical characteristics of the transistor 200 within the plane of the substrate can be suppressed.
  • the invention is not limited to this, and similarly to the insulator 222, the insulator 224 may be configured without patterning.
  • the insulator 222 and the insulator 224 may each have a laminated structure of two or more layers.
  • the structure is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials.
  • the conductor 242a, the conductor 242b, and the conductor 260 it is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion, respectively.
  • the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. Thereby, it is possible to suppress a decrease in the conductivity of the conductor 242a, the conductor 242b, and the conductor 260.
  • a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductive materials containing at least metal and nitrogen. Becomes a body.
  • the conductors 242a and 242b are shown in a two-layer structure.
  • the conductor 242a is a laminated film of a conductor 242a1 and a conductor 242a2 on the conductor 242a
  • the conductor 242b is a laminated film of a conductor 242b1 and a conductor 242b2 on the conductor 242b1.
  • metal nitrides such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, and nitrides containing tantalum and aluminum. It is preferable to use a nitride containing titanium, aluminum, or the like. In one aspect of the invention, nitrides containing tantalum are particularly preferred. Further, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even after absorbing oxygen.
  • hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a1 or the conductor 242b1.
  • hydrogen contained in the oxide 230b etc. is easily diffused into the conductor 242a1 or the conductor 242b1, and the diffused hydrogen is It may combine with nitrogen contained in the conductor 242a1 or the conductor 242b1. That is, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a1 or the conductor 242b1.
  • the conductor 242a2 and the conductor 242b2 have higher conductivity than the conductor 242a1 and the conductor 242b1.
  • the thickness of the conductor 242a2 and the conductor 242b2 be larger than the thickness of the conductor 242a1 and the conductor 242b1.
  • any conductor that can be used for the conductor 205b may be used. With the above structure, the resistance of the conductor 242a2 and the conductor 242b2 can be reduced. Thereby, it is possible to improve the operating speed of the semiconductor device according to this embodiment.
  • tantalum nitride or titanium nitride can be used as the conductor 242a1 and the conductor 242b1, and tungsten can be used as the conductor 242a2 and the conductor 242b2.
  • a crystalline oxide such as CAAC-OS as the oxide 230b.
  • a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin By using CAAC-OS, extraction of oxygen from the oxide 230b by the conductor 242a or the conductor 242b can be suppressed. Further, it is possible to suppress a decrease in the conductivity of the conductor 242a and the conductor 242b.
  • the insulator 255 is disposed in an opening formed in the insulator 280 or the like, and is arranged on the side of the insulator 280, the side of the insulator 275, the side of the insulator 271a, and the insulator. 271b, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the side surface of the conductor 242a1, the side surface of the conductor 242b1, and the top surface of the insulator 222.
  • the insulator 255 has an opening formed so as to expose the island-shaped oxide 230 in the opening.
  • the insulator 250 is in contact with the oxide 230 and the insulator 222 in the region where the opening of the insulator 255 is formed.
  • the insulator 255 has an opening only in the vicinity of the oxide 230 in FIG. 1C, the present invention is not limited to this. It is sufficient that the insulator 255 has an opening at least in a region sandwiched between the conductor 242a1 and the conductor 242b1 of the oxide 230b. Therefore, for example, a configuration may be adopted in which the insulator 255 has almost no area in contact with the insulator 222 and is formed in the shape of a sidewall in an opening formed in the insulator 280.
  • the insulator 255 is an inorganic insulator that is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and protects the conductor 242a2 and the conductor 242b2. Since the insulator 255 is exposed to an oxidizing atmosphere, it is preferably an inorganic insulator that is not easily oxidized. Further, since the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferably an inorganic insulator that does not easily oxidize the conductors 242a2 and 242b2. Therefore, it is preferable to use an insulating material for the insulator 255 that can be used for the insulator 250c having barrier properties against oxygen. For example, silicon nitride can be used as the insulator 255.
  • the conductor 242a2 and the conductor body 242b2 is not excessively oxidized.
  • the thickness of the oxide film on the side surfaces of the conductors 242a2 and 242b2 near the conductor 260 is set to 0.5 nm or more and 5 nm or less, preferably 0.5 nm or more and 3 nm or less, and more preferably 0.5 nm or more and 2 nm or less. be able to.
  • the insulator 255 is preferably thicker than any one of the insulators 250a to 250d.
  • the film thickness of the insulator 255 is preferably 1 nm or more and 20 nm or less, more preferably 1 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less.
  • the film thickness can be about 5 nm.
  • the insulator 255 may have a laminated structure of two or more layers using the above-mentioned inorganic insulator that is not easily oxidized.
  • the insulator 255 can have a two-layer structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.
  • at least one layer may be the above-mentioned inorganic insulator that is not easily oxidized.
  • the insulator 255 can have a two-layer structure of a silicon nitride film and a silicon oxide film on the silicon nitride film.
  • the insulator 255 can have a two-layer structure of an aluminum oxide film and a silicon oxide film on the aluminum oxide film. Further, for example, the insulator 255 can have a two-layer structure of a silicon oxide film and a silicon nitride film on the silicon oxide film. Further, for example, the insulator 255 can have a two-layer structure of a silicon oxide film and an aluminum oxide film on the silicon oxide film.
  • the insulator 255 functions as part of a mask when separating the conductor 242a1 and the conductor 242b1. Therefore, as shown in FIG. 1B, in a cross-sectional view of the transistor 200, it is preferable that the side edge of the insulator 255 substantially coincide with the side edge of the conductor 242a1 and the side edge of the conductor 242b1. .
  • the stacked layers will be different from each other in the top view. It can be said that at least part of the outlines overlap. For example, this includes a case where the lower part of the side edge of the upper layer contacts the upper part of the side edge of the lower layer.
  • the upper layer and the lower layer include a case where the upper layer and the lower layer are processed using the same mask pattern or partially the same mask pattern.
  • the contours do not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case, the side edges roughly match, or The top surface shapes are said to be roughly the same.
  • the portion of the conductor 242a1 on which the insulator 255 is formed on the upper surface is formed to protrude from the conductor 242a2 toward the conductor 260 side.
  • the portion of the conductor 242b1 on which the insulator 255 is formed is formed to protrude from the conductor 242b2 toward the conductor 260 side.
  • the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2.
  • the distance L2 between the conductor 242a1 and the conductor 242b1 is reflected in the channel length of the transistor 200, so it is preferably fine.
  • the distance L2 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and preferably 1 nm or more, or 5 nm or more.
  • the distance L2 is more preferably about 2 nm or more and 20 nm or less. With such a configuration, it is possible to further shorten the distance between the source and drain, and to shorten the channel length accordingly. Therefore, the frequency characteristics of the transistor 200 can be improved. By miniaturizing the semiconductor device in this manner, it is possible to provide a semiconductor device with improved operating speed.
  • the opposing side surfaces of the conductor 242a1 and the conductor 242b1 are approximately perpendicular to the upper surface of the oxide 230b, but the present invention is not limited thereto.
  • the mutually opposing side surfaces of the conductor 242a1 and the conductor 242b1 may have a tapered shape. By adopting such a shape, the distance between the conductor 260 and the oxide 230b becomes small near the side edges of the conductor 242a1 and the side edge of the conductor 242b1, so that the influence of the Loff region can be reduced. I can do it.
  • the opposing sides of the conductor 242a1 and the conductor 242b1 may be tapered, and the opposing sides of the conductor 242a2 and 242b2 may be tapered.
  • the taper angles of the conductors 242a1 and 242b1 may be made more acute than the taper angles of the conductors 242a2 and 242b2.
  • the distance between the conductor 260 and the oxide 230b becomes smaller near the side ends of the conductor 242a1 and the side ends of the conductor 242b1, thereby reducing the influence of the Loff region. be able to.
  • the insulator 271a and the insulator 271b are inorganic insulators that function as an etching stopper during processing of the conductor 242a2 and the conductor 242b2, and protect the conductor 242a2 and the conductor 242b2. Further, since the insulator 271a and the insulator 271b are in contact with the conductor 242a2 and the conductor 242b2, it is preferable that the insulator 271a and the insulator 271b are inorganic insulators that do not easily oxidize the conductors 242a and 242b. Therefore, as shown in FIG.
  • the insulator 271a has a stacked structure of an insulator 271a1 and an insulator 271a2 on the insulator 271a
  • the insulator 271b has a stacked structure of an insulator 271b1 and an insulator 271b2 on the insulator 271b1.
  • the insulators 271a1 and 271b1 it is preferable to use a nitride insulator that can be used for the insulator 250c so that the conductors 242a2 and 242b2 are difficult to oxidize.
  • an oxide insulator that can be used for the insulator 250b so that the insulators 271a2 and 271b2 function as etching stoppers.
  • the insulator 271a1 is in contact with the top surface of the conductor 242a2 and a part of the insulator 275
  • the insulator 271b1 is in contact with the top surface of the conductor 242b2 and a part of the insulator 275
  • the insulator 271a2 is in contact with the upper surface of the insulator 271a1 and the lower surface of the insulator 275
  • the insulator 271b2 is in contact with the upper surface of the insulator 271b1 and the lower surface of the insulator 275.
  • silicon nitride can be used as the insulator 271a1 and the insulator 271b1
  • silicon oxide can be used as the insulator 271a2 and the insulator 271b2.
  • the insulator that is the source of the insulator 271a and the insulator 271b functions as a mask for the conductor that is the source of the conductor 242a and the conductor 242b, so the conductors 242a and 242b have a curved surface between the side surface and the top surface. I don't have it.
  • the ends of the conductor 242a and the conductor 242b, where the side surface and the top surface intersect have an angular shape. Since the ends where the side surfaces and the top surfaces of the conductors 242a and 242b intersect are angular, the cross-sectional area of the conductors 242a and 242b becomes larger than when the ends have curved surfaces.
  • the conductor 260 is placed in the opening formed in the insulator 280 and the insulator 275, as shown in FIGS. 1B and 1C.
  • the conductor 260 is provided in the opening so as to cover the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, and the top surface of the oxide 230b via the insulator 250. Note that a portion of the conductor 260 is provided to overlap the conductor 242a1 and the conductor 242b1.
  • the conductor 260 is arranged such that its upper surface is approximately at the same height as the top of the insulator 250 and the upper surface of the insulator 280.
  • the side wall of the opening may be approximately perpendicular to the upper surface of the insulator 222 or may have a tapered shape. By tapering the sidewall, the coverage of the insulator 255, the insulator 250, etc. provided in the opening of the insulator 280 is improved, and defects such as holes can be reduced.
  • the conductor 260 functions as a first gate electrode of the transistor 200.
  • the conductor 260 is preferably provided extending in the channel width direction, as shown in FIGS. 1A and 1C. With this structure, the conductor 260 functions as a wiring when a plurality of transistors are provided.
  • a curved surface may be provided between the side surface of the oxide 230b and the top surface of the oxide 230b in a cross-sectional view of the transistor 200 in the channel width direction, as shown in FIG. 1C. good. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as round shape).
  • the radius of curvature of the curved surface is larger than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductors 242a and 242b, or smaller than half the length of the region not having the curved surface.
  • the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, and more preferably greater than or equal to 2 nm and less than or equal to 10 nm.
  • a structure of a transistor in which a channel formation region is electrically surrounded by at least the electric field of the first gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the S-channel structure disclosed in this specification and the like has a structure different from the Fin type structure and the planar type structure.
  • the S-channel structure disclosed in this specification and the like can also be regarded as a type of Fin type structure.
  • a Fin type structure refers to a structure in which a gate electrode is arranged so as to surround at least two or more surfaces (specifically, two, three, or four sides) of a channel.
  • the channel formation region can be electrically surrounded.
  • the S-channel structure is a structure that electrically surrounds the channel formation region, it is substantially equivalent to a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. You can say that.
  • the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be formed in the entire bulk of the oxide 230. I can do it. Therefore, it is possible to improve the current density flowing through the transistor, and thus it is expected that the on-state current of the transistor or the field effect mobility of the transistor will be increased.
  • the insulator 224 is arranged in an island shape. Therefore, as shown in FIG. 1C, at least a portion of the lower surface of the conductor 260 can be provided below the lower surface of the oxide 230b. Accordingly, the conductor 260 can be provided opposite the top surface and side surfaces of the oxide 230b, so that the electric field of the conductor 260 can be applied to the top surface and side surfaces of the oxide 230b.
  • the transistor 200 can have an S-channel structure.
  • the transistor 200 illustrated in FIG. 1C has an S-channel structure
  • the semiconductor device of one embodiment of the present invention is not limited thereto.
  • the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a fin structure, and a GAA structure.
  • the conductor 260 is shown as having a two-layer structure.
  • the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a.
  • the conductor 260a is arranged so as to cover the bottom and side surfaces of the conductor 260b.
  • the conductor 260a it is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms.
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms.
  • a conductive material that has a function of suppressing the diffusion of oxygen for example, at least one of oxygen atoms and oxygen molecules).
  • the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the conductor 260b from being oxidized by oxygen contained in the insulator 280 and the like, and thereby reducing its conductivity.
  • the conductive material having the function of suppressing oxygen diffusion it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.
  • the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.
  • the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like.
  • the conductor 260 can be placed overlapping the region between the conductor 242a1 and the conductor 242b1 without alignment.
  • the insulator 216 and the insulator 280 each have a lower dielectric constant than the insulator 222.
  • parasitic capacitance generated between wirings can be reduced.
  • the insulator 216 and the insulator 280 each include silicon oxide, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, and holes. It is preferable to include one or more of silicon oxides.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.
  • the upper surfaces of the insulator 216 and the insulator 280 may each be flattened.
  • the concentration of impurities such as water and hydrogen in the insulator 280 is reduced.
  • the insulator 280 preferably includes an oxide containing silicon, such as silicon oxide or silicon oxynitride.
  • each layer constituting the semiconductor device may have a single layer structure or a laminated structure.
  • a substrate for forming a transistor for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • a semiconductor substrate having an insulator region inside the semiconductor substrate described above for example, an SOI (Silicon On Insulator) substrate, etc.
  • the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • the substrate for example, a substrate having a metal nitride, a substrate having a metal oxide, a substrate having a conductor or a semiconductor provided on an insulator substrate, a substrate having a conductor or an insulator provided on a semiconductor substrate, etc.
  • Examples include a substrate and a substrate in which a conductive substrate is provided with a semiconductor or an insulator.
  • these substrates may be provided with one or more types of elements. Examples of the elements provided on the substrate include a capacitive element, a resistive element, a switch element, a light emitting element, and a memory element.
  • insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.
  • Examples of insulators with a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and silicon and hafnium. Oxynitrides containing silicon and nitrides containing silicon and hafnium are mentioned.
  • Insulators with low dielectric constants include, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and air. Examples include silicon oxide with pores and resin.
  • insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
  • lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or in a stack.
  • examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and Examples include metal oxides such as hafnium and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.
  • the insulator that functions as the gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating.
  • the oxide 230 by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the following, an alloy containing the above-mentioned metal elements as a component, an alloy containing a combination of the above-mentioned metal elements, or the like.
  • Examples of conductors include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and lanthanum and nickel. Examples include oxides containing.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are respectively , a conductive material that is difficult to oxidize, or a material that maintains conductivity even if it absorbs oxygen, so it is preferable.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a conductor with a laminated structure for example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined, a material containing the above-mentioned metal element and a conductive material containing nitrogen, etc. , or a stacked structure that combines a material containing the metal element described above, a conductive material containing oxygen, and a conductive material containing nitrogen may be applied.
  • the conductor that functions as the gate electrode should have a stacked structure that is a combination of a material containing the aforementioned metal element and a conductive material containing oxygen. is preferred. In this case, it is preferable to provide a conductive material containing oxygen on the channel forming region side. By providing a conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as the conductor functioning as the gate electrode.
  • a conductive material containing the aforementioned metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • one or more of the added indium tin oxides may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the metal oxide contains at least indium or zinc.
  • aluminum, gallium, yttrium, tin, antimony, etc. are contained.
  • one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be included.
  • the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc.
  • the element M is aluminum, gallium, yttrium, tin, or antimony.
  • Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.
  • the element M there are cases where a plurality of the above-mentioned elements may be combined.
  • the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.
  • metal oxides containing nitrogen may also be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • In-Ga-Zn oxide will be explained as an example of a metal oxide.
  • the crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). ite), single crystal, and polycrystal (polycrystal), etc.
  • oxide semiconductors may be classified into a different classification from the above.
  • oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors.
  • non-single crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS.
  • non-single crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.
  • CAAC-OS is an oxide semiconductor that has a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film.
  • a crystal region is a region having periodicity in atomic arrangement. Note that if the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region with a uniform lattice arrangement.
  • the CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have distortion.
  • CAAC-OS is an oxide semiconductor that has c-axis orientation and no obvious orientation in the a-b plane direction.
  • each of the plurality of crystal regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the maximum diameter of the crystal region may be about several tens of nanometers.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that in CAAC-OS, reduction in electron mobility due to grain boundaries is less likely to occur. Further, since the crystallinity of an oxide semiconductor may be degraded due to the incorporation of impurities, generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability. Furthermore, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • the nc-OS has minute crystals.
  • the size of the microcrystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the microcrystal is also referred to as a nanocrystal.
  • no regularity is observed in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from a-like OS or an amorphous oxide semiconductor.
  • the a-like OS is an oxide semiconductor having a structure between that of an nc-OS and an amorphous oxide semiconductor.
  • A-like OS has holes or low density areas. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Further, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.
  • CAC-OS relates to material composition.
  • CAC-OS is, for example, a structure of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called a mosaic or a patch.
  • CAC-OS has a structure in which the material is separated into a first region and a second region, resulting in a mosaic shape, and the first region is distributed throughout the film (hereinafter also referred to as cloud shape). ). That is, CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.
  • CAC-OS in In-Ga-Zn oxide refers to a material composition containing In, Ga, Zn, and O, in which a region (first region) whose main component is In and a region This refers to a structure in which regions (second regions) whose main component is Ga are mosaic-like, and these regions exist randomly. Therefore, it is presumed that CAC-OS has a structure in which metal elements are unevenly distributed.
  • the CAC-OS can be formed by sputtering, for example, without heating the substrate. Furthermore, when forming the CAC-OS by sputtering, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. I can do it. Furthermore, the lower the flow rate ratio of oxygen gas to the total flow rate of film-forming gas during film formation, the more preferable it is. For example, the flow rate ratio of oxygen gas to the total flow rate of film forming gas during film formation is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.
  • an inert gas typically argon
  • oxygen gas oxygen gas
  • nitrogen gas nitrogen gas
  • the first region is a region with higher conductivity than the second region.
  • carriers flow through the first region, thereby exhibiting conductivity as a metal oxide. Therefore, by distributing the first region in a cloud shape in the metal oxide, high field effect mobility ( ⁇ ) can be achieved.
  • the second region is a region with higher insulation than the first region. That is, by distributing the second region in the metal oxide, leakage current can be suppressed.
  • CAC-OS when CAC-OS is used in a transistor, the conductivity caused by the first region and the insulation caused by the second region act complementary to each other, thereby providing a switching function (on/off). functions) can be added to CAC-OS.
  • a part of the material has a conductive function
  • a part of the material has an insulating function
  • the entire material has a semiconductor function.
  • CAC-OS is optimal for various semiconductor devices including display devices.
  • Oxide semiconductors have a variety of structures, each with different properties.
  • the oxide semiconductor of one embodiment of the present invention includes two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS. It's okay.
  • a semiconductor material having a band gap (a semiconductor material other than a zero-gap semiconductor) may be used for the semiconductor layer of the transistor.
  • a semiconductor material having a band gap a semiconductor material other than a zero-gap semiconductor
  • a single element semiconductor such as silicon or a compound semiconductor such as gallium arsenide may be used.
  • transition metal chalcogenide that functions as a semiconductor for the semiconductor layer of the transistor.
  • transition metal chalcogenides applicable to the semiconductor layer of a transistor include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ) .
  • tungsten sulfide typically WS 2
  • tungsten selenide typically WSe 2
  • tungsten tellurium typically WTe 2
  • hafnium sulfide typically HfS 2
  • hafnium selenide typically HfSe 2
  • zirconium sulfide typically ZrS 2
  • zirconium selenide typically ZrSe 2
  • the like By applying the above-described transition metal chalcogenide to a semiconductor layer of a transistor, a semiconductor device with a large on-current can be provided.
  • Example of method for manufacturing semiconductor device An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 4A to 15D. Here, the case of manufacturing the semiconductor device shown in FIGS. 1A to 1D will be described as an example.
  • a in each figure indicates a plan view.
  • B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in A in each figure, and is also a cross-sectional view in the channel length direction of the transistor 200.
  • C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in A in each figure, and is also a cross-sectional view in the channel width direction of the transistor 200.
  • D in each figure is a cross-sectional view of a portion indicated by a dashed line A5-A6 in A in each figure, and is also a cross-sectional view in the channel width direction of the transistor 200.
  • some elements are omitted for clarity of the figure.
  • 9A to 9D and FIGS. 12A to 12D are enlarged cross-sectional views of the transistor 200 in the channel length direction.
  • an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor is used by sputtering method, chemical vapor deposition (CVD).
  • the film can be formed by appropriately using a method such as a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an ALD method.
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • sputtering methods include an RF sputtering method that uses a high frequency power source as a sputtering power source, a DC sputtering method that uses a DC power source, and a pulsed DC sputtering method that changes the voltage applied to the electrode in a pulsed manner.
  • the RF sputtering method is mainly used when forming an insulating film
  • the DC sputtering method is mainly used when forming a metal conductive film.
  • the pulsed DC sputtering method is mainly used when forming a film of a compound such as an oxide, nitride, or carbide by a reactive sputtering method.
  • the CVD method can be classified into a plasma CVD (PECVD) method that uses plasma, a thermal CVD (TCVD) method that uses heat, a photo CVD (Photo CVD) method that uses light, etc. Furthermore, depending on the raw material gas used, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method.
  • PECVD plasma CVD
  • TCVD thermal CVD
  • Photo CVD Photo CVD
  • MCVD metal CVD
  • MOCVD metal organic CVD
  • the plasma CVD method can obtain high-quality films at relatively low temperatures. Further, since the thermal CVD method does not use plasma, it is a film forming method that can reduce plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.
  • the ALD method a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, a PEALD method in which a plasma-excited reactant is used, etc. can be used.
  • the CVD method and ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.
  • a film of any composition can be formed by changing the flow rate ratio of source gases.
  • the flow rate ratio of source gases by changing the flow rate ratio of source gases during film formation, it is possible to form a film whose composition changes continuously.
  • the time required for film formation is reduced because it does not require time for transport or pressure adjustment. can do. Therefore, it may be possible to improve the productivity of semiconductor devices.
  • a film of any composition can be formed by simultaneously introducing a plurality of different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles for each precursor.
  • the insulator 215 can be the same insulator as any one of the insulators 224, the insulators 282, and the insulators 283, or a laminated film of a plurality of them.
  • a method for forming the insulator 215 for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method can be used. It is preferable to use a sputtering method that does not require the use of molecules containing hydrogen in the film-forming gas because the hydrogen concentration in the insulator 215 can be reduced.
  • an insulator 216 is formed on the insulator 215.
  • the insulator 216 is preferably formed using a sputtering method.
  • a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulator 216 can be reduced.
  • the method for forming the insulator 216 is not limited to the sputtering method, and may be appropriately performed using a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film is formed as the insulator 216 using a sputtering method.
  • the insulator 215 and the insulator 216 be formed continuously without being exposed to the atmosphere.
  • a multi-chamber type film forming apparatus may be used. Thereby, the insulator 215 and the insulator 216 can be formed while reducing hydrogen in the film, and furthermore, it is possible to reduce the amount of hydrogen mixed into the film between each film forming process.
  • an opening is formed in the insulator 216 to reach the insulator 215.
  • wet etching may be used to form the openings, it is preferable to use dry etching for fine processing.
  • an insulator for the insulator 215 that functions as an etching stopper film when etching the insulator 216 to form a groove.
  • silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove
  • silicon nitride, aluminum oxide, hafnium oxide, or the like is preferably used for the insulator 215.
  • the conductive film serving as the conductor 205a desirably includes a conductor having a function of suppressing permeation of oxygen.
  • a conductor having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it may be a laminated film of a conductor having a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy.
  • the conductive film that becomes the conductor 205a can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • titanium nitride is formed as a conductive film that becomes the conductor 205a.
  • a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like.
  • a metal that easily diffuses such as copper, it is possible to prevent the metal from diffusing out from the conductor 205a.
  • a conductive film that will become the conductor 205b is formed.
  • the conductive film serving as the conductor 205b tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, or the like can be used.
  • the conductive film can be formed using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • tungsten is formed as a conductive film that becomes the conductor 205b.
  • an insulator 222 is formed on the insulator 216 and the conductor 205 (see FIGS. 5A to 5D).
  • an insulator containing an oxide of one or both of aluminum and hafnium it is preferable to form an insulator containing an oxide of one or both of aluminum and hafnium.
  • the insulator containing an oxide of one or both of aluminum and hafnium it is preferable to use, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).
  • hafnium zirconium oxide it is preferable to use hafnium zirconium oxide.
  • An insulator containing oxides of one or both of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water.
  • the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in the structure provided around the transistor are suppressed from diffusing into the inside of the transistor through the insulator 222, thereby preventing oxidation. The generation of oxygen vacancies in the material 230 can be suppressed.
  • the insulator 222 can be a laminated film of an insulator containing an oxide of one or both of aluminum and hafnium, and silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide.
  • the insulator 222 can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • hafnium oxide is formed as the insulator 222 using an ALD method.
  • a laminated film of silicon nitride formed using the PEALD method and hafnium oxide formed using the ALD method may be used.
  • an insulating film 224f is formed on the insulator 222 (see FIGS. 5A to 5D).
  • an insulator corresponding to the insulator 224 described above may be used.
  • the insulating film 224f can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • silicon oxide is formed as the insulating film 224f using a sputtering method.
  • a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f comes into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • heat treatment may be performed before forming the insulating film 224f.
  • the heat treatment may be performed under reduced pressure to continuously form the insulating film 224f without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 222 can be removed, and the moisture concentration and hydrogen concentration in the insulator 222 can be further reduced.
  • the temperature of the heat treatment is preferably 100°C or more and 400°C or less. In this embodiment, the temperature of the heat treatment is 250°C.
  • an oxide film 230af is formed on the insulating film 224f, and an oxide film 230bf is formed on the oxide film 230af (see FIGS. 5A to 5D).
  • a metal oxide corresponding to the oxide 230a may be used
  • the oxide film 230bf a metal oxide corresponding to the oxide 230b may be used. Note that the oxide film 230af and the oxide film 230bf are preferably formed continuously without being exposed to the atmospheric environment.
  • the film By forming the film without exposing it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230af and the oxide film 230bf, and to prevent the vicinity of the interface between the oxide film 230af and the oxide film 230bf from adhering to the oxide film 230af and the oxide film 230bf. Can be kept clean.
  • the oxide film 230af and the oxide film 230bf can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, respectively.
  • a sputtering method is used to form the oxide film 230af and the oxide film 230bf.
  • oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas.
  • a noble gas By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased.
  • an In-M-Zn oxide target or the like can be used.
  • the proportion of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and even more preferably 100%.
  • the oxide film 230bf when forming the oxide film 230bf by sputtering, if the proportion of oxygen contained in the sputtering gas is more than 30% and less than 100%, preferably more than 70% and less than 100%, oxygen-excess oxidation occurs. A physical semiconductor is formed. A transistor using an oxygen-rich oxide semiconductor in a channel formation region has relatively high reliability. However, one embodiment of the present invention is not limited thereto.
  • an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less. Ru.
  • a transistor using an oxygen-deficient oxide semiconductor in a channel formation region can achieve relatively high field-effect mobility. Furthermore, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.
  • a film is formed using an oxide target with a numerical ratio].
  • an oxide target with In:Ga:Zn 4:2:4.1 [atomic ratio]
  • the insulating film 224f, the oxide film 230af, and the oxide film 230bf by a sputtering method without exposing them to the atmosphere.
  • the heat treatment may be performed within a temperature range in which the oxide films 230af and 230bf do not become polycrystalline.
  • the temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and 650°C or lower, 600°C or lower, or 550°C or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas.
  • the oxygen gas content is preferably about 20%.
  • the heat treatment may be performed under reduced pressure.
  • heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less.
  • the heat treatment is performed at a temperature of 450° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • Such heat treatment containing oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf.
  • the crystallinity of the oxide film 230bf can be improved and a denser and more precise structure can be obtained.
  • the crystal regions in the oxide films 230af and 230bf can be increased, and in-plane variations in the crystal regions in the oxide films 230af and 230bf can be reduced. Therefore, in-plane variations in the electrical characteristics of the transistor can be reduced.
  • hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf moves to the insulator 222 and is absorbed into the insulator 222.
  • hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf decrease.
  • the insulating film 224f (later the insulator 224) functions as the second gate insulator of the transistor 200
  • the oxide film 230af and the oxide film 230bf (later the oxide 230a and the oxide 230b) function as the second gate insulator of the transistor 200. Functions as a channel forming region.
  • the transistor 200 formed using the insulating film 224f, the oxide film 230af, and the oxide film 230bf with reduced hydrogen concentration is preferable because it has good reliability.
  • a conductive film 242_1f is formed on the oxide film 230bf, and a conductive film 242_2f is formed on the conductive film 242_1f (see FIGS. 5A to 5D).
  • a conductor corresponding to the conductors 242a1 and 242b1 may be used, and as the conductive film 242_2f, a conductor corresponding to the conductors 242a2 and 242b2 may be used.
  • the conductive film 242_1f is formed in contact with the oxide film 230bf without performing an etching process, so that the upper surface of the oxide film 230bf can be protected by the conductive film 242_1f. This can reduce the diffusion of impurities into the oxide 230 that constitutes the transistor, so that the electrical characteristics and reliability of the semiconductor device can be improved.
  • the conductive film 242_1f and the conductive film 242_2f can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, respectively.
  • tantalum nitride is formed as the conductive film 242_1f and tungsten is formed as the conductive film 242_2f using a sputtering method.
  • heat treatment may be performed before forming the conductive film 242_1f.
  • the heat treatment may be performed under reduced pressure to continuously form the conductive film 242_1f without exposure to the atmosphere. By performing such treatment, it is possible to remove moisture and hydrogen adsorbed on the surface of the oxide 230b, and further reduce the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b.
  • the temperature of the heat treatment is preferably 100°C or more and 400°C or less. In this embodiment, the temperature of the heat treatment is 250°C.
  • an insulating film 271f is formed on the conductive film 242_1f (see FIGS. 5A to 5D).
  • the insulating film 271f can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • As the insulating film 271f it is preferable to use an insulating film having a function of suppressing permeation of oxygen.
  • a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film may be formed by sputtering.
  • the insulating film 271f when forming the insulating film 271f as a laminated film, it is preferable to form the film continuously without exposing it to the atmospheric environment. By forming the film without exposing it to the atmosphere, the vicinity of the interface of the laminated film of the insulating film 271f can be kept clean. Further, it is more preferable that the conductive film 242_1f to the insulating film 271f be formed continuously without being exposed to the atmospheric environment.
  • heat treatment may be performed before forming the insulating film 271f.
  • the heat treatment may be performed under reduced pressure to continuously form the insulating film 271f without exposure to the atmosphere. By performing such processing, it is possible to remove moisture and hydrogen adsorbed on the surfaces of the conductive film 242_1f and the conductive film 242_2f, and further reduce the moisture concentration and hydrogen concentration in the conductive film 242_1f and the conductive film 242_2f. can.
  • the temperature of the heat treatment is preferably 100°C or more and 400°C or less. In this embodiment, the temperature of the heat treatment is 250°C.
  • the insulating film 224f, oxide film 230af, oxide film 230bf, conductive film 242_1f, conductive film 242_2f, and insulating film 271f are processed into island shapes, and the insulator 224, oxide 230a, and oxide
  • the object 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are formed (see FIGS. 6A to 6D).
  • a dry etching method or a wet etching method can be used for the above processing. Processing by dry etching is suitable for microfabrication. Further, the processing of the insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f may be performed under different conditions.
  • the insulator 224, oxide 230a, oxide 230b, conductor 242_1, conductor 242_2, and insulator 271 into an island shape all at once.
  • the side edges of the conductor 242_1 and the side edges of the conductor 242_2 substantially coincide with the side edges of the oxide 230a and the oxide 230b.
  • the side edges of the insulator 224 substantially coincide with the side edges of the oxide 230.
  • the side end portion of the insulator 271 approximately coincides with the side end portion of the conductor 242_2.
  • the insulator 224, oxide 230a, oxide 230b, conductor 242_1, conductor 242_2, and insulator 271 are formed so that at least a portion thereof overlaps with the conductor 205. Further, the insulator 222 is exposed in a region that does not overlap with the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271.
  • the side surfaces of the insulator 224, oxide 230a, oxide 230b, conductor 242_1, conductor 242_2, and insulator 271 may have a tapered shape.
  • the taper angles of the side surfaces of the insulator 224, oxide 230a, oxide 230b, conductor 242_1, conductor 242_2, and insulator 271 may be, for example, 60° or more and less than 90°.
  • the structure is not limited to the above, and the side surfaces of the insulator 224, oxide 230a, oxide 230b, conductor 242_1, conductor 242_2, and insulator 271 are approximately perpendicular to the upper surface of the insulator 222. Good too. With such a configuration, it is possible to reduce the area and increase the density when providing a plurality of transistors.
  • a resist mask is formed by removing or leaving the exposed area using a developer.
  • a conductor, semiconductor, insulator, or the like can be processed into a desired shape.
  • a resist mask can be formed by exposing a resist to light using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the light described above. Note that when using an electron beam or an ion beam, it may not be necessary to use a mask.
  • dry etching treatment such as ashing using oxygen plasma treatment
  • dry etching treatment such as ashing using oxygen plasma treatment
  • wet etching treatment perform wet etching treatment after dry etching treatment
  • dry etching treatment after wet etching treatment perform dry etching treatment after wet etching treatment. It can be removed by doing this.
  • a hard mask made of an insulator or a conductor may be used under the resist mask.
  • an insulating film or a conductive film serving as a hard mask material is formed on the insulating film 271f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask in a desired shape. can do.
  • Etching of the insulating film 271f etc. may be performed after removing the resist mask, or may be performed with the resist mask remaining. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after etching the oxide film 230bf and the like.
  • the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask.
  • a configuration may be adopted in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are formed between the workpiece and the resist mask.
  • SOC film and the SOG film As a mask, it is possible to improve the adhesion with the resist mask and improve the durability of the mask pattern.
  • a configuration in which a lithography method is performed by forming an SOC film, an SOG film, and a resist mask in this order on a workpiece will be explained in the steps shown in FIGS. 9A to 9D and FIGS. 12A to 12D, which will be described later. Therefore, you can refer to the description in the relevant section.
  • an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used.
  • an etching gas containing one or more of fluorine, chlorine, and bromine can be used.
  • C 4 F 6 gas, C 5 F 6 gas, C 4 F 8 gas, CF 4 gas, SF 6 gas, CHF 3 gas, CH 2 F 2 gas, Cl 2 gas, BCl 3 gas, SiCl 4 gas, BBr 3 gas, or the like can be used alone or in combination of two or more gases.
  • oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, hydrocarbon gas, or the like can be added as appropriate to the above etching gas.
  • a gas that does not contain halogen gas but contains hydrocarbon gas or hydrogen gas may be used as the etching gas.
  • Hydrocarbons used for etching gas include methane (CH 4 ), ethane (C 2 H 6 ), propane (C 3 H 8 ), butane (C 4 H 10 ), ethylene (C 2 H 4 ), propylene (C 3 H 6 ), acetylene (C 2 H 2 ), and propyne (C 3 H 4 ).
  • Etching conditions can be set as appropriate depending on the object to be etched.
  • a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used as the dry etching device.
  • a capacitively coupled plasma etching apparatus having parallel plate electrodes may have a configuration in which a high frequency voltage is applied to one electrode of the parallel plate electrodes.
  • a configuration may be adopted in which a plurality of different high frequency voltages are applied to one electrode of a parallel plate type electrode.
  • a configuration may be adopted in which a high frequency voltage of the same frequency is applied to each of the parallel plate type electrodes.
  • a configuration may be adopted in which high frequency voltages having different frequencies are applied to each of the parallel plate type electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • the dry etching device having a high-density plasma source for example, an inductively coupled plasma (ICP) etching device or the like can be used.
  • ICP inductively coupled plasma
  • the insulator 271 can function as an etching stopper that protects the conductor 242_2.
  • the insulator 271 can function as an etching stopper that protects the conductor 242_2.
  • the insulator 271 can function as an etching stopper that protects the conductor 242_2 during the etching process for removing the hard mask.
  • the insulator 275 can be provided in contact with the side surface of the insulator 224 and the top surface of the insulator 222 in a step described later.
  • the insulator 224 can be separated from the insulator 280, which will be manufactured in a later step, by the insulator 275.
  • the insulator 224 of approximately the same size is provided for one transistor 200.
  • the amount of oxygen supplied from the insulator 224 to the oxide 230 becomes approximately the same. Therefore, variations in the electrical characteristics of the transistor 200 within the plane of the substrate can be suppressed.
  • the invention is not limited to this, and similarly to the insulator 222, the insulator 224 may be configured without patterning.
  • an insulator 275 is formed to cover the insulator 224, oxide 230a, oxide 230b, conductor 242_1, conductor 242_2, and insulator 271, and then an insulator 280 is formed on the insulator 275. (See FIGS. 7A to 7D). As the insulator 275 and the insulator 280, the above-mentioned insulators may be used.
  • the insulator 275 is preferably in contact with the upper surface of the insulator 222.
  • the insulator 280 it is preferable to form an insulating film that will become the insulator 280 and perform a CMP process on the insulating film to form an insulator with a flat top surface.
  • silicon nitride may be formed on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280.
  • the insulator 275 and the insulator 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulator 275 it is preferable to use an insulator for the insulator 275 that has a function of suppressing oxygen permeation.
  • the insulator 275 it is preferable to form a film of silicon nitride using the PEALD method.
  • the insulator 275 it is preferable to form a film of aluminum oxide using a sputtering method, and to form a film of silicon nitride thereon using a PEALD method.
  • the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 can be covered with the insulator 275 that has the function of suppressing oxygen diffusion. This can reduce direct diffusion of oxygen from the insulator 280 and the like into the insulator 224, oxide 230a, oxide 230b, conductor 242_1, and conductor 242_2 in a later process.
  • the insulator 280 it is preferable to form a film of silicon oxide using a sputtering method.
  • the insulator 280 containing excess oxygen can be formed by forming an insulating film that will become the insulator 280 by a sputtering method in an atmosphere containing oxygen. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the film-forming gas, the hydrogen concentration in the insulator 280 can be reduced.
  • heat treatment may be performed before forming the insulating film. The heat treatment may be performed under reduced pressure to continuously form the insulating film without exposing it to the atmosphere.
  • the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 are processed to form an opening that reaches the conductor 242_1 and the insulator 222 (see FIGS. 8A to 8D).
  • the conductor 242_2 is divided to form a conductor 242a2 and a conductor 242b2
  • the insulator 271 is divided to form an insulator 271a and an insulator 271b.
  • An opening reaching the conductor 242_1 is formed in a region where the oxide 230b and the conductor 205 overlap.
  • the width of the opening is L1, which corresponds to the distance L1 between the conductor 242a2 and the conductor 242b2 described above.
  • the above methods can be used as appropriate.
  • a lithography method using short wavelength light such as EUV light or an electron beam.
  • a coating film 277f is formed on the insulator 280, and then a coating film 278f is further formed (FIG. 9A).
  • the coating film 277f and the coating film 278f may have a function of improving adhesion to the resist mask.
  • the coating film 277f and the coating film 278f may be formed using, for example, a spin coating method.
  • a non-photosensitive organic resin may be used as the coating film 277f and the coating film 278f.
  • an SOC film is formed as the coating film 277f
  • an SOG film is formed as the coating film 278f.
  • the coating films 277f and 278f contain organic solvents such as alcohol during coating, but the organic substances contained therein may be reduced or removed during subsequent steps or when the semiconductor device is completed.
  • the coating film may be provided as necessary, and the coating film may be configured as a single layer, or if only a resist mask, which will be described later, is sufficient, a configuration may be adopted in which no coating film is provided.
  • a resist mask 279 is formed on the coating film 278f using a lithography method (FIG. 9A).
  • a lithography method FIG. 9A
  • an opening having a width L1 is formed in a cross-sectional view in the channel length direction.
  • a photosensitive organic resin also called photoresist may be used.
  • a positive photoresist or a negative photoresist can be used.
  • the photoresist serving as the resist mask 279 can be formed to have a uniform thickness by, for example, using a spin coating method.
  • the structure shown in FIG. 9A is etched using a dry etching method.
  • the dry etching method allows anisotropic etching and is therefore suitable for forming an opening with a high aspect ratio and a width L1. Note that the above description can be referred to regarding the conditions of the dry etching method and the dry etching apparatus. Further, the etching treatment of the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 may be performed under different conditions.
  • the coating film 278f is processed using the resist mask 279 to form the coating film 278, and the coating film 277f is further processed to form the coating film 277 (FIG. 9B).
  • an opening having a width L1 is formed in the coating film 278 and the coating film 277.
  • CF 4 can be used as the etching gas.
  • H 2 and N 2 can be used as the etching gas.
  • the resist mask 279 may disappear before the coating film 277 is formed. If the resist mask 279 remains after the coating film 277 is formed, the resist mask 279 may be removed.
  • the insulator 280 is processed to form an opening with a width L1
  • the insulator 275 is further processed to form an opening with a width L1 (FIG. 9C).
  • silicon oxide is used for the insulator 280
  • C 4 F 8 , C 4 F 6 , O 2 , and Ar can be used as the etching gas.
  • silicon nitride is used for the insulator 275
  • CH 2 F 2 , O 2 , and Ar can be used as the etching gas.
  • the insulator 271 is processed and divided to form an insulator 271a and an insulator 271b (FIG. 9C).
  • the region between the insulator 271a and the insulator 271b overlaps with the opening having the width L1, and the distance between the insulator 271a and the insulator 271b is L1.
  • etching can be performed using an ICP etching apparatus using CHF 3 and O 2 as etching gases.
  • the conductor 242_2 is processed and divided to form a conductor 242a2 and a conductor 242b2 (FIG. 9D).
  • the region between the conductor 242a2 and the conductor 242b2 overlaps with the opening having the width L1, and the distance between the conductor 242a2 and the conductor 242b2 is L1.
  • etching can be performed using an ICP etching apparatus using CF 4 , Cl 2 , and O 2 as etching gases.
  • the etching process in this step is stopped at the upper surface of the conductor 242_1.
  • the etching process is performed using an ICP etching apparatus under conditions that the etching rate of the conductor 242_2 (hereinafter referred to as the etching selectivity ratio of the conductor 242_2) is larger than the etching rate of the conductor 242_1. conduct.
  • the bias power applied to the lower electrode of the ICP etching apparatus may be less than 50 W, preferably about 25 W or less.
  • the tungsten of the conductor 242_2 becomes a highly volatile reaction product such as WF 6 or WOCl, resulting in a high etching rate.
  • tantalum nitride on the surface of the conductor 242_1 becomes a reaction product with very low volatility, such as tantalum oxide or tantalum oxynitride, and etching is suppressed. Therefore, by increasing the flow rate ratio of oxygen gas in the etching gas, the etching selectivity of the conductor 242_2 can be increased.
  • the flow rate ratio of oxygen gas in the etching gas may be greater than 35%, and may be about 48% or more.
  • the etching selectivity of the conductor 242_2 can be increased. Therefore, the conductor 242_1 can be separated into the conductor 242a2 and the conductor 242b2 without excessively etching the conductor 242_1. Thereby, even a semiconductor device having a fine structure can be processed as designed.
  • the coating film 277 can be formed by performing a dry etching process such as ashing using oxygen plasma, by performing a wet etching process, by performing a wet etching process after a dry etching process, or by performing a dry etching process after a wet etching process. Just remove it.
  • a dry etching process such as ashing using oxygen plasma
  • the processing of the insulator 271 and the conductor 242_2 and the removal of the coating film 277 can be performed continuously without exposing them to the outside air.
  • a multi-chamber type etching apparatus may be used to perform the process without exposing it to the outside air.
  • the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 can be processed to form an opening with the width L1.
  • an insulating film 255A is formed to cover the insulator 280, the conductor 242_1, and the insulator 222 (see FIGS. 10A to 10D).
  • the insulating film 255A is an insulating film that will become the insulator 255 in a later step, and the above-mentioned insulator can be used.
  • the insulating film 255A can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film 255A is formed along the openings formed in the conductor 242a2, the conductor 242b2, the insulator 271, the insulator 275, and the insulator 280, it is preferable that the insulating film 255A has good coverage. Therefore, the insulating film 255A is preferably formed using an ALD method or the like that has good coverage. For example, it is preferable to form silicon nitride as the insulating film 255A using the PEALD method.
  • the conductor 242_1 and the insulating film 255A are processed within the opening formed in the insulator 280 to form an opening that reaches the oxide 230b (see FIGS. 11A to 11D).
  • an insulator 255 having an opening is formed from the insulating film 255A, and the conductor 242_1 is divided to form a conductor 242a1 and a conductor 242b1.
  • the width of the opening is L2, which corresponds to the distance L2 between the conductor 242a1 and the conductor 242b1 described above. Since the opening is formed inside the opening formed in the insulator 280, the distance L2 between the conductor 242a1 and the conductor 242b1 is shorter than the distance L1 between the conductor 242a2 and the conductor 242b2.
  • the above methods can be used as appropriate.
  • a lithography method using short wavelength light such as EUV light or an electron beam.
  • an opening is formed in the insulator 255 to expose the island-shaped oxide 230 in the opening, but the present invention is not limited to this.
  • the conductor 242a1 and the conductor 242b1 may be separated by a distance L2. Therefore, for example, an opening substantially similar to the opening formed in the insulator 280 may be formed in the insulator 255, except for the portions that contact the upper surfaces of the conductor 242a1 and the conductor 242b1.
  • the insulator 255 may be formed in a sidewall shape in contact with the sidewall of the opening formed in the insulator 280.
  • a coating film 287f is formed on the insulating film 255A, and then a coating film 288f is formed (FIG. 12A).
  • the coating film 287f is provided so as to fill the recessed portion of the insulating film 255A.
  • the coating film 287f can have the same configuration as the coating film 277f, and the coating film 288f can have the same configuration as the coating film 278f, so the above description can be referred to.
  • a resist mask 289 is formed on the coating film 288f using a lithography method (FIG. 12A).
  • an opening having a width L2 is formed in a cross-sectional view in the channel length direction.
  • a resist mask 289 is formed so that an opening having a width L2 is located inside the opening of the insulator 280 and overlaps with the oxide 230b when viewed from above.
  • the resist mask 289 can have the same configuration as the resist mask 279, so the above description can be referred to.
  • the structure shown in FIG. 12A is etched using a dry etching method.
  • the dry etching method allows anisotropic etching and is therefore suitable for forming an opening with a high aspect ratio and a width L2. Note that the above description can be referred to regarding the conditions of the dry etching method and the dry etching apparatus. Further, the etching process for the conductor 242_2 and the insulating film 255A may be performed under different conditions.
  • the coating film 288f is processed to form the coating film 288, and the coating film 287f is further processed to form the coating film 287 (FIG. 12B).
  • an opening with a width L2 is formed in the coating film 288 and the coating film 287, and the insulating film 255A is exposed.
  • the processing of the coating film 288f and the coating film 287f is similar to that of the coating film 278f and the coating film 277f, so the above description can be referred to.
  • the insulating film 255A is processed to form an opening, and the insulator 255 is formed.
  • the width of the opening of the insulator 255 is L2.
  • etching can be performed using an ICP etching apparatus using CHF 3 and O 2 as etching gases.
  • the conductor 242_1 is processed and divided to form a conductor 242a1 and a conductor 242b1 (FIG. 12D).
  • etching can be performed using an ICP etching apparatus using Cl 2 and Ar as an etching gas.
  • the region between the conductor 242a1 and the conductor 242b1 overlaps with the opening having the width L2, and the distance between the conductor 242a1 and the conductor 242b1 is L2.
  • the side edge of the insulator 255 is aligned with the side edge of the conductor 242a1 and the conductor 242_1. It is formed to approximately match the side end portion of the body 242b1.
  • the coating film 287 can be formed by performing a dry etching process such as ashing using oxygen plasma, by performing a wet etching process, by performing a wet etching process after a dry etching process, or by performing a dry etching process after a wet etching process. Just remove it.
  • a dry etching process such as ashing using oxygen plasma
  • processing of the insulating film 255A and the conductor 242_1 and the removal of the coating film 287 can be performed continuously without exposing to the outside air.
  • a multi-chamber type etching apparatus may be used to perform the process without exposing it to the outside air.
  • the conductors 242a1 and 242b1 having a distance of L2 from each other can be formed under the conductors 242a2 and 242b2 having a distance of L1 from each other.
  • the distance between the source and drain of the transistor 200 can be shortened, so that the frequency characteristics of the transistor 200 and the operating speed of the semiconductor device can be improved.
  • the above etching process may cause impurities to adhere to the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, the side surfaces of the conductors 242a and 242b, or to diffuse into the interior thereof.
  • a step of removing such impurities may be performed.
  • a damaged region may be formed on the surface of the oxide 230b by the dry etching. Such damaged areas may be removed.
  • the impurities include components included in the insulator 280, the insulator 275, the insulators 271a and 271b, and the conductors 242a and 242b, components included in the members of the device used to form the opening, and Examples include those caused by components contained in the gas or liquid used for etching.
  • Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.
  • impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, it is preferable that impurities such as aluminum and silicon be removed from the surface of the oxide 230b and its vicinity. Moreover, it is preferable that the concentration of the impurity is reduced.
  • the concentration of aluminum atoms on the surface of the oxide 230b and in its vicinity is preferably 5.0 atom % or less, more preferably 2.0 atom % or less, more preferably 1.5 atom % or less, and 1.0 atom % or less. % or less, more preferably less than 0.3 atomic %.
  • the region of the oxide 230b with low crystallinity is preferably reduced or removed.
  • the oxide 230b has a layered CAAC structure.
  • the conductor 242a or the conductor 242b preferably functions as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a or the conductor 242b has a CAAC structure. In this way, the region with low crystallinity of the oxide 230b is removed even at the drain end, which significantly affects the drain breakdown voltage, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor can be further suppressed. . Further, reliability of the transistor can be improved.
  • a cleaning process is performed to remove impurities and the like that adhered to the surface of the oxide 230b in the above etching process.
  • the cleaning method include wet cleaning using a cleaning liquid (also referred to as wet etching treatment), plasma treatment using plasma, cleaning by heat treatment, etc., and the above cleaning may be performed in an appropriate combination. Note that the groove portion may become deeper due to the cleaning treatment.
  • Wet cleaning may be performed using an aqueous solution prepared by diluting one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with carbonated water or pure water, pure water, carbonated water, or the like.
  • ultrasonic cleaning may be performed using an aqueous solution of these, pure water, or carbonated water.
  • these cleanings may be performed in combination as appropriate.
  • an aqueous solution of hydrofluoric acid diluted with pure water may be referred to as diluted hydrofluoric acid
  • an aqueous solution of ammonia water diluted with pure water may be referred to as diluted ammonia water.
  • concentration, temperature, etc. of the aqueous solution are adjusted as appropriate depending on the impurities to be removed, the configuration of the semiconductor device to be cleaned, etc.
  • the ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, more preferably 0.1% or more and 0.5% or less.
  • the hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, more preferably 0.1 ppm or more and 10 ppm or less.
  • a frequency of 200 kHz or more and more preferably a frequency of 900 kHz or more for ultrasonic cleaning.
  • a frequency of 200 kHz or more and more preferably a frequency of 900 kHz or more for ultrasonic cleaning.
  • the above-mentioned cleaning process may be performed multiple times, and the cleaning liquid may be changed for each cleaning process.
  • the first cleaning process may be performed using diluted hydrofluoric acid or diluted aqueous ammonia
  • the second cleaning process may be performed using pure water or carbonated water.
  • wet cleaning is performed using diluted ammonia water.
  • impurities attached to the surface of the oxide 230a, the oxide 230b, or the like or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.
  • the temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and 650°C or lower, 600°C or lower, 550°C or lower, or 400°C or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas.
  • the heat treatment is preferably performed in an atmosphere containing oxygen, and for example, the treatment is preferably performed at a temperature of 350° C. for 1 hour at a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • oxygen can be supplied to the oxide 230a and the oxide 230b, and oxygen vacancies can be reduced. Further, by performing such heat treatment, the crystallinity of the oxide 230b can be improved. Further, the hydrogen remaining in the oxide 230a and the oxide 230b reacts with the supplied oxygen, so that the hydrogen can be removed as H 2 O (dehydrated). This can suppress hydrogen remaining in the oxides 230a and 230b from recombining with oxygen vacancies and forming V O H. Accordingly, the electrical characteristics of the transistor provided with the oxide 230 can be improved, and reliability can be improved. Further, variations in electrical characteristics of a plurality of transistors formed over the same substrate can be suppressed. Note that the above heat treatment may be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, heat treatment may be performed continuously in a nitrogen atmosphere without exposure to the atmosphere.
  • the sheet resistance of the region of the oxide 230b that overlaps with the conductor 242a and the region that overlaps with the conductor 242b decreases.
  • the carrier concentration may increase. Therefore, the resistance of the region of the oxide 230b that overlaps with the conductor 242a and the region that overlaps with the conductor 242b can be reduced in a self-aligned manner.
  • the insulator 255 having an inorganic insulator that is difficult to oxidize is provided in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2.
  • an insulating film 250A that will become the insulator 250 is formed so as to fill the opening formed in the insulator 280 (see FIGS. 13A to 13D).
  • the insulating film 250A is formed so as to be in contact with the insulator 255, but in the region where the opening is formed in the insulator 255, the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b be in contact with
  • the insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film 250A is preferably formed using an ALD method. Similar to the above-described insulator 250, the insulating film 250A is preferably formed to have a small thickness, and it is necessary to minimize variations in the film thickness.
  • the ALD method is a film forming method in which a precursor and a reactant (such as an oxidizing agent) are introduced alternately, and the film thickness can be adjusted by the number of times this cycle is repeated. Film thickness can be adjusted.
  • the insulating film 250A needs to be formed on the bottom and side surfaces of the opening with good coverage.
  • a layer of atoms can be deposited one layer at a time on the bottom and side surfaces of the opening, so the insulating film 250A can be formed with good coverage over the opening.
  • ozone (O 3 ), oxygen (O 2 ), water (H 2 O), or the like can be used as an oxidizing agent.
  • oxygen (O 2 ), or the like that does not contain hydrogen as an oxidizing agent, hydrogen that diffuses into the oxide 230b can be reduced.
  • the insulator 250 can have a layered structure, as shown in FIG. 2A and the like.
  • aluminum oxide is formed as an insulating film to become an insulator 250a by a thermal ALD method
  • silicon oxide is formed as an insulating film to become an insulator 250b by a PEALD method
  • an insulator 250c is formed as an insulating film by a PEALD method.
  • silicon nitride can be formed by the PEALD method.
  • FIG. 2A aluminum oxide is formed as an insulating film to become an insulator 250a by a thermal ALD method
  • silicon oxide is formed as an insulating film to become an insulator 250b by a PEALD method
  • an insulator 250c is formed as an insulating film by a PEALD method.
  • silicon nitride can be formed by the PEALD method.
  • aluminum oxide is formed as an insulating film to become the insulator 250a by a thermal ALD method
  • silicon nitride is formed as an insulating film to become an insulator 250c by a PEALD method. I can do it.
  • aluminum oxide is formed as an insulating film to become an insulator 250a by thermal ALD method
  • silicon oxide is formed as an insulating film to become an insulator 250b by PEALD method.
  • Hafnium oxide can be formed as an insulating film to become the body 250d by a thermal ALD method
  • silicon nitride can be formed by a PEALD method to be an insulating film to become an insulator 250c.
  • microwave processing refers to processing using, for example, a device having a power source that generates high-density plasma using microwaves.
  • microwave refers to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • the microwave treatment is not necessarily performed after all the insulating films 250A are formed. For example, in the case of the structure shown in FIG. 2A, after forming an insulating film to become an insulator 250a and an insulating film to become an insulator 250b, microwave treatment is performed, and then an insulating film to become an insulator 250c is formed. You may.
  • microwave treatment may be performed after forming an insulating film that will become the insulator 250a, and then an insulating film that will become the insulator 250c.
  • microwave treatment is performed after forming an insulating film to become the insulator 250a and an insulating film to become the insulator 250b, and then an insulating film to become the insulator 250d.
  • microwave treatment may be performed, and then an insulating film serving as the insulator 250c may be formed. In this way, the microwave treatment in an atmosphere containing oxygen may be performed multiple times (at least twice or more).
  • the microwave processing device that has a power source that generates high-density plasma using microwaves, for example.
  • the frequency of the microwave processing device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be set to 2.45 GHz, for example.
  • the power of the power source for applying microwaves of the microwave processing device is preferably 1000 W or more and 10000 W or less, and preferably 2000 W or more and 5000 W or less.
  • the microwave processing apparatus may have a power source for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide 230b.
  • the microwave treatment is preferably performed under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, and more preferably 300 Pa or more and 700 Pa or less.
  • the processing temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C.
  • heat treatment may be performed continuously without exposing to outside air.
  • the temperature of the heat treatment is, for example, preferably 100°C or more and 750°C or less, more preferably 300°C or more and 500°C or less.
  • the microwave treatment can be performed using oxygen gas and argon gas.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than or equal to 100%.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than or equal to 50%.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is 10% or more and 40% or less.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is 10% or more and 30% or less.
  • oxygen gas is turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma is transferred between the conductor 242a and the conductor 242b of the oxide 230b. It can be applied to the area.
  • V OH in the region can be separated into oxygen vacancies and hydrogen, and hydrogen can be removed from the region.
  • an insulating film for example, aluminum oxide
  • V OH contained in the channel forming region can be reduced.
  • oxygen vacancies and V OH in the channel formation region can be reduced, and the carrier concentration can be lowered.
  • oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, it is possible to further reduce the oxygen vacancies in the channel formation region and lower the carrier concentration.
  • the oxygen implanted into the channel forming region has various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also referred to as O radicals; atoms, molecules, or ions with unpaired electrons).
  • oxygen injected into the channel forming region may be in one or more of the above-mentioned forms, and oxygen radicals are particularly preferred.
  • the film quality of the insulator 250 can be improved, reliability of the transistor is improved.
  • the oxide 230b has a region that overlaps with either the conductor 242a or 242b.
  • the region can function as a source region or a drain region.
  • the conductors 242a and 242b preferably function as shielding films against the effects of microwaves, high frequencies such as RF, oxygen plasma, and the like when performing microwave processing in an atmosphere containing oxygen. Therefore, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.
  • the conductors 242a and 242b shield the effects of microwaves, high frequencies such as RF, oxygen plasma, and the like, these effects do not extend to the region of the oxide 230b that overlaps with any of the conductors 242a and 242b. Thereby, a reduction in V OH and an excessive amount of oxygen supply do not occur in the source region and the drain region due to the microwave treatment, so that a decrease in carrier concentration can be prevented.
  • an insulator 255 and an insulator 250 having barrier properties against oxygen are provided in contact with the side surfaces of the conductors 242a and 242b. Thereby, formation of an oxide film on the side surfaces of the conductors 242a and 242b due to microwave treatment can be suppressed.
  • oxygen vacancies and V OH are selectively removed in the channel formation region of the oxide semiconductor, thereby making the channel formation region i-type or substantially i-type. Furthermore, it is possible to suppress supply of excessive oxygen to a region functioning as a source region or a drain region, and maintain the conductivity (state of being a low resistance region) before performing microwave treatment. Thereby, it is possible to suppress variations in the electrical characteristics of the transistor, and to suppress variations in the electrical characteristics of the transistor within the plane of the substrate.
  • thermal energy may be directly transmitted to the oxide 230b due to electromagnetic interaction between the microwave and molecules in the oxide 230b. This thermal energy may heat the oxide 230b.
  • Such heat treatment is sometimes called microwave annealing.
  • microwave annealing By performing microwave treatment in an atmosphere containing oxygen, effects equivalent to oxygen annealing may be obtained.
  • the oxide 230b contains hydrogen, it is possible that this thermal energy is transferred to the hydrogen in the oxide 230b, and thereby activated hydrogen is released from the oxide 230b.
  • microwave treatment may not be performed after forming the insulating film 250A, but may be performed before forming the insulating film.
  • heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment after forming the insulating film 250A.
  • hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be efficiently removed. Further, some of the hydrogen may be gettered to the conductors 242a and 242b.
  • the step of performing the heat treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment. By repeatedly performing the heat treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be removed more efficiently.
  • the heat treatment temperature is preferably 300°C or more and 500°C or less.
  • the microwave treatment that is, microwave annealing, may also serve as the heat treatment. If the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.
  • a conductive film 260A that will become the conductor 260a and a conductive film 260B that will become the conductor 260b are sequentially formed (see FIGS. 14A to 14D).
  • the conductive film 260A and the conductive film 260B can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method.
  • titanium nitride is formed as a conductive film 260A using an ALD method
  • tungsten is formed as a conductive film 260B using a CVD method.
  • the insulator 255, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished until the insulator 280 is exposed. That is, the portions of the insulator 255, the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the opening are removed. As a result, an insulator 255, an insulator 250, and a conductor 260 (a conductor 260a and a conductor 260b) are formed in the opening overlapping the conductor 205 (see FIGS. 15A to 15D).
  • the insulator 255 is provided in contact with a part of the side wall and bottom surface of the opening formed in the insulator 280. Further, the insulator 250 is provided in the opening in contact with the insulator 255 and the oxide 230, the insulator 224, and the insulator 222 exposed from the insulator 255. Further, the conductor 260 is arranged so as to fill the opening with the insulator 250 interposed therebetween. In this way, transistor 200 is formed.
  • an insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 1A to 1D).
  • the insulator 282 can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulator 282 is preferably formed using a sputtering method.
  • the hydrogen concentration in the insulator 282 can be reduced by using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas.
  • oxygen can be added to the insulator 280 while forming the film. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate.
  • aluminum oxide is formed as the insulator 282 by sputtering using an aluminum target in an atmosphere containing oxygen gas.
  • the amount of oxygen injected into the layer below the insulator 282 can be controlled by the magnitude of RF power applied to the substrate by sputtering. For example, as the RF power decreases, the amount of oxygen injected into the layer below the insulator 282 decreases, and even if the thickness of the insulator 282 is thin, the amount of oxygen becomes saturated easily. Furthermore, as the RF power increases, the amount of oxygen injected into the layer below the insulator 282 increases. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed.
  • the insulator 282 may be formed in a two-layer stacked structure. At this time, for example, the lower layer of the insulator 282 is formed without applying RF power to the substrate, and the upper layer of the insulator 282 is formed by applying RF power to the substrate.
  • the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate can be.
  • heat treatment may be performed before forming the insulator 282.
  • the heat treatment may be performed under reduced pressure to continuously form the insulator 282 without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed, and the moisture concentration and hydrogen concentration in the insulator 280 can be further reduced.
  • the temperature of the heat treatment is preferably 100°C or more and 400°C or less. In this embodiment, the temperature of the heat treatment is 250°C.
  • an insulator 283 is formed on the insulator 282 (see FIGS. 1A to 1D).
  • the insulator 283 can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulator 283 is preferably formed using a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulator 283 can be reduced.
  • silicon nitride is formed as the insulator 283 by using a sputtering method.
  • the insulator 282 and the insulator 283 be formed continuously without being exposed to the atmospheric environment.
  • the film By forming the film without exposing it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulator 282 and the insulator 283, and to clean the vicinity of the interface between the insulator 282 and the insulator 283. can be kept.
  • the semiconductor device shown in FIG. 1 can be manufactured.
  • the conductor on the oxide semiconductor has a two-layer structure, a conductor that is difficult to oxidize is used in the lower layer, and a conductor with high conductivity is used in the upper layer.
  • a conductor that functions as an electrode or wiring is provided in contact with the upper surface of the physical semiconductor.
  • the conductor functions as a source electrode and a drain electrode of the OS transistor.
  • the distance between the conductors in the lower layer of the source electrode and the drain electrode is made shorter than the distance between the conductors in the upper layer of the source electrode and the drain electrode, thereby achieving miniaturization. It is possible to improve the frequency characteristics and operation speed of the device.
  • an insulator functioning as a protective film is provided in contact with the side surface of the conductor in the upper layer of the source electrode and the drain electrode.
  • the semiconductor device includes an OS transistor. Since an OS transistor has a small off-state current, it is possible to realize a semiconductor device or a memory device with low power consumption. Further, since the OS transistor has high frequency characteristics, it is possible to realize a semiconductor device or a memory device with high operating speed. Further, by using an OS transistor, a semiconductor device with good electrical characteristics, a semiconductor device with less variation in the electrical characteristics of transistors, a semiconductor device with a large on-state current, and a highly reliable semiconductor device or memory device can be realized.
  • the carrier concentration in the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably less than 1 ⁇ 10 17 cm ⁇ 3 , more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , and even more preferably 1 ⁇ It is less than 10 13 cm ⁇ 3 , more preferably less than 1 ⁇ 10 10 cm ⁇ 3 , and more than 1 ⁇ 10 ⁇ 9 cm ⁇ 3 . Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic.
  • an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or a substantially high-purity intrinsic oxide semiconductor.
  • a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has a low defect level density
  • the trap level density may also be low.
  • charges captured in trap levels of an oxide semiconductor may take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.
  • the impurity in the oxide semiconductor refers to, for example, a substance other than the main component that constitutes the oxide semiconductor.
  • an element having a concentration of less than 0.1 atomic % can be considered an impurity.
  • V OH oxygen vacancy in an oxide semiconductor
  • the donor concentration in the channel formation region may increase.
  • the threshold voltage may vary. Therefore, if the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor exhibits normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and current flows through the transistor). It's easy to become. Therefore, impurities, oxygen vacancies, and V OH are preferably reduced as much as possible in the channel formation region in the oxide semiconductor.
  • the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. It is.
  • off-state current also referred to as Ioff
  • Ioff off-state current
  • Si transistors As transistors become smaller, a short channel effect (also referred to as SCE) occurs. Therefore, it is difficult to miniaturize Si transistors.
  • SCE short channel effect
  • silicon has a small band gap.
  • an OS transistor uses an oxide semiconductor, which is a semiconductor material with a large band gap, short channel effects can be suppressed. In other words, an OS transistor is a transistor that has no short channel effect or has very little short channel effect.
  • the short channel effect is a deterioration in electrical characteristics that becomes apparent as transistors become smaller (reduction in channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage in a subthreshold region that causes a drain current to change by one order of magnitude with a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • the characteristic length is an index of the bendability of the potential in the channel forming region. The smaller the characteristic length, the more steeply the potential rises, so it can be said to be resistant to short channel effects.
  • the OS transistor is an accumulation type transistor, and the Si transistor is an inversion type transistor. Therefore, compared to a Si transistor, an OS transistor has a smaller characteristic length between the source region and the channel forming region and a smaller characteristic length between the drain region and the channel forming region. Therefore, OS transistors are more resistant to short channel effects than Si transistors. That is, when it is desired to manufacture a transistor with a short channel length, an OS transistor is more suitable than a Si transistor.
  • the carrier concentration of the oxide semiconductor is lowered until the channel formation region becomes i-type or substantially i-type, conduction in the channel formation region decreases due to the conduction-band-lowering (CBL) effect in short-channel transistors. Since the lower end of the conduction band is lowered, the energy difference at the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to 0.1 eV or more and 0.2 eV or less.
  • the OS transistor has an n + / n- / n + accumulation type junction-less transistor structure, in which the channel forming region becomes an n-type region and the source and drain regions become n + -type regions, or , n + /n ⁇ /n + storage type non-junction transistor structure.
  • the OS transistor By making the OS transistor have the above structure, it can have good electrical characteristics even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and it is 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics cannot be obtained. can. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.
  • the high frequency characteristics of the transistor can be improved.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to 50 GHz or more, preferably 100 GHz or more, more preferably 150 GHz or more, for example in a room temperature environment.
  • OS transistors have superior effects compared to Si transistors, such as lower off-state current and the ability to manufacture transistors with shorter channel lengths.
  • This embodiment mode describes a configuration example of a memory device in which a layer having a functional circuit having a function of amplifying and outputting a data potential held in a memory cell is provided between layers having stacked memory cells. explain.
  • FIG. 16 shows a block diagram of a storage device according to one embodiment of the present invention.
  • the storage device 300 shown in FIG. 16 includes a drive circuit 21 and a memory array 20.
  • the memory array 20 includes a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51.
  • FIG. 16 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). Further, FIG. 16 shows an example in which a functional circuit 51 is provided for each wiring BL functioning as a bit line, and the functional layer 50 includes a plurality of functional circuits 51 provided corresponding to n wirings BL. An example is shown below.
  • the memory cell 10 in the first row and first column is shown as a memory cell 10[1,1] and the memory cell 10 in the mth row and nth column is shown as a memory cell 10[m,n].
  • the memory cell 10 in the mth row and nth column is shown as a memory cell 10[m,n].
  • i line when indicating an arbitrary line, it may be written as i line.
  • column j when indicating an arbitrary column, it may be written as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less.
  • the memory cell 10 in the i-th row and j-th column is referred to as a memory cell 10[i,j].
  • the memory array 20 includes m wires WL extending in the row direction, m wires PL extending in the row direction, and n wires BL extending in the column direction.
  • the wiring WL provided in the first (first row) is referred to as wiring WL[1]
  • the wiring WL provided in m-th (m-th row) is referred to as wiring WL[m].
  • the first wiring PL (first row) is designated as wiring PL[1]
  • the mth wiring PL (mth row) is designated as wiring PL[m].
  • the wiring BL provided in the first (first column) is referred to as wiring BL[1]
  • the wiring BL provided in the nth (nth column) is referred to as wiring BL[n].
  • the plurality of memory cells 10 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]).
  • the plurality of memory cells 10 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).
  • DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory) can be applied to the memory array 20.
  • DOSRAM is a RAM having 1T (transistor) 1C (capacitance) type memory cells, and refers to a memory whose access transistor is an OS transistor. The current flowing between the source and drain of the OS transistor in the off state, that is, the leakage current is extremely small.
  • DOSRAM can hold charge corresponding to data held in a capacitive element (capacitor) for a long time by turning off the access transistor (making it non-conductive). Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM configured with a transistor (Si transistor) having silicon in a channel formation region. As a result, it is possible to reduce power consumption. Further, since the frequency characteristics of the OS transistor are high, reading and writing of the memory device can be performed at high speed. This makes it possible to provide a storage device with high operating speed.
  • a plurality of memory arrays 20[1] to 20[m] can be stacked and provided.
  • the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, it is possible to improve the memory density of the memory cell 10.
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling on or off (conductive state or non-conductive state) of an access transistor functioning as a switch.
  • the wiring PL has a function as a constant potential line connected to the capacitive element.
  • a wiring CL (not shown) can be separately provided as a wiring having a function of transmitting a backgate potential to the backgate of the OS transistor, which is an access transistor. Further, the wiring PL may also have a function of transmitting the back gate potential.
  • the memory cells 10 each of the memory arrays 20[1] to 20[m] have are connected to the functional circuit 51 via the wiring BL.
  • the wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided.
  • the length of the wiring between the memory array 20 and the functional circuit 51 can be reduced. It can be made shorter. Therefore, the signal propagation distance between two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, so that power consumption and signal delay can be reduced. Furthermore, it is possible to operate the memory cell 10 even if the capacitance of the capacitive element is reduced.
  • the functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 via a wiring GBL (not shown) to be described later. With this configuration, a slight potential difference in the wiring BL can be amplified when reading data.
  • the wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided. By providing the wiring BL and wiring GBL extending from the memory cells 10 of the memory arrays 20 [1] to 20 [m] in the vertical direction of the substrate surface, the wiring between the functional circuit 51 and the sense amplifier 46 can be reduced. The length can be shortened. Therefore, the signal propagation distance between the two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL can be significantly reduced, so that power consumption and signal delay can be reduced.
  • the wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a conductor provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the memory cell 10.
  • the wiring BL can be said to be a wiring for electrically connecting each of the sources and drains of the transistors included in the memory cells 10 in each layer of the memory array 20 and the functional circuit 51 in the vertical direction.
  • the memory array 20 can be provided over the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and power consumption and signal delay can be reduced. Furthermore, the storage device 300 can be made smaller.
  • the functional circuit 51 is constructed of OS transistors like the transistors included in the memory cell 10 of the DOSRAM, and can be freely mounted on a circuit using Si transistors in the same way as the memory arrays 20[1] to 20[m]. Since it can be arranged, integration can be easily performed. By configuring the functional circuit 51 to amplify the signal, it is possible to reduce the size of circuits such as the sense amplifier 46, which is a subsequent circuit, so that the storage device 300 can be made smaller.
  • the drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31.
  • the peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, each signal, and each voltage can be removed or discarded as necessary. Alternatively, other circuits or other signals may be added.
  • Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • the signal BW, the signal CE, and the signal GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signal PON1 and signal PON2 are power gating control signals. Note that the signal PON1 and the signal PON2 may be generated by the control circuit 32.
  • the control circuit 32 is a logic circuit that has a function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 300.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling input of the signal CLK to the voltage generation circuit 33. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 10. Further, the peripheral circuit 41 is a circuit that outputs various signals for controlling the functional circuit 51.
  • the peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48 ( It has an Output Cir.) and a sense amplifier 46 (Sense Amplifier).
  • the row decoder 42 and column decoder 44 have a function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying a row to be accessed
  • the column decoder 44 is a circuit for specifying a column to be accessed.
  • the row driver 43 has a function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has a function of writing data into the memory cell 10, a function of reading data from the memory cell 10, a function of holding the read data, and the like.
  • the input circuit 47 has a function of holding the signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written into the memory cell 10.
  • the data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout. Further, the output circuit 48 has a function of outputting Dout to the outside of the storage device 300.
  • the data output from the output circuit 48 is the signal RDA.
  • the PSW 22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • the PSW 23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the storage device 300 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to bring the word line to a high level, and is higher than VDD.
  • the signal PON1 controls the on/off of the PSW22
  • the signal PON2 controls the on/off of the PSW23.
  • the number of power domains to which VDD is supplied is one, but it may be plural. In this case, a power switch may be provided for each power domain.
  • the memory array 20 having the memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and the functional layer 50 can be provided by overlapping multiple layers of the memory array 20 on the drive circuit 21. By overlapping multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased.
  • the memory array 20 provided in the first layer is indicated as memory array 20[1]
  • the memory array 20 provided in the second layer is indicated as memory array 20[2]
  • the memory array 20 provided in the fifth layer is indicated as memory array 20[2].
  • the memory array 20 that has been constructed is shown as a memory array 20[5].
  • the wiring WL, the wiring PL, and the wiring CL provided extending in the X direction, and the wiring BL provided extending in the Z direction (direction perpendicular to the surface of the substrate on which the drive circuit is provided) are illustrated. There is. Note that in order to make the drawing easier to read, some of the wiring WL and wiring PL included in each of the memory arrays 20 are omitted.
  • FIG. 17B is a schematic diagram illustrating a configuration example of the functional circuit 51 connected to the wiring BL illustrated in FIG. 17A and the memory cells 10 included in the memory arrays 20[1] to 20[5] connected to the wiring BL. shows. Further, FIG. 17B illustrates a wiring GBL provided between the functional circuit 51 and the drive circuit 21. Note that a configuration in which a plurality of memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string.” Note that in the drawings, the wiring GBL may be illustrated with thick lines to improve visibility.
  • FIG. 17B illustrates an example of the circuit configuration of the memory cell 10 connected to the wiring BL.
  • the memory cell 10 includes a transistor 11 and a capacitor 12.
  • the transistor 11 the capacitive element 12, and each wiring (such as the wiring BL and the wiring WL), for example, the wiring BL[1] and the wiring WL[1] may be referred to as the wiring BL and the wiring WL.
  • transistor 11 corresponds to transistor 200 described in Embodiment 1.
  • one of the source and drain of the transistor 11 is connected to the wiring BL.
  • the other of the source and drain of the transistor 11 is connected to one electrode of the capacitive element 12.
  • the other electrode of the capacitive element 12 is connected to the wiring PL.
  • the gate of the transistor 11 is connected to the wiring WL.
  • the back gate of the transistor 11 is connected to the wiring CL.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitive element 12.
  • the wiring CL is a constant potential for controlling the threshold voltage of the transistor 11.
  • the wiring PL and the wiring CL may be at the same potential. In this case, by connecting two wires, the number of wires connected to the memory cell 10 can be reduced.
  • FIG. 18A shows a schematic diagram of a storage device 300 in which a repeating unit 70 is a functional circuit 51 and memory arrays 20[1] to 20[m]. Although one wiring GBL is shown in FIG. 18A, the wiring GBL may be provided as appropriate depending on the number of functional circuits 51 provided in the functional layer 50.
  • the wiring GBL is provided in contact with the semiconductor layer of the transistor included in the functional circuit 51.
  • the wiring GBL is provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the functional circuit 51.
  • the wiring GBL is provided in contact with a conductor provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the functional circuit 51.
  • the wiring GBL can be said to be a wiring for electrically connecting one of the source or drain of the transistor included in the functional circuit 51 in the functional layer 50 and the drive circuit 21 in the vertical direction.
  • the repeating unit 70 having the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked.
  • the storage device 300A according to one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as illustrated in FIG. 18B.
  • the wiring GBL is connected to the functional layer 50 that the repeating unit 70 has.
  • the wiring GBL may be provided as appropriate depending on the number of functional circuits 51.
  • OS transistors are provided in a stacked manner, and wiring functioning as a bit line is arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided.
  • the wiring extending from the memory array 20 and functioning as a bit line in a direction perpendicular to the substrate surface the length of the wiring between the memory array 20 and the drive circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be significantly reduced.
  • the layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 having a function of amplifying and outputting the data potential held in the memory cell 10.
  • the present invention is not limited to this.
  • a 3T1C type memory cell may be used in the storage device.
  • the memory cell shown in FIG. 22A includes transistors 11a, 11b, and 11c and a capacitive element 12a.
  • the transistors 11a, 11b, and 11c can have the same configuration as the transistor 11, and the capacitive element 12a can have the same configuration as the capacitive element 12.
  • a RAM having such a configuration may be called a NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).
  • one of the source or drain of the transistor 11a is electrically connected to one of the electrodes of the capacitive element 12a and the first gate of the transistor 11b. Further, one of the source and drain of the transistor 11b is electrically connected to one of the source and drain of the transistor 11c.
  • the second gate, and the other electrode of the capacitive element 12a may be provided with appropriate wiring.
  • the structure of the storage device can be modified as appropriate to match these wirings.
  • a 2T1C type memory cell may be used, which does not include the transistor 11c and has only the transistors 11a and 11b and the capacitive element 12a.
  • a configuration may be adopted in which the capacitive element 12a is not provided, as shown in FIG. 22C.
  • a memory cell is constituted by only the transistor 11a and the transistor 11b.
  • FIG. 19 A configuration example of the functional circuit 51 described in FIGS. 16 to 18 and a configuration example of the sense amplifier 46 included in the memory array 20 and the drive circuit 21 will be described using FIG. 19.
  • the memory cells 10 memory cell 10_A, memory cell 10_B
  • the memory cells 10 memory cell 10_A, memory cell 10_B
  • functional circuits 51 functional circuit 51_A, functional circuit 51_B
  • a drive circuit 21 connected to wiring GBL wiring GBL_A, wiring GBL_B
  • a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write/read circuit 73 are illustrated.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are illustrated as the functional circuits 51_A and 51_B.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b illustrated in FIG. 19 are OS transistors like the transistor 11 included in the memory cell 10.
  • the functional layer 50 having the functional circuit 51 can be provided in a stacked manner similar to the memory arrays 20[1] to 20[m].
  • the wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b.
  • the wiring GBL_A is connected to one of the sources and drains of the transistors 53_a and 54_a.
  • the wiring GBL_B is connected to one of the sources and drains of the transistors 53_b and 54_b.
  • Wirings GBL_A and GBL_B are provided in the vertical direction similarly to wirings BL_A and BL_B, and are connected to transistors included in the drive circuit 21. As shown in FIG. 19, the selection signal MUX, the control signal WE, or the control signal RE is applied to the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b, respectively.
  • Transistors 81_1 to 81_6 and 82_1 to 82_4 that constitute the sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B shown in FIG. 19 are composed of Si transistors.
  • the switches 83_A to 83_D making up the switch circuit 72_A and the switch circuit 72_B can also be made of Si transistors.
  • One of the sources or drains of the transistors 53_a, 53_b, 54_a, and 54_b is connected to a transistor or a switch forming the precharge circuit 71_A, the precharge circuit 71_B, the sense amplifier 46, and the switch circuit 72_A.
  • the precharge circuit 71_A includes n-channel transistors 81_1 to 81_3.
  • the precharge circuit 71_A sets the wiring BL_A and the wiring BL_B to an intermediate potential between a high power supply potential (VDD) and a low power supply potential (VSS) corresponding to a potential VDD/2 according to a precharge signal applied to a precharge line PCL1. This is a circuit for precharging to potential VPC.
  • the precharge circuit 71_B has n-channel transistors 81_4 to 81_6.
  • the precharge circuit 71_B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to an intermediate potential VPC corresponding to the potential VDD/2 between VDD and VSS in accordance with a precharge signal applied to the precharge line PCL2. be.
  • the sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4, which are connected to the wiring VHH or the wiring VLL.
  • the wiring VHH or the wiring VLL is a wiring that has a function of providing VDD or VSS.
  • the transistors 82_1 to 82_4 are transistors forming an inverter loop.
  • the potentials of the wiring GBL_A and the wiring GBL_B can be output to the outside via the switch 83_C, the switch 83_D, and the write/read circuit 73.
  • the wiring BL_A and the wiring BL_B, and the wiring GBL_A and the wiring GBL_B correspond to a bit line pair.
  • writing of a data signal is controlled according to the signal EN_data.
  • the switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and the wiring GBL_B.
  • the switch circuit 72_A is turned on or off under the control of the switching signal CSEL1.
  • the switches 83_A and 83_B are n-channel transistors, they are turned on when the switching signal CSEL1 is at a high level, and turned off when the switching signal CSEL1 is at a low level.
  • the switch circuit 72_B is a circuit for controlling the conduction state between the write/read circuit 73 and the bit line pair connected to the sense amplifier 46.
  • the switch circuit 72_B is turned on or off under the control of the switching signal CSEL2.
  • the switches 83_C and 83_D may be configured in the same manner as the switches 83_A and 83_B.
  • the memory device 300 has a configuration in which the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected via a wiring BL and a wiring GBL provided in the vertical direction, which are the shortest distances. I can do it.
  • the number of functional layers 50 having transistors forming the functional circuit 51 increases, the load on the wiring BL is reduced, so that writing time can be shortened and data can be read easily.
  • each transistor included in the functional circuits 51_A and 51_B is controlled according to control signals WE, RE, and selection signal MUX.
  • Each transistor can output the potential of the wiring BL to the drive circuit 21 via the wiring GBL in accordance with the control signal and the selection signal.
  • the functional circuits 51_A and 51_B can function as sense amplifiers made up of OS transistors. With this configuration, it is possible to amplify a slight potential difference in the wiring BL during reading and drive the sense amplifier 46 using a Si transistor.
  • the X direction is parallel to the channel width direction of the illustrated transistor
  • the Y direction is perpendicular to the X direction
  • the Z direction is perpendicular to the X and Y directions.
  • the memory cell 10 includes a transistor 11 and a capacitor 12.
  • An insulator 285 is provided on the transistor 11, and an insulator 284 is provided on the insulator 285.
  • an insulator that can be used for the insulator 216 may be used.
  • the transistor 11 has the same configuration as the transistor 200 shown in the previous embodiment, and the same components are denoted by the same symbols. For details of the transistor 200, the previous embodiments can be referred to.
  • a conductor 240 is provided in contact with one of the source and drain (conductor 242a) of the transistor 11.
  • the conductor 240 is provided extending in the Z direction, and functions as the wiring BL.
  • the capacitive element 12 includes a conductor 153 on a conductor 242b, an insulator 154 on the conductor 153, and a conductor 160 (a conductor 160a and a conductor 160b) on the insulator 154.
  • the conductor 153, the insulator 154, and the conductor 160 each have at least a portion formed in an opening provided in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285. is located inside.
  • the ends of each of the conductor 153, the insulator 154, and the conductor 160 are located at least on the insulator 282, and preferably on the insulator 285.
  • the insulator 154 is provided to cover the end of the conductor 153. Thereby, the conductor 153 and the conductor 160 can be electrically insulated.
  • the capacitance of the capacitive element 12 can be increased.
  • the semiconductor device can be miniaturized or highly integrated.
  • the conductor 153 has a region that functions as one electrode (lower electrode) of the capacitive element 12.
  • the insulator 154 has a region that functions as a dielectric of the capacitive element 12.
  • the conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitive element 12.
  • the capacitive element 12 constitutes an MIM (Metal-Insulator-Metal) capacitor.
  • the conductor 242b provided in an overlapping manner on the oxide 230 functions as a wiring electrically connected to the conductor 153 of the capacitive element 12.
  • the conductor 153 and the conductor 160 of the capacitive element 12 can be formed using various conductors that can be used for the conductor 205 or the conductor 260, respectively. It is preferable that the conductor 153 and the conductor 160 are each formed using a film formation method with good coverage, such as an ALD method or a CVD method. For example, titanium nitride or tantalum nitride formed using an ALD method or a CVD method can be used as the conductor 153.
  • the lower surface of the conductor 153 is in contact with the upper surface of the conductor 242b2.
  • the contact resistance between the conductor 153 and the conductor 242b can be reduced.
  • titanium nitride formed using an ALD method or CVD method can be used as the conductor 160a
  • tungsten formed using a CVD method can be used as the conductor 160b. Note that if the adhesion of tungsten to the insulator 154 is sufficiently high, a single layer structure of tungsten formed using a CVD method may be used as the conductor 160.
  • a high dielectric constant (high-k) material (a material with a high relative dielectric constant) for the insulator 154 included in the capacitive element 12.
  • the insulator 154 is preferably formed using a film forming method with good coverage, such as an ALD method or a CVD method.
  • Examples of insulators made of high dielectric constant (high-k) materials include oxides, oxynitrides, nitride oxides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Things can be mentioned. Further, the oxide, oxynitride, nitride oxide, or nitride may contain silicon. Furthermore, insulators made of the above-mentioned materials can be stacked and used.
  • insulators of high dielectric constant (high-k) materials e.g. aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, etc. Oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium.
  • the insulator 154 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 12 can be sufficiently secured.
  • insulators made of the above-mentioned materials in a laminated manner, and a laminated structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high dielectric constant (high-k) material is used.
  • high-k high dielectric constant
  • high-k high dielectric constant
  • the insulator 154 an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
  • an insulator in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulator having a relatively high dielectric strength, such as aluminum oxide the dielectric strength can be improved and electrostatic breakdown of the capacitive element 12 can be suppressed.
  • the capacitance of the capacitive element 12 can be increased.
  • the insulator 271b, the insulator 275, the insulator 282, and the insulator 283 function as barrier insulators, it is preferable to set the film thickness according to the barrier properties required of the semiconductor device.
  • the thickness of the conductor 260 that functions as a gate electrode is determined according to the thickness of the insulator 280, the thickness of the insulator 280 is adjusted to the thickness of the conductor 260 required for the semiconductor device. It is preferable to set the
  • the thickness of the insulator 285 may be set in a range from 50 nm to 250 nm, and the depth of the opening may be set to about 150 nm to 350 nm.
  • the capacitive element 12 can have sufficient capacitance, and in a semiconductor device in which multiple layers of memory cells are stacked, the height of one layer is not excessively high. You can keep it from getting too expensive.
  • a structure may be adopted in which the capacitances of the capacitive elements provided in each memory cell are made different in each of the layers of the plurality of memory cells. In the case of this configuration, for example, the thickness of the insulator 285 provided in each memory cell layer may be made different.
  • the side wall of the opening may be approximately perpendicular to the upper surface of the insulator 222, and may have a tapered shape. Good too. By tapering the sidewall, the coverage of the conductor 153 and the like provided in the opening of the insulator 285 and the like can be improved, and defects such as cavities can be reduced.
  • the conductor 242a provided overlappingly on the oxide 230 functions as a wiring electrically connected to the conductor 240.
  • the upper surface and side end portions of a conductor 242a are electrically connected to a conductor 240 extending in the Z direction.
  • the upper surface and side end of the conductor 242a2 and the side end of the conductor 242a1 are in contact with the conductor 240.
  • the conductor 240 be in contact with a part of the upper surface and the side end portion of the conductor 242a. Contact resistance between the conductor 240 and the conductor 242a can be reduced by the conductor 240 being in contact with multiple surfaces of the conductor 242a. In particular, as shown in FIG. 20, the contact resistance between the conductor 240 and the conductor 242a is further reduced by the conductor 240 contacting a part of the upper surface and the side edge of the highly conductive conductor 242a2. be able to.
  • the conductor 240 is provided in openings formed in the insulator 216, insulator 222, insulator 275, insulator 280, insulator 282, insulator 283, insulator 285, and insulator 284.
  • the conductor 240 preferably has a laminated structure of a conductor 240a and a conductor 240b.
  • the conductor 240 can have a structure in which a conductor 240a is provided in contact with the inner wall of the opening, and a conductor 240b is further provided inside.
  • the conductor 240a is closer to the insulators 216, 222, 275, 280, 282, 283, 285, and 284 than the conductor 240b. Placed.
  • the conductor 240a is in contact with the upper surface and side end portions of the conductor 242a.
  • the conductor 240a it is preferable to use a conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen.
  • the conductor 240a can have a single layer structure or a multilayer structure using one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide, for example. This can prevent impurities such as water and hydrogen from entering the oxide 230 through the conductor 240.
  • the conductor 240 also functions as wiring, it is preferable to use a conductor with high conductivity.
  • a conductor with high conductivity For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used for the conductor 240b.
  • the conductor 240a is a conductor containing titanium and nitrogen
  • the conductor 240b is a conductor containing tungsten.
  • the conductor 240 may have a single layer structure or a laminated structure of three or more layers.
  • an insulator 241 be provided in contact with the side surface of the conductor 240.
  • the insulator 241 is provided in contact with the inner wall of the opening of the insulator 216, insulator 222, insulator 275, insulator 280, insulator 282, insulator 283, insulator 285, and insulator 284.
  • an insulator 241 is also formed on the side surfaces of the insulator 224, oxide 230, and conductor 242a that are formed to protrude into the opening.
  • at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. That is, the conductor 240 is provided so as to fill the inside of the opening with the insulator 241 interposed therebetween.
  • the top of the insulator 241 formed below the conductor 242a is preferably located below the upper surface of the conductor 242a.
  • the conductor 240 can be in contact with at least a portion of the side end portion of the conductor 242a.
  • the insulator 241 formed below the conductor 242a preferably has a region in contact with the side surface of the oxide 230. With this configuration, impurities such as water and hydrogen contained in the insulator 280 and the like can be suppressed from entering the oxide 230 through the conductor 240.
  • the insulator 241 a barrier insulating film that can be used for the insulator 275 or the like may be used.
  • the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, silicon nitride oxide, or the like.
  • impurities such as water and hydrogen contained in the insulator 280 and the like can be suppressed from entering the oxide 230 through the conductor 240.
  • silicon nitride is suitable because it has a high blocking property against hydrogen. Furthermore, absorption of oxygen contained in the insulator 280 into the conductor 240 can be suppressed.
  • FIG. 20 shows a configuration in which the insulator 241 is a single layer, the present invention is not limited to this.
  • the insulator 241 may have a laminated structure of two or more layers.
  • a barrier insulating film against oxygen is used for the first layer in contact with the inner wall of the opening of the insulator 280, etc.
  • a barrier insulating film against hydrogen is used for the second layer inside the first layer.
  • aluminum oxide formed by ALD may be used as the first layer
  • silicon nitride formed by PEALD may be used as the second layer.
  • the side wall of the opening may be approximately perpendicular to the upper surface of the insulator 222 or may have a tapered shape. By tapering the side wall, coverage of the insulator 241 and the like provided in the opening is improved.
  • the storage device 300 includes a drive circuit 21, which is a layer including a transistor 310, a functional layer 50, which is a layer including transistors 52, 53, 54, 55, etc., on the drive circuit 21, and a functional layer 50, which is a layer including transistors 52, 53, 54, 55, etc. It has memory arrays 20[1] to 20[m]. In FIG. 21, only memory arrays 20[1] and 20[2] are illustrated. Note that the transistor 52 corresponds to the transistors 52_a and 52_b, the transistor 53 corresponds to the transistors 53_a and 53_b, the transistor 54 corresponds to the transistors 54_a and 54_b, and the transistor 55 corresponds to the transistors 55_a and 55_b. corresponds to
  • FIG. 21 illustrates a transistor 310 included in the drive circuit 21.
  • the transistor 310 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes a part of the substrate 311, and a low voltage layer that functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b.
  • the transistor 310 may be either a p-channel transistor or an n-channel transistor.
  • the substrate 311 for example, a single crystal silicon substrate can be used.
  • a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween.
  • the conductor 316 may be made of a material that adjusts the work function.
  • Such a transistor 310 is also called a FIN type transistor because it utilizes a convex portion of a semiconductor substrate.
  • an insulator may be provided in contact with the upper portion of the convex portion to function as a mask for forming the convex portion.
  • a semiconductor film having a convex shape may be formed by processing an SOI (Silicon on Insulator) substrate.
  • transistor 310 shown in FIG. 21 is an example, and the structure is not limited, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. Further, a plurality of wiring layers can be provided depending on the design. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided as interlayer films. Further, a conductor 328 and the like are embedded in the insulator 320 and the insulator 322. Furthermore, a conductor 330 and the like are embedded in the insulator 324 and the insulator 326. Note that the conductor 328 and the conductor 330 function as a contact plug or a wiring.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape underneath.
  • the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like in order to improve flatness.
  • CMP chemical mechanical polishing
  • transistors 52, 53, and 55 included in the functional layer 50 are illustrated.
  • the transistors 52, 53, and 55 have the same configuration as the transistor 11 included in the memory cell 10.
  • the sources and drains of the transistors 52, 53, and 55 are connected in series.
  • An insulator 208 is provided over the transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Further, an insulator 210 is provided on the insulator 208, and a conductor 209 is provided in the opening formed in the insulator 210. Further, an insulator 212 is provided on the insulator 210, and an insulator 214 is provided on the insulator 212. A portion of the conductor 240 provided in the memory array 20[1] is embedded in the openings formed in the insulator 212 and the insulator 214.
  • an insulator that can be used for the insulator 216 can be used.
  • an insulator that can be used for the insulator 283 can be used.
  • an insulator that can be used for the insulator 282 can be used.
  • the lower surface of the conductor 207 is provided in contact with the upper surface of the conductor 260 of the transistor 52. Further, the upper surface of the conductor 207 is provided in contact with the lower surface of the conductor 209. Further, the upper surface of the conductor 209 is provided in contact with the lower surface of the conductor 240 provided in the memory array 20[1]. With such a configuration, the conductor 240 corresponding to the wiring BL and the gate of the transistor 52 can be electrically connected.
  • Each of the memory arrays 20[1] to 20[m] includes a plurality of memory cells 10.
  • the conductor 240 of each memory cell 10 is electrically connected to the conductor 240 in the upper layer and the conductor 240 in the lower layer.
  • adjacent memory cells 10 share a conductor 240. Further, in the adjacent memory cells 10, the configuration on the right side and the configuration on the left side are arranged symmetrically with the conductor 240 as a boundary.
  • a conductor 261 functioning as a second gate electrode can be formed in the same layer.
  • the conductor 160 of the capacitive element 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer can be formed to be embedded in an opening formed in the same insulator 216.
  • the above structure is obtained by forming the conductor 160 of the capacitive element 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer by processing one conductive film. At this time, the conductor 160 of the capacitive element 12 in the lower layer has the same material as the conductor 261 of the transistor 11 in the upper layer.
  • the manufacturing process of the memory device according to this embodiment can be reduced.
  • the productivity of the storage device can be improved.
  • a plurality of memory arrays 20[1] to 20[m] can be stacked and provided.
  • the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, it is possible to improve the memory density of the memory cell 10.
  • the memory array 20 can be fabricated using the same manufacturing process repeatedly in the vertical direction.
  • the storage device 300 can reduce the manufacturing cost of the memory array 20.
  • a plurality of circuits (systems) are mounted on the chip 1200 shown in FIGS. 23A and 23B.
  • the technology of integrating a plurality of circuits (systems) onto one chip in this way is sometimes called system on chip (SoC).
  • SoC system on chip
  • the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • the chip 1200 is provided with bumps (not shown) and is connected to the first surface of the package substrate 1201, as shown in FIG. 23B. Furthermore, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 and are connected to a motherboard 1203.
  • the motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222.
  • storage devices such as a DRAM 1221 and a flash memory 1222.
  • the DOSRAM described in the previous embodiment can be used as the DRAM 1221. This allows the DRAM 1221 to have lower power consumption, higher speed, and larger capacity.
  • the CPU 1211 has multiple CPU cores. Further, it is preferable that the GPU 1212 has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory that temporarily stores data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The above-mentioned DOSRAM can be used as the memory. Further, the GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing or product-sum calculation. By providing the image processing circuit using the OS transistor described in the previous embodiment or the product-sum operation circuit in the GPU 1212, it becomes possible to perform image processing or product-sum operation with low power consumption. .
  • the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212 and between the memory of the CPU 1211 and the GPU 1212 is possible. , and after the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation section 1213 may be provided with the above product-sum calculation circuit.
  • the memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. Controllers include mice, keyboards, game controllers, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • HDMI High-Definition Multimedia Interface
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.
  • LAN Local Area Network
  • the above circuit (system) can be formed on the chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • a package substrate 1201 provided with a chip 1200 having a GPU 1212, a motherboard 1203 provided with a DRAM 1221, and a flash memory 1222 can be called a GPU module 1204.
  • the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Furthermore, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
  • a product-sum calculation circuit using the GPU 1212 can be used to create deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks ( DBN), the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • DNNs deep neural networks
  • CNNs convolutional neural networks
  • RNNs recurrent neural networks
  • DBMs deep Boltzmann machines
  • DBN deep belief networks
  • FIG. 24A A perspective view of a board (mounted board 704) on which electronic component 700 is mounted is shown in FIG. 24A.
  • An electronic component 700 shown in FIG. 24A includes a semiconductor device 710 within a mold 711. In FIG. 24A, some descriptions are omitted to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711. Land 712 is electrically connected to electrode pad 713, and electrode pad 713 is electrically connected to semiconductor device 710 via wire 714.
  • the electronic component 700 is mounted on a printed circuit board 702, for example.
  • a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702.
  • the semiconductor device 710 includes a drive circuit layer 715 and a memory layer 716.
  • the storage layer 716 has a structure in which a plurality of memory cell arrays are stacked.
  • the structure in which the drive circuit layer 715 and the memory layer 716 are stacked can be a monolithic stacked structure.
  • each layer can be connected without using a through electrode technology such as TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding.
  • connection wiring etc.
  • connection wiring etc.
  • TSV through silicon vias
  • connection pins By increasing the number of connection pins, parallel operation becomes possible, thereby making it possible to improve the memory bandwidth (also referred to as memory bandwidth).
  • the plurality of memory cell arrays included in the storage layer 716 be formed using OS transistors, and the plurality of memory cell arrays be monolithically stacked.
  • OS transistors the plurality of memory cell arrays be monolithically stacked.
  • bandwidth is the amount of data transferred per unit time
  • access latency is the time from access to the start of data exchange.
  • the semiconductor device 710 may be referred to as a die.
  • a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also referred to as a wafer) and cutting it into dice in the semiconductor chip manufacturing process.
  • semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also referred to as a silicon wafer
  • a silicon die is sometimes referred to as a silicon die.
  • the electronic component 730 is an example of SiP (System in Package) or MCM (Multi Chip Module).
  • an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.
  • the semiconductor device 710 is used as a high bandwidth memory (HBM).
  • the semiconductor device 735 is an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array). Can be used in circuits.
  • a CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • FPGA Field Programmable Gate Array
  • a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732.
  • the interposer 731 for example, a silicon interposer or a resin interposer can be used.
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches.
  • the plurality of wirings are provided in a single layer or in multiple layers.
  • the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732.
  • the interposer is sometimes called a "rewiring board” or an "intermediate board.”
  • a through electrode is provided in the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode.
  • TSV can also be used as the through electrode.
  • HBM In HBM, it is necessary to connect many wires to achieve a wide memory bandwidth. For this reason, an interposer mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer for mounting the HBM.
  • a silicon interposer in SiP, MCM, etc. using a silicon interposer, reliability is less likely to deteriorate due to the difference in expansion coefficient between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional packaging) in which a plurality of integrated circuits are arranged side by side on an interposer.
  • 2.5D package 2.5-dimensional packaging
  • a monolithic stacked structure using OS transistors is suitable. It may also be a composite structure in which a memory cell array stacked using TSVs and a memory cell array stacked monolithically are combined.
  • a heat sink may be provided overlapping the electronic component 730.
  • a heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
  • the heights of the semiconductor device 710 and the semiconductor device 735 are the same.
  • an electrode 733 may be provided on the bottom of the package board 732.
  • FIG. 24B shows an example in which the electrode 733 is formed with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized.
  • the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of implementation methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), and QFJ (Quad Flat J-lead). d package) and QFN (Quad Flat Non-leaded package) can be mentioned.
  • FIG. 25A a perspective view of electronic device 6500 is shown in FIG. 25A.
  • Electronic device 6500 shown in FIG. 25A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • An electronic device 6600 shown in FIG. 25B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like.
  • the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that it is preferable to use the semiconductor device of one embodiment of the present invention for the above-described control device 6509 and control device 6616 because power consumption can be reduced.
  • FIG. 25C a perspective view of large computer 5600 is shown in FIG. 25C.
  • a plurality of rack-mount computers 5620 are stored in a rack 5610.
  • the large computer 5600 may be called a supercomputer.
  • the computer 5620 can have the configuration shown in the perspective view shown in FIG. 25D.
  • a computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.
  • a PC card 5621 shown in FIG. 25E is an example of a processing board that includes a CPU, GPU, storage device, and the like.
  • PC card 5621 has a board 5622.
  • the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 25E illustrates semiconductor devices other than the semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, these semiconductor devices are described below. The description of semiconductor device 5628 can be referred to.
  • connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • Examples of the standard of the connection terminal 5629 include PCIe.
  • connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used as an interface for supplying power, inputting signals, etc. to the PC card 5621, for example. Further, for example, it can be used as an interface for outputting a signal calculated by the PC card 5621.
  • the respective standards of the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples include.
  • USB Universal Serial Bus
  • SATA Serial ATA
  • SCSI Serial Computer System Interface
  • Examples include.
  • HDMI registered trademark
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and by inserting the terminal into a socket (not shown) provided on the board 5622, the semiconductor device 5626 and the board 5622 can be connected. Can be electrically connected.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • an electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5628 include a storage device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • the large computer 5600 can also function as a parallel computer. By using the large-scale computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence learning and inference.
  • a semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as equipment that processes and stores information.
  • a semiconductor device of one embodiment of the present invention can include an OS transistor.
  • the OS transistor has small variations in electrical characteristics due to radiation irradiation. In other words, since it has high resistance to radiation, it can be suitably used in environments where radiation may be incident. For example, OS transistors can be suitably used when used in outer space.
  • FIG. 26 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is illustrated in outer space.
  • outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include the thermosphere, mesosphere, and stratosphere.
  • the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit. It is preferable to use an OS transistor in the battery management system or battery control circuit described above because it has low power consumption and high reliability even in outer space.
  • BMS battery management system
  • OS transistor it is preferable to use an OS transistor in the battery management system or battery control circuit described above because it has low power consumption and high reliability even in outer space.
  • outer space is an environment with more than 100 times higher radiation levels than on the ground.
  • radiation include electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays, and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. It will be done.
  • the electric power necessary for the operation of the artificial satellite 6800 is generated.
  • the power necessary for satellite 6800 to operate may not be generated.
  • the solar panel is sometimes called a solar cell module.
  • the satellite 6800 can generate signals.
  • the signal is transmitted via antenna 6803 and can be received by, for example, a ground-based receiver or other satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a storage device.
  • a semiconductor device which is one embodiment of the present invention, is preferably used for the control device 6807.
  • OS transistors Compared to Si transistors, OS transistors have smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, it is highly reliable and can be suitably used even in environments where radiation may be incident.
  • the artificial satellite 6800 can be configured to include a sensor.
  • the artificial satellite 6800 can have a function of detecting sunlight reflected by hitting an object provided on the ground.
  • the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface.
  • the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.
  • OS transistors have superior effects compared to Si transistors, such as being able to realize a wide memory bandwidth and having high radiation resistance.
  • a semiconductor device can be suitably used in, for example, a storage system applied to a data center or the like.
  • Data centers are required to perform long-term data management, including ensuring data immutability.
  • it is necessary to install storage and servers to store huge amounts of data, secure a stable power supply to retain data, or secure cooling equipment required to retain data, etc. due to large buildings. ization is required.
  • the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, the power required to hold data can be reduced and the semiconductor device that holds data can be made smaller. Therefore, it is possible to downsize the storage system, downsize the power supply for holding data, and downsize the cooling equipment. Therefore, it is possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, heat generation from the circuit can be reduced. Therefore, the adverse effect of the heat generation on the circuit itself, peripheral circuits, and module can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
  • FIG. 27 shows a storage system applicable to data centers.
  • the storage system 7000 shown in FIG. 27 includes a plurality of servers 7001sb as hosts 7001 (shown as Host Computer). It also includes a plurality of storage devices 7003md as storage 7003 (shown as Storage).
  • a host 7001 and a storage 7003 are shown connected via a storage area network 7004 (SAN: Storage Area Network) and a storage control circuit 7002 (Storage Controller).
  • SAN Storage Area Network
  • Storage Controller Storage Controller
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • the storage 7003 uses flash memory to shorten the data access speed, that is, the time required to store and output data, this time is the same as the time required by DRAM, which can be used as a cache memory in the storage. It is much longer than .
  • a cache memory is usually provided in the storage to shorten data storage and output.
  • the cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the storage control circuit 7002 and the cache memory in the storage 7003, and then output to the host 7001 or the storage 7003.
  • an OS transistor as a transistor for storing data in the cache memory described above and maintaining a potential according to the data, the frequency of refreshing can be reduced and power consumption can be reduced. Further, size reduction is possible by using a structure in which memory cell arrays are stacked.
  • the semiconductor device of one embodiment of the present invention by applying the semiconductor device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, power consumption can be reduced. There is expected. Therefore, as energy demand is expected to increase due to higher performance or higher integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention will reduce the greenhouse effect typified by carbon dioxide (CO 2 ). It also becomes possible to reduce the amount of gas discharged. Further, since the semiconductor device of one embodiment of the present invention has low power consumption, it is effective as a countermeasure against global warming.
  • CO 2 carbon dioxide
  • FIGS. 8A to 12D the processing shown in FIGS. 8A to 12D was performed to produce a structure including the oxide 230, and the results of cross-sectional STEM observation will be described.
  • an island-shaped stacked body is provided on a hafnium oxide film (hereinafter referred to as an HfOx film) on a silicon substrate, and the island-shaped stacked body is covered.
  • a sample was prepared in which a silicon nitride film (hereinafter referred to as SiNx_1 film) and a silicon oxide film (hereinafter referred to as SiOx_2 film) were laminated in this order, and the processing shown in FIGS. 8A to 12D was performed on the sample.
  • the island-shaped stacked body includes a silicon oxide film (hereinafter referred to as SiOx_1 film), an In-Ga-Zn oxide film (hereinafter referred to as IGZO film), and a tantalum nitride film (hereinafter referred to as TaNx film). ), a tungsten film (hereinafter referred to as W film), and a laminated film of silicon nitride and silicon oxide (hereinafter referred to as SiNx ⁇ SiOx film).
  • SiOx_1 film silicon oxide film
  • IGZO film In-Ga-Zn oxide film
  • TaNx film tantalum nitride film
  • W film tungsten film
  • SiNx ⁇ SiOx film a laminated film of silicon nitride and silicon oxide
  • the HfOx film corresponds to the insulator 222.
  • the SiOx_1 film corresponds to the insulator 224.
  • the IGZO film corresponds to a laminated film of an oxide 230a and an oxide 230b.
  • the TaNx film corresponds to the conductor 242_1.
  • the W film corresponds to the conductor 242_2.
  • the SiNx ⁇ SiOx film corresponds to the insulator 271.
  • the SiNx_1 film corresponds to the insulator 275.
  • the SiOx_2 film corresponds to the insulator 280.
  • the etching conditions required in the step shown in FIG. 9D were selected. Similarly to FIG. 9D, when etching the W film, it is necessary to have a sufficient selectivity with respect to the TaNx film so that the etch can be stopped on the TaNx film. Specifically, conditions for bias power and oxygen gas flow rate ratio were selected so that a sufficient selectivity with respect to the TaNx film could be obtained.
  • etching selectivity ratio of the W film to the TaNx film (hereinafter referred to as W/TaNx selectivity) was calculated.
  • bias power conditions were selected. In selecting bias power conditions, 55 sccm of CF 4 gas, 45 sccm of Cl 2 gas, and 55 sccm of O 2 gas were used, the pressure was 0.67 Pa, the ICP power was 1000 W, and the substrate temperature was -10°C. The etching rate was measured under each condition with bias power of 25 W, 50 W, and 100 W.
  • FIG. 28A shows the measurement results of the etching rate and etching selectivity when selecting bias power conditions.
  • the horizontal axis represents bias power (Bias [W])
  • the left vertical axis represents etching rate [nm/min]
  • the right vertical axis represents etching selectivity.
  • black circles indicate the etching rate of the W film
  • black diamonds indicate the etching rate of the TaNx film
  • white circles indicate the W/TaNx selectivity ratio.
  • the etching rates of the TaNx film and the W film increased, and in particular, the etching rate of the W film increased significantly. Therefore, as the bias power is decreased, the W/TaNx selection ratio becomes relatively larger, and at a bias power of 25 W, the W/TaNx selection ratio becomes maximum. Therefore, it was decided to adopt a bias power condition of 25 W in the etching process of the W film.
  • oxygen gas flow rate ratio is the ratio of the oxygen gas flow rate to the total etching gas flow rate, and is defined as O 2 /(CF 4 +Cl 2 +O 2 ).
  • FIG. 28B shows the measurement results of the etching rate and etching selectivity when selecting the conditions of the oxygen gas flow rate ratio.
  • the horizontal axis represents the oxygen gas flow rate ratio (O 2 Ratio)
  • the left vertical axis represents the etching rate [nm/min]
  • the right vertical axis represents the etching selectivity.
  • black circles indicate the etching rate of the W film
  • black diamonds indicate the etching rate of the TaNx film
  • white circles indicate the W/TaNx selectivity ratio.
  • the HfOx film is formed by an ALD method and has a thickness of 20 nm.
  • the SiOx_1 film is formed by a sputtering method and has a thickness of 20 nm.
  • the IGZO film is formed by a sputtering method and is a laminated film of a 10 nm thick IGZO (132) film and a 15 nm thick IGZO (111) film thereon.
  • the film was formed using a target with an atomic ratio of .2.
  • the TaNx film is formed by sputtering and has a thickness of 5 nm.
  • the W film is formed by sputtering and has a thickness of 15 nm.
  • the SiNx ⁇ SiOx film is continuously formed by sputtering, and the thickness of the SiNx film is 5 nm, and the thickness of the SiOx film is 10 nm.
  • the SiNx_1 film is formed by the PEALD method and has a thickness of 5 nm.
  • the SiOx_2 film is a film formed by a sputtering method.
  • an SOC film (corresponding to the coating film 277f) is formed on the SiOx_2 film using a spin coating method, and then an SOG film (corresponding to the coating film 278f) is formed using a spin coating method on top of the SOC film (corresponding to the coating film 278f). ) was deposited.
  • a positive resist film was formed, and the resist film was irradiated with an electron beam to form a resist mask (corresponding to the resist mask 279) in which an opening was formed.
  • a dry etching process corresponding to FIG. 9C was performed using an ICP etching apparatus.
  • the etching conditions were as follows: CHF 3 gas 67 sccm and O 2 gas 13 sccm were used as etching gases, the pressure was 0.67 Pa, the ICP power was 3000 W, the bias power was 25 W, and the substrate temperature was -10°C.
  • a dry etching process corresponding to FIG. 9D was performed continuously without exposure to the atmosphere. As a result, openings were formed in the W film and the W film was divided.
  • the dry etching process was performed using an ICP etching apparatus.
  • the etching conditions were such that a sufficient selectivity with respect to the TaNx film could be achieved. That is, the conditions were such that the bias power was 25 W and the oxygen gas flow rate ratio was 0.484 (CF 4 gas 44 sccm, Cl 2 gas 36 sccm, O 2 gas 75 sccm). Other conditions were a pressure of 0.67 Pa, an ICP power of 1000 W, and a substrate temperature of -10°C.
  • the SOC film was removed by continuously performing plasma ashing using oxygen gas without exposing it to the atmosphere. As a result, a structure having an opening having a width L1 corresponding to FIGS. 8A to 8D was formed.
  • a SiNx_2 film (corresponding to the insulating film 255A) was formed to cover the above structure.
  • the SiNx_2 film is formed by the PEALD method and has a thickness of 5 nm.
  • an SOC film (corresponding to the coating film 287f) is formed on the SiNx_2 film using a spin coating method, and an SOG film (corresponding to the coating film 288f) is further formed using a spin coating method on top of the SOC film (corresponding to the coating film 287f). corresponding) was deposited.
  • a positive resist film was formed, and the resist film was irradiated with an electron beam to form a resist mask (corresponding to the resist mask 289) in which an opening was formed.
  • the width L2 of the opening formed in the resist mask in this step is smaller than the width L1 of the opening formed in the W film in the above-mentioned step.
  • the opening formed in the resist mask in this step is located inside the opening formed in the W film.
  • a dry etching process corresponding to FIG. 12C was performed using the SOC film and SOG film in which the openings were formed.
  • an opening was formed in the SiNx_2 film.
  • the SOG film disappeared during etching of the SiNx_2 film.
  • the dry etching process was performed using an ICP etching apparatus.
  • the etching conditions were as follows: CHF 3 gas 67 sccm and O 2 gas 13 sccm were used as etching gases, the pressure was 0.67 Pa, the ICP power was 3000 W, the bias power was 25 W, and the substrate temperature was -10°C.
  • a dry etching process corresponding to FIG. 12D was performed continuously without exposure to the atmosphere. As a result, openings were formed in the TaNx film and the TaNx film was divided.
  • the dry etching process was performed using an ICP etching apparatus. Etching conditions were as follows: 80 sccm of Cl 2 gas and 20 sccm of Ar gas were used as etching gases, the pressure was 0.51 Pa, the ICP power was 1000 W, and the substrate temperature was -10°C. Note that the bias power was initially set to 100 W, and was increased to 10 W from the middle.
  • the SOC film was removed by continuously performing plasma ashing using oxygen gas without exposing it to the atmosphere.
  • a structure was formed in which the distance between the separated W films was L1 and the distance between the separated TaNx films was L2, corresponding to FIGS. 11A to 11D.
  • a cross-sectional STEM image was taken of the sample prepared as described above.
  • the cross-sectional STEM images were taken using Hitachi High-Tech's "HD-2700" at an accelerating voltage of 200 kV.
  • FIG. 29 is a cross section corresponding to FIG. 11B.
  • the distance L2 between the TaNx films could be made shorter than the distance L1 between the W films.
  • the upper surface of the TaNx film was not excessively etched, and protrusions of the TaNx film were formed as designed.
  • a SiNx_2 film could be formed in contact with the inner side surface of the W film and the top surface of the TaNx film.
  • the source and drain electrodes of the OS transistor can have a stacked structure of a TaNx film with high oxidation resistance and a W film with high conductivity.
  • a TaNx film with high oxidation resistance By providing the SiNx_2 film in contact with the inside of the W film, oxidation of the W film can be prevented and the conductivity of the W film can be maintained at a high level.
  • the TaNx film to protrude from the W film the distance between the source electrode and the drain electrode can be shortened, and the frequency characteristics of the OS transistor can be improved.
  • sample 2A and sample 2B semiconductor devices having the transistor 200 shown in FIGS. 1A to 1D were manufactured, and the results of observing cross-sectional STEM images and evaluating electrical characteristics will be described. explain.
  • Sample 2A and Sample 2B were produced using the method described in FIGS. 4A to 15D.
  • the heat treatment described in the above embodiment after forming the conductor 242a1 and the conductor 242b1 was not performed.
  • the samples 2A and 2B include an insulator 215 disposed on a substrate (not shown), an insulator 216 on the insulator 215, and an insulator 216 embedded in the insulator 216.
  • the conductor 205 (conductor 205a and conductor 205b) provided as shown in FIG.
  • 230 oxide 230a and oxide 230b
  • conductor 242a conductor 242a1 and conductor 242a2
  • conductor 242b conductor 242b1 and conductor 242b2
  • an insulator 255 is provided between the conductor 242a1, the conductor 242b1, the conductor 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, and the insulator 280 and the insulator 250. Further, an insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. Insulator 255, insulator 250, and conductor 260 are embedded in openings provided in insulator 280 and insulator 275. Further, an insulator 282 is provided over the insulator 280 and the conductor 260, and an insulator 283 is provided over the insulator 282.
  • the insulator 215 is a laminated film of a 60 nm thick silicon nitride film and a 40 nm thick aluminum oxide film on the silicon nitride film.
  • the silicon nitride film and the aluminum oxide film were each formed using a sputtering method.
  • the insulator 216 is a silicon oxide film with a thickness of 200 nm formed by a sputtering method.
  • the conductor 205 is a laminated film of a conductor 205a and a conductor 205b, and is provided so as to be embedded in the opening of the insulator 216.
  • the conductor 205a is a tantalum nitride film formed by sputtering.
  • the conductor 205b is a titanium nitride film formed by a CVD method and a tungsten film on the titanium nitride film.
  • the insulator 222 is a laminated film of a 3 nm thick silicon nitride film and a 17 nm thick hafnium oxide film on the silicon nitride film.
  • the silicon nitride film was formed by the PEALD method, and the hafnium oxide film was formed by the thermal ALD method.
  • the insulator 224 is a 20 nm thick silicon oxide film formed by sputtering.
  • the conductor 242a1 and the conductor 242b1 are tantalum nitride films with a thickness of 5 nm formed by sputtering.
  • the conductor 242a2 and the conductor 242b2 are tungsten films with a thickness of 15 nm formed by sputtering.
  • the insulator 271a and the insulator 271b are laminated films of a 5 nm thick silicon nitride film and a 10 nm thick silicon oxide film on the silicon nitride film.
  • the silicon nitride film and the silicon oxide film were each formed using a sputtering method.
  • the insulator 275 is a 5 nm thick silicon nitride film formed by sputtering.
  • the insulator 280 is a silicon oxide film formed by sputtering.
  • the insulator 255, the insulator 250, and the conductor 260 are provided so as to be embedded in the openings provided in the insulator 280 and the insulator 275.
  • the insulator 255 is a 5 nm thick silicon nitride film formed by the PEALD method.
  • the insulator 250 is a laminated film of an insulator 250a, an insulator 250b, and an insulator 250c.
  • the insulator 250a is an aluminum oxide film with a thickness of 1 nm formed by a thermal ALD method.
  • the insulator 250b is a silicon oxide film with a thickness of 3 nm formed by the PEALD method.
  • the insulator 250c is a 3 nm thick silicon nitride film formed by the PEALD method.
  • the conductor 260 is a laminated film of a conductor 260a and a conductor 260b.
  • the conductor 260a is a titanium nitride film formed by a CVD method.
  • the conductor 260b is a tungsten film formed by a CVD method.
  • the insulator 282 is a 10 nm thick aluminum oxide film formed by sputtering.
  • the insulator 283 is a 20 nm thick silicon nitride film formed by sputtering.
  • the opening in the insulator 280, the opening in the insulator 275, the insulator 271a, the insulator 271b, the conductor 242a2, and the conductor 242b2 were formed using the method shown in FIGS. 9A to 9D. Since it is formed by the same method as in Example 1, the description of Example 1 can be referred to for details.
  • the insulator 255, conductor 242a1, and conductor 242b1 were formed using the method shown in FIGS. 12A to 12D. Since it is formed by the same method as in Example 1, the description of Example 1 can be referred to for details.
  • sample 2A heat treatment was performed after forming the conductor 242a1 and the conductor 242b1 shown in FIG. 12D.
  • atmospheric pressure heat treatment was performed at 350° C. for 1 hour in a mixed atmosphere with a N 2 gas flow rate of 4 slm and an O 2 gas flow rate of 1 slm. Note that sample 2B was not subjected to the heat treatment.
  • microwave treatment was performed after forming the insulating film that would become the insulator 250b.
  • 150 sccm of argon gas and 50 sccm of oxygen gas were used as processing gases, the power was 4000 W, the pressure was 400 Pa, the processing temperature was 250° C., and the processing time was 600 seconds.
  • Sample 2A and Sample 2B manufactured as described above are TEGs (Test Element Groups) having design values of a transistor with a channel length of 30 nm and a channel width of 30 nm, and a transistor with a channel length of 60 nm and a channel width of 60 nm.
  • TEGs Test Element Groups
  • nine transistors were manufactured, including a transistor with a channel length of 30 nm and a channel width of 30 nm, and a transistor with a channel length of 60 nm and a channel width of 60 nm.
  • cross-sectional STEM images were taken of transistors with a channel length of 30 nm and a channel width of 30 nm of Sample 2A and Sample 2B.
  • the cross-sectional STEM images were taken using Hitachi High-Tech's "HD-2700" at an accelerating voltage of 200 kV.
  • FIGS. 30A to 30C Cross-sectional STEM images of sample 2A are shown in FIGS. 30A to 30C, and cross-sectional STEM images of sample 2B are shown in FIGS. 31A and 31B.
  • FIGS. 30A and 31A are TE images of a cross section in the channel length direction of the transistor of each sample.
  • FIGS. 30B and 31B are ZC images in which the vicinity of the conductor 242a2 in FIG. 30A or FIG. 31A is enlarged, respectively.
  • FIG. 30C is a TE image of a cross section in the channel width direction of the transistor of sample 2A.
  • the distance between the conductor 242a1 and the conductor 242b1 could be made shorter than the distance between the conductor 242a2 and the conductor 242b2.
  • the protrusions of the conductor 242a1 and the conductor 242b1 could be formed as designed, and the protrusions and a portion of the conductor 260 could be formed overlapping each other.
  • sample 2B could also be formed with the same structure as sample 2A.
  • the boundary between the insulator 255 and the insulator 250 is difficult to see, but the part where the insulator 255 and the insulator 250 are stacked on the conductors 242a1 and 242b1 is thinner than the part where the insulator 250 is alone. It can be seen that an insulator 255 is formed because the thickness is increased. Further, in FIG. 30C, in a portion where the conductor 260 and the insulator 255 overlap, the shape of the bottom surface of the conductor 260 is deformed to reflect the shape of the insulator 255.
  • the thickness of the oxide film on the side surface of the conductor 242a2 of sample 2A was 1.5 nm. Further, as shown in FIG. 31B, the thickness of the oxide film on the side surface of the conductor 242a2 of sample 2B was 1.3 nm. In other words, the thickness of the oxide film on the side surface of the conductor 242a2 and the conductor 242b2 of the transistor hardly changed depending on whether heat treatment was performed after forming the conductor 242a1 and the conductor 242b1. This is considered to be because oxidation of the side surfaces of the conductor 242a2 and the conductor 242b2 is suppressed by providing the insulator 255 in contact with the side surfaces of the conductor 242a2 and the conductor 242b2.
  • the Id-Vg characteristics (drain current-gate voltage characteristics) of each element were measured using a semiconductor parameter analyzer manufactured by Keysight Technologies. The Id-Vg characteristics were measured by setting the drain potential Vd to 0.1V or 1.2V, the source potential Vs to 0V, the bottom gate potential Vbg to 0V, and the top gate potential Vg from -4.0V to 4.0V. It was swept in 0.1V steps.
  • FIGS. 32A to 33B The measurement results of Id-Vg characteristics are shown in FIGS. 32A to 33B.
  • 32A shows the measurement results of nine transistors of sample 2A with a channel length of 30 nm and a channel width of 30 nm
  • FIG. 32B shows the measurement results of nine transistors of sample 2B with a channel length of 30 nm and a channel width of 30 nm
  • FIG. 33B shows the measurement results of nine transistor elements of Sample 2A with a channel length of 60 nm and a channel width of 60 nm
  • FIG. 33B shows the measurement results of nine transistor elements of Sample 2B with a channel length of 60 nm and a channel width of 60 nm.
  • FIGS. 32A shows the measurement results of nine transistors of sample 2A with a channel length of 30 nm and a channel width of 30 nm
  • FIG. 33B shows the measurement results of nine transistor elements of Sample 2A with a channel length of 60 nm and a channel width of
  • the horizontal axis represents the top gate potential Vg [V]
  • the vertical axis represents the drain current Id [A].
  • the shift voltage Vsh, on-current Ion, and S value were calculated from the measurement results of the Id-Vg characteristics shown in FIGS. 32A to 33B.
  • the shift voltage Vsh takes a positive value near 0 V, and the variation in the shift voltage Vsh within the substrate surface is small. This is because in Sample 2A and Sample 2B, as described above, oxidation of the side surfaces of the conductors 242a2 and 242b2 was suppressed, so a sufficient amount of oxygen was supplied to the oxide 230, and oxygen vacancies in the oxide 230 were reduced. This is thought to be due to the
  • the transistors of Sample 2A and Sample 2B exhibit good S values.
  • the transistors with a channel length of 60 nm and the channel width of 60 nm in Samples 2A and 2B have the same or higher performance as the transistors with a channel length of 30 nm and a channel width of 30 nm in Samples 2A and 2B. Electrical properties were obtained.
  • the source and drain electrodes of the OS transistor can be formed using conductors 242a1 and 242b1 with high oxidation resistance and conductors 242a2 and 242b2 with high conductivity. It can be made into a laminated structure.
  • the insulator 255 in contact with the insides of the conductors 242a2 and 242b2, oxidation of the conductors 242a2 and 242b2 can be prevented and high conductivity can be maintained.
  • the conductors 242a1 and 242b1 to protrude from the conductors 242a2 and 242b2, the distance between the source electrode and the drain electrode can be shortened. As described above, it is possible to provide a semiconductor device including a transistor having good electrical characteristics and less variation in electrical characteristics.
  • ADDR Signal, BL[1]: Wiring, BL[j]: Wiring, BL[n]: Wiring, BL_A: Wiring, BL_B: Wiring, BL: Wiring, BW: Signal, CE: Signal, CLK: Signal, EN_data : Signal, GBL_A: Wiring, GBL_B: Wiring, GBL: Wiring, GW: Signal, MUX: Selection signal, PL[1]: Wiring, PL[i]: Wiring, PL[m]: Wiring, PL: Wiring, RDA : Signal, RE: Control signal, VHH: Wiring, VLL: Wiring, VPC: Intermediate potential, WAKE: Signal, WDA: Signal, WE: Control signal, WL[1]: Wiring, WL[i]: Wiring, WL[ m]: Wiring, WL: Wiring, 10[1,1]: Memory cell, 10[i,j]: Memory cell, 10[m,n]: Memory cell, 10_A: Memory cell

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JP2016058751A (ja) * 2012-10-17 2016-04-21 株式会社半導体エネルギー研究所 半導体装置
JP2020047357A (ja) * 2018-09-14 2020-03-26 株式会社半導体エネルギー研究所 Ｉｃカード、半導体装置、および、電子機器

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