WO2023206877A1 - 一种led外延片及其制造方法 - Google Patents

一种led外延片及其制造方法 Download PDF

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WO2023206877A1
WO2023206877A1 PCT/CN2022/114586 CN2022114586W WO2023206877A1 WO 2023206877 A1 WO2023206877 A1 WO 2023206877A1 CN 2022114586 W CN2022114586 W CN 2022114586W WO 2023206877 A1 WO2023206877 A1 WO 2023206877A1
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layer
bulk
thickness
led epitaxial
doping concentration
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PCT/CN2022/114586
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English (en)
French (fr)
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王文君
江汉
黎国昌
徐洋洋
程虎
苑树伟
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聚灿光电科技股份有限公司
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Priority to US17/927,508 priority Critical patent/US20240258463A1/en
Publication of WO2023206877A1 publication Critical patent/WO2023206877A1/zh

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    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
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    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
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    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
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    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present application relates to the field of LED technology, and in particular to an LED epitaxial wafer and a manufacturing method thereof.
  • LED Light-Emitting Diode, light-emitting diode
  • LED epitaxial wafer refers to a specific single crystal film grown on a substrate heated to an appropriate temperature.
  • an LED epitaxial wafer usually includes a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer and a P-type GaN layer arranged in sequence from bottom to top.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • the N-type GaN layer structure of LED epitaxial wafers grown by MOCVD equipment includes two types: N_Bulk structure and N_SL structure.
  • the N_Bulk structure can provide a higher electron concentration, but it has a large lattice mismatch with the lower U-shaped GaN layer and the upper quantum well light-emitting layer, affecting the crystal quality of the quantum well light-emitting layer.
  • the N_SL structure can effectively reduce the lattice mismatch between the N-type GaN layer and the underlying U-type GaN layer.
  • the N_SL structure will cause large fluctuations in the luminescence voltage due to differences in N electrode etching.
  • the SiH4 valve group of MOCVD equipment requires a higher switching frequency, which reduces the service life of the SiH4 valve group and increases production costs.
  • LEDs In addition, during the manufacturing, installation and use of LEDs, they will inevitably be affected by static electricity and generate induced charges. If the induced charges are not released in time, a higher voltage will be formed across the PN junction. Traditional LED epitaxial wafers have poor antistatic capabilities. When the voltage exceeds the maximum withstand value of the LED epitaxial wafer, the electrostatic charge will be discharged at both ends of the PN junction in a very short moment, causing the PN junction to breakdown and causing the LED to fail.
  • This application provides an LED epitaxial wafer and a manufacturing method thereof to solve the problems of traditional LED epitaxial wafers such as large lattice mismatch, high production cost, and poor antistatic ability.
  • the present application provides an LED epitaxial wafer, including a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, a P-type electron blocking layer and a P-type GaN layer that are stacked in sequence.
  • the N-type GaN layer includes: an N_SL layer and an N_Bulk layer disposed on the N_SL layer. The thickness of the N_SL layer is smaller than the thickness of the N_Bulk layer.
  • the N_SL layer includes several first N_SL layers and several second N_SL layers.
  • the N_Bulk layer includes a first N_Bulk layer and a second N_Bulk layer disposed on the first N_Bulk layer.
  • the silicon doping concentration of the first N_SL layer is smaller than the silicon doping concentration of the second N_SL layer.
  • the silicon doping concentration of the first N_Bulk layer is greater than the silicon doping concentration of the second N_Bulk layer.
  • the silicon doping concentration of the first N_SL layer is smaller than the silicon doping concentration of the second N_Bulk layer.
  • the N_SL layer and the N_Bulk layer effectively form multiple capacitor structures. Different concentrations of silicon doping enhance current diffusion and improve the antistatic ability of the LED epitaxial wafer.
  • the structural settings of the N_SL layer and N_Bulk layer reduce the dislocation density of the growing quantum well light-emitting layer and improve the lattice quality of the quantum well light-emitting layer.
  • the first N_SL layer and the second N_SL layer are set cyclically from bottom to top, and the number of cycles is between 10 and 20.
  • the silicon doping concentration of the first N_SL layer is between 1 ⁇ 10 18 and 5 ⁇ 10 18 /cm -3 ; the silicon doping concentration of the second N_SL layer is between 1 ⁇ 10 19 and 3 ⁇ 10 19 / Between cm -3 ; the silicon doping concentration of the first N_Bulk layer is between 1 ⁇ 10 19 ⁇ 3 ⁇ 10 19 /cm - 3 ; the silicon doping concentration of the second N_Bulk layer is 5 ⁇ 10 18 ⁇ 1 ⁇ 10 Between 19 /cm -3 .
  • the thickness of the first N_SL layer is between 15 and 20 nm; the thickness of the second N_SL layer is between 30 and 35 nm; and the thickness of the N_SL layer is between 450 and 550 nm.
  • the thickness of the first N_Bulk layer is between 500 and 600 nm; the thickness of the second N_Bulk layer is between 500 and 600 nm; and the thickness of the N_Bulk layer is between 1000 and 1200 nm.
  • the quantum well light-emitting layer includes a periodically set GaN layer and an In x Ga 1-x N layer. between; the thickness of the In x Ga 1-x N layer is between 2 and 5 nm.
  • this application also provides a method for manufacturing LED epitaxial wafers, which is used to manufacture the above-mentioned LED epitaxial wafers, including:
  • the growth temperature of the buffer layer is between 800 and 1100°C;
  • a U-shaped GaN layer is grown on the buffer layer; the growth temperature of the U-shaped GaN layer is between 1000 and 1400°C;
  • the first N_SL layer and the second N_SL layer are cyclically grown on the U-shaped GaN layer in sequence to obtain the N_SL layer; the number of cycles is between 10 and 20; the growth temperature of the first N_SL layer is between 1000 and 1200°C; the first N_SL The growth thickness of the layer is between 15 and 20nm; the growth temperature of the second N_SL layer is between 1000 and 1200°C; the growth thickness of the second N_SL layer is between 30 and 35nm;
  • the first N_Bulk layer is grown on the N_SL layer; the growth temperature of the first N_Bulk layer is between 1000 and 1200°C; the growth thickness of the first N_Bulk layer is between 500 and 600nm;
  • the growth temperature of the second N_Bulk layer is between 900 and 1100°C; the growth thickness of the second N_Bulk layer is between 500 and 600nm;
  • the growth temperature of the quantum well light-emitting layer is between 700 and 800°C;
  • a P-type electron blocking layer is grown on the quantum well light-emitting layer; the growth temperature of the P-type electron blocking layer is between 800 and 1000°C;
  • a P-type GaN layer is grown on the P-type electron blocking layer; the growth temperature of the P-type GaN layer is between 900 and 1100°C.
  • the silicon doping concentration of the first N_SL layer is between 1 ⁇ 10 18 and 5 ⁇ 10 18 /cm -3 ; the silicon doping concentration of the second N_SL layer is between 1 ⁇ 10 19 and 3 ⁇ 10 19 / Between cm -3 ; the silicon doping concentration of the first N_Bulk layer is between 1 ⁇ 10 19 ⁇ 3 ⁇ 10 19 /cm - 3 ; the silicon doping concentration of the second N_Bulk layer is 5 ⁇ 10 18 ⁇ 1 ⁇ 10 Between 19 /cm -3 .
  • the LED epitaxial wafer includes a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, a P-type electron blocking layer and P-type GaN layer.
  • the N-type GaN layer includes an N_SL layer and an N_Bulk layer disposed on the N_SL layer.
  • the N_SL layer includes several first N_SL layers and several second N_SL layers.
  • the first N_SL layer and the second N_SL layer are arranged cyclically from bottom to top.
  • the N_Bulk layer includes the first N_Bulk layer and the second N_Bulk layer.
  • the silicon doping concentration of the first N_SL layer is less than the silicon doping concentration of the second N_SL layer.
  • the silicon doping concentration of the first N_Bulk layer is greater than the silicon doping concentration of the second N_Bulk layer.
  • the silicon doping concentration of the first N_SL layer is less than Silicon doping concentration of the second N_Bulk layer.
  • the N_SL layer and the N_Bulk layer effectively form multiple capacitor structures. At the same time, different concentrations of silicon doping enhance current diffusion and improve the antistatic ability of the LED epitaxial wafer.
  • the structural settings of the N_SL layer and N_Bulk layer reduce the dislocation density of the growing quantum well light-emitting layer and improve the lattice quality of the quantum well light-emitting layer.
  • the SiH4 valve group of the MOCVD equipment does not need a higher switching frequency, thereby increasing the service life of the SiH4 valve group.
  • Figure 1 is a schematic diagram of a traditional LED epitaxial wafer in this application.
  • Figure 2 is a schematic diagram of an LED epitaxial wafer in an embodiment of the present application.
  • Figure 3 is a schematic diagram of the N-type GaN layer structure of the LED epitaxial wafer in the embodiment of the present application.
  • FIG. 4 is a schematic diagram of the equivalent capacitance of the N-type GaN layer of the LED epitaxial wafer in the embodiment of the present application.
  • LED epitaxial wafer refers to a specific single crystal film grown on a substrate heated to an appropriate temperature.
  • a traditional LED epitaxial wafer usually includes a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer and a P-type GaN layer arranged in sequence from bottom to top.
  • N-type GaN layer structures usually include two types: N_Bulk structure and N_SL structure.
  • the conventional N_SL structure includes multiple cyclically alternately stacked silicon-doped GaN layers and silicon-doped GaN layers, and the N_Bulk structure includes two stacked silicon-doped GaN layers.
  • the N_Bulk structure can have a higher electron concentration, but the lattice mismatch with the underlying U-shaped GaN layer is large, causing dislocations to be derived to the quantum well light-emitting layer, affecting the lattice quality of the quantum well light-emitting layer and reducing luminescence. efficiency.
  • the N_SL structure can effectively reduce the lattice mismatch between the N-type GaN layer and the underlying U-type GaN layer, reduce the dislocations derived from the underlying quantum well light-emitting layer, and improve the lattice quality.
  • the N_SL structure will cause luminescence due to the difference in N electrode etching depth. The voltage fluctuates greatly.
  • the N_SL structure requires a higher switching frequency of the SiH4 valve group of the MOCVD equipment during the manufacturing process, which reduces the service life of the SiH4 valve group.
  • traditional LED epitaxial wafers have poor antistatic capabilities. If the PN junction is broken down, the LED will fail.
  • the LED epitaxial wafer in this embodiment includes a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, a P-type electron blocking layer and a P-type GaN layer arranged in sequence from bottom to top.
  • the N-type GaN layer includes an N_SL layer and an N_Bulk layer, and the N_Bulk layer is disposed above the N_SL layer.
  • the N_SL layer includes several first N_SL layers and several second N_SL layers.
  • the first N_SL layers and the second N_SL layers are arranged cyclically from bottom to top, and the number of cycles is between 10 and 20.
  • the N_Bulk layer includes a first N_Bulk layer and a second N_Bulk layer, and the second N_Bulk layer is disposed above the first N_Bulk layer.
  • the N-type GaN layer structure of the LED epitaxial wafer in the embodiment of the present application effectively forms multiple capacitor structures.
  • the potential difference between the two ends of the capacitor accelerates the electron transmission rate and can increase the electron concentration of the quantum well light-emitting layer, thereby improving the LED luminescence. brightness.
  • the lattice mismatch with the U-type GaN layer can be gradually reduced, the dislocation density of the growing quantum well light-emitting layer can be reduced, and the lattice quality of the quantum well light-emitting layer can be improved. Thereby improving the luminous efficiency.
  • the thickness of the N_SL layer is smaller than the thickness of the N_Bulk layer.
  • the thickness of each layer can be set according to production requirements.
  • the thickness of the first N_SL layer is between 15 and 20 nm
  • the thickness of the second N_SL layer is between 30 and 35 nm.
  • the thickness of the N_SL layer composed of multiple cycles of the first N_SL layer and the second N_SL layer is between 450 and 550 nm.
  • the thickness of the first N_Bulk layer is between 500 and 600 nm
  • the thickness of the second N_Bulk layer is between 500 and 600 nm.
  • the thickness of the N_Bulk layer is between 1000 and 1200nm.
  • Table 2 For the LED epitaxial wafer structure in the embodiment of the present application, see Table 2 for a comparison of the working parameters of the thickness of the N_SL layer and the thickness of the N_Bulk layer in different value ranges.
  • sample 11 indicates that the thickness of the first N_SL layer is 18nm, the thickness of the second N_SL layer is 32nm, the thickness of the N_SL layer is 500nm, the thickness of the first N_Bulk layer is 550nm, and the thickness of the second N_Bulk layer is 550nm, LED epitaxial wafer with N_Bulk layer thickness of 1100nm.
  • Sample 12 shows that the thickness of the first N_SL layer is 15nm, the thickness of the second N_SL layer is 30nm, the thickness of the N_SL layer is 450nm, the thickness of the first N_Bulk layer is 500nm, the thickness of the second N_Bulk layer is 500nm, the thickness of the N_Bulk layer It is a 1000nm LED epitaxial wafer.
  • Sample 13 shows that the thickness of the first N_SL layer is 20nm, the thickness of the second N_SL layer is 35nm, the thickness of the N_SL layer is 550nm, the thickness of the first N_Bulk layer is 600nm, the thickness of the second N_Bulk layer is 600nm, the thickness of the N_Bulk layer It is a 1200nm LED epitaxial wafer.
  • Sample 21 represents an LED epitaxial wafer in which the thicknesses of the N_SL layer and the N_Bulk layer are both slightly less than the minimum values of the corresponding ranges in the embodiments of the present application (ie, the thickness of the N_SL layer is slightly less than 450 nm, and the thickness of the N_Bulk layer is slightly less than 1000 nm).
  • Sample 22 represents an LED epitaxial wafer in which the thicknesses of the N_SL layer and the N_Bulk layer are both slightly larger than the maximum values of the corresponding ranges in the embodiments of the present application (ie, the thickness of the N_SL layer is slightly larger than 550 nm, and the thickness of the N_Bulk layer is slightly larger than 1200 nm).
  • the range of "slightly less than” and/or “slightly greater than” in the embodiments of this application is within ten percent of the length of the value interval in the embodiments of this application.
  • the working parameter in the embodiment of this application, Lop is used to characterize the brightness of the sample, and the larger the value, the better the performance.
  • VF1 is the working voltage of the sample. The smaller the value, the less energy consumption.
  • IR is reverse breakdown current, which is used to characterize crystal quality. The smaller the value, the better the crystal quality.
  • ESD is the anti-static ability, which indicates the probability of the sample passing the anti-static test. The larger the value, the better the anti-static ability.
  • WLD is the sample luminescence wavelength.
  • LED epitaxial wafers whose N_SL layer thickness and N_Bulk layer thickness are within the value range in this application have higher brightness, lower operating voltage, better crystal quality, and stronger antistatic ability.
  • the silicon doping concentration of the first N_SL layer is less than the silicon doping concentration of the second N_SL layer.
  • the silicon doping concentration of the first N_Bulk layer is greater than the silicon doping concentration of the second N_Bulk layer.
  • the silicon doping concentration of the first N_SL layer is less than Silicon doping concentration of the second N_Bulk layer.
  • the silicon doping concentration of the first N_SL layer is between 1 ⁇ 10 18 and 5 ⁇ 10 18 /cm -3 , and the growth temperature of the first N_SL layer is between 1000 and 1200°C.
  • the silicon doping concentration of the second N_SL layer is between 1 ⁇ 10 19 and 3 ⁇ 10 19 /cm -3 , and the growth temperature of the second N_SL layer is between 1000 and 1200°C.
  • the silicon doping concentration of the first N_Bulk layer is between 1 ⁇ 10 19 and 3 ⁇ 10 19 /cm -3 , and the growth temperature of the first N_Bulk layer is between 1000 and 1200°C.
  • the silicon doping concentration of the second N_Bulk layer is between 5 ⁇ 10 18 and 1 ⁇ 10 19 /cm -3 , and the growth temperature of the second N_Bulk layer is between 900 and 1100°C.
  • Table 4 For the LED epitaxial wafer structure in the embodiment of the present application, see Table 4 for a comparison of the working parameters of the silicon doping concentration of the N_SL layer and the silicon doping concentration of the N_Bulk layer in different value ranges.
  • sample 14 indicates that the silicon doping concentration of the first N_SL layer is 3 ⁇ 10 18 /cm -3 , the silicon doping concentration of the second N_SL layer is 2 ⁇ 10 19 /cm -3 , and the first N_Bulk The silicon doping concentration of the second N_Bulk layer is 2 ⁇ 10 19 /cm -3 and the silicon doping concentration of the second N_Bulk layer is 8 ⁇ 10 18 /cm -3 for the LED epitaxial wafer.
  • Sample 15 indicates that the silicon doping concentration of the first N_SL layer is 1 ⁇ 10 18 /cm -3 , the silicon doping concentration of the second N_SL layer is 1 ⁇ 10 19 /cm -3 , and the silicon doping concentration of the first N_Bulk layer
  • the LED epitaxial wafer has a silicon doping concentration of 1 ⁇ 10 19 /cm -3 and the second N_Bulk layer is 5 ⁇ 10 18 /cm -3 .
  • Sample 16 indicates that the silicon doping concentration of the first N_SL layer is 5 ⁇ 10 18 /cm -3 , the silicon doping concentration of the second N_SL layer is 3 ⁇ 10 19 /cm -3 , and the silicon doping concentration of the first N_Bulk layer
  • the LED epitaxial wafer has a silicon doping concentration of 3 ⁇ 10 19 /cm -3 and the second N_Bulk layer is 1 ⁇ 10 19 /cm -3 .
  • Sample 31 represents an LED epitaxial wafer in which the silicon doping concentrations of the first N_SL layer, the second N_SL layer, the first N_Bulk layer and the second N_Bulk layer are all slightly smaller than the minimum values of the corresponding ranges in the embodiments of the present application.
  • Sample 32 represents an LED epitaxial wafer in which the silicon doping concentration of the first N_SL layer, the second N_SL layer, the first N_Bulk layer and the second N_Bulk layer is slightly greater than the maximum value of the corresponding range in the embodiment of the present application.
  • LED epitaxial wafers whose silicon doping concentration of the N_SL layer and the silicon doping concentration of the N_Bulk layer are within the value range in this application have higher brightness, lower operating voltage, better crystal quality, and higher resistance to Stronger electrostatic capability.
  • Table 6 Based on the LED epitaxial wafer structure in the embodiment of the present application, see Table 6 for a comparison of the working parameters of the growth temperature of the N_SL layer and the growth temperature of the N_Bulk layer in different value ranges. Among them, referring to Table 5, sample 17 indicates that the growth temperature of the first N_SL layer is 1100°C, the growth temperature of the second N_SL layer is 1100°C, the growth temperature of the first N_Bulk layer is 1100°C, and the growth temperature of the second N_Bulk layer is 1000°C LED epitaxial wafer.
  • Sample 18 represents an LED epitaxial wafer in which the growth temperature of the first N_SL layer is 1000°C, the growth temperature of the second N_SL layer is 1000°C, the growth temperature of the first N_Bulk layer is 1000°C, and the growth temperature of the second N_Bulk layer is 900°C.
  • Sample 19 represents an LED epitaxial wafer in which the growth temperature of the first N_SL layer is 1200°C, the growth temperature of the second N_SL layer is 1200°C, the growth temperature of the first N_Bulk layer is 1200°C, and the growth temperature of the second N_Bulk layer is 1100°C. .
  • Sample 41 represents an LED epitaxial wafer in which the growth temperatures of the first N_SL layer, the second N_SL layer, the first N_Bulk layer, and the second N_Bulk layer are all slightly lower than the minimum values of the corresponding ranges in the embodiments of the present application.
  • Sample 42 represents an LED epitaxial wafer in which the growth temperatures of the first N_SL layer, the second N_SL layer, the first N_Bulk layer, and the second N_Bulk layer are all slightly higher than the maximum values of the corresponding ranges in the embodiments of the present application.
  • LED epitaxial wafers whose growth temperature of the N_SL layer and the growth temperature of the N_Bulk layer are within the value range in this application have higher brightness, lower operating voltage, better crystal quality, and stronger antistatic ability. .
  • the embodiment of the present application sets different silicon doping concentrations, growth thicknesses, and growth temperatures for the N_SL layer and the N_Bulk layer.
  • High and low silicon doping can enhance current diffusion.
  • High and low silicon doping include high silicon doping and low silicon doping.
  • the low silicon doping part has a certain ability to restrict electrons, which can increase the concentration of two-dimensional electron gas, thus enhancing the performance of LED epitaxial wafers. Antistatic ability. At the same time, it can increase electron mobility, reduce luminescence voltage, and improve luminescence voltage stability.
  • the combination of high and low silicon doping and high and low temperature growth can further release stress, thus improving the growth quality of the overall epitaxial structure.
  • the SiH4 valve group of the MOCVD equipment since the LED epitaxial wafer in the embodiment of the present application requires silicon doping during the entire growth stage of the N-type GaN layer, the SiH4 valve group of the MOCVD equipment remains in a normally open state. It is only necessary to adjust the opening degree of the SiH4 valve group according to different silicon doping concentrations, avoiding high-frequency switching of the SiH4 valve group's switching state, thereby extending the service life of the SiH4 valve group.
  • the quantum well light-emitting layer in the embodiment of the present application is a multi-period GaN/In x Ga 1-x N structure, in which the GaN layer is a barrier layer and the In x Ga 1-x N layer is a well layer.
  • the number of cycles is between 7 and 12
  • the value of x is between 0.2 and 0.3
  • the thickness of the barrier layer is between 8 and 12 nm
  • the thickness of the well layer is between 2 and 5 nm.
  • sample 0 represents a conventional LED epitaxial wafer
  • sample 1 represents the LED epitaxial wafer in the embodiment of the present application.
  • the N_Sl layer and the N_Bulk layer include a multi-layer structure.
  • the thickness, growth temperature and silicon doping concentration of different layer structures improves the luminous brightness, reduces the operating voltage, improves the crystal quality, and has good anti-static ability.
  • An embodiment of the present application also provides a method for manufacturing an LED epitaxial wafer, which is used to manufacture the above-mentioned LED epitaxial wafer in the embodiment of the present application.
  • Method steps include:
  • a substrate is prepared, and a buffer layer is grown on the substrate.
  • the growth temperature of the buffer layer is between 800 and 1100°C.
  • the growth thickness of the buffer layer is between 15 and 30nm.
  • the substrate can be a sapphire (Al 2 O 3 ) substrate.
  • a U-shaped GaN layer is grown on the buffer layer.
  • the growth temperature of the U-shaped GaN layer is between 1000 and 1400°C.
  • the growth thickness of the U-shaped GaN layer is between 2 and 4 ⁇ m.
  • the first N_SL layer and the second N_SL layer are grown sequentially and cyclically on the U-shaped GaN layer to obtain the N_SL layer. According to production needs, the number of cycles is between 10 and 20.
  • the silicon doping concentration of the first N_SL layer is between 1 ⁇ 10 18 and 5 ⁇ 10 18 /cm -3 .
  • the growth temperature of the first N_SL layer is between 1000 and 1200°C.
  • the growth thickness of the first N_SL layer is 15 ⁇ 20nm.
  • the silicon doping concentration of the second N_SL layer is between 1 ⁇ 10 19 and 3 ⁇ 10 19 /cm -3 .
  • the growth temperature of the second N_SL layer is between 1000 and 1200°C.
  • the growth thickness of the second N_SL layer is 30 ⁇ 35nm.
  • a first N_Bulk layer is grown on the N_SL layer.
  • the silicon doping concentration of the first N_Bulk layer is between 1 ⁇ 10 19 and 3 ⁇ 10 19 /cm - 3.
  • the growth temperature of the first N_Bulk layer is between 1000 and 1200°C.
  • the growth thickness of the first N_Bulk layer is 500 ⁇ 600nm.
  • a second N_Bulk layer is grown on the first N_Bulk layer.
  • the silicon doping concentration of the second N_Bulk layer is between 5 ⁇ 10 18 and 1 ⁇ 10 19 /cm -3
  • the growth temperature of the second N_Bulk layer is between 900 and 1100°C
  • the growth thickness of the second N_Bulk layer is 500 ⁇ 600nm.
  • the growth rate of the first N_Bulk layer and the second N_Bulk layer is between 6 and 9 ⁇ m/h.
  • a quantum well light emitting layer is grown on the second N_Bulk layer.
  • the growth temperature of the quantum well light-emitting layer is between 700°C and 800°C.
  • a P-type electron blocking layer is grown on the quantum well light-emitting layer.
  • the growth temperature of the P-type electron blocking layer is between 800°C and 1000°C.
  • a P-type GaN layer is grown on the P-type electron blocking layer.
  • the growth temperature of the P-type GaN layer is between 900 and 1100°C.
  • the LED epitaxial wafer includes a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, a P-type electron blocking layer and P-type GaN layer.
  • the N-type GaN layer includes an N_SL layer and an N_Bulk layer disposed on the N_SL layer.
  • the N_SL layer includes several first N_SL layers and several second N_SL layers.
  • the first N_SL layer and the second N_SL layer are arranged cyclically from bottom to top.
  • the N_Bulk layer includes the first N_Bulk layer and the second N_Bulk layer.
  • the silicon doping concentration of the first N_SL layer is less than the silicon doping concentration of the second N_SL layer.
  • the silicon doping concentration of the first N_Bulk layer is greater than the silicon doping concentration of the second N_Bulk layer.
  • the silicon doping concentration of the first N_SL layer is less than Silicon doping concentration of the second N_Bulk layer.
  • the N_SL layer and the N_Bulk layer effectively form multiple capacitor structures. At the same time, different concentrations of silicon doping enhance current diffusion and improve the antistatic ability of the LED epitaxial wafer.
  • the structural settings of the N_SL layer and N_Bulk layer reduce the dislocation density of the growing quantum well light-emitting layer and improve the lattice quality of the quantum well light-emitting layer.
  • the SiH4 valve group of the MOCVD equipment does not need a higher switching frequency, thereby increasing the service life of the SiH4 valve group.

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Abstract

本申请提供一种LED外延片及其制造方法，LED外延片的N型GaN层包括N_SL层和N_Bulk层。N_SL层包括第一N_SL层和第二N_SL层，第一N_SL层和第二N_SL层从下至上依次循环设置，N_Bulk层包括第一N_Bulk层和第二N_Bulk层。N_SL层和N_Bulk层等效形成多个电容结构，不同浓度的硅掺杂度增强电流扩散，提升LED外延片的抗静电能力。N_SL层和N_Bulk层结构设置降低生长量子阱发光层位错密度，提升量子阱发光层晶格质量。本申请提供的LED外延片在制造过程中，MOCVD设备的SiH4阀组不需要较高的开关频率，提高SiH4阀组的使用寿命。

Description

一种LED外延片及其制造方法 技术领域
本申请涉及LED技术领域，尤其涉及一种LED外延片及其制造方法。
背景技术
LED(Light-Emitting Diode，发光二极管)是一种将电能转换为光能的半导体发光器件。LED外延片是指在一块加热至适当温度的衬底基片上，所生长出来的特定单晶薄膜。参见图1，LED外延片通常包括从下至上依次设置的衬底、缓冲层、U型GaN层、N型GaN层、量子阱发光层和P型GaN层。LED外延片的生长主要采用MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气象沉淀)设备实现。
MOCVD设备生长的LED外延片的N型GaN层结构，包括N_Bulk结构和N_SL结构两种类型。其中N_Bulk结构可以提供较高的电子浓度，但是与下层的U型GaN层以及上层的量子阱发光层晶格失配较大，影响量子阱发光层晶体质量。相对于N_Bulk结构，N_SL结构可以有效降低N型GaN层与下层U型GaN层的晶格失配，但是N_SL结构会因N电极蚀刻差异导致发光电压波动较大。并且在生长过程中，MOCVD设备的SiH4阀组需要较高的开关频率，降低SiH4阀组的使用寿命，增加生产成本。
另外，LED在生产制造及安装使用等过程中，难免会受到静电影响而产生感应电荷，若感应电荷得不到及时释放，会在PN结两端形成较高的电压。传统的LED外延片抗静电能力较差，当电压超过LED外延片的最大承受值后，静电电荷将以极短的瞬间在PN结两端进行放电，导致PN结被击穿，使LED失效。
发明内容
本申请提供一种LED外延片及其制造方法，以解决传统LED外延片晶格失配大、生产成本高、抗静电能力差的问题。
一方面，本申请提供一种LED外延片，包括依次叠层设置的衬底、缓冲层、U型GaN层、N型GaN层、量子阱发光层、P型电子阻挡层和P型GaN层。N型GaN层包括：N_SL层和设置于N_SL层上的N_Bulk层，N_SL层的厚度小于N_Bulk层的厚度。
N_SL层包括若干个第一N_SL层和若干个第二N_SL层。N_Bulk层包括第一N_Bulk层和设置在第一N_Bulk层上的第二N_Bulk层。
第一N_SL层的硅掺杂浓度小于第二N_SL层的硅掺杂浓度。第一N_Bulk层的硅掺杂浓度大于第二N_Bulk层的硅掺杂浓度。第一N_SL层的硅掺杂浓度小于第二N_Bulk层的硅掺杂浓度。
N_SL层和N_Bulk层等效形成多个电容结构，不同浓度的硅掺杂度增强电流扩散，提升LED外延片的抗静电能力。N_SL层和N_Bulk层结构设置降低生长量子阱发光层位错密度，提升量子阱发光层晶格质量。
可选的，第一N_SL层和第二N_SL层从下至上依次循环设置，循环次数在10～20之间。
可选的，第一N_SL层的硅掺杂浓度为1×10 18～5×10 18/cm -3之间；第二N_SL层的硅掺杂浓度为1×10 19～3×10 19/cm -3之间；第一N_Bulk层的硅掺杂浓度为1×10 19～3×10 19/cm - 3之间；第二N_Bulk层的硅掺杂浓度为5×10 18～1×10 19/cm -3之间。
可选的，第一N_SL层的厚度为15～20nm之间；第二N_SL层的厚度为30～35nm之间；N_SL层的厚度为450～550nm之间。
可选的，第一N_Bulk层的厚度为500～600nm之间；第二N_Bulk层的厚度为500～600nm之间；N_Bulk层的厚度为1000～1200nm之间。
可选的，量子阱发光层包括周期设置的GaN层和In xGa 1-xN层，x设置为0.2～0.3之间，周期数在7～12之间；GaN层的厚度为8～12nm之间；In xGa 1-xN层厚度为2～5nm之间。
另一方面，本申请还提供一种LED外延片制造方法，用于制造上述LED外延片，包括：
制备衬底，在衬底上生长缓冲层；缓冲层的生长温度为800～1100℃之间；
在缓冲层上生长U型GaN层；U型GaN层的生长温度为1000～1400℃之间；
在U型GaN层上依次循环生长第一N_SL层和第二N_SL层，得到N_SL层；循环次数为10～20之间；第一N_SL层的生长温度为1000～1200℃之间；第一N_SL层的生长厚度为15～20nm之间；第二N_SL层的生长温度为1000～1200℃之间；第二N_SL层的生长厚度为30～35nm之间；
在N_SL层上生长第一N_Bulk层；第一N_Bulk层的生长温度为1000～1200℃之间；第一N_Bulk层的生长厚度为500～600nm之间；
在第一N_Bulk层上生长第二N_Bulk层；第二N_Bulk层的生长温度为900～1100℃之间；第二N_Bulk层的生长厚度为500～600nm之间；
在第二N_Bulk层上生长量子阱发光层；量子阱发光层的生长温度为700～800℃之间；
在量子阱发光层上生长P型电子阻挡层；P型电子阻挡层的生长温度为800～1000℃之间；
在P型电子阻挡层上生长P型GaN层；P型GaN层的生长温度为900～1100℃之间。
可选的，第一N_SL层的硅掺杂浓度为1×10 18～5×10 18/cm -3之间；第二N_SL层的硅掺杂浓度为1×10 19～3×10 19/cm -3之间；第一N_Bulk层的硅掺杂浓度为1×10 19～3×10 19/cm - 3之间；第二N_Bulk层的硅掺杂浓度为5×10 18～1×10 19/cm -3之间。
本申请中的一种LED外延片及其制造方法，LED外延片包括依次叠层设置的衬底、缓冲层、U型GaN层、N型GaN层、量子阱发光层、P型电子阻挡层和P型GaN层。其中，N型GaN层包括N_SL层和设置于N_SL层上的N_Bulk层。N_SL层包括若干个第一N_SL层和若干个第二N_SL层，第一N_SL层和第二N_SL层从下至上依次循环设置，N_Bulk层包括第一N_Bulk层和第二N_Bulk层。第一N_SL层的硅掺杂浓度小于第二N_SL层的硅掺杂浓度，第一N_Bulk层的硅掺杂浓度大于第二N_Bulk层的硅掺杂浓度，第一N_SL层的硅掺杂浓度小于第二N_Bulk层的硅掺杂浓度。N_SL层和N_Bulk层等效形成多个电容结构，同时，不同浓度的硅掺杂度增强电流扩散，提升LED外延片的抗静电能力。N_SL层和N_Bulk层结构设置降低生长量子阱发光层位错密度，提升量子阱发光层晶格质量。本申请中的LED外延片在制造过程中，MOCVD设备的SiH4阀组不需要较高的开关频率，提高SiH4阀组的使用寿命。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请中的传统的LED外延片示意图；
图2为本申请实施例中的LED外延片示意图；
图3为本申请实施例中的LED外延片的N型GaN层结构示意图；
图4为本申请实施例中的LED外延片的N型GaN层等效电容示意图。
具体实施方式
下面将详细地对实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下实施例中描述的实施方式并不代表与本申请相一致的所有实施方式。仅是与权利要求书中所详述的、本申请的一些方面相一致的系统和方法的示例。
LED外延片是指在一块加热至适当温度的衬底基片上，所生长出来的特定单晶薄膜。参见图1，传统的LED外延片通常包括从下至上依次设置的衬底、缓冲层、U型GaN层、N型GaN层、量子阱发光层和P型GaN层。N型GaN层结构通常包括N_Bulk结构和N_SL结构两种类型。常规的N_SL结构包括多个循环交替层叠的不掺硅GaN层和掺硅GaN层，N_Bulk结构包括两个层叠的掺硅GaN层。其中，N_Bulk结构可以具有较高的电子浓度，但是与下层的U型GaN层晶格失配较大，导致位错会衍生至量子阱发光层，影响量子阱发光层的晶格质量，降低发光效率。N_SL结构可以有效降低N型GaN层与下层U型GaN层的晶格失配，降低底层衍生至量子阱发光层的位错，提升晶格质量，但是N_SL结构会因N电极蚀刻深度差异导致发光电压波动较大。并且N_SL结构在制造过程中需要MOCVD设备的SiH4阀组较高的开关频率，降低SiH4阀组的使用寿命。此外，传统的LED外延片抗静电能力较差，若PN结被击穿会导致LED失效。
基于上述问题，本申请实施例提供一种LED外延片。参见图2，本实施例中的LED外延片包括从下至上依次设置的衬底、缓冲层、U型GaN层、N型GaN层、量子阱发光层、P型电子阻挡层和P型GaN层。其中，N型GaN层包括N_SL层和N_Bulk层，N_Bulk层设置于N_SL层上方。参见图3，N_SL层包括若干第一N_SL层和若干第二N_SL层，第一N_SL层和第二N_SL层从下至上依次循环设置，循环次数为10～20之间。N_Bulk层包括第一N_Bulk层和第二N_Bulk层，第二N_Bulk层设置在第一N_Bulk层上方。
参见图4，本申请实施例中的LED外延片的N型GaN层结构等效形成多个电容结构，电容两端的电势差加快电子传输速率，可以提高量子阱发光层的电子浓度，从而提高LED发光亮度。通过N_SL层和N_Bulk层的多层结构设计，可以逐级过渡减小与U型GaN层的晶格失配，降低生长量子阱发光层的位错密度，提升量子阱发光层的晶格质量，从而提升发光效率。
N_SL层的厚度小于N_Bulk层的厚度。可以根据生产需求设置各层的厚度，在一种实施方式中，第一N_SL层的厚度为15～20nm之间，第二N_SL层的厚度为30～35nm之间。由第一N_SL层和第二N_SL层多次循环构成的N_SL层的厚度为450～550nm之间。第一N_Bulk层的厚度为500～600nm之间，第二N_Bulk层的厚度为500～600nm之间。N_Bulk层的厚度为1000～1200nm之间。
本申请实施例中的LED外延片结构，N_SL层的厚度和N_Bulk层的厚度在不同取值范围内的工作参数对比参见表2。其中，参见表1，样品11表示第一N_SL层的厚度为18nm，第二N_SL层的厚度为32nm，N_SL层的厚度为500nm，第一N_Bulk层的厚度为550nm，第二N_Bulk层的厚度为550nm，N_Bulk层的厚度为1100nm的LED外延片。样品12表示第一N_SL层的厚度为15nm，第二N_SL层的厚度为30nm，N_SL层的厚度为450nm，第一N_Bulk层的厚度为500nm，第二N_Bulk层的厚度为500nm，N_Bulk层的厚度为1000nm的LED外延片。样品13表示第一N_SL层的厚度为20nm，第二N_SL层的厚度为35nm，N_SL层的厚度为550nm，第一N_Bulk层的厚度为600nm，第二N_Bulk层的厚度为600nm，N_Bulk层的厚度为1200nm的LED外延片。样品21表示N_SL层和N_Bulk层的厚度均略小于本申请实施例中的相应范围的最小值(即N_SL层的厚度略小于450nm，N_Bulk层的厚度略小于1000nm)的LED外延片。样品22表示N_SL层和N_Bulk层的厚度均略大于本申请实施例中的相应范围的最大值(即N_SL层的厚度略大于550nm，N_Bulk层的厚度略大于1200nm)的LED外延片。
本申请实施例中“略小于”和/或“略大于”的范围为，本申请实施例中的取值区间长度的百分之十以内。例如，本申请实施例中的N_SL层的厚度为450～550nm之间，取值区间长度即550nm-450nm＝100nm。样品21中N_SL层的厚度略小于450nm，即N_SL层的厚度为440～450nm之间(440nm＝450nm-(550nm-450nm)×10％)。样品22中N_SL层的厚度略大于550nm，即N_SL层的厚度为550～560nm之间(560nm＝550nm+(550nm-450nm)×10％)。
本申请实施例中的工作参数，Lop用于表征样品亮度，其数值越大代表性能越好。VF1为样品工作电压，其数值越小耗能越少。IR为反向击穿电流，用于表征晶体质量，数值越小晶体质量越好。ESD为抗静电能力，表示样品通过抗静电测试的概率，数值越大抗静电能力越好。WLD为样品发光波长。
表1
Figure PCTCN2022114586-appb-000001
表2
Figure PCTCN2022114586-appb-000002
从表2可以看出，N_SL层的厚度和N_Bulk层的厚度在本申请中的取值范围内的LED外延片，亮度更高、工作电压更低、晶体质量更好、抗静电能力更强。
第一N_SL层的硅掺杂浓度小于第二N_SL层的硅掺杂浓度，第一N_Bulk层的硅掺杂浓度大于第二N_Bulk层的硅掺杂浓度，第一N_SL层的硅掺杂浓度小于第二N_Bulk层的 硅掺杂浓度。
在一种实施方式中，第一N_SL层的硅掺杂浓度为1×10 18～5×10 18/cm -3之间，第一N_SL层的生长温度为1000～1200℃之间。第二N_SL层的硅掺杂浓度为1×10 19～3×10 19/cm -3之间，第二N_SL层的生长温度为1000～1200℃之间。第一N_Bulk层的硅掺杂浓度为1×10 19～3×10 19/cm -3之间，第一N_Bulk层的生长温度为1000～1200℃之间。第二N_Bulk层的硅掺杂浓度为5×10 18～1×10 19/cm -3之间，第二N_Bulk层的生长温度为900～1100℃之间。
本申请实施例中的LED外延片结构，N_SL层的硅掺杂浓度和N_Bulk层的硅掺杂浓度在不同取值范围内的工作参数对比参见表4。其中，参见表3，样品14表示第一N_SL层的硅掺杂浓度为3×10 18/cm -3，第二N_SL层的硅掺杂浓度为2×10 19/cm -3，第一N_Bulk层的硅掺杂浓度为2×10 19/cm -3，第二N_Bulk层的硅掺杂浓度为8×10 18/cm -3的LED外延片。样品15表示第一N_SL层的硅掺杂浓度为1×10 18/cm -3，第二N_SL层的硅掺杂浓度为1×10 19/cm -3，第一N_Bulk层的硅掺杂浓度为1×10 19/cm -3，第二N_Bulk层的硅掺杂浓度为5×10 18/cm -3的LED外延片。样品16表示第一N_SL层的硅掺杂浓度为5×10 18/cm -3，第二N_SL层的硅掺杂浓度为3×10 19/cm -3，第一N_Bulk层的硅掺杂浓度为3×10 19/cm -3，第二N_Bulk层的硅掺杂浓度为1×10 19/cm -3的LED外延片。样品31表示第一N_SL层、第二N_SL层、第一N_Bulk层和第二N_Bulk层的硅掺杂浓度均略小于本申请实施例中的相应范围的最小值的LED外延片。样品32表示第一N_SL层、第二N_SL层、第一N_Bulk层和第二N_Bulk层的硅掺杂浓度均略大于本申请实施例中的相应范围的最大值的LED外延片。
表3
Figure PCTCN2022114586-appb-000003
表4
Figure PCTCN2022114586-appb-000004
从表4可以看出，N_SL层的硅掺杂浓度和N_Bulk层的硅掺杂浓度在本申请中取值范围内的LED外延片，亮度更高、工作电压更低、晶体质量更好、抗静电能力更强。
基于本申请实施例中的LED外延片结构，N_SL层的生长温度和N_Bulk层的生长温度在不同取值范围内的工作参数对比参见表6。其中，参见表5，样品17表示第一N_SL层的生长温度为1100℃，第二N_SL层的生长温度为1100℃，第一N_Bulk层的生长温度为1100℃，第二N_Bulk层的生长温度为1000℃的LED外延片。样品18表示第一N_SL层的生长温度为1000℃，第二N_SL层的生长温度为1000℃，第一N_Bulk层的生长温度为1000℃，第二N_Bulk层的生长温度为900℃的LED外延片。样品19表示第一N_SL层的生长温度为 1200℃，第二N_SL层的生长温度为1200℃，第一N_Bulk层的生长温度为1200℃，第二N_Bulk层的生长温度为1100℃的LED外延片。样品41表示第一N_SL层、第二N_SL层、第一N_Bulk层和第二N_Bulk层的生长温度均略低于本申请实施例中相应范围的最小值的LED外延片。样品42表示第一N_SL层、第二N_SL层、第一N_Bulk层和第二N_Bulk层的生长温度均略高于本申请实施例中相应范围的最大值的LED外延片。
表5
Figure PCTCN2022114586-appb-000005
表6
Figure PCTCN2022114586-appb-000006
从表6可以看出，N_SL层的生长温度和N_Bulk层的生长温度在本申请中取值范围内的LED外延片，亮度更高、工作电压更低、晶体质量更好、抗静电能力更强。
本申请实施例对N_SL层和N_Bulk层设置不同的硅掺杂浓度、生长厚度和生长温度。高低硅掺可以增强电流扩散，高低硅掺包括高硅掺和低硅掺，其中低硅掺部分对电子具备一定的限制能力，可以提高二维电子气的存在集中度，从而增强LED外延片的抗静电能力。同时可以提高电子迁移率，降低发光电压，提升发光电压稳定性。高低硅掺和高低温度搭配生长，可以进一步释放应力，从而提升整体外延结构的生长质量。并且，本申请实施例中的LED外延片，由于整个N型GaN层的生长阶段都需要进行掺硅操作，MOCVD设备的SiH4阀组保持常开状态。仅需根据不同的硅掺杂浓度调整SiH4阀组打开的程度大小，避免了SiH4阀组开关状态的高频率切换，从而延长SiH4阀组使用寿命。
本申请实施例中的量子阱发光层为多周期的GaN/In xGa 1-xN结构，其中GaN层为势垒层，In xGa 1-xN层为势阱层。在一种实施方式中，周期数为7～12之间，x取值在0.2～0.3之间，势垒层的厚度为8～12nm之间，势阱层的厚度为2～5nm之间。
本申请实施例中的LED外延片与常规LED外延片工作参数对比参见表7。其中，样品0表示常规LED外延片，样品1表示本申请实施例中的LED外延片。
表7
Figure PCTCN2022114586-appb-000007
由表7可以看出，与常规LED外延片相比，本申请实施例中的LED外延片中，N_Sl层 和N_Bulk层包括多层结构，通过限定不同层结构的厚度、生长温度以及硅掺浓度，提高了发光亮度、降低工作电压、提升晶体质量，具有良好的抗静电能力。
本申请实施例还提供一种LED外延片制造方法，用于制造本申请实施例中上述LED外延片。方法步骤包括：
制备衬底，在衬底上生长缓冲层。缓冲层的生长温度为800～1100℃之间。缓冲层的生长厚度在15～30nm之间。其中，衬底可以采用蓝宝石(Al 2O 3)衬底。
在缓冲层上生长U型GaN层。U型GaN层的生长温度为1000～1400℃之间。U型GaN层的生长厚度在2～4μm之间。
在U型GaN层上依次循环生长第一N_SL层和第二N_SL层，得到N_SL层。根据生产需求，循环次数为10～20之间。第一N_SL层的硅掺杂浓度为1×10 18～5×10 18/cm -3之间，第一N_SL层的生长温度为1000～1200℃之间，第一N_SL层的生长厚度为15～20nm之间。第二N_SL层的硅掺杂浓度为1×10 19～3×10 19/cm -3之间，第二N_SL层的生长温度为1000～1200℃之间，第二N_SL层的生长厚度为30～35nm之间。
在N_SL层上生长第一N_Bulk层。第一N_Bulk层的硅掺杂浓度为1×10 19～3×10 19/cm - 3之间，第一N_Bulk层的生长温度为1000～1200℃之间，第一N_Bulk层的生长厚度为500～600nm之间。
在第一N_Bulk层上生长第二N_Bulk层。第二N_Bulk层的硅掺杂浓度为5×10 18～1×10 19/cm -3之间，第二N_Bulk层的生长温度为900～1100℃之间，第二N_Bulk层的生长厚度为500～600nm之间。
第一N_Bulk层和第二N_Bulk层的生长速度为6～9μm/h之间。
在第二N_Bulk层上生长量子阱发光层。量子阱发光层的生长温度为700℃～800℃之间。
在量子阱发光层上生长P型电子阻挡层。P型电子阻挡层的生长温度为800℃～1000℃之间。
在P型电子阻挡层上生长P型GaN层。P型GaN层的生长温度为900～1100℃之间。
本申请中的一种LED外延片及其制造方法，LED外延片包括依次叠层设置的衬底、缓冲层、U型GaN层、N型GaN层、量子阱发光层、P型电子阻挡层和P型GaN层。其中，N型GaN层包括N_SL层和设置于N_SL层上的N_Bulk层。N_SL层包括若干个第一N_SL层和若干个第二N_SL层，第一N_SL层和第二N_SL层从下至上依次循环设置，N_Bulk层包括第一N_Bulk层和第二N_Bulk层。第一N_SL层的硅掺杂浓度小于第二N_SL层的硅掺杂浓度，第一N_Bulk层的硅掺杂浓度大于第二N_Bulk层的硅掺杂浓度，第一N_SL层的硅掺杂浓度小于第二N_Bulk层的硅掺杂浓度。N_SL层和N_Bulk层等效形成多个电容结构，同时，不同浓度的硅掺杂度增强电流扩散，提升LED外延片的抗静电能力。N_SL层和N_Bulk层结构设置降低生长量子阱发光层位错密度，提升量子阱发光层晶格质量。本申请的LED外延片在制造过程中，MOCVD设备的SiH4阀组不需要较高的开关频率，提高SiH4阀组的使用寿命。
本申请实施例之间的相似部分相互参见即可，以上介绍的具体实施方式只是本申请总的构思下的几个示例，并不构成本申请保护范围的限定。对于本领域的技术人员而言，在不付出创造性劳动的前提下依据本申请方案所扩展出的任何其他实施方式都属于本申请 的保护范围。

Claims (7)

  1. 一种LED外延片，包括依次叠层设置的衬底、缓冲层、U型GaN层、N型GaN层、量子阱发光层、P型电子阻挡层和P型GaN层，其特征在于，所述N型GaN层包括：N_SL层和设置于所述N_SL层上的N_Bulk层；所述N_SL层的厚度小于所述N_Bulk层的厚度；
    所述N_SL层包括若干个第一N_SL层和若干个第二N_SL层；所述N_Bulk层包括第一N_Bulk层和设置在所述第一N_Bulk层上的第二N_Bulk层；
    所述第一N_SL层的硅掺杂浓度小于所述第二N_SL层的硅掺杂浓度；所述第一N_Bulk层的硅掺杂浓度大于所述第二N_Bulk层的硅掺杂浓度；所述第一N_SL层的硅掺杂浓度小于所述第二N_Bulk层的硅掺杂浓度；
    所述第一N_SL层和所述第二N_SL层从下至上依次循环设置，循环次数为10～20；
    所述第一N_SL层的生长温度为1000～1200℃，所述第二N_SL层的生长温度为1000～1200℃，所述第一N_Bulk层的生长温度为1000～1200℃，所述第二N_Bulk层的生长温度为900～1100℃。
  2. 根据权利要求1所述的LED外延片，其特征在于，所述第一N_SL层的硅掺杂浓度为1×10 18～5×10 18/cm -3；所述第二N_SL层的硅掺杂浓度为1×10 19～3×10 19/cm - 3；所述第一N_Bulk层的硅掺杂浓度为1×10 19～3×10 19/cm -3；所述第二N_Bulk层的硅掺杂浓度为5×10 18～1×10 19/cm -3。
  3. 根据权利要求2所述的LED外延片，其特征在于，所述第一N_SL层的厚度为15～20nm；所述第二N_SL层的厚度为30～35nm；所述N_SL层的厚度为450～550nm。
  4. 根据权利要求2所述的LED外延片，其特征在于，所述第一N_Bulk层的厚度为500～600nm；所述第二N_Bulk层的厚度为500～600nm；所述N_Bulk层的厚度为1000～1200nm。
  5. 根据权利要求1所述的LED外延片，其特征在于，所述量子阱发光层包括周期设置的GaN层和In xGa 1-xN层，x设置为0.2～0.3，周期数为7～12；所述GaN层的厚度为8～12nm；所述In xGa 1-xN层厚度为2～5nm。
  6. 一种LED外延片制造方法，用于制造权利要求1-5任意一项所述的LED外延片，其特征在于，包括：
    制备衬底，在衬底上生长缓冲层；所述缓冲层的生长温度为800～1100℃；
    在所述缓冲层上生长U型GaN层；所述U型GaN层的生长温度为1000～1400℃；
    在所述U型GaN层上依次循环生长第一N_SL层和第二N_SL层，得到N_SL层；循环次数为10～20；所述第一N_SL层的生长温度为1000～1200℃；所述第一N_SL层的生长厚度为15～20nm；所述第二N_SL层的生长温度为1000～1200℃；所述第二N_SL层的生长厚度为30～35nm；
    在所述N_SL层上生长第一N_Bulk层；所述第一N_Bulk层的生长温度为1000～1200℃；所述第一N_Bulk层的生长厚度为500～600nm；
    在所述第一N_Bulk层上生长第二N_Bulk层；所述第二N_Bulk层的生长温度为900～1100℃；所述第二N_Bulk层的生长厚度为500～600nm；
    在所述第二N_Bulk层上生长量子阱发光层；所述量子阱发光层的生长温度为 700～800℃；
    在所述量子阱发光层上生长P型电子阻挡层；所述P型电子阻挡层的生长温度为800～1000℃；
    在所述P型电子阻挡层上生长P型GaN层；所述P型GaN层的生长温度为900～1100℃。
  7. 根据权利要求6所述的LED外延片制造方法，其特征在于，所述第一N_SL层的硅掺杂浓度为1×10 18～5×10 18/cm -3；所述第二N_SL层的硅掺杂浓度为1×10 19～3×10 19/cm -3；所述第一N_Bulk层的硅掺杂浓度为1×10 19～3×10 19/cm -3；所述第二N_Bulk层的硅掺杂浓度为5×10 18～1×10 19/cm -3。
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