WO2023206659A1 - 信号检测系统和存储器检测方法 - Google Patents

信号检测系统和存储器检测方法 Download PDF

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Publication number
WO2023206659A1
WO2023206659A1 PCT/CN2022/093714 CN2022093714W WO2023206659A1 WO 2023206659 A1 WO2023206659 A1 WO 2023206659A1 CN 2022093714 W CN2022093714 W CN 2022093714W WO 2023206659 A1 WO2023206659 A1 WO 2023206659A1
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Prior art keywords
signal
test
clock
circuit
output
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PCT/CN2022/093714
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English (en)
French (fr)
Inventor
秦建勇
李简妮
刘忠来
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长鑫存储技术有限公司
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Priority to US17/955,670 priority Critical patent/US20230012586A1/en
Publication of WO2023206659A1 publication Critical patent/WO2023206659A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
    • G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
    • G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of semiconductor circuit design, and in particular to a signal detection system and a memory detection method.
  • the memory's data processing uses clock signals, and the transmission frequency of the clock signal determines the number of operations the memory performs in the same time, which determines how fast the memory processes data; that is, the memory processes data based on high-speed clock signals.
  • the performance improvement of memory is of great significance.
  • Embodiments of the present disclosure provide a signal detection system, applied to a memory, for performing duty cycle testing on the output signals of each test path in the memory according to the test circuit in the memory, including: a signal generator, generating a reference based on external parameters Test signal, the reference test signal is a clock signal that meets the preset duty cycle; perform a duty cycle test on the reference test signal based on the test circuit to determine whether the function of the test circuit is normal; if the function of the test circuit is normal, based on the test control signal Different test modules are selected in turn, and the duty cycle test is performed on the signal output by the selected test module based on the test circuit; the test module includes: a signal conversion module and a write clock path; among which, the signal conversion module is used to generate a signal based on the reference test signal Internal clock signal; the write clock path includes: write divider, write clock tree and signal loading circuit; the write divider is used to generate a parallel write clock based on the internal clock signal, and the write clock tree is used to adjust the delay of
  • Figure 1 is a schematic structural diagram of a signal detection system provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a signal generator provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a ring oscillator provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of a tetrahedral oscillator provided by an embodiment of the present disclosure
  • Figure 5 is a schematic structural diagram of a duty cycle correction module provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of the correction principle of the first adjustment unit and the second adjustment unit provided by an embodiment of the present disclosure
  • Figure 7 is a schematic structural diagram of the first adjustment unit and the second adjustment unit provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of a correction unit provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of the correction principle of the correction unit provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of an amplitude adjustment module provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic diagram of the adjustment principle of the amplitude adjustment module provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram of a test circuit provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic structural diagram of a first integrating circuit and a second integrating circuit provided by an embodiment of the present disclosure
  • Figure 14 is a schematic structural diagram of a comparison circuit provided by an embodiment of the present disclosure.
  • Figure 15 is a schematic structural diagram of a pre-stored circuit provided by an embodiment of the present disclosure.
  • Figure 16 is a schematic diagram of the control logic of a control module provided by an embodiment of the present disclosure.
  • Figure 17 is a schematic structural diagram of a control module provided by an embodiment of the present disclosure.
  • Figure 18 is a schematic structural diagram of a clock generation circuit provided by an embodiment of the present disclosure.
  • Figure 19 is a timing diagram of a four-phase signal provided by an embodiment of the present disclosure.
  • Figure 20 is a timing diagram for generating equidistant four-phase signals according to an embodiment of the present disclosure
  • Figure 21 is a schematic structural diagram of a selection module provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a signal detection system that selects different test paths to test whether the duty cycles of high-speed clock signals in different transmission paths meet the requirements to ensure the stability of memory data processing.
  • the signal detection system 1000 is applied to the memory and is used to perform duty cycle testing on the output signals of each test path in the memory according to the test circuit in the memory.
  • a signal detection system 1000 includes:
  • the signal generator 100 generates a reference test signal AltWck based on external parameters.
  • the reference test signal AltWck is a clock signal that satisfies a preset duty cycle.
  • the duty cycle test of the reference test signal AltWck is performed based on the test circuit 400 to determine whether the function of the test circuit 400 is normal; if the function of the test circuit 400 is normal, different test modules are selected in sequence based on the test control signal DcmCtrl, and based on the test circuit 400 The signal output by the selected test module is tested for duty cycle.
  • the test module includes: signal conversion module 1002 and write clock path 1003.
  • the signal conversion module 1002 is used to generate the internal clock signal PWCK according to the reference test signal AltWck;
  • the write clock path 1003 includes: write divider 1013, write clock tree 1023 and Signal loading circuit 805, write divider 1013 is used to generate a parallel write clock Clk_W according to the internal clock signal PWCK, write clock tree 1023, the input end is connected to the output end of the write divider 1013, used to adjust the delay of the input signal to generate Parallel write clock Clk_W, signal loading circuit 805, the input end is connected to the output end of the write clock tree 1023, the output end is connected to the test circuit 400, used to sample the preset data according to the parallel write clock Clk_W to generate the first indication signal Pup and the second indication signal Pdn.
  • the test circuit 400 performs a duty cycle test on the reference test signal AltWck, where the duty cycle of the reference test signal AltWck is known, which is used to determine whether the duty cycle test function of the test circuit 400 is normal. If the duty cycle of the test circuit 400 If the test function is normal, then select different test modules based on the test control signal DcmCtrl, and test the duty ratios of the output signals of the different test modules in sequence through the test circuit 400 to test whether the duty ratios of the signals output by the different test modules are normal, thereby Complete functional testing of different test modules.
  • the test module also includes: a read clock path 1004.
  • the read clock path 1004 includes: a read frequency divider 1014 and a read clock conversion circuit 1024.
  • the read frequency divider 1014 is used to adjust the internal clock signal according to the internal clock signal.
  • PWCK generates a parallel read clock Clk_R1
  • the read clock conversion circuit 1024 is used to generate a serial read clock Clk_R2 according to the parallel read clock Clk_R1.
  • the write divider 1013 and the read divider 1014 in the memory can be implemented based on one divider.
  • the signal generator 100 includes:
  • the oscillation generation module 101 is configured to generate an initial oscillation signal Osc0 based on the oscillation control signal OscAdj, and the oscillation control signal OscAdj is used to adjust the frequency of the generated initial oscillation signal Osc0.
  • the duty cycle correction module 102 is connected to the output end of the oscillation generation module 101.
  • the duty cycle correction module 102 is configured to: adjust the duty cycle of the initial oscillation signal Osc0 based on the duty cycle control signal Duty to generate an intermediate test signal. Pretest.
  • the amplitude adjustment module 103 is connected to the output end of the duty cycle correction module 102.
  • the amplitude adjustment module 103 is configured to adjust the amplitude of the intermediate test signal Pretest based on the amplitude adjustment signal OBControl to generate the reference test signal AltWck.
  • the oscillation generation module 101 includes a ring oscillator, the ring oscillator is used to generate an initial oscillation signal Osc0 according to the oscillation control signal OscAdj, and the oscillation control signal OscAdj is used to adjust the interface.
  • number of inverters into the ring oscillator It can be understood that the number of inverters connected to the ring oscillator is related to the oscillation frequency of the initial oscillation signal Osc0. Specifically, the greater the number of inverters connected to the ring oscillator, the oscillation frequency of the initial oscillation signal Osc0 The lower.
  • the oscillation generation module 101 includes a tetrahedral oscillator, and the tetrahedral oscillator includes an inner ring inverter and an outer ring inverter, wherein the outer ring inverter has the same driving capability, and the inner ring inverter has the same driving capability.
  • the driving capabilities of the ring inverters are the same, and the driving capability of the inner ring inverter is 0.3 to 0.8 times that of the outer ring inverter.
  • the tetrahedral oscillator is used to generate the initial oscillation signal Osc0 according to the oscillation control signal OscAdj, and the oscillation control signal OscAdj is used to adjust the driving capability of the inner ring inverter; in one example, the oscillation control signal OscAdj is used It is used to adjust the driving capability of the transistors constituting the inner ring inverter to adjust the driving capability of the inner ring inverter.
  • the stronger the driving capability of the inner ring inverter in the tetrahedral oscillator the smaller the delay caused by the inverter, and the greater the frequency of the initial oscillation signal Osc0 generated by the oscillation generation module 101; in In practical applications, the frequency of the initial oscillation signal Osc0 generated by the oscillation generation module 101 can be controlled by changing the ratio of the driving capability of the inner ring inverter to the driving capability of the outer ring inverter.
  • the driving capability of the inner ring inverter can be set to 0.4 times, 0.5 times, 0.6 times or 0.7 times the driving capability of the outer ring inverter; preferably, the driving capability of the inner ring inverter is set to 0.4 times, 0.5 times, 0.6 times or 0.7 times that of the outer ring inverter.
  • the inverter driving capability is 0.7 times to increase the frequency of the initial oscillation signal Osc0 generated by the oscillation generation module 101.
  • the outer ring inverter includes: first inverter 1, second inverter 2, third inverter 3 and fourth inverter 4; the inner ring inverter includes: Fifth inverter 5, sixth inverter 6, seventh inverter 7 and eighth inverter 8.
  • the output terminal of the first inverter 1 is connected to the input terminal of the second inverter 2; the output terminal of the second inverter 2 is connected to the input terminal of the third inverter 3; the output terminal of the third inverter 3
  • the input terminal of the fourth inverter 4 is connected to the input terminal of the fourth inverter 4; the output terminal of the fourth inverter 4 is connected to the input terminal of the first inverter 1; the input terminal of the fifth inverter 5 is connected to the output of the first inverter 1 terminal, the output terminal is connected to the input terminal of the fourth inverter 4; the input terminal of the sixth inverter 6 is connected to the output terminal of the second inverter 2, and the output terminal is connected to the input terminal of the first inverter 1; the seventh The input terminal of the inverter 7 is connected to the output terminal of the third inverter 3, and the output terminal is connected to the input terminal of the second inverter 2; the input terminal of the eighth inverter 8 is connected to the output terminal of the fourth inverter
  • the duty cycle correction module 102 includes: a first adjustment unit 112, connected to the oscillation generation module 101, and the first adjustment unit 112 is configured to increase the duty of the initial oscillation signal Osc0. to generate the first adjustment signal T1.
  • the second adjustment unit 122 is connected to the oscillation generation module 101.
  • the second adjustment unit 122 is configured to reduce the duty cycle of the initial oscillation signal Osc0 to generate the second adjustment signal T2.
  • the correction unit 132 is connected to the first adjustment unit 112 and the second adjustment unit 122.
  • the correction unit 132 is configured to generate the intermediate test signal Pretest according to the duty cycle control signal Duty, the first adjustment signal T1 and the second adjustment signal T2;
  • the duty cycle control signal Duty is used to adjust the signal proportion of the first adjustment signal T1 and the signal proportion of the second adjustment signal T2 in the generated intermediate test signal Pretest.
  • the first adjustment unit T1 and the second adjustment unit T2 adjust the duty cycle of the signal by delaying the rising edge and falling edge of the signal to varying degrees.
  • Ratio for example, the delay for the rising edge of the initial signal is t1, and the delay for the falling edge of the initial signal is t2; when t1>t2, the distance from the rising edge to the falling edge of the delayed signal is shortened, and the duty cycle of the signal is ratio decreases, when t1 ⁇ t2, the distance from the rising edge to the falling edge of the delayed signal is extended, and the duty cycle of the signal increases.
  • the first adjustment unit 112 includes: a first switch P tube ⁇ KP1>, a first switch N tube ⁇ KN1>, a second switch P tube ⁇ KP2> and a second switch N tube ⁇ KN2>.
  • the gate of the first switch P tube ⁇ KP1> is connected to the gate of the first switch N tube ⁇ KN1> for receiving the initial oscillation signal Osc0, and the source of the first switch P tube ⁇ KP1> is connected to the first
  • the drain of the pull-up transistor ⁇ LP1>, the source of the first pull-up transistor ⁇ LP1> is used to receive the high level
  • the source of the first switch N tube ⁇ KN1> is connected to the drain of the first pull-down transistor ⁇ LN1>
  • the source of the first pull-down transistor ⁇ LN1> is used to receive the low level
  • the drain of the first switch P tube ⁇ KP1> is connected to the drain of the first switch N tube ⁇ KN1>, and is connected to the second switch P tube
  • the gate of ⁇ KP2> and the gate of the second switch N tube ⁇ KN2>, the source of the second switch P tube ⁇ KP2> are connected to the drain of the second pull-up transistor
  • the first pull-up transistor ⁇ LP1> and the first pull-down transistor ⁇ LN1> are turned on based on the duty cycle control signal Duty, and the driving capability of the first pull-down transistor ⁇ LN1> is greater than that of the first pull-up transistor ⁇ LP1> capability; the second pull-up transistor ⁇ LP2> and the second pull-down transistor ⁇ LN2> are turned on based on the duty cycle control signal Duty, and the driving capability of the second pull-down transistor ⁇ LN2> is less than that of the second pull-up transistor ⁇ LP2> ability.
  • the second adjustment unit 122 includes: a third switch P tube ⁇ KP3>, a third switch N tube ⁇ KN3>, a fourth switch P tube ⁇ KP4>, and a fourth switch N tube ⁇ KN4>.
  • the gate of the third switch P tube ⁇ KP3> is connected to the gate of the third switch N tube ⁇ KN3> for receiving the initial oscillation signal Osc0
  • the source of the third switch P tube ⁇ KP3> is connected to the third on The drain of the pull-up transistor ⁇ LP3>
  • the source of the third pull-up transistor ⁇ LP3> is used to receive the high level
  • the source of the third switch N tube ⁇ KN3> is connected to the drain of the third pull-down transistor ⁇ LN3>
  • the source of the third pull-down transistor ⁇ LN3> is used to receive a low level.
  • the drain of the third switch P tube ⁇ KP3> is connected to the drain of the third switch N tube ⁇ KN3> and connected to the fourth switch P tube ⁇ KP4 >
  • the gate and the gate of the fourth switch N tube ⁇ KN4>, the source of the fourth switch P tube ⁇ KP4> are connected to the drain of the fourth pull-up transistor ⁇ LP4>, and the source of the fourth pull-up transistor ⁇ LP4>
  • the source electrode of the fourth switch N tube ⁇ KN4> is connected to the drain electrode of the fourth pull-down transistor ⁇ LN4>, and the source electrode of the fourth pull-down transistor ⁇ LN4> is used to receive a low level.
  • the drain of the switch P tube ⁇ KP4> is connected to the drain of the fourth switch N tube ⁇ KN4> for outputting the second adjustment signal T2.
  • the third pull-up transistor ⁇ LP3> and the third pull-down transistor ⁇ LN3> are turned on based on the duty cycle control signal Duty, and the driving capability of the third pull-down transistor ⁇ LN3> is greater than the driving capability of the third pull-up transistor ⁇ LP3>;
  • the fourth pull-up transistor ⁇ LP4> and the fourth pull-down transistor ⁇ LN4> are turned on based on the duty cycle control signal Duty, and the driving capability of the fourth pull-down transistor ⁇ LN4> is smaller than the driving capability of the fourth pull-up transistor ⁇ LP4>.
  • the three pull-down transistors ⁇ LN3>, the fourth pull-up transistor ⁇ LP4> and the fourth pull-down transistor ⁇ LN4> can be turned on directly according to the duty cycle control signal Duty, or they can be turned on according to the duty cycle enable signal.
  • the duty cycle The enable signal is generated based on the duty cycle control signal Duty.
  • the first adjustment signal T1 is easily pulled up and difficult to be pulled down; therefore, the first adjustment signal T1 Compared with the initial oscillation signal Osc0, the adjustment signal T1 has a smaller rising edge delay and a larger falling edge delay.
  • the second adjustment signal T2 is easily pulled down and difficult to be pulled up; therefore, the second adjustment signal T2 Compared with the initial oscillation signal Osc0, the adjustment signal T2 has a larger rising edge delay and a smaller falling edge delay.
  • the driving capability of the first pull-up transistor ⁇ LP1>, the driving capability of the second pull-down transistor ⁇ LN2>, the driving capability of the third pull-down transistor ⁇ LN3> and the driving capability of the fourth pull-up transistor ⁇ LP4> The capabilities are the same; the driving capabilities of the first pull-down transistor ⁇ LN1>, the driving capabilities of the second pull-up transistor ⁇ LP2>, the driving capabilities of the third pull-up transistor ⁇ LP3> and the driving capabilities of the fourth pull-down transistor ⁇ LN4> are the same .
  • the driving capabilities of the first pull-up transistor ⁇ LP1>, the driving capabilities of the second pull-down transistor ⁇ LN2>, the driving capabilities of the third pull-down transistor ⁇ LN3> and the fourth pull-up transistor ⁇ LP4> The driving capability of The driving ability is A; among them, the driving ability represented by A is greater than the driving ability represented by B.
  • the driving capability of the first pull-up transistor ⁇ LP1>, the driving capability of the second pull-down transistor ⁇ LN2>, the driving capability of the third pull-down transistor ⁇ LN3> and the driving capability of the fourth pull-up transistor ⁇ LP4> are the same, and Set the driving capability of the first pull-down transistor ⁇ LN1>, the driving capability of the second pull-up transistor ⁇ LP2>, the driving capability of the third pull-up transistor ⁇ LP3> and the driving capability of the fourth pull-down transistor ⁇ LN4> to be the same, by The same transistor controls the first adjustment unit 112 to have the same adjustment capability for the rising edge and the second adjustment unit 122 to adjust the falling edge.
  • the same transistor controls the first adjustment unit 112 to adjust the falling edge capability and the second adjustment unit 122 to adjust the rising edge.
  • the adjustment capabilities are the same, so that the total adjustment delay of the first adjustment unit 112 for the rising edge and the falling edge is consistent with the total delay of the second adjustment unit 122 for the rising edge and the falling edge, so as to ensure that the first adjustment signal T1 and the first adjustment signal T1 are the same.
  • the two adjustment signals T2 have the same period, which facilitates the correction module 132 to adjust the duty cycle according to the first adjustment signal T1 and the second adjustment signal T2.
  • the first adjustment unit 112 and the second adjustment unit 122 further include a correction tube set 142 .
  • the correction tube group 142 includes: x correction transistors arranged in parallel.
  • the driving capability of the n-th correction transistor is twice that of the n-1th correction transistor, where x is greater than or equal to 2 n is an integer less than or equal to Capability refers to the equivalent drive capability of multiple correction transistors that are turned on.
  • the correction tube group 142 is respectively connected with the first pull-up transistor ⁇ LP1>, the first pull-down transistor ⁇ LN1>, the second pull-up transistor ⁇ LP2>, the second pull-down transistor ⁇ LN2>, and the third pull-up transistor ⁇ LP3 >, the third pull-down transistor ⁇ LN3>, the fourth pull-up transistor ⁇ LP4> and the fourth pull-down transistor ⁇ LN4> are arranged in parallel, and the type of the correction transistor in the correction tube group 142 is the same as the type of the parallel-connected transistor.
  • the type of the correction transistor in the correction tube group 142 is the same as the type of the parallel-connected transistor.
  • the correction transistor group 142 includes a first correction transistor, a second correction transistor, a third correction transistor, a fourth correction transistor and a fifth correction transistor; wherein, the driver of the first correction transistor The driving capability of the second correction transistor is C, the driving capability of the second correction transistor is 2C, the driving capability of the third correction transistor is 4C, the driving capability of the fourth correction transistor is 8C, and the driving capability of the fifth correction transistor is 16C; the first driving transistor, The second driving transistor, the third driving transistor, the fourth driving transistor and the fifth driving transistor are selectively turned on based on the duty cycle control signal Duty, thereby controlling the first adjustment unit 112 and the second adjustment unit 122 to perform the initial oscillation signal Osc0 Different degrees of signal delay.
  • the "C" mentioned above represents a preset unit value, which can be designed accordingly according to the circuit design in specific applications.
  • the above description is only to reflect the multiple relationship between the driving capabilities of the correction transistors.
  • the plurality of correction transistors in the correction tube group 142 are arranged in parallel.
  • the plurality of correction transistors in the correction tube group can also be arranged in series, or in a series+parallel combination. form settings.
  • the correction unit 132 includes: a plurality of first driving sub-units arranged in parallel with each other, the input end is connected to the first adjustment unit 112, and is also used to receive the duty cycle control signal Duty; A plurality of second driving sub-units are provided, the input end is connected to the second adjustment unit 122, and is also used to receive the duty cycle control signal Duty; wherein the duty cycle control signal Duty is used to control the plurality of first driving sub-units.
  • the third driving sub-unit 213 has an input terminal connected to the output terminal of the first driving sub-unit and the output terminal of the second driving sub-unit, and the output terminal is used to output the intermediate test signal Pretest .
  • the duty cycle of the intermediate test signal Pretest output by the third driving sub-unit 213 is more biased towards the first adjustment signal.
  • the first adjustment signal T1 accounts for a larger proportion; when the driving capabilities of the multiple second driving sub-units are greater than the multiple first The driving capability of the driving sub-unit, through the duty cycle of the intermediate test signal Pretest output by the third driving sub-unit 213, is more biased towards the second adjustment signal T2, that is, the intermediate test generated according to the first adjustment signal T1 and the second adjustment signal T2 In the signal Pretest, the second adjustment signal T2 accounts for a larger proportion.
  • the driving capabilities of the plurality of first driving sub-units refer to the equivalent driving capabilities of the turned-on first driving sub-units among the plurality of first driving sub-units.
  • the driving capabilities of the plurality of second driving sub-units are The driving capability of a subunit refers to the equivalent driving capability of the turned-on second driving subunit among the plurality of second driving subunits.
  • the signal generator 100 includes: a first inverter group 211 for receiving the duty cycle control signal Duty; the first inverter group 211 includes a plurality of first inverters connected in parallel. Adjusting the inverter 201, each first adjusting inverter 201 serves as a first driving sub-unit, and the duty cycle control signal Duty is used to select the first adjusting inverter 201 in the first inverter group 211. conduction.
  • the second inverter group 212 has an input end connected to the second adjustment unit 122 and is also used to receive the duty cycle control signal Duty; the second inverter group 212 includes a plurality of second adjustment inverters 202 connected in parallel, each A second regulating inverter 202 serves as a second driving subunit, and the duty cycle control signal Duty is used to selectively conduct the second regulating inverter 202 in the second inverter group 212 .
  • the third driving subunit 213 includes: a third regulating inverter 203, the input terminals are respectively connected to the output terminals of the first inverter group 211 and the output terminals of the second inverter group 212, and the output terminals are used to output intermediate test signals. Pretest.
  • the first inverter group 211 includes a plurality of first inverters 201 connected in parallel
  • the second inverter group 212 includes a plurality of second inverters 202 connected in parallel
  • each of the parallel inverters is turned on.
  • the correction unit includes three first driving sub-units and three second driving sub-units.
  • the conduction situation of the first driving sub-unit and the second driving sub-unit can be divided into: (1) 3 conduction The first drive sub-unit and 0 second drive sub-units.
  • the duty cycle of the intermediate test signal Pretest and the first adjustment signal T1 is the same, and the duration of the high-level signal is tpH3; (2) Turn on the 2 first drive sub-units. Drive sub-unit and 1 second drive sub-unit.
  • the intermediate test signal Pretest is biased towards the first adjustment signal T1, and the duration of the high-level signal is tpH2; (3) Turn on 1 first drive sub-unit and 2 The second drive sub-unit, at this time, the intermediate test signal Pretest is biased towards the second adjustment signal T2, and the duration of the high-level signal is tpH1; (4) Turn on 0 first drive sub-units and 3 second drive sub-units, At this time, the duty cycle of the intermediate test signal Pretest and the second adjustment signal T2 are the same, and the duration of the high-level signal is tpH0.
  • the amplitude adjustment module 103 includes: a first signal generation unit 113 configured to pull up the output signal based on the intermediate test signal Pretest, and pull down the output signal based on the inverted test signal Pretest, to Generate a reference test signal AltWck with the same phase as the intermediate test signal Pretest.
  • the second signal generation unit 123 is configured to pull up the output signal based on the inverted test signal Pretest- and pull down the output signal based on the intermediate test signal Pretest to generate the inverted reference test signal AltWck with the same phase as the inverted test signal Pretest-. -.
  • the intermediate test signal Pretest and the inverted test signal Pretest have the same amplitude and opposite phase.
  • the gate of the first driver tube ⁇ QN1> is used to receive the intermediate test signal Pretest
  • the drain is used to receive the high level
  • the gate of the second driver tube ⁇ QN2> is used to receive the inverted test signal Pretest-.
  • the source is used to receive a low level
  • the source of the first driver tube ⁇ QN1> is connected to the drain of the second driver tube ⁇ QN2> for outputting the reference test signal AltWck.
  • the amplitude control signal OBControl is used to adjust the driving capability of the first driving tube ⁇ QN1>.
  • the amplitude control signal OBControl changes the driving capability of the first signal generating unit 113 by adjusting the driving capability of the first driving tube ⁇ QN1>; in other embodiments, it can be set to amplitude control
  • the signal changes the driving capability of the first signal generating unit by adjusting the driving capability of the second driving tube or jointly adjusting the first driving tube and the second driving tube.
  • the second signal generating unit 123 includes: a third drive tube and a fourth drive tube.
  • the gate of the third driver tube ⁇ QN3> is used to receive the intermediate test signal Pretest, and the drain is used to receive the high level.
  • the gate of the fourth driver tube ⁇ QN4> is used to receive the inverted test signal Pretest-, and the source is used to receive the high level.
  • the source of the third driver tube ⁇ QN3> is connected to the drain of the fourth driver tube ⁇ QN4> for outputting the inverted reference test signal AltWck-.
  • the amplitude control signal OBControl is used to adjust the driving capability of the third driving tube ⁇ QN3>.
  • the amplitude control signal OBControl changes the driving capability of the second signal generating unit 123 by adjusting the driving capability of the third driving tube ⁇ QN3>; in other embodiments, it can be set to amplitude control
  • the signal changes the driving capability of the second signal generating unit by adjusting the driving capability of the fourth driving tube or jointly adjusting the third driving tube and the fourth driving tube.
  • the amplitude control signal OBControl can adjust the first driving tube ⁇ QN1> and the third driving tube by changing the aspect ratio or the substrate voltage of the first driving tube ⁇ QN1> and the third driving tube ⁇ QN3>
  • the driving capabilities of ⁇ QN3> similarly, the driving capabilities of the second drive tube and the fourth drive tube can be adjusted in a similar way.
  • the first signal generating unit 113 also includes: a first switching transistor ⁇ B1>, a second switching transistor ⁇ B2>, and a first anti-interference transistor ⁇ B3>.
  • the source of the first switching transistor ⁇ B1> is coupled to the power node and the drain is connected to the drain of the first driving tube ⁇ QN1>.
  • the gate is used to receive the amplitude control signal OBControl.
  • the source of the second switching transistor ⁇ B2> is coupled to the ground. line node, the drain is connected to the drain of the second drive tube ⁇ QN2>, and the gate is used to receive the amplitude control signal OBControl, so as to be turned on after receiving the amplitude control signal OBControl, thereby reducing the idle time of the first signal generation unit 113 power consumption;
  • the first anti-interference transistor ⁇ B3> is connected in parallel with the second drive tube ⁇ QN2>, and the gate is used to receive the amplitude control signal OBControl.
  • the amplitude control signal OBControl is also used to adjust the driving capability of the first anti-interference transistor ⁇ B3>, thereby adjusting the anti-interference capability of the first anti-interference transistor ⁇ B3>. Since the driving capability of the first driving tube ⁇ QN1> can be adjusted based on the amplitude control signal OBControl, that is, when the driving capability of the first driving tube ⁇ QN1> is large, the amplitude of the output reference test signal AltWck is larger, and anti-interference is required.
  • the first anti-interference transistor is adjusted accordingly through the amplitude control signal OBControl ⁇ B3>'s anti-interference capability to ensure the accuracy of the reference test signal AltWck generated by the first signal generation unit 113 and reduce the power consumption of the first anti-interference transistor ⁇ B3>.
  • the amplitude control signal OBControl is also used to enable the first switching transistor ⁇ B1>, the second switching transistor ⁇ B2> and the first anti-interference transistor ⁇ B3>, and simultaneously adjust the first anti-interference transistor ⁇ B3 >Driving capability; in other embodiments, it can be configured that the first switching transistor, the second switching transistor and the first anti-interference transistor are turned on based on the amplitude enable signal, where the amplitude enable signal is generated based on the amplitude control signal.
  • the second signal generating unit 123 also includes: a third switching transistor ⁇ B4>, a fourth switching transistor ⁇ B5>, and a second anti-interference transistor ⁇ B6>.
  • the source electrode of the third switching transistor ⁇ B4> is coupled to the power node and the drain electrode is connected to the drain electrode of the fourth driver tube ⁇ QN4>.
  • the gate electrode is used to receive the amplitude control signal OBControl.
  • the source electrode of the fourth switching transistor ⁇ B5> is coupled to the ground.
  • the drain is connected to the drain of the fifth drive tube ⁇ QN5>, and the gate is used to receive the amplitude control signal OBControl, so as to be turned on after receiving the amplitude control signal OBControl, thereby reducing the idle time of the second signal generation unit 123 power consumption;
  • the second anti-interference transistor ⁇ B6> is connected in parallel with the fifth drive tube ⁇ QN5>, and the gate is used to receive the amplitude control signal OBControl.
  • the amplitude control signal OBControl is also used to adjust the driving capability of the second anti-interference transistor ⁇ B6>, thereby adjusting the anti-interference capability of the second anti-interference transistor ⁇ B6>.
  • the driving capability of the third driving tube ⁇ QN3> can be adjusted based on the amplitude control signal OBControl, that is, when the driving capability of the third driving tube ⁇ QN3> is large, the amplitude of the output inverted reference test signal AltWck- is larger, and the required The anti-interference ability is strong; when the driving ability of the third drive tube ⁇ QN3> is small, the amplitude of the output inverted reference test signal AltWck- is small, and the required anti-interference ability is weak; therefore, the amplitude control signal OBControl is used accordingly
  • the anti-interference capability of the second anti-interference transistor ⁇ B6> is adjusted to ensure the accuracy of the inverted reference test signal AltWck- generated by the second signal generation unit 123 and to reduce the power consumption of the second anti-interference transistor ⁇ B6>.
  • the amplitude control signal OBControl is also used to enable the third switching transistor ⁇ B4>, the fourth switching transistor ⁇ B5> and the second anti-interference transistor ⁇ B6>, and simultaneously adjust the second anti-interference transistor ⁇ B6 >Driving capability; in other embodiments, it may be configured that the third switching transistor, the fourth switching transistor and the second anti-interference transistor are turned on based on the amplitude enable signal, where the amplitude enable signal is generated based on the amplitude control signal. It should be noted that this embodiment uses the first signal generation unit 113 to generate the reference test signal AltWck and the second signal generation unit 123 to generate the inverted reference test signal AltWck- as an example for detailed description, which does not constitute a limitation on this embodiment. In other embodiments, it may be configured that the first signal generating unit generates the inverted test signal, and the second signal generating unit generates the test signal.
  • the amplitude adjustment module 103 also includes: a signal generation unit 300, which is connected to the amplitude adjustment module 103 and the duty cycle correction module 102, and is configured to generate the inverted test signal Pretest- based on the intermediate test signal Pretest.
  • the first signal generating unit 113 includes: a first drive tube ⁇ QN1> and a second drive tube ⁇ QN2>.
  • the amplitude control signal OBControl is also used to control the input of the intermediate test signal Pretest and the inverted test signal Pretest-.
  • the signal generator 100 also includes: a first driving unit 301 and a second Drive unit 302.
  • the first driving unit 301 is used to receive the amplitude control signal OBControl and the intermediate test signal Pretest.
  • the first driving unit 301 is configured to output the intermediate test signal Pretest or the inverted test if the amplitude control signal OBControl and the intermediate test signal Pretest are received at the same time.
  • One of the signals Pretest-; the second driving unit 302 is used to receive the amplitude control signal OBControl and the inverted test signal Pretest-.
  • the second driving unit 302 is configured to, if the amplitude control signal OBControl and the inverted test signal are received simultaneously Pretest-, outputs the other of the intermediate test signal Pretest or the inverted test signal Pretest-. Specifically, if the first driving unit 301 is based on the NAND gate design, if it receives the amplitude control signal OBControl and the intermediate test signal Pretest at the same time, it will output the inverted test signal Pretest-; if the first driving unit 301 is based on the AND gate design, At this time, if the amplitude control signal OBControl and the intermediate test signal Pretest are received at the same time, the intermediate test signal Pretest is output; if the second driving unit 302 is based on a NAND gate design, if the amplitude control signal OBControl and the inverted test signal Pretest are received at the same time, -, output the intermediate test signal Pretest; if the second driving unit 302 is based on the AND gate design, if it receives the amplitude control signal
  • the amplitude control signal OBControl is also used to enable the first driving unit 301 and the second driving unit 302; in other embodiments, it can be set that the first driving unit and the driving unit are based on the amplitude.
  • the enable signal is turned on, wherein the amplitude enable signal is generated based on the amplitude control signal.
  • the amplitude adjustment module 103 also includes: a first input adjustment unit 310, a second input adjustment unit 320, and a third input adjustment unit. 330 and the fourth input adjustment unit 340.
  • the first input adjustment unit 310 is connected to the first signal generation unit 113 and is configured to drive the intermediate test signal Pretest provided to the first signal generation unit 113
  • the second input adjustment unit 320 is connected to the second signal generation unit 123 , is configured to drive the intermediate test signal Pretest provided to the second signal generation unit 123
  • the third input adjustment unit 330 is connected to the first signal generation unit 113, and is configured to drive the inverse test signal Pretest provided to the first signal generation unit 113.
  • the fourth input adjustment unit 340 is connected to the second signal generation unit 123 and is configured to drive the inverted test signal Pretest- provided to the second signal generation unit 123.
  • the first input adjustment unit 310 , the second input adjustment unit 320 , the third input adjustment unit 330 and the fourth input adjustment unit 340 include an even number of inverters.
  • the first input adjustment unit 310 , the second input adjustment unit 320 , the third input adjustment unit 330 and the fourth input adjustment unit 340 include an odd number of inverters.
  • the first input adjustment unit 310 uses In order to provide the inverted test signal Pretest- to the first signal generating unit 113; the second input adjustment unit 320 is used to provide the inverted test signal Pretest- to the second signal generating unit 123; and the third input adjustment unit 330 is used to provide the inverted test signal Pretest- to the first signal generating unit 113.
  • the signal generation unit 113 provides the intermediate test signal Pretest; the fourth input adjustment unit 340 is used to provide the intermediate test signal Pretest to the second signal generation unit 123 .
  • the intermediate test signal Pretest and the inverted test signal Pretest- generate the test signal AltWck and the inverted reference test signal AltWck- after passing through the amplitude adjustment module 103.
  • the phases are the same, and the amplitude is changed from V1 to V2 to meet the subsequent requirements. Usage requirements.
  • the first integration circuit 401 used to receive the first test signal Test1 is configured to integrate the first test signal Test1 to output the first integrated signal FltNdT.
  • the second integrating circuit 402 is used to receive the second test signal Test2 and is configured to integrate the second test signal Test2 to output the second integrated signal FltNdC.
  • the first test signal Test1 is the signal to be tested input to the test circuit 400.
  • the first test signal Test1 and the second test signal Test2 are inverse signals of each other.
  • the voltage value of the first integrated signal FltNdT is the voltage value of the first test signal Test1.
  • the comparison circuit 403 has one input end connected to the first integration circuit 401 and the other input end connected to the second integration circuit 402; the comparison circuit 403 is configured to compare the magnitudes of the first integration signal FltNdT and the second integration signal FltNdC. When the integrated signal FltNdT is greater than the second integrated signal FltNdC, a high-level signal is output, and when the second integrated signal FltNdC is greater than the first integrated signal FltNdT, a low-level signal is output.
  • the first integration circuit 401 includes: a first filtering unit 501 , a first preprocessing unit 510 and a second preprocessing unit 520 .
  • the first filtering unit 501 is used to integrate the received signal, that is, the first filtering unit 501 is used to integrate the first test signal Test1.
  • the first preprocessing unit 510 includes: a first pass transistor ⁇ DT1>, a first precharge P transistor ⁇ YP1>, and a first precharge N transistor ⁇ YN1>.
  • the drain of the first pass transistor ⁇ DT1> is used to receive the first test signal Test1, the source is connected to the input end of the first filter unit 501, and the gate is used to receive the first switching signal PassA; the first precharge P tube ⁇ The source of YP1> is used to receive a high level, the drain is connected to the input end of the first filter unit 501, and the gate is used to receive the integral charging signal ClampF; the source of the first precharge N tube ⁇ YN1> is used to receive a low level. level, the drain is connected to the input end of the first filter unit 501, and the gate is used to receive the first integrated discharge signal ClpGnd. Specifically, the first switch signal PassA is used to start the first pre-processing unit 510.
  • the first filter unit 501 receives the first test signal Test1 and starts to The first test signal Test1 is integrated; the first precharge P tube ⁇ YP1> is turned on based on the integrated charging signal ClampF, thereby indirectly connecting the input end of the first filter unit 501 to a high level, thereby pulling up the first filter unit 501 The potential of the input terminal; the first precharge N tube ⁇ YN1> is turned on based on the first integrated discharge signal ClpGnd, thereby indirectly connecting the input terminal of the first filter unit 501 to a low level, thereby pulling down the input of the first filter unit 501 terminal potential.
  • the second preprocessing unit 520 includes: a second pass transistor ⁇ DT2>, a second precharge P transistor ⁇ YP2>, and a second precharge N transistor ⁇ YN2>.
  • the drain of the second pass transistor ⁇ DT2> is connected to the output end of the first filter unit 501, the source is used to output the first integrated signal FltNdT, and the gate is used to receive the second switching signal PassB; the second precharge P tube ⁇
  • the source of YP2> is used to receive a high level, the drain is connected to the output end of the first filter unit 501, and the gate is used to receive the integrated charging signal ClampF; the drain of the second precharge N tube ⁇ YN2> is used to receive a low level.
  • the drain is connected to the input end of the first filter unit 501, and the gate is used to receive the first integrated discharge signal ClpGnd.
  • the second switch signal PassB is used to start the second preprocessing unit 520.
  • the second switch signal PassB turns on the second pass transistor ⁇ DT2>
  • the first integrated signal FltNdT obtained by integrating the first filter unit 501 can be Output to the comparison circuit 403;
  • the second precharge P tube ⁇ YP2> is turned on based on the integrated charging signal ClampF, thereby indirectly connecting the output end of the first filter unit 501 to a high level, thereby pulling up the output end of the first filter unit 501.
  • the second integration circuit 402 includes: a second filtering unit 502, a third preprocessing unit 530 and a fourth preprocessing unit 540.
  • the second filtering unit 502 is used to integrate the received signal, that is, the second filtering unit 502 is used to integrate the second test signal Test2.
  • the third preprocessing unit 530 includes: a third pass transistor ⁇ DT3>, a third precharge P transistor ⁇ YP3>, and a third precharge N transistor ⁇ YN3>.
  • the drain of the third pass transistor ⁇ DT3> is used to receive the second test signal Test2, the source is connected to the input end of the second filter unit 502, and the gate is used to receive the first switch signal PassA; the third precharge P tube ⁇
  • the source of YP3> is connected to the gate, and is used to receive a high level, and the drain is connected to the input end of the second filter unit 502; the source of the third precharge N tube ⁇ YN3> is used to receive a low level, and the drain is connected to the input end of the second filter unit 502.
  • the pole is connected to the input end of the second filter unit 502, and the gate is used to receive the second integrated discharge signal Clamp.
  • the first switch signal PassA is used to start the third preprocessing unit 530.
  • the second filter unit 502 receives the second test signal Test2 and starts to The second test signal Test2 is integrated; the gate and source of the third precharge P tube ⁇ YP3> receive a high level at the same time, so that the third precharge P tube ⁇ YP3> is in a cut-off state to prevent the high level from affecting the second
  • the potential of the input terminal of the filter unit 502 is pulled high; the third precharge N tube ⁇ YN3> is turned on based on the second integrated discharge signal Clamp, thereby indirectly connecting the input terminal of the second filter unit 502 to a low level, thereby pulling the third precharge N tube ⁇ YN3> low.
  • the fourth preprocessing unit 540 includes: a fourth pass transistor ⁇ DT3>, a fourth precharge P transistor ⁇ YP4>, and a fourth precharge N transistor ⁇ YN4>.
  • the drain of the fourth pass transistor ⁇ DT3> is connected to the output end of the second filter unit 502, the source is used to output the second integral signal FltNdC, the gate is used to receive the second switching signal PassB, and the fourth precharge P transistor ⁇
  • the source of YP4> is connected to the gate, and is used to receive a high level, and the drain is connected to the output end of the second filter unit 502; the source of the fourth precharge N tube ⁇ YN4> is used to receive a low level, and the drain is connected to the output end of the second filter unit 502.
  • the pole is connected to the output end of the second filter unit 502, and the gate is used to receive the second integrated discharge signal Clamp.
  • the second switch signal PassB is used to start the fourth preprocessing unit 540.
  • the second switch signal PassB turns on the fourth pass transistor ⁇ DT3>
  • the second integrated signal FltNdC obtained by integrating the second filtering unit 502 can be Output to the comparison circuit 403;
  • the gate and source of the fourth precharge P tube ⁇ YP4> receive a high level at the same time, making the fourth precharge P tube ⁇ YP4> in a cut-off state to prevent the high level from affecting the second filter unit
  • the potential of the output terminal of 502 is pulled high;
  • the fourth precharge N tube ⁇ YN4> is turned on based on the second integrated discharge signal Clamp, thereby indirectly connecting the output terminal of the second filter unit 502 to a low level, thereby pulling down the second filter
  • the first filtering unit 501 adopts a second-order RC filter setting; correspondingly, the second filtering unit 502 also adopts a second-order RC filter setting.
  • the first filtering unit and the second filtering unit may simultaneously adopt first-order or high-order RC filter settings; accordingly, in some embodiments, the first filtering unit and the second filtering unit
  • the order of the unit's RC filter can also be set to different orders.
  • the test circuit 400 further includes: a first equalization circuit 521 and a second equalization circuit 522 .
  • One end of the first equalization circuit 521 is connected to the input end of the first integrating circuit 401, and the other end is connected to the input end of the second integrating circuit 402; the first equalizing circuit 521 is configured to make the first equalizing circuit 521 based on the first equalizing signal EqA.
  • the input terminals of the integrating circuit 401 and the second integrating circuit 402 have the same voltage; one end of the second equalizing circuit 522 is connected to the output end of the first integrating circuit 401, and the other end is connected to the output end of the second integrating circuit 402; the second equalizing circuit 522 is It is configured to make the initial voltages of the first integrated signal FltNdT and the second integrated signal FltNdC the same based on the second equalized signal EqB.
  • the first balancing circuit 521 includes: a first balancing P tube ⁇ EP1> and a first balancing N tube ⁇ EN1>; wherein, the source of the first balancing P tube ⁇ EP1> and the first balancing N tube
  • the drain of the balanced N-tube ⁇ EN1> is coupled to the input end of the first integrating circuit 401, and the drain of the first balanced P-tube ⁇ EP1> and the source of the first balanced N-tube ⁇ EN1> are coupled to the second integrating circuit 402
  • the input terminals, the gate of the first balancing P tube ⁇ EP1> and the gate of the first balancing N tube ⁇ EN1> are used to receive the first balancing signal EqA.
  • the second balancing circuit 522 includes: a second balancing P tube ⁇ EP2> and a second balancing N tube ⁇ EN2>; wherein, the source of the second balancing P tube ⁇ EP2> and the drain of the second balancing N tube ⁇ EN2> Coupled to the output terminal of the first integrating circuit 401, the drain of the second balanced P tube ⁇ EP2> and the source of the second balanced N tube ⁇ EN2> are coupled to the output terminal of the second integrating circuit 402.
  • the second balanced P tube The gate of ⁇ EP2> and the gate of the second balancing N-tube ⁇ EN2> are used to receive the second balancing signal EqB.
  • One end of the first equalization circuit 521 is connected to the input end of the first filter unit 501, and the other end is connected to the input end of the second filter unit 502; the first equalization circuit 521 is configured to, based on the first equalization signal EqA, make the first filter unit The voltages at the input terminals of 501 and the second filter unit 502 are the same; one end of the second balancing circuit 522 is connected to the drain of the second pass transistor ⁇ DT2>, and the other end is connected to the drain of the fourth pass transistor ⁇ DT4>; the second The equalization circuit 522 is configured to make the initial voltages of the first integrated signal FltNdT and the second integrated signal FltNdC the same based on the second equalized signal EqB.
  • the balancing tubes required to be turned on can be set according to the actual requirements after the test circuit is balanced. For example, if it is required that the input terminals of the first filter unit 501 and the second filter unit 502 be equalized by the first equalization circuit 521 to be at an intermediate level, then the first equalization P tube ⁇ EP1> is used to equalize the first filter unit 501 and the second filter unit 502.
  • the input potential of the filter unit 502 if it is required that the input terminals of the first filter unit 501 and the second filter unit 502 are equalized to a low level after being equalized by the first equalizing circuit 521, then the first equalizing N tube ⁇ EN1> is used to equalize the first The input terminal potentials of the filter unit 501 and the second filter unit 502; if the initial voltages of the first integrated signal FltNdT and the second integrated signal FltNdC are required to be equalized to the middle level by the second equalizing circuit 522, then the second equalizing P tube is used ⁇ EP2> Balance the initial voltages of the first integrated signal FltNdT and the second integrated signal FltNdC; if it is required that the initial voltages of the first integrated signal FltNdT and the second integrated signal FltNdC are low level after being balanced by the second equalizing circuit 522, then use The second balancing N transistor ⁇ EN2> balances the initial voltages of the first integrated signal FltNdT and the
  • the comparison circuit 403 includes: a first input P tube ⁇ SP1>, the gate is used to receive the first integrated signal FltNdT, and the source is connected to the third input P tube ⁇ SP3 >The drain is connected to the source of the first comparison P tube ⁇ BP1>.
  • the gate of the second input P tube ⁇ SP2> is used to receive the second integrated signal FltNdC, the source is connected to the drain of the third input P tube ⁇ SP3>, and the drain is connected to the source of the second comparison P tube ⁇ BP2>.
  • the gate of the third input P tube ⁇ SP3> is used to receive the comparison enable signal CkN, and the source is used to receive the high level signal, that is, the third input P tube ⁇ SP3> serves as the high level protection of the comparison circuit 403
  • the transistor provides the high level required for the operation of the comparison circuit 403 through the comparison enable signal CkN.
  • the gate of the first input N tube ⁇ SN1> is used to receive the comparison enable signal CkN, the source is used to receive the low-level signal, and the drain is connected to the source of the first comparison P tube ⁇ BP1>.
  • the gate of the second input N tube ⁇ SN2> is used to receive the comparison enable signal CkN, the source is used to receive the low-level signal, and the drain is connected to the source of the second comparison P tube ⁇ BP2>.
  • the gate of the third input N tube ⁇ SN3> is used to receive the comparison enable signal CkN, the source is used to receive the low level signal, and the drain is connected to the drain of the first comparison N tube ⁇ BN1>.
  • the fourth input N transistor ⁇ SN4> has a gate for receiving the comparison enable signal CkN, a source for receiving a low level signal, and the source is connected to the drain of the second comparison N transistor ⁇ BN2>.
  • the drain of the first comparison P tube ⁇ BP1> is connected to the drain of the first comparison N tube ⁇ BN1>, the gate is connected to the drain of the second comparison N tube ⁇ BN2>, and the drain of the second comparison P tube ⁇ BP2> Connect the drain of the second comparison N tube ⁇ BN2>, the gate is connected to the drain of the first comparison N tube ⁇ BN1>, the source of the first comparison N tube ⁇ BN1> is used to receive low-level signals, and the drain is To output the first comparison output signal OutP, the gate is connected to the drain of the second comparison N-tube ⁇ BN2>, the source of the second comparison N-tube ⁇ BN2> is used to receive the low-level signal, and the drain is used to output the second Comparison output signal OutN, the gate is connected to the drain of the first comparison N tube; wherein, one of the first comparison output signal OutP and the second comparison output signal OutN is used as the output signal of the comparison circuit 403, and the other is used as the output signal.
  • the gate of the first input P tube ⁇ SP1> is used to receive the first integrated signal FltNdT
  • the gate of the second input P tube ⁇ SP2> is used to receive the second integrated signal FltNdC.
  • the comparison circuit 403 After the signal FltNdT and the second integrated signal FltNdC are compared and amplified, a first comparison output signal OutP and a second comparison output signal OutN are generated, wherein one of the first comparison output signal OutP or the second comparison output signal OutN is used to represent the third comparison output signal OutP.
  • the comparison result of the first integrated signal FltNdT and the second integrated signal FltNdC, and the other one serves as the inverse signal of the signal representing the comparison result.
  • the first comparison output signal OutP is used to represent the comparison result of the first integration signal FltNdT and the second integration signal FltNdC
  • the second comparison output signal OutN is used as the comparison result of the first comparison output signal OutP.
  • the inverted signal is used as an example for detailed description, which does not constitute a limitation of this embodiment.
  • the second comparison output signal can also be used to represent the comparison result between the first integrated signal and the second integrated signal.
  • the corresponding generated first comparison output signal OutP is high level; if the integrated value is greater than 1/ 2*power supply amplitude, then the corresponding generated first comparison output signal OutP is low level.
  • the test circuit 400 also includes: a pre-storage circuit 600, connected to the output end of the comparison circuit 400, and receiving the first clock signal Clk and the second clock signal Clklat; the pre-storage circuit 600 is configured to, based on The first clock signal Clk pre-stores the level signal output by the comparison circuit 403, or outputs the pre-stored level signal based on the second clock signal Clklat.
  • the pre-stored circuit 600 is used to ensure that the signal output timing of the test circuit 400 is consistent with the signal output timing of the memory to which the test circuit 400 belongs, thereby ensuring that the test circuit 400 is applicable to different types of memories.
  • the pre-storage circuit 600 includes: a latch 601, one end of which is connected to the output end of the comparison circuit 601, and the other end is used to receive the first clock signal Clk; the latch 601 is configured to, when the first clock signal Clk is a valid signal, based on the comparison The output level of the circuit generates the indication signal Result.
  • the input terminal D is connected to the output terminal of the latch 601, the clock terminal C is used to receive the second clock signal Clklat, and the enable terminal RN is used to receive the output enable signal ComEn; the register 602 is configured to, when the second clock The signal Clklat and the output enable signal ComEn are valid signals, and the indication signal Result is output.
  • the latch 601 includes: a first latched NAND gate, one input terminal is used to receive the first comparison output signal OutP, and the other input terminal is used to receive the first clock signal Clk; a second latched NAND gate , one input terminal is used to receive the second comparison output signal OutN, and the other input terminal is used to receive the first clock signal Clk; the third latch NAND gate has an input terminal connected to the output terminal of the first latch NAND gate, The other input terminal is connected to the output terminal of the fourth latched NAND gate; the fourth latched NAND gate, one input terminal is connected to the output terminal of the second latched NAND gate, and the other input terminal is connected to the third latched NAND gate.
  • the output terminal of the gate is used to output the indication signal Result.
  • the register 603 may adopt the FF register setting.
  • the test circuit 400 also includes a control module 700.
  • the control module 700 is configured to, based on the control enable signal ControlEn, provide the first integrating circuit 401, the second integrating circuit 402 and the comparison circuit 403 to perform Control signal required for duty cycle detection.
  • the control signals required by the first integrating circuit 401, the second integrating circuit 402 and the comparing circuit 403 for duty cycle detection include: the first equalizing signal EqA and the second equalizing signal EqB, the integral charging signal ClampF, the first integrating signal EqA and the second equalizing signal EqB.
  • the control module 700 includes: a clock unit 710 configured to generate a control clock signal ControlClk based on the control enable signal ControlEn.
  • the timing unit 720 is connected to the output end of the clock unit 710 and stores the signal count value B.
  • the timing unit 720 is configured to accumulate the control signal count value B by one when the control enable signal ControlEn and the control clock signal ControlClk are valid signals.
  • the logic unit 730 is connected to the output end of the timing unit 720, stores the control signal corresponding to the signal count value B, and is configured to provide the control signal corresponding to the signal count value B based on the signal count value B.
  • the clock unit 710 adopts a ring oscillator setting, and the control enable signal ControlEn is used as the enable signal of the ring oscillator; the signal count value B takes a 7-bit signal composed of 7 bits as an example, and does not constitute a limitation of this embodiment. limit, in actual configuration, the number of digits of the signal count value can be configured according to actual needs.
  • the timing unit 720 is also used to receive the test control signal ProbeMode. When the test control signal ProbeMode is valid, at least one new data bit Bmax is added to the signal count value B. The new data bit Bmax is added by adding The bits of the signal count value B thereby increase the change period of the control clock signal ControlClk, thereby controlling the memory in the test mode more accurately.
  • the test control signal DcmCtrl is set to at least three bits to constitute a plurality of signal values.
  • the memory also includes a logic control signal circuit 1006 configured to identify the test control signal DcmCtrl and based on The test control signal DcmCtrl generates a conduction signal PathEns corresponding to the test control signal DcmCtrl.
  • the conduction signal PathEns is used to select the test module corresponding to the conduction to form different test paths. The different test paths are directed to the test circuit 400 or the external test system. 10 Output the signal to be tested.
  • one of the values of the test control signal DcmCtrl is configured to select the test circuit 400 to perform a duty cycle test on the reference test signal AltWck; at this time, the conduction signal PathEns is used to conduct the signal between the conduction signal generator 100 and the test circuit 400 The data transmission path is used to test whether the test function of the test circuit 400 is normal through the reference test signal AltWck with a known duty cycle.
  • test control signal DcmCtrl is configured such that the control signal conversion module 1002 receives the reference test signal AltWck and gives the test circuit to perform a duty cycle test on the internal clock signal PWCK output by the signal conversion module 1002 .
  • the turn-on signal PathEns is used to turn on the data transmission path between the signal generator 100 and the signal conversion module 1002, and the data transmission path between the signal conversion module 1002 and the test circuit 400, so as to test the signal through the test circuit 400. Whether the function of the conversion module 1002 is normal.
  • test control signal DcmCtrl is configured to select the duty cycle test of the serial read clock Clk_R2 output by the read clock path 1004 based on the test circuit 400; at this time, the conduction signal PathEns is used to conduct the conduction signal generator 100 and the data transmission path between the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the read clock path 1004, and the data transmission path between the read clock path 1004 and the test circuit 400, so as to be tested by the test circuit 400 Read clock path 1004 is functioning properly.
  • test control signal DcmCtrl is configured to select the duty cycle test based on the test circuit 400 on the first indication signal Pup and the second indication signal Pdn output by the write clock path 1003; at this time, the conduction signal PathEns is used to conduct The data transmission path between the signal generator 100 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the write clock path 1003, and the data transmission path between the write clock path 1003 and the test circuit 400 are repeated to The test tuning generates equidistant parallel write clocks Clk_W.
  • the memory also includes: a clock driver 1005, the input end is connected to the output end of the signal conversion module 1002, the output end is connected to the test circuit 400, and is used to drive the internal clock signal PWCK output by the signal conversion module 1002 to prevent the internal clock from During the transmission process of the signal PWCK to the test circuit 400 for testing, a large signal attenuation occurs, which ensures the accuracy of the test results of the test circuit 400 .
  • the memory further includes: a first output component 1100, connected to the output end of the duty cycle correction module 102 (refer to FIG. 2), for outputting the intermediate test signal Pretest to the external test system 10.
  • the external test system 10 It is used to test whether the intermediate test signal Pretest satisfies the preset duty cycle, that is, the first output component 1100 is used to obtain the intermediate test signal Pretest that satisfies the preset duty cycle.
  • the process of outputting the intermediate test signal Pretest to the external test system is also used to divide the frequency of the intermediate test signal Pretest, so that the external test system 10 can adjust the frequency of the intermediate test signal Pretest. Detection is performed to reduce the detection accuracy requirements of the external test system 10 for the signal frequency.
  • the write frequency divider 1013 includes: a four-phase clock generation circuit 801 for receiving the internal clock signal PWCK, configured to, based on the internal clock The signal PWCK generates a parallel write clock Clk_W.
  • the parallel write clock Clk_W is the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1 and the fourth clock signal WCK2TF1 with the same period; write clock The tree 1023 includes: a signal delay circuit 802 for receiving the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1, the fourth clock signal WCK2TF1 and a delay command, and is configured to, based on the delay command, The first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1 and the fourth clock signal WCK2TF1 are respectively delayed, and the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1 and the third clock signal WCK2TF0 are respectively delayed. The delays between the four clock signals WCK2TF1 are different.
  • the signal delay inside the four-phase clock generation circuit 801 is large, corresponding to the K value of the four-phase clock generation circuit 801 is large, the period of the first clock signal WCK2TR0 generated at this time can be the period of the internal clock signal PWCK 5 times or more of the period; in another example, the signal delay inside the four-phase clock generation circuit 801 is small, corresponding to the small K value of the four-phase clock generation circuit 801, and the first clock signal WCK2TR0 generated at this time is The period can be 4 times the period of the internal clock signal PWCK or less; refer to Figure 19 and Figure 20.
  • the second clock signal WCK2TF0, the third clock signal WCK2TR1 and the fourth clock signal WCK2TF1 have the same period.
  • the period of signal WCK2TF1 is also twice the period of internal clock signal WCK.
  • the signal delay circuit 802 delays the first clock signal WCK2TR0 to generate a first delayed clock signal WCK2TWRTR0, delays the second clock signal WCK2TF0 to generate a second delayed clock signal WCK2TWRTF0, and delays the third clock signal WCK2TR1.
  • the third delayed clock signal WCK2TWRTR1 is generated, and the fourth delayed clock signal WCK2TF1 is delayed to generate the fourth delayed clock signal WCK2TWRTF1.
  • the delay of the second delayed clock signal WCK2TWRTF0 relative to the first delayed clock signal WCK2TWRTR0 is Ts1
  • the delay of the third delayed clock signal WCK2TWRTR1 relative to the second delayed clock signal WCK2TWRTF0 is Ts2.
  • the delay of the fourth delayed clock signal WCK2TWRTF1 relative to the third delayed clock signal WCK2TWRTR1 is Ts3
  • the delay of the first delayed clock signal WCK2TWRTR0 relative to the fourth delayed clock signal WCK2TWRTF1 is Ts4.
  • the delay command includes a first delay command cmR0, a second delay command cmF0, a third delay command cmR1 and a fourth delay command cmF1.
  • the signal delay circuit 802 includes a first delay command cmF0. time sub-circuit 901, second delay sub-circuit 902, third delay sub-circuit 903 and fourth delay sub-circuit 904.
  • the first delay sub-circuit 901 is used to perform signal delay on the first clock signal WCK2TF0 according to the first delay command cm R0 to generate the first delayed clock signal WCK2TWRTR0; the second delay sub-circuit 902 is used according to The second delay command cm F0 performs signal delay on the second clock signal WCK2TF0 to generate the second delayed clock signal WCK2TWRTF0; the third delay sub-circuit 903 is used to perform signal delay on the third clock signal according to the third delay command cm R1 WCK2TR1 performs signal delay to generate the third delayed clock signal WCK2TWRTR1.
  • the fourth delay sub-circuit 904 is used to perform signal delay on the fourth clock signal WCK2TF1 according to the fourth delay command cm F1 to generate the fourth delay. Clock signal WCK2TWRTF1.
  • the first delay sub-circuit 901 includes: a first delay inverter 811 whose input terminal is used to receive the first clock signal WCK2TF0; a first second delay inverter 812 whose input terminal is connected to the first clock signal WCK2TF0.
  • the output end of the phase inverter 813 is used to output the delayed first clock signal, that is, the first delayed clock signal WCK2TWRTR0;
  • the first charge and discharge module 851 has one end connected to the output end of the first delay inverter 811, and the other end One end is coupled to a low-potential power node, and the low-potential power node is used to receive a low level;
  • the fifth charge and discharge module 855 has one end connected to the output terminals of the first and second delay inverters 812, and the other end is coupled to the low-potential power node;
  • the first The charge and discharge capabilities of the charge and discharge module 851 and the fifth charge and discharge module 855 are adjusted according to the first delay command cm R0
  • first charging and discharging module 851 and the fifth charging and discharging module 855 may also be coupled to high-potential power nodes, and the high-potential power nodes are used to receive high levels.
  • the second delay sub-circuit 902 includes: a second delay inverter 821 whose input terminal is used to receive the second clock signal WCK2TF0; a second delay inverter 822 whose input terminal is connected to the second clock signal WCK2TF0.
  • the first delay inverter 821; the second third delay inverter 823, the input end is connected to the second second delay inverter 822; the second fourth delay inverter 824, the input end is connected to the second third delay inverter
  • the output end of the phase inverter 823 is used to output the delayed second clock signal, that is, the second delayed clock signal WCK2TWRTF0; the second charging and discharging module 852 has one end connected to the output end of the second delayed inverter 821 and the other end.
  • the sixth charge and discharge module 856 has one end connected to the output end of the second delay inverter 822, and the other end is coupled to the low-potential power node; the second The charge and discharge capabilities of the charge and discharge module 852 and the sixth charge and discharge module 856 are adjusted according to the second delay command cm F0. It should be noted that in other embodiments, the other ends of the second charge and discharge module 852 and the sixth charge and discharge module 856 may also be coupled to a high-potential power node, and the high-potential power node is used to receive a high level.
  • the third delay sub-circuit 903 includes: a third delay inverter 831 whose input terminal is used to receive the third clock signal WCK2TR1; a third delay inverter 832 whose input terminal is connected to the third clock signal WCK2TR1.
  • the first delay inverter 831; the third and third delay inverters 833, the input terminal is connected to the third and second delay inverters 832; the third and fourth delay inverters 834, the input terminal is connected to the third and third delay inverters.
  • the output end of the phase inverter 833 is used to output the delayed third clock signal, that is, the third delayed clock signal WCK2TWRTR1;
  • the third charging and discharging module 853 has one end connected to the output end of the third delay inverter 831 and the other end. One end is coupled to a low-potential power node, and the low-potential power node is used to receive a low level;
  • the seventh charge and discharge module 857 has one end connected to the output end of the third delay inverter 832, and the other end is coupled to the low-potential power node; the third The charge and discharge capabilities of the charge and discharge module 853 and the seventh charge and discharge module 857 are adjusted according to the third delay command cm R1.
  • the other ends of the third charge and discharge module 853 and the seventh charge and discharge module 857 can also be coupled to a high-potential power node, and the high-potential power node is used to receive a high level.
  • the fourth delay sub-circuit 904 includes: a fourth first delay inverter 841 whose input terminal is used to receive the fourth clock signal WCK2TF1; a fourth second delay inverter 842 whose input terminal is connected to the fourth clock signal WCK2TF1.
  • the output end of the phase inverter 843 is used to output the delayed fourth clock signal, that is, the fourth delayed clock signal WCK2TWRTF1;
  • the fourth charging and discharging module 854 has one end connected to the output end of the fourth delayed inverter 841, and the other end One end is coupled to a low-potential power node, and the low-potential power node is used to receive a low level;
  • the eighth charge and discharge module 858 has one end connected to the output end of the fourth second delay inverter 842, and the other end is coupled to the low-potential power node; fourth The charge and discharge capabilities of the charge and discharge module 854 and the eighth charge and discharge module 858 are adjusted according to the fourth delay command cm F1. It should be noted that in other embodiments, the other
  • the more charges that can be stored the faster the discharge speed, and the delay of the rising edge of the signal.
  • the charging and discharging capabilities of the discharging module 857 and the eighth charging and discharging module 858 delay the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1 and the fourth clock signal WCK2TF1 to varying degrees.
  • the first charge and discharge module 851 and the fifth charge and discharge module 855 are controlled based on the same delay command, that is, the rising edge and falling edge of the first clock signal WCK2TF0 are delayed to the same extent to ensure that the first clock signal is not changed.
  • the charge and discharge module 857 and the eighth charge and discharge module 858 are implemented through a capacitor. The charge and discharge capability of the capacitor depends on the maximum storage charge amount C of the capacitor and the discharge current I.
  • the discharge current I is controlled by a bias transistor, and the delay command cm controls the first charge and discharge module 851, the second charge and discharge module 852, the third charge and discharge module 853, the fourth charge and discharge module 854, the fifth charge and discharge module 855, and the sixth charge and discharge module 856 by controlling the discharge current I. , the delay performance of the seventh charge and discharge module 857 and the eighth charge and discharge module 858.
  • the low-level power node coupled to the first delay sub-circuit 901, the second delay sub-circuit 902, the third delay sub-circuit 903 and the fourth delay sub-circuit 904 receives
  • the low level is adjustable, thereby realizing the overall adjustment of the charging and discharging capabilities of the first delay sub-circuit 901, the second delay sub-circuit 902, the third delay sub-circuit 903 and the fourth delay sub-circuit 904.
  • the signal loading circuit 805 generates the first indication signal Pup and the second indication signal Pdn based on the first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0, the third delayed clock signal WCK2TWRTR1 and the fourth delayed clock signal WCK2TWRTF1.
  • the signal loading module 805 includes: a data generation module 803 for generating four-bit first loading data Data1 and second loading data Data2.
  • the data loading module 804 is used to sample the first loading data Data1 according to the delayed first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to generate the first indication signal Pup; wherein, at that time When the first loading data Data1 corresponding to the clock signal sampling edge is high level, the generated first indication signal Pup is high level. When the first loading data Data1 corresponding to the clock signal sampling edge is low level, the generated first indication signal Pup is high level. Pup is low level; the data loading module 804 is also used to sample the second loading data Data2 according to the delayed first clock signal, second clock signal, third clock signal, and fourth clock signal to generate a second instruction.
  • the generated second indication signal Pdn is high level.
  • the bits of the generated first loading data Data1 and the second loading data Data2 are equal to the number of clock signals driving the data loading module 804. Since the data loading module 804 can be driven by four clock signals in this embodiment , so the first load data Data1 and the second load data Data2 are four bits.
  • the data generation module 803 is controlled to be turned on based on the generation control signal, and the data generation module is controlled to be started only when in use, thereby saving power consumption of the clock generation circuit.
  • the test circuit 400 and the connection signal loading circuit 805 are configured to perform a duty cycle test based on the first indication signal Pup and the second indication signal Pdn. Specifically, the output signal of the test circuit 400 is used to represent the magnitude relationship between the first indication signal Pup and the second indication signal Pdn. If the output signal of the test circuit is high level, the first indication signal Pup is greater than the second indication signal Pdn. , if the output signal of the test circuit is low level, the second indication signal Pdn is not less than the first indication signal Pup.
  • the first indication signal Pup is generated based on the delayed first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0 and the third delayed clock signal WCK2TWRTR1, and based on the delayed third delayed clock signal WCK2TWRTR1 and the fourth delayed clock signal WCK2TWRTR1, the first instruction signal Pup is generated.
  • the clock signal WCK2TWRTF1 and the first delayed clock signal WCK2TWRTR0 generate the second indication signal Pdn; combined with Figure 19 and Figure 20, it can be seen that the duty cycle of the first indication signal Pup at this time is (Ts1+Ts2)/(Ts1+Ts2+Ts3+ Ts4), the duty cycle of the second indication signal Pdn is (Ts3+Ts4)/(Ts1+Ts2+Ts3+Ts4). If the output signal of the test circuit 400 is high level, it proves that the duty cycle of the first indication signal Pup is greater than the duty cycle of the second indication signal Pdn, that is, (Ts1+Ts2)>(Ts3+Ts4).
  • the delay to the first clock signal can be reduced and the delay to the second clock signal and the third clock signal can be increased at the same time.
  • Ts1+Ts2 is increased and Ts3+Ts4 is decreased
  • (Ts1+Ts2) (Ts3+Ts4)
  • the sum of Ts1+Ts2+Ts3+Ts4 remains unchanged, so as not to change the overall period of the four-phase clock signal .
  • the above example does not reflect the sampling of the delayed clock signal that the first indication signal Pup and the second indication signal Pdn have nothing to do with the duty cycle result.
  • the first indication signal Pup and the second indication signal Pdn are all adopted based on the first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0, the third delayed clock signal WCK2TWRTR1 and the fourth delayed clock signal WCK2TWRTF1.
  • the third indication signal Pup is generated based on the delayed first clock signal WCK2TWRTR0 and the second clock signal WCK2TWRTF0, and the fourth indication signal Pdn is generated based on the delayed second clock signal WCK2TWRTF0 and the third delayed clock signal WCK2TWRTR1; combined with Figure 19
  • the duty cycle of the third indication signal Pup is Ts1/(Ts1+Ts2)
  • the duty cycle of the fourth indication signal Pdn is Ts2/(Ts1+Ts2). If the output signal of the test circuit 400 is high level, it proves that the duty cycle of the third indication signal Pup is greater than the duty cycle of the fourth indication signal Pdn, that is, Ts1>Ts2.
  • the third indication signal Pup and the fourth indication signal Pdn are all adopted based on the first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0, the third delayed clock signal WCK2TWRTR1 and the fourth delayed clock signal WCK2TWRTF1.
  • the fifth indication signal Pup is generated based on the delayed third clock signal WCK2TWRTR1 and the fourth clock signal WCK2TWRTF1, and the sixth indication signal Pdn is generated based on the delayed fourth clock signal WCK2TWRTF1 and the first clock signal WCK2TWRTR0; combined with Figure 19 and It can be seen from Figure 20 that at this time, the duty cycle of the fifth indication signal Pup is Ts3/(Ts3+Ts4), and the duty cycle of the sixth indication signal Pdn is Ts4/(Ts3+Ts4). If the output signal of the test circuit 400 is high level, it proves that the duty cycle of the fifth indication signal Pup is greater than the duty cycle of the sixth indication signal Pdn, that is, Ts3>Ts4.
  • the fifth indication signal Pup and the sixth indication signal Pdn are all adopted based on the first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0, the third delayed clock signal WCK2TWRTR1 and the fourth delayed clock signal WCK2TWRTF1.
  • the above example describes a situation where the delays of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal can all be adjusted; in a specific implementation, due to the rising edge of the first clock signal WCK2TR0 It needs to be aligned with the rising edge of the internal clock signal WCK_T, that is, the delay of the first clock signal WCK2TR0 cannot be adjusted. At this time, the delay change of the first clock signal WCK2TR0 is ignored, and the above example is still applicable.
  • the memory further includes a second output component 1200, connected to the output end of the write clock tree 1023, for outputting the parallel write clock Clk_W to the external test system 10.
  • the external test system 10 uses To test whether the parallel write clock Clk_W is an equidistant clock, that is, after testing and adjusting the write clock tree 1023, the signal loading circuit 805 and the test circuit 400, it is determined whether the actually obtained parallel write clock Clk_W is an equidistant clock.
  • one of the values of the test control signal is configured to control the memory to output the parallel write clock output by the write clock path 1003 to the external test system 10 for duty cycle detection; at this time, the conduction signal PathEns is used to generate the conduction signal.
  • the data transmission path between the processor 100 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the write clock path 1003, and the data transmission path between the write clock path 1003 and the external test system are used to determine the parallel write Check whether the input clock Clk_W is an equidistant clock.
  • the signal conversion module 1002 is also used to receive an external clock signal WCK with a preset duty cycle, and generate an internal clock signal PWCK according to the external clock signal WCK, where the external clock signal WCK is required for the normal operation of the memory. clock signal.
  • the memory also includes: a selection module 1001 having a first input terminal, a second input terminal and an output terminal.
  • the first input terminal is used to receive the reference test signal AltWck, and the second input terminal is used to receive an external clock.
  • Signal WCK the output end is connected to the input end of the signal conversion module 1002, the control end is used to receive the test control signal DcmCtrl, and connect the first input end and the output end or connect the second input end and the output end based on the test control signal DcmCtrl.
  • the source of the first input MOS tube is connected to the output end of the amplitude adjustment module 103, and the drain is used to output the reference test signal AltWck; the source of the second input MOS tube is connected to the first input MOS tube.
  • the drain is connected to the source of the first input MOS tube, the third input MOS tube, the source is used to receive the external clock signal WCK, the drain is connected to the drain of the first input MOS tube, and is used to output the external clock
  • the signal WCK, the gate of the first input MOS tube, the gate of the second input MOS tube and the gate of the third input MOS tube are used to receive the test control signal DcmCtrl, and the gate of the first input MOS tube and the second input
  • the signal received by the gate of the MOS tube is an inverted signal, that is, the gate of one of the first input MOS tube and the second input MOS tube is used to receive the test control signal DcmCtrl, and the gate of the other is used to receive the inverted signal.
  • Phase test control signal DcmCtrl- In some embodiments, only one of the first input MOS transistor and the third input MOS transistor receives the clock signal, and both can be turned on at the same time; in other embodiments, the first input MOS transistor and the third input MOS transistor Select one of the MOS tubes to be turned on.
  • test control signal DcmCtrl the details are as follows:
  • test control signal DcmCtrl is configured to control the memory to output the generated intermediate test signal Pretest to the external test system for duty cycle detection; at this time, the conduction signal PathEns is used to conduct the conduction signal generator 100 and the external test system 10 data transmission path between to obtain the reference test signal AltWck whose duty cycle meets the preset duty cycle.
  • test control signal DcmCtrl is configured to select the duty cycle test of the reference test signal AltWck based on the test circuit; at this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the test circuit 400 , to test whether the test function of the test circuit 400 is normal through the reference test signal AltWck with a known duty cycle.
  • test control signal DcmCtrl is configured to select the test circuit 400 to perform a duty cycle test on the internal clock signal PWCK output by the signal conversion module 1002 based on the reference test signal AltWck; at this time, the conduction signal PathEns is used to conduct the conduction signal
  • test control signal DcmCtrl is configured to select the test circuit 400 to perform a duty cycle test on the internal clock signal PWCK output by the signal conversion module 1002 based on the external clock signal WCK; at this time, the conduction signal PathEns is used for conduction selection.
  • the data transmission path between the module 1001 and the data pad (used to receive the external clock signal WCK), the data transmission path between the selection module 1001 and the signal conversion module 1002, and the data between the signal conversion module 1002 and the test circuit 400 The transmission path is used to test whether the signal conversion module 1002 functions normally when working based on the external clock signal WCK through the test circuit 400 .
  • test control signal DcmCtrl is configured to select the test circuit 400 to perform a duty cycle test on the serial read clock Clk_R2 output by the read clock path 1004 based on the reference test signal AltWck; at this time, the conduction signal PathEns is used to conduct The data transmission path between the signal generator 100 and the selection module 1001, the data transmission path between the selection module 1001 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the read clock path 1004, and the read clock The data transmission path between the path 1004 and the test circuit 400 is used to test whether the function of the read clock path 1004 is normal when working based on the reference test signal AltWck through the test circuit 400.
  • test control signal DcmCtrl is configured to select the test circuit 400 to perform a duty cycle test on the serial read clock Clk_R2 output by the read clock path 1004 based on the external clock signal WCK; at this time, the conduction signal PathEns is used to conduct The data transmission path between the selection module 1001 and the data pad (used to receive the external clock signal WCK), the data transmission path between the selection module 1001 and the signal conversion module 1002, and the signal conversion module 1002 and the read clock path 1004 The data transmission path and the data transmission path between the read clock path 1004 and the test circuit 400 are used to test through the test circuit 400 whether the function of the read clock path 1004 is normal when working based on the external clock signal WCK.
  • test control signal DcmCtrl is configured to select the test circuit 400 to perform a duty cycle test on the first indication signal Pup and the second indication signal Pdn output by the write clock path 1003 based on the reference test signal AltWck; at this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the selection module 1001, the data transmission path between the selection module 1001 and the signal conversion module 1002, and the data transmission path between the signal conversion module 1002 and the write clock path 1003. , and the data transmission path between the write clock path 1003 and the test circuit 400 to repeatedly test and adjust to generate equidistant parallel write clocks Clk_W based on the reference test signal AltWck.
  • test control signal DcmCtrl is configured to select the test circuit 400 to perform a duty cycle test on the first indication signal Pup and the second indication signal Pdn output by the write clock path 1003 based on the external clock signal WCK; at this time, the conduction signal PathEns is used to conduct the data transmission path between the selection module 1001 and the data pad (used to receive the external clock signal WCK), the data transmission path between the selection module 1001 and the signal conversion module 1002, the signal conversion module 1002 and the write clock
  • the data transmission path between the paths 1003 and the data transmission path between the write clock path 1003 and the test circuit 400 are used to repeatedly test and adjust to generate equidistant parallel write clocks Clk_W based on the external clock signal WCK.
  • test control signal DcmCtrl is configured to control the memory to output the parallel write clock Clk_W generated based on the reference test signal AltWck to the external test system 10 for duty cycle detection; at this time, the conduction signal PathEns is used to generate the conduction signal
  • test control signal DcmCtrl is configured to control the memory to output the parallel write clock Clk_W generated based on the external clock signal WCK to the external test system 10 for duty cycle detection; at this time, the conduction signal PathEns is used for the conduction selection module
  • the data transmission path between 1001 and the data pad (used to receive the external clock signal WCK), the data transmission path between the selection module 1001 and the signal conversion module 1002, the data transmission between the signal conversion module 1002 and the write clock path 1003 path, and the data transmission path between the write clock path 1003 and the external test system to determine whether the parallel write clock Clk_W generated based on the external clock signal WCK is an equidistant clock.
  • driving capability refers to the driving capability of the source and drain current of the transistor when the gates of the transistors are turned on to the same degree.
  • the test circuit 400 is used to perform a duty cycle test on the reference test signal AltWck.
  • the duty cycle of the reference test signal AltWck is known, and is used to determine whether the duty cycle test function of the test circuit 400 is normal. If the duty cycle test function of the test circuit 400 is normal, The duty cycle test function is normal, and then select different test modules based on the test control signal DcmCtrl, and test the duty cycles of the output signals of the different test modules in sequence through the test circuit 400 to test whether the duty cycles of the signals output by the different test modules are Normal, thus completing the functional testing of different test modules.
  • Another embodiment of the present disclosure provides a memory detection method. Based on the signal detection system provided in the above embodiment, the duty cycle test is performed on the output signals of each test path in the memory. By selecting different test paths, the high-speed clock signal is tested at different times. Whether the duty cycle in the transmission path meets the requirements to ensure the stability of memory data processing.

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Abstract

本公开涉及半导体电路设计领域，特别涉及一种信号检测系统和存储器检测方法，包括：信号产生器(100)，基于外部参数生成参考测试信号，参考测试信号为满足预设占空比的时钟信号；基于测试电路(400)对参考测试信号进行占空比测试，以判断测试电路(400)的功能是否正常；若测试电路(400)的功能正常，基于测试控制信号依次选择不同测试模块，并基于测试电路(400)对所选择的测试模块所输出的信号进行占空比测试；测试模块包括：信号转换模块(1002)和写时钟路径(1003)，通过选择不同测试路径，以测试高速时钟信号在不同传输路径中的占空比是否满足要求，以保证存储器数据处理的稳定性。

Description

信号检测系统和存储器检测方法
交叉引用
本公开要求于2022年04月26日递交的名称为“信号检测系统和存储器检测方法”、申请号为202210450141.8的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开涉及半导体电路设计领域，特别涉及一种信号检测系统和存储器检测方法。
背景技术
随着技术的进步，高科技产品不断更新换代，产品性能更是不断提升，而高科技产品的工作离不开存储器对于数据的存储；因此，对存储器的数据存取速率和数据存取稳定性的提升，是当下迫在眉睫的问题。
存储器的对数据的处理都会用到时钟信号，而时钟信号的传输频率决定了存储器在相同时间内执行操作的次数，即决定了存储器处理数据的快慢；即存储器基于高速时钟信号进行数据处理，对存储器的性能提升具有重大意义。
如何测试高速时钟信号的占空比是否满足要求，如何保证高速时钟信号测试的准确性，以及如何基于高速时钟信号产生等距并行的时钟信号，是当下亟待解决的问题。
发明内容
本公开实施例提供了一种信号检测系统，应用于存储器，用于根据存储器中的测试电路对存储器中各测试路径的输出信号进行占空比测试，包括：信号产生器，基于外部参数生成参考测试信号，参考测试信号为满足预设占空比的时钟信号；基于测试电路对参考测试信号进行占空比测试，以判断测试电路的功能是否正常；若测试电路的功能正常，基于测试控制信号依次选择不同测试模块，并基于测试电路对所选择的测试模块所输出的信号进行占空比测试；测试模块包括：信号转换模块和写时钟路径；其中，信号转换模块用于根据参考测试信号生成内部时钟信号；写时钟路径包括：写分频器、写时钟树和信号加载电路；写分频器用于根据内部时钟信号生成并行写入时钟，写时钟树用于调节并行写入时钟的延迟，信号加载电路用于根据并行写入时钟对预设数据进行采样，以生成第一指示信号和第二指示信号。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的信号检测系统的结构示意图；
图2为本公开一实施例提供的信号产生器的结构示意图；
图3为本公开一实施例提供的环形振荡器的结构示意图；
图4为本公开一实施例提供的四面体振荡器的结构示意图；
图5为本公开一实施例提供的占空比修正模块的结构示意图；
图6为本公开一实施例提供的第一调整单元和第二调整单元的修正原理示意图；
图7为本公开一实施例提供的第一调整单元和第二调整单元的结构示意图；
图8为本公开一实施例提供的校正单元的结构示意图；
图9为本公开一实施例提供的校正单元的校正原理示意图；
图10为本公开一实施例提供的振幅调整模块的结构示意图；
图11为本公开一实施例提供的振幅调整模块的调整原理示意图；
图12为本公开一实施例提供的测试电路的结构示意图；
图13为本公开一实施例提供的第一积分电路和第二积分电路的结构示意图；
图14为本公开一实施例提供的比较电路的结构示意图；
图15为本公开一实施例提供的预存电路的结构示意图；
图16为本公开一实施例提供的控制模块的控制逻辑示意图；
图17为本公开一实施例提供的控制模块的结构示意图；
图18为本公开一实施例提供的时钟生成电路的结构示意图；
图19为本公开一实施例提供的四相位信号的时序示意图；
图20为本公开一实施例提供的生成等距四相位信号的时序示意图；
图21为本公开一实施例提供的选择模块的具体结构示意图。
具体实施方式
如何测试高速时钟信号的占空比是否满足要求，如何保证高速时钟信号测试的准确性，以及如何基于高速时钟信号产生等距并行的时钟信号，是当下亟待解决的问题。
本公开一实施例提供了一种信号检测系统，通过选择不同测试路径，以测试高速时钟信号在不同传输路径中的占空比是否满足要求，以保证存储器数据处理的稳定性。
本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
以下结合附图对本实施例提供的信号检测系统作进一步详细说明，具体如下：
信号检测系统1000，应用于存储器，用于根据存储器中的测试电路对存储器中各测试路径的输出信号进行占空比测试。
参考图1，信号检测系统1000，包括：
信号产生器100，基于外部参数生成参考测试信号AltWck，参考测试信号AltWck为满足预设占空比的时钟信号。
基于测试电路400对参考测试信号AltWck进行占空比测试，以判断测试电路400的功能是否正常；若测试电路400的功能正常，基于测试控制信号DcmCtrl依次选择不同测试模块，并基于测试电路400对所选择的测试模块所输出的信号进行占空比测试。
其中，测试模块包括：信号转换模块1002和写时钟路径1003，信号转换模块1002用于根据参考测试信号AltWck生成内部时钟信号PWCK；写时钟路径1003包括：写分频器1013、写时钟树1023和信号加载电路805，写分频器1013用于根据内部时钟信号PWCK生成并行写入时钟Clk_W，写时钟树1023，输入端连接写分频器1013的输出端，用于调节输入信号的延迟以生成并行写入时钟Clk_W，信号加载电路805，输入端连接写时钟树1023的输出端，输出端连接测试电路400，用于根据并行写入时钟Clk_W对预设数据进行采样，以生成第一指示信号Pup和第二指示信号Pdn。
通过测试电路400对参考测试信号AltWck进行占空比测试，其中参考测试信号AltWck的占空比已知，用于判断测试电路400的占空比测试功能是否正常，若测试电路400的占空比测试功能正常，再基于测试控制信号DcmCtrl选择不同测试模块，通过测试电路400依次对不同测试模块输出信 号的占空比进行测试，以测试不同测试模块所输出的信号的占空比是否正常，从而完成对不同测试模块的功能测试。
继续参考图1，在一些实施例中，测试模块还包括：读时钟路径1004，读时钟路径1004包括：读分频器1014和读时钟转换电路1024，读分频器1014用于根据内部时钟信号PWCK生成并行读取时钟Clk_R1，读时钟转换电路1024用于根据并行读取时钟Clk_R1生成串行读取时钟Clk_R2。
需要说明的是，在一些实施例中，存储器中的写分频器1013和读分频器1014可以基于一个分频器实现。
对于信号产生器100，参考图2，信号产生器100包括：
振荡产生模块101，被配置为，基于振荡控制信号OscAdj产生初始振荡信号Osc0，振荡控制信号OscAdj用于调整产生的初始振荡信号Osc0的频率。
占空比修正模块102，连接振荡产生模块101的输出端，占空比修正模块102被配置为：基于占空比控制信号Duty对初始振荡信号Osc0的占空比进行调整，以生成中间测试信号Pretest。
振幅调整模块103，连接占空比修正模102的输出端，振幅调整模块103被配置为，基于振幅调整信号OBControl对中间测试信号Pretest的振幅进行调整，以生成参考测试信号AltWck。
对于振荡产生模块101，参考图3，在一些实施例中，振荡产生模块101包括环形振荡器，环形振荡器用于根据振荡控制信号OscAdj产生初始振荡信号Osc0，且振荡控制信号OscAdj用于调整接入环形振荡器的反相器的数量。可以理解的是，接入环形振荡器的反相器的数量与初始振荡信号Osc0的振荡频率相关，具体地，接入环形振荡器的反相器的数量越多，初始振荡信号Osc0的振荡频率越低。参考图4，在一些实施例中，振荡产生模块101包括四面体振荡器，四面体振荡器包括内圈反相器和外圈反相器，其中，外圈反相器的驱动能力相同，内圈反相器的驱动能力相同，且内圈反相器的驱动能力为外圈反相器的驱动能力的0.3～0.8倍。对于四面体振荡器，四面体振荡器用于根据振荡控制信号OscAdj产生初始振荡信号Osc0，且振荡控制信号OscAdj用于调节内圈反相器的驱动能力；在一个例子中，振荡控制信号OscAdj用于调节构成内圈反相器的晶体管的驱动能力以调节内圈反相器的驱动能力。可以理解的是，四面体振荡器中内圈反相器的驱动能力越强，反相器所造成的延时越小，振荡产生模块101产生的生的初始振荡信号Osc0的频率越大；在实际应用中，可以通过改变内圈反相器的驱动能力与外圈反相器的驱动能力的比值，从而控制通过振荡产生模块101产生的生的初始振荡信号Osc0的频率。在一个例子中，内圈反相器的驱动能力可以设置在外圈反相器驱动能力的0.4倍、0.5倍、0.6倍或0.7倍；优选地，内圈反相器的驱动能力设置为外圈反相器驱动能力0.7倍，以增大振荡产生模块101产生的初始振荡信号Osc0的频率。在一个具体的示例中，外圈反相器包括：第一反相器1、第二反相器2、第三反相器3和第四反相器4；内圈反相器包括：第五反相器5、第六反相器6、第七反相器7和第八反相器8。其中，第一反相器1的输出端连接第二反相器2的输入端；第二反相器2的输出端连接第三反相器3的输入端；第三反相器3的输出端连接第四反相器4的输入端；第四反相器4的输出端连接第一反相器1的输入端；第五反相器5的输入端连接第一反相器1的输出端，输出端连接第四反相器4的输入端；第六反相器6的输入端连接第二反相器2的输出端，输出端连接第一反相器1的输入端；第七反相器7的输入端连接第三反相器3的输出端，输出端连接第二反相器2的输入端；第八反相器8的输入端连接第四反相器4的输出端，输出端连接第三反相器3的输入端。
对于占空比修正模块102，参考图5，占空比修正模块102包括：第一调整单元112，连接振荡产生模块101，第一调整单元112被配置为，增大初始振荡信号Osc0的占空比以生成第一调节信号T1。第二调整单元122，连接振荡产生模块101，第二调整单元122被配置为，减小初始振荡信号Osc0的占空比以生成第二调节信号T2。校正单元132，连接第一调整单元112和第二调整单元122，校正单元132被配置为，根据占空比控制信号Duty、第一调节信号T1和第二调节信号T2，生成中间测试信号Pretest；其中，占空比控制信号Duty用于调整生成的中间测试信号Pretest中第一调节信号T1的信号占比和第二调节信号T2的信号占比。
对于第一调整单元T1和第二调整单元T2，参考图6，第一调整单元T1和第二调整单元T2通过对信号的上升沿和下降沿进行不同程度的延时，从而调整信号的占空比；例如，对初始信号上升 沿的延时为t1，对初始信号下降沿的延时为t2；当t1＞t2时，延时后的信号上升沿至下降沿的间距缩短，信号的占空比下降，当t1＜t2时，延时后的信号上升沿至下降沿的间距延长，信号的占空比上升。
在一个具体的示例中，参考图7，第一调整单元112包括：第一开关P管<KP1>、第一开关N管<KN1>、第二开关P管<KP2>和第二开关N管<KN2>。其中，第一开关P管<KP1>的栅极和第一开关N管<KN1>的栅极相连，用于接收初始振荡信号Osc0，第一开关P管<KP1>的源极连接第一上拉晶体管<LP1>的漏极，第一上拉晶体管<LP1>的源极用于接收高电平，第一开关N管<KN1>的源极连接第一下拉晶体管<LN1>的漏极，第一下拉晶体管<LN1>的源极用于接收低电平，第一开关P管<KP1>的漏极和第一开关N管<KN1>漏极相连，且连接第二开关P管<KP2>的栅极和第二开关N管<KN2>的栅极，第二开关P管<KP2>的源极连接第二上拉晶体管<LP2>的漏极，第二上拉晶体管<LP2>的源极用于接收高电平，第二开关N管<KN2>的源极连接第二下拉晶体管<LN2>的漏极，第二下拉晶体管<LN2>的源极用于接收低电平，第二开关P管<KP2>和第二开关N管<KN2>的漏极相连，用于输出第一调节信号T1。第一上拉晶体管<LP1>和第一下拉晶体管<LN1>基于占空比控制信号Duty导通，且第一下拉晶体管<LN1>的驱动能力大于第一上拉晶体管<LP1>的驱动能力；第二上拉晶体管<LP2>和第二下拉晶体管<LN2>基于占空比控制信号Duty导通，且第二下拉晶体管<LN2>的驱动能力小于第二上拉晶体管<LP2>的驱动能力。第二调整单元122包括：第三开关P管<KP3>、第三开关N管<KN3>、第四开关P管<KP4>和第四开关N管<KN4>。其中，第三开关P管<KP3>的栅极和第三开关N管<KN3>的栅极相连，用于接收初始振荡信号Osc0，第三开关P管<KP3>的源极连接第三上拉晶体管<LP3>的漏极，第三上拉晶体管<LP3>的源极用于接收高电平，第三开关N管<KN3>的源极连接第三下拉晶体管<LN3>的漏极，第三下拉晶体管<LN3>的源极用于接收低电平，第三开关P管<KP3>的漏极和第三开关N管<KN3>漏极相连，且连接第四开关P管<KP4>栅极和第四开关N管<KN4>的栅极，第四开关P管<KP4>的源极连接第四上拉晶体管<LP4>的漏极，第四上拉晶体管<LP4>的源极用于接收高电平，第四开关N管<KN4>的源极连接第四下拉晶体管<LN4>的漏极，第四下拉晶体管<LN4>的源极用于接收低电平，第四开关P管<KP4>和第四开关N管<KN4>的漏极相连，用于输出第二调节信号T2。第三上拉晶体管<LP3>和第三下拉晶体管<LN3>基于占空比控制信号Duty导通，且第三下拉晶体管<LN3>的驱动能力大于第三上拉晶体管<LP3>的驱动能力；第四上拉晶体管<LP4>和第四下拉晶体管<LN4>基于占空比控制信号Duty导通，且第四下拉晶体管<LN4>的驱动能力小于第四上拉晶体管<LP4>的驱动能力。需要说明的是，第一上拉晶体管<LP1>、第一下拉晶体管<LN1>、第二上拉晶体管<LP2>、第二下拉晶体管<LN2>、第三上拉晶体管<LP3>、第三下拉晶体管<LN3>、第四上拉晶体管<LP4>和第四下拉晶体管<LN4>可以直接根据占空比控制信号Duty导通，也可以根据占空比使能信号导通，占空比使能信号基于占空比控制信号Duty产生。对于第一调整单元112，由于第二上拉晶体管<LP2>的驱动能力大于第二下拉晶体管<LN2>的驱动能力，使得第一调整信号T1容易被上拉，难以被下拉；因此，第一调整信号T1相对于初始振荡信号Osc0而言，上升沿延时较小，下降沿延时较大。对于第二调整单元122，由于第四上拉晶体管<LP4>的驱动能力小于第四下拉晶体管<LN2>的驱动能力，使得第二调整信号T2容易被下拉，难以被上拉；因此，第二调整信号T2相对于初始振荡信号Osc0而言，上升沿延时较大，下降沿延时较小。
在一些实施例中，第一上拉晶体管<LP1>的驱动能力、第二下拉晶体管<LN2>的驱动能力、第三下拉晶体管<LN3>的驱动能力和第四上拉晶体管<LP4>的驱动能力相同；第一下拉晶体管<LN1>的驱动能力、第二上拉晶体管<LP2>的驱动能力、第三上拉晶体管<LP3>的驱动能力和第四下拉晶体管<LN4>的驱动能力相同。继续参考图7，具体地，第一上拉晶体管<LP1>的驱动能力、第二下拉晶体管<LN2>的驱动能力、第三下拉晶体管<LN3>的驱动能力和第四上拉晶体管<LP4>的驱动能力为B；第一下拉晶体管<LN1>的驱动能力、第二上拉晶体管<LP2>的驱动能力、第三上拉晶体管<LP3>的驱动能力和第四下拉晶体管<LN4>的驱动能力为A；其中，A所表征的驱动能力大于B所表征的驱动能力。通过设置第一上拉晶体管<LP1>的驱动能力、第二下拉晶体管<LN2>的驱动能力、第三下拉晶体管<LN3>的驱动能力和第四上拉晶体管<LP4>的驱动能力相同，且设置第一下拉晶体管<LN1>的驱动能力、第二上拉晶体管<LP2>的驱动能力、第三上拉晶体管<LP3>的驱动能力和第四下拉晶体管<LN4>的驱动能力相同，通过相同晶体管控制第一调整单元112对上升沿调节能力和第二调整单元122对下降沿的调节能力相同，通过相同晶体管控制第一调整单元112对下降沿调节能力和第二调整单元122对上升沿的调节能力相同，从而使得第一调整单元112对上升沿和下降沿的调节总延时和第二调节单元122对上升沿和下降沿的总延时一致，以确保第一调节信号T1和第二调节信号T2的周期相同，从 而便于校正模块132根据第一调节信号T1和第二调节信号T2进行占空比调整。
在本实施例中，第一调整单元112和第二调整单元122还包括修正管组142。修正管组142包括：并联设置的x个修正晶体管，x个修正晶体管中，第n个修正晶体管的驱动能力是第n-1个修正晶体管的驱动能力的两倍，其中，x为大于等于2的整数，n为小于等于x，且大于等于2的任意整数；进一步地，占空比控制信号Duty还用于选择导通修正管组142中的修正晶体管；此时，修正晶体管组142的驱动能力指被导通的多个修正晶体管的等效驱动能力。其中，修正管组142分别与第一上拉晶体管<LP1>、第一下拉晶体管<LN1>、第二上拉晶体管<LP2>、第二下拉晶体管<LN2>、第三上拉晶体管<LP3>、第三下拉晶体管<LN3>、第四上拉晶体管<LP4>和第四下拉晶体管<LN4>并联设置，且修正管组142中的修正晶体管的类型与所并联的晶体管的类型相同。在一个具体的示例中，继续参考图7，修正管组142包括第一修正晶体管、第二修正晶体管、第三修正晶体管、第四修正晶体管和第五修正晶体管；其中，第一修正晶体管的驱动能能力为C，第二修正晶体管的驱动能力为2C，第三修正晶体管的驱动能力为4C，第四修正晶体管的驱动能力为8C，第五修正晶体管的驱动能力为16C；第一驱动晶体管、第二驱动晶体管、第三驱动晶体管、第四驱动晶体管和第五驱动晶体管基于占空比控制信号Duty进行选择导通，从而控制第一调整单元112和第二调整单元122对初始振荡信号Osc0进行不同程度的信号延时。需要说明的是，上述提到的“C”表征一个预设单位值，在具体应用中可以根据电路设计进行相应设计，上述说明仅为了体现修正晶体管之间驱动能力的倍数关系。需要说明的是，本实施例中修正管组142中的多个修正晶体管为并联设置，在其他实施例中，修正管组中的多个修正晶体管也可以采用串联设置，或者采用串联+并联组合的形式设置。
对于校正单元132，参考图8，校正单元132包括：相互并联设置的多个第一驱动子单元，输入端连接所述第一调整单元112，还用于接收占空比控制信号Duty；相互并联设置的多个第二驱动子单元，输入端连接所述第二调整单元122，还用于接收占空比控制信号Duty；其中，占空比控制信号Duty用于对多个第一驱动子单元和多个第二驱动子单元进行选择导通；第三驱动子单元213，输入端连接第一驱动子单元的输出端和第二驱动子单元的输出端，输出端用于输出中间测试信号Pretest。具体地，当多个第一驱动子单元的驱动能力大于多个第二驱动子单元的驱动能力，通过第三驱动子单元213输出的中间测试信号Pretest的占空比更偏向于第一调节信号T1，即根据第一调节信号T1和第二调节信号T2生成的中间测试信号Pretest中，第一调节信号T1的占比更大；当多个第二驱动子单元的驱动能力大于多个第一驱动子单元的驱动能力，通过第三驱动子单元213输出的中间测试信号Pretest的占空比更偏向于第二调节信号T2，即根据第一调节信号T1和第二调节信号T2生成的中间测试信号Pretest中，第二调节信号T2的占比更大。可以理解的是，多个第一驱动子单元的驱动能力指的是多个第一驱动子单元中被导通的第一驱动子单元的等效驱动能力，同理的，多个第二驱动子单元的驱动能力指的是多个第二驱动子单元中被导通的第二驱动子单元的等效驱动能力。
在本实施例中，继续参考图8，信号产生器100包括：第一反相器组211，用于接收占空比控制信号Duty；第一反相器组211中包括并联的多个第一调节反相器201，每一第一调节反相器201作为一个第一驱动子单元，占空比控制信号Duty用于对第一反相器组211中的第一调节反相器201进行选择导通。第二反相器组212，输入端连接第二调整单元122，还用于接收占空比控制信号Duty；第二反相器组212中包括并联的多个第二调节反相器202，每一第二调节反相器202作为一个第二驱动子单元，占空比控制信号Duty用于对第二反相器组212中的第二调节反相器202进行选择导通。第三驱动子单元213包括：第三调节反相器203，输入端分别连接第一反相器组211的输出端和第二反相器组212的输出端，输出端用于输出中间测试信号Pretest。由于第一反相器组211中包括多个并联的第一反相器201，第二反相器组212中包括多个并联的第二反相器202，并联的反相器导通的个数越多，作为整体的第一反相器201或第二反相器202的驱动能力越好，即通过控制第一反相器组211和第二反相器组212中第一反相器201和第二反相器202的导通数量，从而调整中间测试信号Pretest的占空比。
在一个具体的示例中，参考图8并结合图9，假设第一反相器组211中包括三个第一反相器201，第二反相器组212中包括三个第二反相器202，即校正单元包括三个第一驱动子单元和三个第二驱动子单元，此时第一驱动子单元和第二驱动子单元的导通情况可分为：(1)导通3个第一驱动子单元和0个第二驱动子单元，此时中间测试信号Pretest与第一调整信号T1的占空比相同，高电平信号的时长为tpH3；(2)导通2个第一驱动子单元和1个第二驱动子单元，此时中间测试信号Pretest偏 向于第一调整信号T1，高电平信号的时长为tpH2；(3)导通1个第一驱动子单元和2个第二驱动子单元，此时中间测试信号Pretest偏向于第二调整信号T2，高电平信号的时长为tpH1；(4)导通0个第一驱动子单元和3个第二驱动子单元，此时中间测试信号Pretest与第二调整信号T2的占空比相同，高电平信号的时长为tpH0。
对于振幅调整模块103，参考图10，振幅调整模块103，包括：第一信号产生单元113，被配置为，基于中间测试信号Pretest上拉输出信号，基于反相测试信号Pretest-下拉输出信号，以生成与中间测试信号Pretest相位相同的参考测试信号AltWck。第二信号产生单元123，被配置为，基于反相测试信号Pretest-上拉输出信号，基于中间测试信号Pretest下拉输出信号，以生成与反相测试信号Pretest-相位相同的反相参考测试信号AltWck-。其中，中间测试信号Pretest和反相测试信号Pretest-幅值相同，相位相反。具体地，第一驱动管<QN1>的栅极用于接收中间测试信号Pretest，漏极用于接收高电平，第二驱动管<QN2>的栅极用于接收反相测试信号Pretest-，源极用于接收低电平，第一驱动管<QN1>的源极与第二驱动管<QN2>的漏极相连，用于输出参考测试信号AltWck。其中，振幅控制信号OBControl用于调节第一驱动管<QN1>的驱动能力。需要说明的是，在本实施例中，振幅控制信号OBControl通过调节第一驱动管<QN1>的驱动能力来改变第一信号产生单元113的驱动能力；在其他实施例中，可以设置为振幅控制信号通过调节第二驱动管的驱动能力或者共同调整第一驱动管和第二驱动管来改变第一信号产生单元的驱动能力。第二信号产生单元123包括：第三驱动管和第四驱动管。第三驱动管<QN3>的栅极用于接收中间测试信号Pretest，漏极用于接收高电平，第四驱动管<QN4>的栅极用于接收反相测试信号Pretest-，源极用于接收低电平，第三驱动管<QN3>的源极与第四驱动管<QN4>的漏极相连，用于输出反相参考测试信号AltWck-。其中，振幅控制信号OBControl用于调节第三驱动管<QN3>的驱动能力。需要说明的是，在本实施例中，振幅控制信号OBControl通过调节第三驱动管<QN3>的驱动能力来改变第二信号产生单元123的驱动能力；在其他实施例中，可以设置为振幅控制信号通过调节第四驱动管的驱动能力或者共同调整第三驱动管和第四驱动管来改变第二信号产生单元的驱动能力。在一个例子中，振幅控制信号OBControl可以通过改变第一驱动管<QN1>和第三驱动管<QN3>的宽长比或衬底电压，以调节第一驱动管<QN1>和第三驱动管<QN3>的驱动能力，同理，第二驱动管和第四驱动管的驱动能力可以通过类似的方式进行调整。进一步地，第一信号产生单元113还包括：第一开关晶体管<B1>、第二开关晶体管<B2>和第一抗干扰晶体管<B3>。第一开关晶体管<B1>的源极耦合电源节点、漏极连接第一驱动管<QN1>的漏极，栅极用于接收振幅控制信号OBControl，第二开关晶体管<B2>的源极耦合地线节点，漏极连接第二驱动管<QN2>的漏极，栅极用于接收振幅控制信号OBControl，以在接收到振幅控制信号OBControl之后导通，从而降低第一信号产生单元113在闲时的功耗；此外，第一抗干扰晶体管<B3>与第二驱动管<QN2>并联，栅极用于接收振幅控制信号OBControl。其中，振幅控制信号OBControl还用于调节第一抗干扰晶体管<B3>的驱动能力，进而调整第一抗干扰晶体管<B3>的抗干扰能力。由于第一驱动管<QN1>的驱动能力可基于振幅控制信号OBControl调整，即当第一驱动管<QN1>的驱动能力大，输出的参考测试信号AltWck的幅值较大，需要的抗干扰的能力强；当第一驱动管<QN1>的驱动能力小，输出的参考测试信号AltWck的幅值较小，需要的抗干扰的能力弱；因此，通过振幅控制信号OBControl相应调节第一抗干扰晶体管<B3>的抗干扰能力，以确保第一信号产生单元113产生的参考测试信号AltWck的准确性，以及降低第一抗干扰晶体管<B3>的功耗。在本实施例中，振幅控制信号OBControl还用于使能第一开关晶体管<B1>、第二开关晶体管<B2>和第一抗干扰晶体管<B3>，并同时调节第一抗干扰晶体管<B3>驱动能力；在其他实施例中，可以设置为第一开关晶体管、第二开关晶体管和第一抗干扰晶体管基于振幅使能信号导通，其中振幅使能信号基于振幅控制信号生成。第二信号产生单元123还包括：第三开关晶体管<B4>、第四开关晶体管<B5>和第二抗干扰晶体管<B6>。第三开关晶体管<B4>的源极耦合电源节点、漏极连接第四驱动管<QN4>的漏极，栅极用于接收振幅控制信号OBControl，第四开关晶体管<B5>的源极耦合地线节点，漏极连接第五驱动管<QN5>的漏极，栅极用于接收振幅控制信号OBControl，以在接收到振幅控制信号OBControl之后导通，从而降低第二信号产生单元123在闲时的功耗；此外，第二抗干扰晶体管<B6>与第五驱动管<QN5>并联，栅极用于接收振幅控制信号OBControl。其中，振幅控制信号OBControl还用于调节第二抗干扰晶体管<B6>的驱动能力，进而调整第二抗干扰晶体管<B6>的抗干扰能力。由于第三驱动管<QN3>的驱动能力可基于振幅控制信号OBControl调整，即当第三驱动管<QN3>的驱动能力大，输出的反相参考测试信号AltWck-的幅值较大，需要的抗干扰的能力强；当第三驱动管<QN3>的驱动能力小，输出的反相参考测试信号AltWck- 的幅值较小，需要的抗干扰的能力弱；因此，通过振幅控制信号OBControl相应调节第二抗干扰晶体管<B6>的抗干扰能力，以确保第二信号产生单元123产生的反相参考测试信号AltWck-的准确性，以及降低第二抗干扰晶体管<B6>的功耗。在本实施例中，振幅控制信号OBControl还用于使能第三开关晶体管<B4>、第四开关晶体管<B5>和第二抗干扰晶体管<B6>，并同时调节第二抗干扰晶体管<B6>驱动能力；在其他实施例中，可以设置为第三开关晶体管、第四开关晶体管和第二抗干扰晶体管基于振幅使能信号导通，其中振幅使能信号基于振幅控制信号生成。需要说明的是，本实施例以第一信号产生单元113产生参考测试信号AltWck，第二信号产生单元123产生反相参考测试信号AltWck-为例进行详细说明，并不构成对本实施例的限定，在其他实施例中，可以设置为以第一信号产生单元产生反相测试信号，以第二信号产生单元产生测试信号。
具体地，在本实施例中，振幅调整模块103还包括：信号生成单元300，连接振幅调整模块103和占空比修正模块102，被配置为，基于中间测试信号Pretest生成反相测试信号Pretest-，在一个具体的示例中，第一信号产生单元113包括：第一驱动管<QN1>和第二驱动管<QN2>。
在本实施例中，振幅控制信号OBControl还用于控制中间测试信号Pretest和反相测试信号Pretest-的输入，在一个具体的示例中，信号产生器100还包括：第一驱动单元301和第二驱动单元302。第一驱动单元301，用于接收振幅控制OBControl和中间测试信号Pretest，第一驱动单元301被配置为，若同时接收到振幅控制信号OBControl和中间测试信号Pretest，输出中间测试信号Pretest或反相测试信号Pretest-的其中一者；第二驱动单元302，用于接收振幅控制OBControl和反相测试信号Pretest-，第二驱动单元302被配置为，若同时接收到振幅控制信号OBControl和反相测试信号Pretest-，输出中间测试信号Pretest或反相测试信号Pretest-的另一者。具体地，若第一驱动单元301基于与非门设计，此时若同时接收到振幅控制信号OBControl和中间测试信号Pretest，输出反相测试信号Pretest-；若第一驱动单元301基于与门设计，此时若同时接收到振幅控制信号OBControl和中间测试信号Pretest，输出中间测试信号Pretest；若第二驱动单元302基于与非门设计，此时若同时接收到振幅控制信号OBControl和反相测试信号Pretest-，输出中间测试信号Pretest；若第二驱动单元302基于与门设计，此时若同时接收到振幅控制信号OBControl和反相测试信号Pretest-，输出反相测试信号Pretest-。需要说明的是，在本实施例中，振幅控制信号OBControl还用于使能第一驱动单元301和第二驱动单元302；在其他实施例中，可以设置为第一驱动单元和驱动单元基于振幅使能信号导通，其中振幅使能信号基于振幅控制信号生成。继续参考图10，由于第一驱动单元301和第二驱动单元302与第一信号产生单元113和第二信号产生单元123之间的器件距离较远，输出的中间测试信号Pretest和反相测试信号Pretest-可能会出现信号衰减的现象，为了避免这一现象的发生，在一些实施例中，振幅调整模块103还包括：第一输入调节单元310、第二输入调节单元320、第三输入调节单元330和第四输入调节单元340。其中，第一输入调节单元310，连接第一信号产生单元113，被配置为，驱动向第一信号产生单元113提供的中间测试信号Pretest；第二输入调节单元320，连接第二信号产生单元123，被配置为，驱动向第二信号产生单元123提供的中间测试信号Pretest；第三输入调节单元330，连接第一信号产生单元113，被配置为，驱动向第一信号产生单元113提供的反相测试信号Pretest-；第四输入调节单元340，连接第二信号产生单元123，被配置为，驱动向第二信号产生单元123提供的反相测试信号Pretest-。在一个例子中，第一输入调节单元310、第二输入调节单元320、第三输入调节单元330和第四输入调节单元340中包括偶数个反相器。在另一个例子中，第一输入调节单元310、第二输入调节单元320、第三输入调节单元330和第四输入调节单元340包括奇数个反相器，此时，第一输入调节单元310用于向第一信号产生单元113提供反相测试信号Pretest-；第二输入调节单元320用于向第二信号产生单元123提供反相测试信号Pretest-；第三输入调节单元330用于向第一信号产生单元113提供中间测试信号Pretest；第四输入调节单元340用于向第二信号产生单元123提供中间测试信号Pretest。
参考图11，中间测试信号Pretest和反相测试信号Pretest-经过振幅调整模块103后生成的测试信号AltWck和反相参考测试信号AltWck-，相位相同，幅值由V1变更到V2，以满足后续的使用需求。
对于测试电路400，参考图12，第一积分电路401，用于接收第一测试信号Test1，被配置为，对第一测试信号Test1积分以输出第一积分信号FltNdT。第二积分电路402，用于接收第二测试信号Test2，被配置为，对第二测试信号Test2积分以输出第二积分信号FltNdC。其中，第一测试信号Test1 即输入到测试电路400的待测信号，第一测试信号Test1和第二测试信号Test2互为反相信号，第一积分信号FltNdT的电压值为第一测试信号Test1的占空比与电源幅值的乘积，第二积分信号FltNdC的电压值为第二测试信号Test2的占空比与电源幅值的乘积。比较电路403，一输入端连接第一积分电路401，另一输入端连接第二积分电路402；比较电路403被配置为，比较第一积分信号FltNdT和第二积分信号FltNdC的大小，当第一积分信号FltNdT大于第二积分信号FltNdC，以输出高电平信号，当第二积分信号FltNdC大于第一积分信号FltNdT，以输出低电平信号。
具体地，在本实施例中，参考图13，对于第一积分电路401，包括：第一滤波单元501、第一预处理单元510和第二预处理单元520。其中，第一滤波单元501用于对接收到的信号进行积分，即第一滤波单元501用于对第一测试信号Test1进行积分。第一预处理单元510包括：第一导通晶体管<DT1>、第一预充P管<YP1>和第一预充N管<YN1>。第一导通晶体管<DT1>的漏极用于接收第一测试信号Test1，源极连接第一滤波单元501的输入端，栅极用于接收第一开关信号PassA；第一预充P管<YP1>的源极用于接收高电平，漏极连接第一滤波单元501的输入端，栅极用于接收积分充电信号ClampF；第一预充N管<YN1>的源极用于接收低电平，漏极连接第一滤波单元501的输入端，栅极用于接收第一积分放电信号ClpGnd。具体地，第一开关信号PassA用于启动第一预处理单元510，当第一开关信号PassA导通第一导通晶体管<DT1>，第一滤波单元501接收到第一测试信号Test1，开始对第一测试信号Test1进行积分；第一预充P管<YP1>基于积分充电信号ClampF导通，从而将第一滤波单元501的输入端间接连接至高电平，从而拉高第一滤波单元501的输入端的电位；第一预充N管<YN1>基于第一积分放电信号ClpGnd导通，从而将第一滤波单元501的输入端间接连接至低电平，从而拉低第一滤波单元501的输入端的电位。第二预处理单元520包括：第二导通晶体管<DT2>、第二预充P管<YP2>和第二预充N管<YN2>。第二导通晶体管<DT2>的漏极连接第一滤波单元501的输出端，源极用于输出第一积分信号FltNdT，栅极用于接收第二开关信号PassB；第二预充P管<YP2>的源极用于接收高电平，漏极连接第一滤波单元501的输出端，栅极用于接收积分充电信号ClampF；第二预充N管<YN2>的漏极用于接收低电平，漏极连接第一滤波单元501的输入端，栅极用于接收第一积分放电信号ClpGnd。具体地，第二开关信号PassB用于启动第二预处理单元520，当第二开关信号PassB导通第二导通晶体管<DT2>，第一滤波单元501积分获取的第一积分信号FltNdT可被输出至比较电路403；第二预充P管<YP2>基于积分充电信号ClampF导通，从而将第一滤波单元501的输出端间接连接至高电平，从而拉高第一滤波单元501的输出端的电位；第二预充N管<YN2>基于第一积分放电信号ClpGnd导通，从而将第一滤波单元501的输出端间接连接至低电平，从而拉低第一滤波单元501的输出端的电位。对于第二积分电路402，包括：第二滤波单元502、第三预处理单元530和第四预处理单元540。其中，第二滤波单元502用于对接收到的信号进行积分，即第二滤波单元502用于第二测试信号Test2进行积分。第三预处理单元530包括：第三导通晶体管<DT3>、第三预充P管<YP3>和第三预充N管<YN3>。第三导通晶体管<DT3>的漏极用于接收第二测试信号Test2，源极连接第二滤波单元502的输入端，栅极用于接收第一开关信号PassA；第三预充P管<YP3>的源极和栅极相连，且用于接收高电平，漏极连接第二滤波单元502的输入端；第三预充N管<YN3>的源极用于接收低电平，漏极连接第二滤波单元502的输入端，栅极用于接收第二积分放电信号Clamp。具体地，第一开关信号PassA用于启动第三预处理单元530，当第一开关信号PassA导通第三导通晶体管<DT3>，第二滤波单元502接收到第二测试信号Test2，开始对第二测试信号Test2进行积分；第三预充P管<YP3>栅极和源极同时接收高电平，使第三预充P管<YP3>处于截止状态，以防止高电平对第二滤波单元502的输入端的电位拉高；第三预充N管<YN3>基于第二积分放电信号Clamp导通，从而将第二滤波单元502的输入端间接连接至低电平，从而拉低第二滤波单元502的输出端的电位。第四预处理单元540包括：第四导通晶体管<DT3>、第四预充P管<YP4>和第四预充N管<YN4>。第四导通晶体管<DT3>的漏极连接第二滤波单元502的输出端，源极用于输出第二积分信号FltNdC，栅极用于接收第二开关信号PassB，第四预充P管<YP4>的源极和栅极相连，且用于接收高电平，漏极连接第二滤波单元502的输出端；第四预充N管<YN4>的源极用于接收低电平，漏极连接第二滤波单元502的输出端，栅极用于接收第二积分放电信号Clamp。具体地，第二开关信号PassB用于启动第四预处理单元540，当第二开关信号PassB导通第四导通晶体管<DT3>，第二滤波单元502积分获取的第二积分信号FltNdC可被输出至比较电路403；第四预充P管<YP4>栅极和源极同时接收高电平，使第四预充P管<YP4>处于截止状态，以防止高电平对第二滤波单元502的输出端的电位拉高；第四预充N管<YN4>基于第二积分放电信号Clamp导通，从而将第二滤波单元502的输出端间接连接至 低电平，从而拉低第二滤波单元502的输出端的电位。
在本实施例中，第一滤波单元501采用二阶RC滤波器设置；相应地，第二滤波单元502也采用二阶RC滤波器设置。需要说明的是，在其他实施例中，第一滤波单元和第二滤波单元可以同时采用一阶或高阶RC滤波器设置；相应地，在一些实施例中，第一滤波单元和第二滤波单元的RC滤波器的阶数也可以设置不同阶。
继续参考图13，在本实施例中，测试电路400还包括：第一均衡电路521和第二均衡电路522。其中，第一均衡电路521的一端连接第一积分电路401的输入端，另一端连接第二积分电路402的输入端；第一均衡电路521被配置为，基于第一均衡信号EqA，使第一积分电路401和第二积分电路402的输入端的电压相同；第二均衡电路522的一端连接第一积分电路401的输出端，另一端连接第二积分电路402的输出端；第二均衡电路522被配置为，基于第二均衡信号EqB，使第一积分信号FltNdT和第二积分信号FltNdC的初始电压相同。具体地，在本实施例中，第一均衡电路521包括：第一均衡P管<EP1>和第一均衡N管<EN1>；其中，第一均衡P管<EP1>的源极和第一均衡N管<EN1>的漏极耦合至第一积分电路401的输入端，第一均衡P管<EP1>的漏极和第一均衡N管<EN1>的源极耦合至第二积分电路402的输入端，第一均衡P管<EP1>的栅极和第一均衡N管<EN1>的栅极用于接收第一均衡信号EqA。第二均衡电路522包括：第二均衡P管<EP2>和第二均衡N管<EN2>；其中，第二均衡P管<EP2>的源极和第二均衡N管<EN2>的漏极耦合至第一积分电路401的输出端，第二均衡P管<EP2>的漏极和第二均衡N管<EN2>的源极耦合至第二积分电路402的输出端，第二均衡P管<EP2>的栅极和第二均衡N管<EN2>的栅极用于接收第二均衡信号EqB。第一均衡电路521的一端连接第一滤波单元501的输入端，另一端连接第二滤波单元502的输入端；第一均衡电路521被配置为，基于第一均衡信号EqA，使第一滤波单元501和第二滤波单元502的输入端的电压相同；第二均衡电路522的一端连接第二导通晶体管<DT2>的漏极，另一端连接第四导通晶体管<DT4>的漏极；第二均衡电路522被配置为，基于第二均衡信号EqB，使第一积分信号FltNdT和第二积分信号FltNdC的初始电压相同。需要说明的是，对于第一均衡电路521和第二均衡电路522，可以根据测试电路均衡后的实际需求，设置所需导通的均衡管。例如，若需求第一滤波单元501和第二滤波单元502的输入端经过第一均衡电路521均衡后为中间电平，则采用第一均衡P管<EP1>均衡第一滤波单元501和第二滤波单元502的输入端电位；若需求第一滤波单元501和第二滤波单元502的输入端经过第一均衡电路521均衡后为低电平，则采用第一均衡N管<EN1>均衡第一滤波单元501和第二滤波单元502的输入端电位；若需求第一积分信号FltNdT和第二积分信号FltNdC的初始电压经过第二均衡电路522均衡后为中间电平，则采用第二均衡P管<EP2>均衡第一积分信号FltNdT和第二积分信号FltNdC的初始电压；若需求第一积分信号FltNdT和第二积分信号FltNdC的初始电压经过第二均衡电路522均衡后为低电平，则采用第二均衡N管<EN2>均衡第一积分信号FltNdT和第二积分信号FltNdC的初始电压。通过在第一积分电路401和第二积分电路402积分前，均衡第一积分电路401和第二积分电路402的输入端电压和输出端电压，保证第一积分电路401的第二积分电路402积分值差异的准确性，进一步保证后续获取的信号占空比的准确性；另外，后续将第一积分信号FltNdT和第二积分信号FltNdC输出的过程中，通过开启第一均衡电路521和第二均衡电路522，可以进一步降低测试电路的功耗。
对于比较电路403，参考图14，在本实施例中，比较电路403包括：第一输入P管<SP1>，栅极用于接收第一积分信号FltNdT，源极连接第三输入P管<SP3>的漏极，漏极连接第一比较P管<BP1>的源极。第二输入P管<SP2>，栅极用于接收第二积分信号FltNdC，源极连接第三输入P管<SP3>的漏极，漏极连接第二比较P管<BP2>的源极。所述第三输入P管<SP3>的栅极用于接收比较使能信号CkN，源极用于接收高电平信号，即第三输入P管<SP3>作为比较电路403的高电平保护晶体管，通过比较使能信号CkN提供比较电路403工作所需的高电平。第一输入N管<SN1>，栅极用于接收比较使能信号CkN，源极用于接收低电平信号，漏极连接第一比较P管<BP1>的源极。第二输入N管<SN2>，栅极用于接收比较使能信号CkN，源极用于接收低电平信号，漏极连接第二比较P管<BP2>的源极。第三输入N管<SN3>，栅极用于接收比较使能信号CkN，源极用于接收低电平信号，漏极连接第一比较N管<BN1>的漏极。第四输入N管<SN4>，栅极用于接收比较使能信号CkN，源极用于接收低电平信号，源极连接第二比较N管<BN2>的漏极。第一比较P管<BP1>的漏极连接第一比较N管<BN1>的漏极，栅极连接第二比较N管<BN2>的漏极，第二比较P管<BP2>的漏极连接第二比较N管<BN2>的漏极，栅极连接第一比较N管<BN1>的漏极，第一比较N管<BN1>的源极用于接收低电 平信号，漏极用于输出第一比较输出信号OutP，栅极连接第二比较N管<BN2>的漏极，第二比较N管<BN2>的源极用于接收低电平信号，漏极用于输出第二比较输出信号OutN，栅极连接第一比较N管的漏极；其中，第一比较输出信号OutP和第二比较输出信号OutN的其中一者作为比较电路403的输出信号，另一者作为输出信号的反相信号。第一输入P管<SP1>的栅极用于接收第一积分信号FltNdT，第二输入P管<SP2>的栅极用于接收第二积分信号FltNdC，此时，比较电路403对第一积分信号FltNdT和第二积分信号FltNdC比较放大后，生成第一比较输出信号OutP和第二比较输出信号OutN，其中，第一比较输出信号OutP或第二比较输出信号OutN的其中一者用于表征第一积分信号FltNdT和第二积分信号FltNdC的比较结果，另一者作为表征比较结果的信号的反相信号。需要说明的是，在本实施例中，以第一比较输出信号OutP用于表征第一积分信号FltNdT和第二积分信号FltNdC的比较结果，第二比较输出信号OutN作为第一比较输出信号OutP的反相信号为例进行详细说明，并不构成本实施例的限定，在其他实施例中，同样可以采用第二比较输出信号用于表征第一积分信号和第二积分信号的比较结果。更具体地，对于第一积分信号FltNdT和第二积分信号FltNdC，若积分值大于1/2*电源幅值，则对应生成的第一比较输出信号OutP为高电平；若积分值大于1/2*电源幅值，则对应生成的第一比较输出信号OutP为低电平。
在本实施例中，参考图15，测试电路400还包括：预存电路600，连接比较电路400的输出端，并接收第一时钟信号Clk和第二时钟信号Clklat；预存电路600被配置为，基于第一时钟信号Clk预存比较电路403输出的电平信号，或基于第二时钟信号Clklat输出预存的电平信号。通过预存电路600，以保证测试电路400的信号输出时序与测试电路400所属存储器的信号输出时序保持一致，以确保测试电路400的可适用于不同类型的存储器。预存电路600包括：锁存器601，一端连接比较电路601的输出端，另一端用于接收第一时钟信号Clk；锁存器601被配置为，当第一时钟信号Clk为有效信号，基于比较电路的输出电平生成指示信号Result。寄存器602，输入端D连接锁存器601的输出端，时钟端C用于接收第二时钟信号Clklat，使能端RN用于接收输出使能信号ComEn；寄存器602被配置为，当第二时钟信号Clklat和输出使能信号ComEn为有效信号，输出指示信号Result。具体地，锁存器601包括：第一锁存与非门，一输入端用于接收第一比较输出信号OutP，另一输入端用于接收第一时钟信号Clk；第二锁存与非门，一输入端用于接收第二比较输出信号OutN，另一输入端用于接收第一时钟信号Clk；第三锁存与非门，一输入端连接第一锁存与非门的输出端，另一输入端连接第四锁存与非门的输出端；第四锁存与非门，一输入端连接第二锁存与非门的输出端，另一输入端连接第三锁存与非门的输出端，输出端用于输出指示信号Result。需要说明的是，在一些实施例中，寄存器603可以采用FF寄存器设置。
在本实施例中，参考图16，测试电路400还包括控制模块700，控制模块700被配置为，基于控制使能信号ControlEn，提供第一积分电路401、第二积分电路402和比较电路403进行占空比检测所需的控制信号。具体地，第一积分电路401、第二积分电路402和比较电路403进行占空比检测所需的控制信号包括：第一均衡信号EqA和第二均衡信号EqB、积分充电信号ClampF、第一积分放电信号ClpGnd和第二积分放电信号Clamp、第一开关信号PassA和第二开关信号PassB、比较使能信号CkN、第一时钟信号Clk、第二时钟信号Clklat和输出使能信号ComEn。
更具体地，参考图17，控制模块700包括：时钟单元710，被配置为，基于控制使能信号ControlEn产生控制时钟信号ControlClk。计时单元720，连接时钟单元710的输出端，存储器信号计数值B，计时单元720被配置为，当控制使能信号ControlEn和控制时钟信号ControlClk为有效信号，控制信号计数值B累积加一。逻辑单元730，连接计时单元720的输出端，存储有信号计数值B所对应的控制信号，被配置为，基于信号计数值B，提供信号计数值B所对应的控制信号。具体地，时钟单元710采用环形振荡器设置，控制使能信号ControlEn作为环形振荡器的使能信号；信号计数值B以7位构成的7比特信号为例进行举例说明，并不构成对本实施例的限定，在实际配置中，信号计数值的位数可以根据实际需求进行配置。在一些实施例中，计时单元720还用于接收测试控制信号ProbeMode，当测试控制信号ProbeMode有效，于信号计数值B中添加至少一比特位的新增数据位Bmax，新增数据位Bmax通过增加信号计数值B的比特位，从而增加控制时钟信号ControlClk的变化周期，从而更加准确地对处于测试模式下的存储器进行控制。
继续参考图1，对于上述信号检测系统1000，测试控制信号DcmCtrl设置为至少三比特位，以构成多个信号值，存储器还包括逻辑控制信号电路1006，被配置为，识别测试控制信号DcmCtrl 并基于测试控制信号DcmCtrl生成对应于测试控制信号DcmCtrl的导通信号PathEns，导通信号PathEns用于选择导通对应的测试模块，以形成不同的测试路径，不同的测试路径向测试电路400或外部测试系统10输出待测试信号。
具体地，测试控制信号DcmCtrl其中一值被配置为，选择测试电路400对参考测试信号AltWck进行占空比测试；此时导通信号PathEns用于导通信号产生器100与测试电路400之间的数据传输路径，以通过已知占空比的参考测试信号AltWck测试测试电路400的测试功能是否正常。
测试控制信号DcmCtrl其中一值被配置为，控制信号转换模块1002接收参考测试信号AltWck，并给予测试电路对信号转换模块1002输出的内部时钟信号PWCK进行占空比测试。此时，导通信号PathEns用于导通信号产生器100与信号转换模块1002之间的数据传输路径，以及信号转换模块1002与测试电路400之间的数据传输路径，以通过测试电路400测试信号转换模块1002的功能是否正常。
测试控制信号DcmCtrl其中一值被配置为，选择基于测试电路400对读时钟路径1004输出的串行读取时钟Clk_R2进行占空比测试；此时，导通信号PathEns用于导通信号产生器100与信号转换模块1002之间的数据传输路径、信号转换模块1002与读时钟路径1004之间的数据传输路径、以及读时钟路径1004与测试电路400之间的数据传输路径，以通过测试电路400测试读时钟路径1004的功能是否正常。
测试控制信号DcmCtrl其中一值被配置为，选择基于测试电路400对写时钟路径1003输出的第一指示信号Pup和第二指示信号Pdn进行占空比测试；此时导通信号PathEns用于导通信号产生器100与信号转换模块1002之间的数据传输路径、信号转换模块1002与写时钟路径1003之间的数据传输路径、以及写时钟路径1003与测试电路400之间的数据传输路径，以反复测试调整生成等距的并行写入时钟Clk_W。
在一些实施例中，存储器还包括：时钟驱动器1005，输入端连接信号转换模块1002的输出端，输出端连接测试电路400，用于驱动信号转换模块1002输出的内部时钟信号PWCK，以防止内部时钟信号PWCK传输至测试电路400进行测试的传输过程中，出现较大的信号衰减，保证测试电路400的测试结果的准确性。
在一些实施例中，存储器还包括：第一输出组件1100，连接占空比修正模块102(参考图2)的输出端，用于将中间测试信号Pretest输出到外部测试系统10，外部测试系统10用于测试中间测试信号Pretest是否满足预设占空比，即第一输出组件1100用于获取满足预设占空比的中间测试信号Pretest。需要说明的是，在一些实施例中，将中间测试信号Pretest输出到外部测试系统的过程中，还用于对中间测试信号Pretest进行分频，以便于外部测试系统10对中间测试信号Pretest的频率进行检测，降低外部测试系统10对于信号频率所需的检测精度要求。
对于测试电路400测试写分频器1013的测试逻辑，具体如下：参考图18，写分频器1013包括：四相时钟产生电路801，用于接收内部时钟信号PWCK，被配置为，基于内部时钟信号PWCK生成并行写入时钟Clk_W，在本实施例中，并行写入时钟Clk_W为周期相同的第一时钟信号WCK2TF0、第二时钟信号WCK2TR0、第三时钟信号WCK2TR1和第四时钟信号WCK2TF1；写时钟树1023包括：信号延时电路802，用于接收第一时钟信号WCK2TF0、第二时钟信号WCK2TR0、第三时钟信号WCK2TR1、第四时钟信号WCK2TF1和延时命令，被配置为，基于延时命令，分别对第一时钟信号WCK2TF0、第二时钟信号WCK2TR0、第三时钟信号WCK2TR1和第四时钟信号WCK2TF1进行信号延时，且第一时钟信号WCK2TF0、第二时钟信号WCK2TR0、第三时钟信号WCK2TR1和第四时钟信号WCK2TF1之间的延时不同。
在一个例子中，四相时钟产生电路801内部的信号延迟较大，对应于四相时钟产生电路801的K值较大，此时生成的第一时钟信号WCK2TR0的周期可以为内部时钟信号PWCK的周期的5倍及以上；在另一个例子中，四相时钟产生电路801内部的信号延迟较小，对应于四相时钟产生电路801的K值较小，此时生成的第一时钟信号WCK2TR0的周期可以为内部时钟信号PWCK的周期的4倍及以下；参考图19和图20，需要说明的是，存储器一般采用双沿采样，即在信号上升沿下降沿都进行数据采样，即一个时钟周期传输两次数据，在后续拆分为四相位时钟后，若基于每个时钟采样一次，则对应于两个周期的内部时钟信号PWCK的采样次数，因此，在本实施例中，以第一时钟信号 WCK2TR0的周期为内部时钟信号PWCK的周期的2倍(即K＝2)为例进行具体说明，并不构成对本实施例的限定，在具体使用于可以根据所需生成时钟的频率和存储器内部时钟信号PWCK的频率，相应设置四相时钟产生电路801的信号延时。可以理解的是，由于第一时钟信号WCK2TR0、第二时钟信号WCK2TF0、第三时钟信号WCK2TR1和第四时钟信号WCK2TF1的周期相同，此时第二时钟信号WCK2TF0、第三时钟信号WCK2TR1和第四时钟信号WCK2TF1的周期也为内部时钟信号WCK的周期的2倍。
信号延时电路802对第一时钟信号WCK2TR0延时后生成第一延时时钟信号WCK2TWRTR0，对第二时钟信号WCK2TF0延时后生成第二延时时钟信号WCK2TWRTF0，对第三时钟信号WCK2TR1延时后生成第三延时时钟信号WCK2TWRTR1，对第四时钟信号WCK2TF1延时后生成第四延时时钟信号WCK2TWRTF1。参考图19和图20，第二延时时钟信号WCK2TWRTF0相对于第一延时时钟信号WCK2TWRTR0的延时为Ts1，第三延时时钟信号WCK2TWRTR1相对于第二延时时钟信号WCK2TWRTF0的延时为Ts2，第四延时时钟信号WCK2TWRTF1相对于第三延时时钟信号WCK2TWRTR1的延时为Ts3，第一延时时钟信号WCK2TWRTR0相对于第四延时时钟信号WCK2TWRTF1的延时为Ts4。
在本实施例中，延时命令包括第一延时命令cmR0、第二延时命令cmF0、第三延时命令cmR1和第四延时命令cmF1，相应地，信号延时电路802包括第一延时子电路901、第二延时子电路902、第三延时子电路903和第四延时子电路904。
其中，第一延时子电路901用于根据第一延时命令cm R0对第一时钟信号WCK2TF0进行信号延时，以生成第一延时时钟信号WCK2TWRTR0；第二延时子电路902用于根据第二延时命令cm F0对第二时钟信号WCK2TF0进行信号延时，以生成第二延时时钟信号WCK2TWRTF0；第三延时子电路903用于根据第三延时命令cm R1对第三时钟信号WCK2TR1进行信号延时，以生成第三延时时钟信号WCK2TWRTR1，第四延时子电路904用于根据第四延时命令cm F1对第四时钟信号WCK2TF1进行信号延时，以生成第四延时时钟信号WCK2TWRTF1。
在一个例子中，第一延时子电路901包括：第一一延时反相器811，输入端用于接收第一时钟信号WCK2TF0；第一二延时反相器812，输入端连接第一一延时反相器811；第一三延时反相器813，输入端连接第一二延时反相器812；第一四延时反相器814，输入端连接第一三延时反相器813，输出端用于输出延时后的第一时钟信号，即第一延时时钟信号WCK2TWRTR0；第一充放电模块851，一端连接第一一延时反相器811的输出端，另一端耦合低电位电源节点，低电位电源节点用于接收低电平；第五充放电模块855，一端连接第一二延时反相器812的输出端，另一端耦合低电位电源节点；第一充放电模块851和第五充放电模块855的充放电能力根据第一延时命令cm R0调节。需要说明的是，在其他实施例中，第一充放电模块851和第五充放电模块855的另一端还可以耦合高电位电源节点，高电位电源节点用于接收高电平。
在一个例子中，第二延时子电路902包括：第二一延时反相器821，输入端用于接收第二时钟信号WCK2TF0；第二二延时反相器822，输入端连接第二一延时反相器821；第二三延时反相器823，输入端连接第二二延时反相器822；第二四延时反相器824，输入端连接第二三延时反相器823，输出端用于输出延时后的第二时钟信号，即第二延时时钟信号WCK2TWRTF0；第二充放电模块852，一端连接第二一延时反相器821的输出端，另一端耦合低电位电源节点，低电位电源节点用于接收低电平；第六充放电模块856，一端连接第二二延时反相器822的输出端，另一端耦合低电位电源节点；第二充放电模块852和第六充放电模块856的充放电能力根据第二延时命令cm F0调节。需要说明的是，在其他实施例中，第二充放电模块852和第六充放电模块856的另一端还可以耦合高电位电源节点，高电位电源节点用于接收高电平。
在一个例子中，第三延时子电路903包括：第三一延时反相器831，输入端用于接收第三时钟信号WCK2TR1；第三二延时反相器832，输入端连接第三一延时反相器831；第三三延时反相器833，输入端连接第三二延时反相器832；第三四延时反相器834，输入端连接第三三延时反相器833，输出端用于输出延时后的第三时钟信号，即第三延时时钟信号WCK2TWRTR1；第三充放电模块853，一端连接第三一延时反相器831的输出端，另一端耦合低电位电源节点，低电位电源节点用于接收低电平；第七充放电模块857，一端连接第三二延时反相器832的输出端，另一端耦合低电位电源节点； 第三充放电模块853和第七充放电模块857的充放电能力根据第三延时命令cm R1调节。需要说明的是，在其他实施例中，第三充放电模块853和第七充放电模块857的另一端还可以耦合高电位电源节点，高电位电源节点用于接收高电平。
在一个例子中，第四延时子电路904包括：第四一延时反相器841，输入端用于接收第四时钟信号WCK2TF1；第四二延时反相器842，输入端连接第四一延时反相器841；第四三延时反相器843，输入端连接第四二延时反相器842；第四四延时反相器844，输入端连接第四三延时反相器843，输出端用于输出延时后的第四时钟信号，即第四延时时钟信号WCK2TWRTF1；第四充放电模块854，一端连接第四一延时反相器841的输出端，另一端耦合低电位电源节点，低电位电源节点用于接收低电平；第八充放电模块858，一端连接第四二延时反相器842的输出端，另一端耦合低电位电源节点；第四充放电模块854和第八充放电模块858的充放电能力根据第四延时命令cm F1调节。需要说明的是，在其他实施例中，第四充放电模块854和第八充放电模块858的另一端还可以耦合高电位电源节点，高电位电源节点用于接收高电平。
具体地，对于第一充放电模块851、第二充放电模块852、第三充放电模块853和第四充放电模块854，可存储电荷越多，放电速度越快，对信号上升沿的延时越高；对于第五充放电模块855、第六充放电模块856、第七充放电模块857、第八充放电模块858，可存储电荷越多，充电速度越快，对信号下降沿的延时越高；通过调节第一充放电模块851、第二充放电模块852、第三充放电模块853、第四充放电模块854、第五充放电模块855、第六充放电模块856、第七充放电模块857和第八充放电模块858的充放电能力，从而对第一时钟信号WCK2TF0、第二时钟信号WCK2TR0、第三时钟信号WCK2TR1和第四时钟信号WCK2TF1进行不同程度的延时。
同时，由于第一充放电模块851和第五充放电模块855基于同一延时命令控制，即对第一时钟信号WCK2TF0的上升沿和下降沿进行相同程度的延时，以保证不改变第一时钟信号WCK2TF0的占空比；由于第二充放电模块852和第六充放电模块856基于同一延时命令控制，即对第二时钟信号WCK2TR0的上升沿和下降沿进行相同程度的延时，以保证不改变第二时钟信号WCK2TR0的占空比；由于第三充放电模块853和第七充放电模块857基于同一延时命令控制，即对第三时钟信号WCK2TR1的上升沿和下降沿进行相同程度的延时，以保证不改变第三时钟信号WCK2TR1的占空比；由于第四充放电模块854和第八充放电模块858基于同一延时命令控制，即对第四时钟信号WCK2TF1的上升沿和下降沿进行相同程度的延时，以保证不改变第四时钟信号WCK2TF1的占空比。
在本实施例中，第一充放电模块851、第二充放电模块852、第三充放电模块853、第四充放电模块854、第五充放电模块855、第六充放电模块856、第七充放电模块857和第八充放电模块858通过电容实现，电容的充放电能力取决于电容的最大存储电荷量C和放电电流I，具体地，放电电流I由一个偏置晶体管控制，延时命令cm通过控制放电电流I的控制相应第一充放电模块851、第二充放电模块852、第三充放电模块853、第四充放电模块854、第五充放电模块855、第六充放电模块856、第七充放电模块857和第八充放电模块858的延迟性能。
需要说明的是，在一些实施例中，第一延时子电路901、第二延时子电路902、第三延时子电路903和第四延时子电路904耦合的低电位电源节点所接收的低电平可调，从而实现对第一延时子电路901、第二延时子电路902、第三延时子电路903和第四延时子电路904充放电能力的整体调整。
在理想情况下，通过信号延时电路802即可生成等距的(Ts1＝Ts2＝Ts3＝Ts4)的四相时钟信号，但由于实际器件偏差等原因，由信号延时电路802生成的四相时钟信号的相应延迟并不相等，即无法保证Ts1＝Ts2＝Ts3＝Ts4。
信号加载电路805基于第一延时时钟信号WCK2TWRTR0、第二延时时钟信号WCK2TWRTF0、第三延时时钟信号WCK2TWRTR1和第四延时时钟信号WCK2TWRTF1生成第一指示信号Pup和第二指示信号Pdn。具体地，参考图18，信号加载模块805包括：数据产生模块803，用于产生四比特的第一加载数据Data1和第二加载数据Data2。数据加载模块804，用于根据延时后的第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号对第一加载数据Data1进行采样以生成第一指示信号Pup；其中，当时钟信号采样沿对应的第一加载数据Data1为高电平时，生成的第一指示信号Pup为高电平当时钟信号采样沿对应的第一加载数据Data1为低电平时，生成的第一指示信号Pup为低电平；数据加载模块804还用于根据延时后的第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号对第 二加载数据Data2进行采样以生成第二指示信号Pdn；其中，当时钟信号采样沿对应的第二加载数据Data2为高电平时，生成的第二指示信号Pdn为高电平。对于数据产生模块803，产生的第一加载数据Data1和第二加载数据Data2的比特位与驱动数据加载模块804的时钟信号的数量相等，由于本实施例中数据加载模块804可由四个时钟信号驱动，因此第一加载数据Data1和第二加载数据Data2为四比特。在一些实施例中，数据产生模块803基于发生控制信号控制开启，通过控制仅在使用时启动数据产生模块，从而节约时钟产生电路的功耗。
测试电路400，连接信号加载电路805被配置为，基于第一指示信号Pup和第二指示信号Pdn进行占空比测试。具体地，测试电路400的输出信号用于表征第一指示信号Pup和第二指示信号Pdn的大小关系，若测试电路的输出信号为高电平，则第一指示信号Pup大于第二指示信号Pdn，若测试电路的输出信号为低电平，则第二指示信号Pdn不小于第一指示信号Pup。
具体地，基于延时得到的第一延迟时钟信号WCK2TWRTR0、第二延迟时钟信号WCK2TWRTF0和第三延迟时钟信号WCK2TWRTR1生成第一指示信号Pup，基于延时得到的第三延迟时钟信号WCK2TWRTR1、第四延迟时钟信号WCK2TWRTF1和第一延迟时钟信号WCK2TWRTR0生成第二指示信号Pdn；结合图19和图20可知，此时第一指示信号Pup的占空比为(Ts1+Ts2)/(Ts1+Ts2+Ts3+Ts4)，第二指示信号Pdn的占空比为(Ts3+Ts4)/(Ts1+Ts2+Ts3+Ts4)。若测试电路400输出信号为高电平，则证明第一指示信号Pup的占空比大于第二指示信号Pdn的占空比，即(Ts1+Ts2)＞(Ts3+Ts4)，此时可以增大对第一时钟信号并同时减小对第二时钟信号和第三时钟信号的延时，即减小Ts1+Ts2并增大Ts3+Ts4，以使(Ts1+Ts2)＝(Ts3+Ts4)，且Ts1+Ts2+Ts3+Ts4的和不变，以不改变四相时钟信号的整体周期，若测试电路400输出信号为低电平，则证明第一指示信号Pup的占空比小于第二指示信号Pdn的占空比，即(Ts1+Ts2)＜(Ts3+Ts4)，此时可以减小对第一时钟信号的延时并同时增大对第二时钟信号和第三时钟信号的延时，即增大Ts1+Ts2和减小Ts3+Ts4，(Ts1+Ts2)＝(Ts3+Ts4)，且Ts1+Ts2+Ts3+Ts4的和不变，以不改变四相时钟信号的整体周期。需要说明的是，上述示例中并未体现第一指示信号Pup和第二指示信号Pdn与占空比结果无关的延时时钟信号的采样，在实际应用中，第一指示信号Pup和第二指示信号Pdn都基于第一延迟时钟信号WCK2TWRTR0、第二延迟时钟信号WCK2TWRTF0、第三延迟时钟信号WCK2TWRTR1和第四延迟时钟信号WCK2TWRTF1进行采用。
基于延时后的第一时钟信号WCK2TWRTR0和第二时钟信号WCK2TWRTF0生成第三指示信号Pup，基于延时后的第二时钟信号WCK2TWRTF0和第三延迟时钟信号WCK2TWRTR1生成第四指示信号Pdn；结合图19和图20可知，此时第三指示信号Pup的占空比为Ts1/(Ts1+Ts2),第四指示信号Pdn的占空比为Ts2/(Ts1+Ts2)。若测试电路400输出信号为高电平，则证明第三指示信号Pup的占空比大于第四指示信号Pdn的占空比，即Ts1＞Ts2，此时可以增大对第一时钟信号的延时并减小对第二时钟信号的延时，即减小Ts1并增大Ts2，以使Ts1＝Ts2，且第一时钟信号和第二时钟信号的信号总延时不变，即Ts1+Ts2的和不变，以保证(Ts1+Ts2)＝(Ts3+Ts4)；若测试电路400输出信号为低电平，则证明第三指示信号Pup的占空比小于第四指示信号Pdn的占空比，即Ts1＜Ts2，此时可以减小对第一时钟信号的延时并增大对第二时钟信号的延时，即增大Ts1并减小Ts2，以使Ts1＝Ts2，且第一时钟信号和第二时钟信号的信号总延时不变，即Ts1+Ts2的和不变，以保证(Ts1+Ts2)＝(Ts3+Ts4)。需要说明的是，上述示例中并未体现第三指示信号Pup和第四指示信号Pdn与占空比结果无关的延时时钟信号的采样，在实际应用中，第三指示信号Pup和第四指示信号Pdn都基于第一延迟时钟信号WCK2TWRTR0、第二延迟时钟信号WCK2TWRTF0、第三延迟时钟信号WCK2TWRTR1和第四延迟时钟信号WCK2TWRTF1进行采用。
基于延时后的第三时钟信号WCK2TWRTR1和第四时钟信号WCK2TWRTF1生成第五指示信号Pup，基于延时后的第四时钟信号WCK2TWRTF1和第一时钟信号WCK2TWRTR0生成第六指示信号Pdn；结合图19和图20可知，此时第五指示信号Pup的占空比为Ts3/(Ts3+Ts4),第六指示信号Pdn的占空比为Ts4/(Ts3+Ts4)。若测试电路400输出信号为高电平，则证明第五指示信号Pup的占空比大于第六指示信号Pdn的占空比，即Ts3＞Ts4此时可以增大对第三时钟信号的延时并减小对第四时钟信号的延时，即减小Ts3并增大Ts4，以使Ts3＝Ts4，且第三时钟信号和第四时钟信号的信号总延时不变，即Ts3+Ts4的和不变，以保证(Ts1+Ts2)＝(Ts3+Ts4)；若测试电路400输出信号为低电平，则证明第五指示信号Pup的占空比小于第六指示信号Pdn的占空比，即Ts3＜Ts4，此时可以增大 对第三时钟信号的延时并减小对第四时钟信号的延时，即增大Ts3并减小Ts4，以使Ts3＝Ts4，且第三时钟信号和第四时钟信号的信号总延时不变，即Ts3+Ts4的和不变，以保证(Ts1+Ts2)＝(Ts3+Ts4)。需要说明的是，上述示例中并未体现第五指示信号Pup和第六指示信号Pdn与占空比结果无关的延时时钟信号的采样，在实际应用中，第五指示信号Pup和第六指示信号Pdn都基于第一延迟时钟信号WCK2TWRTR0、第二延迟时钟信号WCK2TWRTF0、第三延迟时钟信号WCK2TWRTR1和第四延迟时钟信号WCK2TWRTF1进行采用。
需要说明的是，上述示例描述对第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的延迟皆可调整的情况；在具体实施中，由于第一时钟信号WCK2TR0的上升沿需要与内部时钟信号WCK_T的上升沿对齐，即对第一时钟信号WCK2TR0的延时无法调整，此时，忽略对第一时钟信号WCK2TR0的延时改变，上述示例依然适用。
继续参考图1，在一些实施例中，存储器还包括，第二输出组件1200，连接写时钟树1023的输出端，用于将并行写入时钟Clk_W输出到外部测试系统10，外部测试系统10用于测试并行写入时钟Clk_W是否为等距时钟，即通过对写时钟树1023、信号加载电路805和测试电路400的测试和调整后，判断实际获得的并行写入时钟Clk_W是否为等距时钟。
此时，测试控制信号其中一值被配置为，控制存储器将写时钟路径1003输出的并行写入时钟输出到外部测试系统10进行占空比检测；此时导通信号PathEns用于导通信号产生器100与信号转换模块1002之间的数据传输路径、信号转换模块1002与写时钟路径1003之间的数据传输路径、以及写时钟路径1003与外部测试系统之间的数据传输路径，以判断并行写入时钟Clk_W是否为等距时钟。
在一些实施例中，信号转换模块1002还用于接收具有预设占空比的外部时钟信号WCK，以及根据外部时钟信号WCK生成内部时钟信号PWCK，其中外部时钟信号WCK为存储器正常工作所需接收的时钟信号。
相应地，参考图1，存储器还包括：选择模块1001，具有第一输入端、第二输入端以及输出端，第一输入端用于接收参考测试信号AltWck，第二输入端用于接收外部时钟信号WCK，输出端连接信号转换模块1002的输入端，控制端用于接收测试控制信号DcmCtrl，并基于测试控制信号DcmCtrl连通第一输入端和输出端或者连接第二输入端和输出端。
在一个例子中，参考图21，第一输入MOS管，源极连接振幅调整模块103的输出端，漏极用于输出参考测试信号AltWck；第二输入MOS管，源极连接第一输入MOS管的漏极，漏极连接第一输入端MOS管的源极，第三输入MOS管，源极用于接收外部时钟信号WCK，漏极连接第一输入MOS管的漏极，并用于输出外部时钟信号WCK，第一输入MOS管的栅极、第二输入MOS管的栅极和第三输入MOS管的栅极用于接收测试控制信号DcmCtrl，且第一输入MOS管的栅极和第二输入MOS管的栅极接收的信号为反相信号，即第一输入端MOS管和第二输入MOS管其中一者的栅极用于接收测试控制信号DcmCtrl，另一者的栅极用于接收反相测试控制信号DcmCtrl-。在一些实施例中，第一输入MOS管和第三输入MOS管中仅有一者接收时钟信号，此时两者可同时导通；在另一些实施例中，第一输入MOS管和第三输入MOS管择一导通。
相应地，继续参考图1，对于测试控制信号DcmCtrl，具体如下：
测试控制信号DcmCtrl其中一值被配置为，控制存储器将生成的中间测试信号Pretest输出到外部测试系统进行占空比检测；此时导通信号PathEns用于导通信号产生器100与外部测试系统10之间的数据传输路径，以获取占空比满足预设占空比的参考测试信号AltWck。
测试控制信号DcmCtrl其中一值被配置为，选择基于测试电路对参考测试信号AltWck进行占空比测试；此时导通信号PathEns用于导通信号产生器100与测试电路400之间的数据传输路径，以通过已知占空比的参考测试信号AltWck测试测试电路400的测试功能是否正常。
测试控制信号DcmCtrl其中一值被配置为，选择基于测试电路400对信号转换模块1002基于参考测试信号AltWck输出的内部时钟信号PWCK进行占空比测试；此时，导通信号PathEns用于导通信号产生器100与选择模块1001之间的数据传输路径，选择模块1001与信号转换模块1002之 间的数据传输路径，以及信号转换模块1002与测试电路400之间的数据传输路径，以通过测试电路400测试信号转换模块1002基于参考测试信号AltWck工作时的功能是否正常。
测试控制信号DcmCtrl其中一值被配置为，选择基于测试电路400对信号转换模块1002基于外部时钟信号WCK输出的内部时钟信号PWCK进行占空比测试；此时，导通信号PathEns用于导通选择模块1001与数据焊盘(用于接收外部时钟信号WCK)之间的数据传输路径，选择模块1001与信号转换模块1002之间的数据传输路径，以及信号转换模块1002与测试电路400之间的数据传输路径，以通过测试电路400测试信号转换模块1002基于外部时钟信号WCK工作时的功能是否正常。
测试控制信号DcmCtrl其中一值被配置为，选择基于测试电路400对读时钟路径1004基于参考测试信号AltWck输出的串行读取时钟Clk_R2进行占空比测试；此时，导通信号PathEns用于导通信号产生器100与选择模块1001之间的数据传输路径，选择模块1001与信号转换模块1002之间的数据传输路径、信号转换模块1002与读时钟路径1004之间的数据传输路径、以及读时钟路径1004与测试电路400之间的数据传输路径，以通过测试电路400测试读时钟路径1004基于参考测试信号AltWck工作时的功能是否正常。
测试控制信号DcmCtrl其中一值被配置为，选择基于测试电路400对读时钟路径1004基于外部时钟信号WCK输出的串行读取时钟Clk_R2进行占空比测试；此时，导通信号PathEns用于导通选择模块1001与数据焊盘(用于接收外部时钟信号WCK)之间的数据传输路径，选择模块1001与信号转换模块1002之间的数据传输路径、信号转换模块1002与读时钟路径1004之间的数据传输路径、以及读时钟路径1004与测试电路400之间的数据传输路径，以通过测试电路400测试读时钟路径1004基于外部时钟信号WCK工作时的功能是否正常。
测试控制信号DcmCtrl其中一值被配置为，选择基于测试电路400对写时钟路径1003基于参考测试信号AltWck输出的第一指示信号Pup和第二指示信号Pdn进行占空比测试；此时导通信号PathEns用于导通信号产生器100与选择模块1001之间的数据传输路径，选择模块1001与信号转换模块1002之间的数据传输路径、信号转换模块1002与写时钟路径1003之间的数据传输路径、以及写时钟路径1003与测试电路400之间的数据传输路径，以反复测试调整基于参考测试信号AltWck生成等距的并行写入时钟Clk_W。
测试控制信号DcmCtrl其中一值被配置为，选择基于测试电路400对写时钟路径1003基于外部时钟信号WCK输出的第一指示信号Pup和第二指示信号Pdn进行占空比测试；此时导通信号PathEns用于导通选择模块1001与数据焊盘(用于接收外部时钟信号WCK)之间的数据传输路径，选择模块1001与信号转换模块1002之间的数据传输路径、信号转换模块1002与写时钟路径1003之间的数据传输路径、以及写时钟路径1003与测试电路400之间的数据传输路径，以反复测试调整基于外部时钟信号WCK生成等距的并行写入时钟Clk_W。
测试控制信号DcmCtrl其中一值被配置为，控制存储器将基于参考测试信号AltWck生成的并行写入时钟Clk_W输出到外部测试系统10进行占空比检测；此时导通信号PathEns用于导通信号产生器100与选择模块1001之间的数据传输路径，选择模块1001与信号转换模块1002之间的数据传输路径、信号转换模块1002与写时钟路径1003之间的数据传输路径、以及写时钟路径1003与外部测试系统之间的数据传输路径，以判断基于参考测试信号AltWck生成的并行写入时钟Clk_W是否为等距时钟。
测试控制信号DcmCtrl其中一值被配置为，控制存储器将基于外部时钟信号WCK生成的并行写入时钟Clk_W输出到外部测试系统10进行占空比检测；此时导通信号PathEns用于导通选择模块1001与数据焊盘(用于接收外部时钟信号WCK)之间的数据传输路径，选择模块1001与信号转换模块1002之间的数据传输路径、信号转换模块1002与写时钟路径1003之间的数据传输路径、以及写时钟路径1003与外部测试系统之间的数据传输路径，以判断基于外部时钟信号WCK生成的并行写入时钟Clk_W是否为等距时钟。
需要说明的是，本公开实施例中提到的“驱动能力”，指晶体管在栅极开启程度相同的情况下，晶体管源漏电流的驱动能力。
本实施例通过测试电路400对参考测试信号AltWck进行占空比测试，其中参考测试信号 AltWck的占空比已知，用于判断测试电路400的占空比测试功能是否正常，若测试电路400的占空比测试功能正常，再基于测试控制信号DcmCtrl选择不同测试模块，通过测试电路400依次对不同测试模块输出信号的占空比进行测试，以测试不同测试模块所输出的信号的占空比是否正常，从而完成对不同测试模块的功能测试。
需要说明的是，上述实施例所提供的信号检测系统中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的信号检测系统实施例。
本公开另一实施例提供一种存储器检测方法，基于上述实施例提供的信号检测系统对存储器中各测试路径的输出信号进行占空比测试，通过选择不同测试路径，以测试高速时钟信号在不同传输路径中的占空比是否满足要求，以保证存储器数据处理的稳定性。
本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。

Claims (15)

  1. 信号检测系统，应用于存储器，用于根据所述存储器中的测试电路对所述存储器中各测试路径的输出信号进行占空比测试，包括：
    信号产生器，基于外部参数生成参考测试信号，所述参考测试信号为满足预设占空比的时钟信号；
    基于所述测试电路对所述参考测试信号进行占空比测试，以判断所述测试电路的功能是否正常；
    若所述测试电路的功能正常，基于测试控制信号依次选择不同测试模块，并基于所述测试电路对所选择的所述测试模块所输出的信号进行占空比测试；所述测试模块包括：信号转换模块和写时钟路径；其中，所述信号转换模块用于根据所述参考测试信号生成内部时钟信号；所述写时钟路径包括：写分频器、写时钟树和信号加载电路；
    所述写分频器用于根据所述内部时钟信号生成并行写入时钟，所述写时钟树用于调节所述并行写入时钟的延迟，所述信号加载电路用于根据所述并行写入时钟对预设数据进行采样，以生成第一指示信号和第二指示信号。
  2. 根据权利要求1所述的信号检测系统，其中，所述测试模块还包括：读时钟路径，所述读时钟路径包括：读分频器和读时钟转换电路，所述读分频器用于根据所述内部时钟信号生成并行读取时钟，所述读时钟转换电路用于根据所述并行读取时钟生成串行读取时钟。
  3. 根据权利要求2所述的信号检测系统，其中，所述存储器还包括：时钟驱动器，输入端连接所述信号转换模块的输出端，输出端连接所述测试电路。
  4. 根据权利要求3所述的信号检测系统，其中，所述测试控制信号设置为至少四比特位，以构成多个信号值；
    其中一值被配置为，选择基于所述测试电路对所述参考测试信号进行占空比测试；
    其中一值被配置为，控制所述信号转换模块接收所述参考测试信号，并基于所述测试电路对所述信号转换模块输出的所述内部时钟信号进行占空比测试；
    其中一值被配置为，选择基于所述测试电路对所述读时钟路径输出的所述串行读取时钟进行占空比测试；
    其中一值被配置为，选择基于所述测试电路对所述写时钟路径输出的所述第一指示信号和所述第二指示信号进行占空比测试；
    所述存储器还包括逻辑控制信号电路，被配置为，识别所述测试控制信号并基于所述测试控制信号生成对应于所述测试控制信号的导通信号，所述导通信号用于选择导通对应的所述测试模块，以形成不同的测试路径，不同的所述测试路径向所述测试电路或所述外部测试系统输出待测试信号。
  5. 根据权利要求3所述的信号检测系统，其中，所述生成模块包括：
    振荡产生模块，被配置为，基于振荡控制信号产生初始振荡信号，所述振荡控制信号用于调整产生的所述初始振荡信号的频率；
    占空比修正模块，连接所述振荡产生模块的输出端，被配置为，基于占空比控制信号对所述初始振荡信号的占空比进行调整，以生成中间测试信号；
    振幅调整模块，连接占空比修正模块的输出端，被配置为，基于振幅调整信号对所述中间测试信号的幅值进行调整，以生成所述参考测试信号。
  6. 根据权利要求5所述的信号检测系统，其中，所述存储器包括：
    第一输出组件，连接所述占空比修正模块的输出端，用于将所述中间测试信号输出到外部测试系统，所述外部测试系统用于测试所述中间测试信号是否满足所述预设占空比。
  7. 根据权利要求5所述的信号检测系统，其中，所述存储器包括：
    所述信号转换模块还用于接收具有所述预设占空比的外部时钟信号，以及根据所述外部时钟信号 生成所述内部时钟信号；
    第二输出组件，连接所述写时钟树的输出端，用于将所述并行写入时钟输出到外部测试系统，所述外部测试系统用于测试所述并行写入时钟是否为等距时钟。
  8. 根据权利要求7所述的信号检测系统，其中，所述存储器还包括：
    选择模块，具有第一输入端、第二输入端以及输出端，所述第一输入端用于接收所述参考测试信号，所述第二输入端用于接收所述外部时钟信号，所述输出端连接于所述信号转换模块的输入端，以及用于接收所述测试控制信号，并基于所述测试控制信号连通所述第一输入端和输出端或者连通所述第二输入端和所述输出端。
  9. 根据权利要求8所述的信号检测系统，其中，所述选择模块包括：
    第一输入MOS管，源极连接所述振幅调整模块的输出端，漏极用于输出所述参考测试信号；
    第二输入MOS管，源极连接所述第一输入MOS管的漏极，漏极连接所述第一输入MOS管的源极；
    第三输入MOS管，源极用于接收所述外部时钟信号，漏极连接所述第一输入MOS管的漏极，并用于输出所述外部时钟信号；
    所述第一输入MOS管的栅极、所述第二输入MOS管的栅极和所述第三输入MOS管的栅极用于接收所述测试控制信号，且所述第一输入MOS管的栅极和所述第二输入MOS管的栅极接收的信号为反相信号。
  10. 根据权利要求8所述的信号检测系统，其中，所述测试控制信号还包括：
    其中一值被配置为，控制所述存储器将生成的中间测试信号输出到外部测试系统进行占空比检测；
    其中一值被配置为，选择基于所述测试电路对所述参考测试信号进行占空比测试；
    其中一值被配置为，控制所述存储器将基于所述外部时钟信号生成的所述并行写入时钟输出到所述外部测试系统进行占空比检测；
    其中一值被配置为，控制所述存储器将基于所述参考测试信号生成的所述并行写入时钟输出到所述外部测试系统进行占空比检测；
    其中一值被配置为，选择基于所述测试电路对所述信号转换模块基于所述参考测试信号输出的所述内部时钟信号进行占空比测试；
    其中一值被配置为，选择基于所述测试电路对所述信号转换模块基于所述外部时钟信号输出的所述内部时钟信号进行占空比测试；
    其中一值被配置为，选择基于所述测试电路对所述读时钟路径基于所述参考测试信号输出的所述串行读取时钟进行占空比测试；
    其中一值被配置为，选择基于所述测试电路对所述写时钟路径基于所述参考测试信号输出的所述第一指示信号和所述第二指示信号进行占空比测试；
    其中一值被配置为，选择基于所述测试电路对所述读时钟路径基于所述外部时钟信号输出的所述串行读取时钟进行占空比测试；
    其中一值被配置为，选择基于所述测试电路对所述写时钟路径基于所述外部时钟信号输出的所述第一指示信号和所述第二指示信号进行占空比测试。
  11. 根据权利要求5所述的信号检测系统，其中，所述振幅调整模块包括：
    第一信号产生单元，被配置为，基于所述中间测试信号上拉输出信号，基于反相测试信号下拉输出信号，以生成与所述中间测试信号相位相同的所述参考测试信号；
    第二信号产生单元，被配置为，基于所述反相测试信号上拉输出信号，基于所述中间测试信号下 拉输出信号，以生成与所述反相测试信号相位相同的反相参考测试信号；
    其中，所述中间测试信号和所述反相测试信号幅值相同，相位相反。
  12. 根据权利要求1所述的信号检测系统，其中，包括：
    所述写分频器包括：四相时钟产生电路，用于接收所述内部时钟信号，被配置为，基于所述内部时钟信号生成周期相同的第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；
    所述写时钟树包括：信号延时电路，用于接收所述第一时钟信号、所述第二时钟信号、所述第三时钟信号、所述第四时钟信号和延时命令，被配置为，基于所述延时命令，分别对所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号进行信号延时，且所述第一时钟信号、所述第二时钟信号、第三时钟信号和第四时钟信号之间的延时不同。
  13. 根据权利要求12所述的信号检测系统，其中，包括：
    所述延时命令包括第一延时命令、第二延时命、第三延时命令和第四延时命令；所述延时电路包括第一延时子电路、第二延时子电路、第三延时子电路和第四延时子电路；
    其中，所述第一延时子电路用于根据所述第一延时命令对所述第一时钟信号进行信号延时，所述第二延时子电路用于根据所述第二延时命令对所述第二时钟信号进行信号延时，所述第三延时子电路用于根据所述第三延时命令对所述第三时钟信号进行信号延时，所述第四延时子电路用于根据所述第四延时命令对所述第四时钟信号进行信号延时。
  14. 根据权利要求12所述的信号检测系统，其中，所述信号加载电路包括：
    数据产生模块，用于产生四比特的第一加载数据和第二加载数据；
    数据加载模块，用于根据所述第一时钟信号、所述第二时钟信号、所述第三时钟信号、所述第四时钟信号对所述第一加载数据进行采样以生成所述第一指示信号；其中，当所述时钟信号采样沿对应的第一加载数据为高电平时，生成的所述第一指示信号为高电平；
    所述数据加载模块还用于根据所述第一时钟信号、所述第二时钟信号、所述第三时钟信号、所述第四时钟信号对所述第二加载数据进行采样以生成所述第二指示信号；其中，当所述时钟信号采用沿对应的第二加载数据为高电平时，生成的所述第二指示信号为高电平。
  15. 一种存储器检测方法，基于权利要求1～14任一项信号检测系统对存储器中各测试路径的输出信号进行占空比测试。
PCT/CN2022/093714 2022-04-26 2022-05-19 信号检测系统和存储器检测方法 WO2023206659A1 (zh)

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