WO2023206636A1 - 延迟电路及半导体存储器 - Google Patents

延迟电路及半导体存储器 Download PDF

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Publication number
WO2023206636A1
WO2023206636A1 PCT/CN2022/092997 CN2022092997W WO2023206636A1 WO 2023206636 A1 WO2023206636 A1 WO 2023206636A1 CN 2022092997 W CN2022092997 W CN 2022092997W WO 2023206636 A1 WO2023206636 A1 WO 2023206636A1
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Prior art keywords
signal
input terminal
target
output
terminal
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PCT/CN2022/092997
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English (en)
French (fr)
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杨宇
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长鑫存储技术有限公司
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Priority to US18/230,096 priority Critical patent/US20230378948A1/en
Publication of WO2023206636A1 publication Critical patent/WO2023206636A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of integrated circuits, and in particular, to a delay circuit and a semiconductor memory.
  • the signal transmission path in the traditional delay circuit is affected by the real-time environment, resulting in a deviation between the actual delay time and the preset delay time, which affects the stability and reliability of the integrated circuit.
  • a delay circuit and a semiconductor memory are provided.
  • the first aspect of the present disclosure provides a delay circuit, including a temperature compensation control module and a delay module.
  • the temperature compensation control module is used to compensate the enable signal according to the received initial control signal, the temperature signal of the real-time environment, and the temperature coefficient. and a temperature coefficient control signal to generate a target temperature compensation control signal;
  • the delay module is connected to the temperature compensation control module and is used to generate a temperature-compensated target delay signal based on the received target temperature compensation control signal and the initial delay signal.
  • the temperature compensation control module includes a target temperature compensation module, an addition module and a logic output module.
  • the target temperature compensation module is configured as follows: the first type input terminal is used to receive the temperature signal of the real-time environment, and the second type input terminal is used to receive the temperature signal of the real-time environment.
  • the control terminal is used to receive the initial selection signal, and the output terminal is used to output the target temperature compensation signal;
  • the adder module is configured as: the first type input terminal is used to receive the initial control signal, and the second type input The terminal is connected to the output terminal of the target temperature compensation module to receive the target temperature compensation signal, the carry input terminal is used to receive the initial carry signal, the first type output terminal is used to output the initial temperature compensation control signal, and the carry output terminal is used to output the target carry signal;
  • the logic output module is configured as follows: the first type input terminal is connected to the first type output terminal of the adding module to receive the initial temperature compensation control signal, the second type input terminal is connected to the carry output terminal of the adding module to receive the target carry signal, and the third type input terminal is connected to the carry output terminal of the adding module to receive the target carry signal.
  • the input terminal is used to receive the initial selection signal, perform logical processing on the initial temperature compensation control signal, the target carry signal and the initial selection signal, and then output the target temperature compensation control signal through
  • the adder module includes N cascaded adders, N>1, and N is a positive integer.
  • the carry output terminal of each stage adder is connected to the carry input terminal of the adjacent next stage adder.
  • the first The carry input terminal of the first-stage adder is used as the carry input terminal of the addition module and is used to receive the initial carry signal.
  • the carry output terminal of the last-stage adder is used as the carry output terminal of the addition module and is used to output the target carry signal; all levels of addition
  • the signal output terminals of the adder together constitute the first type output terminal of the adder module, and are connected to the first type input terminal of the logic output module; the first input terminals of the adders at all levels jointly constitute the first type input terminal of the adder module; each level The second input terminals of the adder together form a second type input terminal of the adder module.
  • the logic output module includes a target overflow prevention unit and N logic output units.
  • the target overflow prevention unit is configured as follows: a first type input terminal serves as a third type input terminal of the logic output module to receive an initial selection signal; The second type input terminal serves as the second type input terminal of the logic output module and is connected to the carry output terminal of the last stage adder; the first input terminal of the i-th logic output unit among the N logic output units is connected to the i-th stage adder.
  • each logic output unit The signal output end, the second input end of each logic output unit is connected to the first output end of the target overflow prevention unit, the third input end of each logic output unit is connected to the second output end of the target overflow prevention unit, each logic output unit
  • the target overflow prevention unit includes a first NOR gate and a first AND gate.
  • the first NOR gate is configured as follows: a first input terminal is used to receive an initial selection signal, and a second input terminal is connected to the last stage of addition.
  • the carry output terminal of the device serves as the first output terminal of the target overflow prevention unit, and is connected to the second input terminal of each logical output unit;
  • the first AND gate is configured as: the first input terminal is used to receive the initial selection signal, The second input terminal is connected to the carry output terminal of the last stage adder, and the output terminal is used as the second output terminal of the target overflow prevention unit, and is connected to the third input terminal of each logic output unit; wherein, the first terminal of the first NOR gate
  • the input terminal and the first input terminal of the first AND gate together constitute the first type input terminal of the target overflow prevention unit, and the second input terminal of the first NOR gate and the second input terminal of the first AND gate together constitute the target anti-overflow unit.
  • Type 2 input of the unit is the first input terminal is used to receive the initial selection signal, The second input terminal is connected to the carry output terminal of the last stage adder, and the output terminal is used as the second output terminal of the target overflow prevention unit, and is connected to the third input terminal of each logic output
  • the logic output unit includes a first inverter, a second NOR gate and a first OR gate.
  • the input terminal of the first inverter serves as the first input terminal of the logic output unit;
  • the second NOR gate is The configuration is: the first input terminal is connected to the output terminal of the first inverter, the second input terminal serves as the second input terminal of the logic output unit and is connected to the output terminal of the first NOR gate;
  • the first OR gate is configured as: An input terminal is connected to the output terminal of the second NOR gate, the second input terminal is used as the third input terminal of the logic output unit and is connected to the output terminal of the first AND gate, and the output terminal is used as the output terminal of the logic output unit.
  • the temperature signal of the real-time environment includes N sub-temperature signals
  • the target temperature compensation signal includes N sub-target temperature compensation signals
  • the target temperature compensation module includes N target temperature compensation units
  • the i-th target temperature compensation unit is configured as : The first input terminal is used to receive the i-th sub-temperature signal, the second input terminal is used to receive the temperature coefficient compensation enable signal, the control terminal is used to receive the initial selection signal, and the output terminal is used to provide the second input signal to the i-th stage adder.
  • the input terminal provides the i-th sub-target temperature compensation signal; i ⁇ (1, N], i is a positive integer; the first input terminal of each target temperature compensation unit jointly constitutes the first type input terminal of the target temperature compensation module, and each target The second input terminals of the temperature compensation units together constitute the second type input terminal of the target temperature compensation module, and the control terminals of each target temperature compensation unit jointly constitute the control terminal of the target temperature compensation module.
  • the target temperature compensation unit includes a first NAND gate and a selected output unit.
  • the first NAND gate is configured such that the first input terminal serves as the first input terminal of the target temperature compensation unit and is used to receive the sub-temperature. signal, the second input terminal serves as the second input terminal of the target temperature compensation unit, and is used to receive the temperature coefficient compensation enable signal, and the output terminal outputs the intermediate sub-temperature signal;
  • the selection output unit is configured as: the input terminal is connected to the first and non- At the output end of the gate, the control end serves as the control end of the target temperature compensation unit and is used to receive the initial selection signal.
  • the output end serves as the output end of the target temperature compensation unit and is used to output the sub-target temperature compensation signal; where, if the initial selection If the signal is high level, the sub-target temperature compensation signal and the intermediate sub-temperature signal are inverted signals. If the initial selection signal is low level, the sub-target temperature compensation signal and the intermediate sub-temperature signal are in-phase signals.
  • the temperature compensation control module further includes a temperature coefficient control module, and the temperature coefficient control module is configured as follows: a first input terminal for receiving a temperature coefficient compensation enable signal, and a second input terminal for receiving a temperature coefficient control signal, The third input terminal is used to receive the Nth sub-temperature signal, and the output terminal outputs an initial selection signal; wherein, the output terminal of the temperature coefficient control module is connected to the control terminal of the target temperature compensation module.
  • the temperature coefficient control module includes a first XOR gate and a second AND gate.
  • the first XOR gate is configured such that the first input terminal serves as the third input terminal of the temperature coefficient control module and is used to receive the third input terminal.
  • N sub-temperature signals the second input terminal serves as the second input terminal of the temperature coefficient control module, and is used to receive the temperature coefficient control signal;
  • the second AND gate is configured as: the first input terminal is connected to the output terminal of the first XOR gate , the second input terminal serves as the first input terminal of the temperature coefficient control module and is used to receive the temperature coefficient compensation enable signal, and the output terminal serves as the output terminal of the temperature coefficient control module and is used to output the initial selection signal.
  • the initial select signal and the initial carry signal are inverse signals of each other.
  • the initial control signal includes N sub-initial control signals
  • the first input end of the i-th stage adder is used to receive the i-th sub-initial control signal, i ⁇ (1, N], i is a positive integer.
  • the target temperature compensation control signal includes N sub-target temperature compensation control signals
  • the i-th logic output unit is used to output the i-th sub-target temperature compensation control signal.
  • the delay module includes N target delay units and N target logic input units; the input end of the first target delay unit is used to receive the initial delay signal; the i-th target logic input unit is configured as: the first The input terminal is connected to the input terminal of the i-th target delay unit, the second input terminal is connected to the output terminal of the i-th target delay unit, and the third input terminal is used to receive the i-th sub-target temperature compensation control signal; the N-th target logic input The output end of the unit serves as the output end of the delay module and is used to output the target delay signal; where, the input end of the jth target delay unit is connected to the output end of the j-1th target logic input unit, j ⁇ [2, N ], j is a positive integer.
  • the target logic input unit includes a second OR gate and a third AND gate
  • the second OR gate is configured such that: the first input terminal serves as the second input terminal of the target logic input unit, and the second input terminal serves as the target logic
  • the third input terminal of the input unit is used to receive the sub-target temperature compensation control signal;
  • the third AND gate is configured such that the first input terminal serves as the first input terminal of the target logic input unit, and the second input terminal is connected to the second OR gate
  • the output terminal serves as the output terminal of the target logic input unit.
  • a second aspect of the disclosure provides a semiconductor memory including the delay circuit in any embodiment of the disclosure.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the temperature compensation control module is used to generate the target temperature compensation control signal according to the received initial control signal, the temperature signal of the real-time environment, the temperature coefficient compensation enable signal and the temperature coefficient control signal, And use the target temperature compensation control signal to control the delay module to compensate for the change in signal delay time due to temperature changes, and obtain the target delay signal after temperature compensation, so that the actual delay time of the delay circuit reaches the expected value, realizing the real-time environment according to The temperature signal dynamically compensates the target delay signal generated by the delay circuit to avoid the situation where the actual generated target delay signal is significantly different from the required target delay signal due to temperature changes, improves the stability and accuracy of signal transmission, and improves Performance and reliability of integrated circuits.
  • the delay circuit and semiconductor memory provided by the embodiments of the present disclosure can dynamically compensate the delay time of the signal according to the temperature of the real-time environment, avoid the situation where the delay time of the signal does not reach the expected value due to temperature changes, and improve signal transmission.
  • the stability and accuracy improve the performance and reliability of integrated circuits.
  • Figures 1-6 are schematic diagrams of the principles of delay circuits provided in different embodiments of the present disclosure.
  • Figure 7 is a circuit schematic diagram of a temperature compensation control module in a delay circuit provided in an embodiment of the present disclosure
  • FIG. 8 is a schematic circuit diagram of a semiconductor memory provided in an embodiment of the present disclosure.
  • connection is intended to express an indirect or direct electrical connection. Accordingly, if one device is connected to another device, the connection may be through a direct electrical connection, or through an indirect electrical connection through other devices and connectors.
  • a delay circuit 100 including a temperature compensation control module 10 and a delay module 20.
  • the temperature compensation control module 10 is used to adjust the temperature according to the received initial control signal Mde and the real-time environment.
  • the temperature signal Tempcode, the temperature coefficient compensation enable signal Testmode_En and the temperature coefficient control signal Testmode_PosEn generate the target temperature compensation control signal Testmode_DLY;
  • the delay module 20 is connected to the temperature compensation control module 10 and is used to compensate the control signal Testmode_DLY according to the received target temperature and the initial Delay the signal Signal_in to generate the temperature-compensated target delay signal Signal_out.
  • the temperature compensation control module 10 uses the temperature compensation control module 10 to generate the target temperature compensation control signal Testmode_DLY according to the received initial control signal Mde, the temperature signal Tempcode of the real-time environment, the temperature coefficient compensation enable signal Testmode_En, and the temperature coefficient control signal Testmode_PosEn. , and use the target temperature compensation control signal Testmode_DLY to control the delay module 20 to compensate for the change in the signal delay time due to temperature changes, and obtain the temperature-compensated target delay signal Signal_out, so that the actual delay time of the delay circuit 100 reaches the expected value.
  • the temperature compensation control module 10 includes a target temperature compensation module 11, an addition module 12 and a logic output module 13.
  • the target temperature compensation module 11 is configured as: a first type input terminal for receiving real-time The ambient temperature signal Tempcode, the second type input terminal is used to receive the temperature coefficient compensation enable signal Testmode_En, the control terminal is used to receive the initial selection signal En, and the output terminal is used to output the target temperature compensation signal Temp_out;
  • the addition module 12 is configured as:
  • the first type input terminal is used to receive the initial control signal Mde.
  • the second type input terminal is connected to the output terminal of the target temperature compensation module 11 to receive the target temperature compensation signal Temp_out.
  • the carry input terminal is used to receive the initial carry signal C0.
  • the first type output The terminal is used to output the initial temperature compensation control signal S, and the carry output terminal is used to output the target carry signal Cout;
  • the logic output module 13 is configured as: the first type input terminal is connected to the first type output terminal of the adder module 12 to receive the initial temperature compensation. Control signal S, the second type input terminal is connected to the carry output terminal of the adder module 12 to receive the target carry signal Cout, the third type input terminal is used to receive the initial selection signal En, and the initial temperature compensation control signal S, the target carry signal Cout and After the initial selection signal En is logically processed, the target temperature compensation control signal Testmode_DLY is output through the output terminal.
  • the target temperature compensation module 11 By setting the target temperature compensation module 11 to generate the temperature-compensated target temperature compensation signal Temp_out according to the received real-time environment temperature signal Tempcode, temperature coefficient compensation enable signal Testmode_En and initial selection signal En, and then using the addition module 12 to compensate the target temperature
  • the signal Temp_out and the initial control signal Mde are added together to obtain the initial temperature compensation control signal S, so that the logic output module 13 performs logical processing on the received initial temperature compensation control signal S, the target carry signal Cout and the initial selection signal En, and then outputs the target temperature.
  • the control signal Testmode_DLY is compensated so that the delay module 20 generates a temperature-compensated target delay signal Signal_out according to the received target temperature compensation control signal Testmode_DLY and the initial delay signal Signal_in. It can be understood that the signals involved in the present disclosure are all represented by digital signals and can perform binary operations.
  • the adder module 12 includes an adder 1210, the adder 1210 is configured as follows: a first input terminal is used to receive the initial control signal Mde, and a second input terminal is connected to the target temperature compensation module 11 The output terminal is used to receive the target temperature compensation signal Temp_out, the carry input terminal is used to receive the initial carry signal C0, the signal output terminal is connected to the first type input terminal of the logic output module 13, and is used to provide the initial temperature compensation control signal to the logic output module 13 S, the carry output terminal is used to output the target carry signal Cout and is provided to the logic output module 13 .
  • the target temperature compensation module 11 After receiving the temperature signal Tempcode of the real-time environment collected by the temperature sensor, the target temperature compensation module 11 generates the target temperature compensation signal Temp_out according to the received temperature signal Tempcode of the real-time environment, the initial selection signal En and the temperature coefficient compensation enable signal Testmode_En; the adder 1210
  • the initial temperature compensation control signal S and the target carry signal Cout are provided to the logic output module 13 according to the received target temperature compensation signal Temp_out and the initial carry signal C0, so that the logic output module 13 provides the initial temperature compensation control signal S and the target carry signal Cout according to the received initial temperature compensation control signal S and the target carry signal Cout.
  • the initial selection signal En generates the target temperature compensation control signal Testmode_DLY, so that the delay module 20 generates the temperature-compensated target delay signal Signal_out according to the received target temperature compensation control signal Testmode_DLY and the initial delay signal Signal_in.
  • the adding module 12 includes N cascaded adders 1210,..., adders 121i-1,... and adders 121N-1,i ⁇ (1,N], i and N are both positive integers, N>1; the carry output terminal of each stage adder is connected to the carry input terminal of the adjacent next stage adder, and the carry input terminal of the first stage adder 1210 is used as the carry of the addition module 12 The input terminal is used to receive the initial carry signal C0.
  • the carry output terminal of the last stage adder 121N-1 is used as the carry output terminal of the adder module 12 and is used to output the target carry signal Cout; the signal output terminals of all levels of adder are common It constitutes the first type output terminal of the adder module 12 and is connected to the first type input terminal of the logic output module 13.
  • the signal output terminals of the adders at each stage output the corresponding initial temperature compensation control signal S ⁇ N-1:0> and provide To the logic output module 13; the first input terminals of the adders at all levels together constitute the first type input terminal of the adder module 12, used to receive the initial control signal Mde ⁇ N-1:0>; the second input terminals of the adders 121 at all levels The input terminals together constitute the second type input terminal of the adder module 12 and are used for receiving the target temperature compensation signal Temp_out ⁇ N-1:0>.
  • the initial control signal Mde can be set to include sub-initial control signals Mde ⁇ 0>,..., sub-initial control signals Mde ⁇ i-1>,... and sub-initial control signals Mde There are a total of N sub-initial control signals including ⁇ N-1>.
  • the initial temperature compensation control signal S includes sub-initial temperature compensation control signals S ⁇ 0>,..., sub-initial temperature compensation control signals S ⁇ i-1>,...
  • the target temperature compensation signal Temp_out includes the sub-target temperature compensation signal Temp_out ⁇ 0>,..., the sub-target temperature compensation signal A total of N sub-target temperature compensation signals including Temp_out ⁇ i-1>,...
  • the carry input end of the first-stage adder 1210 is used to receive the initial carry signal C0,
  • the carry output terminal of the last stage adder 121N-1 is used to output the target carry signal Cout;
  • the first input terminal of the i-th stage adder 121i-1 is used to receive the i-th sub-initial control signal Mde ⁇ i-1>,
  • the second input terminal is used to receive the sub-target temperature compensation signal Temp_out ⁇ i-1>, the carry output terminal is connected to the carry input terminal of the i+1th stage adder 121i of the adjacent next stage, and the signal output terminal outputs the corresponding sub-initial temperature compensation
  • the control signal S ⁇ i-1> is provided to the logic output module 13, i ⁇ (1, N], i and N are both positive integers, N>1.
  • the addition module 12 By setting the addition module 12 to include the temperature signal Tempcode with the real-time environment there are equal numbers of adders for neutron temperature signals, and a cascade of adders is set up to facilitate dynamic compensation of the delay time of the initial control signal by using each sub-temperature signal in the temperature signal Tempcode of the real-time environment to obtain the target delay after temperature compensation.
  • signal Signal_out so that the actual delay time of the delay circuit 100 reaches the expected value, avoiding the situation where the delay time of the actually generated target delay signal Signal_out is significantly different from the required delay time of the target delay signal Signal_out due to temperature changes, and improving signal transmission.
  • the stability and accuracy improve the performance and reliability of integrated circuits.
  • the logic output module 13 includes a target overflow prevention unit 131 and N logic output units, and the N logic output units include logic output units 1320,..., logic output units 132i-1,... ...and the logic output unit 132N-1;
  • the target overflow prevention unit 131 is configured as follows: the first type input terminal serves as the third type input terminal of the logic output module 13 for receiving the initial selection signal En, and the second type input terminal serves as the logic The second type input terminal of the output module 13 is connected to the carry output terminal of the last stage adder 121N-1 for receiving the target carry signal Cout; among the N logic output units, the i-th logic output unit 132i-1 One input terminal is connected to the signal output terminal of the i-th stage adder 121i-1 for receiving the corresponding sub-initial temperature compensation control signal S ⁇ i-1>; the second input terminal of each logic output unit is connected to the target overflow prevention unit.
  • the first output end of 131 is to receive the first overflow prevention signal y1; the third input end of each logic output unit is connected to the second output end of the target overflow prevention unit 131 to receive the second overflow prevention signal y2; each logic output
  • the output terminals of the units jointly constitute the output terminals of the logic output module 13 and are used to output the target temperature compensation control signal Testmode_DLY ⁇ N-1:0>; the first input terminals of each logic output unit jointly constitute the first type of the logic output module 13
  • the input terminal is used to receive the initial temperature compensation control signal S; i ⁇ (1, N], i and N are both positive integers, N>1; among them, the target overflow prevention unit 131 is used to prevent the operation result of the addition module 12 from overflowing. .
  • the target temperature compensation control signal Testmode_DLY may be set to include sub-target temperature compensation control signals Testmode_DLY ⁇ 0>,..., sub-target temperature compensation control signals Testmode_DLY ⁇ i-1>,... and a total of N sub-target temperature compensation control signals including the sub-target temperature compensation control signal Testmode_DLY ⁇ N-1>.
  • the i-th logical output unit 132i-1 is configured as follows: the first input terminal is connected to the i-th stage adder 121i- The signal output end of 1 is used to receive the corresponding sub-initial temperature compensation control signal S ⁇ i-1>, and the second input end is connected to the first output end of the target overflow prevention unit 131 and is used to receive the first overflow prevention signal y1, The third input terminal is connected to the second output terminal of the target overflow prevention unit 131 for receiving the second overflow prevention signal y2, and the output terminal is used for outputting the i-th sub-target temperature compensation control signal Testmode_DLY ⁇ i-1>, i ⁇ (1 , N], i and N are both positive integers, N>1.
  • each sub-temperature signal in the ambient temperature signal Tempcode dynamically compensates the delay time of the initial control signal, and sets a one-to-one logic output unit with the adder.
  • Each logic output unit responds to the received first anti-overflow signal y1, the third After the secondary overflow prevention signal y2 and the initial temperature compensation control signal S are logically processed, the target temperature compensation control signal Testmode_DLY is output.
  • the temperature signal Tempcode of the real-time environment includes sub-temperature signals Tempcode ⁇ 0>,..., sub-temperature signals Tempcode ⁇ i-1>,... and sub-temperature signals Tempcode ⁇ N-1 >, a total of N sub-temperature signals including the target temperature compensation signal Temp_out include sub-target temperature compensation signals Temp_out ⁇ 0>,..., sub-target temperature compensation signals Temp_out ⁇ i-1>,... and sub-target temperature compensation signals Temp_out A total of N sub-target temperature compensation signals including ⁇ N-1>; the target temperature compensation module 11 includes a total of target temperature compensation units 1110,..., target temperature compensation unit 111i-1 and target temperature compensation unit 111N-1.
  • the i-th target temperature compensation unit 111i-1 is configured as follows: the first input terminal is used to receive the i-th sub-temperature signal Tempcode ⁇ i-1>, and the second input terminal is used to receive temperature coefficient compensation Enable signal Testmode_En, the control terminal is used to receive the initial selection signal En, and the output terminal is used to provide the i-th sub-target temperature compensation signal Temp_out ⁇ i-1>; i ⁇ to the second input terminal of the i-th stage adder 121i-1 (1, N], i and N are both positive integers, N>1; the first input terminal of each target temperature compensation unit jointly constitutes the first type input terminal of the target temperature compensation module 11, used to receive the corresponding sub-temperature signal; the second input terminals of each target temperature compensation unit jointly constitute the second type input terminal of the target temperature compensation module 11, which is used to receive the temperature coefficient compensation enable signal Testmode_En; the control terminals of each target temperature compensation unit jointly constitute the target temperature compensation The control end of the module is used to receive the
  • the target temperature compensation unit has a one-to-one signal setting.
  • Each target temperature compensation unit outputs a corresponding sub-target temperature compensation signal according to the received sub-temperature signal, the temperature coefficient compensation enable signal Testmode_En and the initial selection signal En.
  • the temperature compensation control module also includes a temperature coefficient control module 14.
  • the temperature coefficient control module 14 is configured as follows: a first input terminal for receiving the temperature coefficient compensation enable signal Testmode_En, a second input terminal The terminal is used to receive the temperature coefficient control signal Testmode_PosEn, the third input terminal is used to receive the Nth sub-temperature signal Tempcode ⁇ N-1>, and the output terminal outputs the initial selection signal En, i ⁇ (1, N], i and N are both Positive integer, N>1; wherein, the output end of the temperature coefficient control module 14 is connected to the control end of the target temperature compensation module 11.
  • the temperature The coefficient compensation enable signal Testmode_En and the temperature coefficient control signal Testmode_PosEn generate the initial selection signal En.
  • the initial selection signal En and the initial carry signal C0 can be set to be inverse signals of each other to provide the initial carry signal C0 for the addition module 12 and prevent the target from overflowing.
  • the unit 131 generates the first anti-overflow signal y1 and the second anti-overflow signal y2 according to the initial selection signal En and the target carry signal Cout to prevent the operation result of the addition module 12 from overflowing.
  • the Nth sub-temperature signal Tempcode ⁇ N-1> to be high level to indicate low temperature, and conversely to be low level to indicate high temperature; and set the temperature coefficient compensation enable signal Testmode_En to During the low level, the temperature coefficient of the initial control signal Mde ⁇ N-1:0> is not adjusted, that is, the delay time of the target delay signal is not temperature compensated.
  • the target temperature compensation control signal Testmode_DLY ⁇ N-1:0> is different from the initial control
  • the signals Mde ⁇ N-1:0> are correspondingly equal; the period during which the temperature coefficient compensation enable signal Testmode_En is high level and the temperature coefficient control signal Testmode_PosEn is high level can be defined as the positive temperature coefficient mode.
  • the initial control signal Mde ⁇ N -1:0> make adjustments to control the delay time of the target delay signal to achieve targeted compensation for the change in delay time due to temperature in positive temperature coefficient mode and negative temperature coefficient mode, meeting the needs of a variety of different application scenarios and improving The performance and application scope of the product.
  • the high level and low level mentioned in the above embodiment are relative concepts (that is, the high level voltage value is higher than the corresponding low level voltage value), not The specific voltage value of the high level is limited, and the specific voltage value of the low level is not limited.
  • the high levels applied on different signal lines in the embodiments of the present disclosure are equal.
  • Those skilled in the art should understand that according to the process Nodes, speed requirements, reliability requirements, etc. can set the corresponding high level and low level values by themselves.
  • the delay module can be configured to include N target delay units and N target logic input units; the input end of the first target delay unit is used to receive the initial delay signal Signal_in; the i-th target logic input unit is configured is: the first input terminal is connected to the input terminal of the i-th target delay unit, the second input terminal is connected to the output terminal of the i-th target delay unit, and the third input terminal is used to receive the i-th sub-target temperature compensation control signal Testmode_DLY ⁇ i -1>; The output end of the Nth target logic input unit is used as the output end of the delay module and is used to output the target delay signal Signal_out; i ⁇ (1, N], i and N are both positive integers, N>1; Among them, the input end of the jth target delay unit is connected to the output end of the j-1th target logic input unit, j ⁇ [2, N], j is a positive integer.
  • the delay time of different target delay units It can be different.
  • the delay time of the j-th target delay unit is greater than the delay time of the j-1th target delay unit.
  • the initial control signal Mde ⁇ N-1:0> can control whether the corresponding target delay unit delays the initial delay signal. Processing. For example, when the sub-initial control signal Mde ⁇ 0> is high level, that is, the digital signal "1", the first target delay unit will not perform the first-level delay operation on the initial delay signal Signal_in.
  • the first target delay unit when When the sub-initial control signal Mde ⁇ 0> is low level, that is, when the digital signal is "0", the first target delay unit will perform the first-level delay operation on the initial delay signal Signal_in; in addition, the initial control signal Mde ⁇ N- 1:0> represents a binary value.
  • the target temperature compensation control signal Testmode_DLY ⁇ N-1:0> is obtained by performing temperature compensation on the initial control signal Mde ⁇ N-1:0>, and the target temperature compensation control signal Testmode_DLY is used to control the delay module to adjust the signal delay time due to temperature changes. The resulting change is compensated to obtain the target delay signal Signal_out after temperature compensation, so that the actual delay time of the delay circuit reaches the expected value.
  • the target overflow prevention unit 131 includes a first NOR gate Nor1 and a first AND gate And1.
  • the first NOR gate Nor1 is configured as follows: the first input terminal is used to receive the initial selection signal En, and the second input terminal is connected to the last stage of addition.
  • the carry output terminal of the device 1212 is used as the first output terminal of the target overflow prevention unit 131 and is connected to the second input terminal of the logic output unit 1320, the logic output unit 1321 and the logic output unit 1322;
  • the first AND gate And1 is configured is: the first input terminal is used to receive the initial selection signal En, the second input terminal is connected to the carry output terminal of the last stage adder 1212, the output terminal serves as the second output terminal of the target overflow prevention unit 131, and is connected to the logic output unit 1320 , the third input terminal of the logic output unit 1321 and the logic output unit 1322; wherein, the first input terminal of the first NOR gate Nor1 and the first input terminal of the first AND gate And1 together constitute the first input terminal of the target overflow prevention unit 131.
  • the type input terminal, the second input terminal of the first NOR gate Nor1 and the second input terminal of the first AND gate And1 together constitute the second type input terminal of the target overflow prevention unit 131 .
  • the logic output unit 1320 , the logic output unit 1321 and the logic output unit 1322 each include a first inverter Inv1 , a second NOR gate Nor2 and a first OR gate Or1 .
  • the following takes the logic output unit 1320 as an example to illustrate the circuit structure and specific implementation principles of the logic output unit 1320, the logic output unit 1321, and the logic output unit 1322.
  • the input terminal of the first inverter Inv1 serves as the first input terminal of the logic output unit 1320;
  • the second NOR gate Nor2 is configured as: the first input terminal is connected to the output terminal of the first inverter Inv1 , the second input terminal serves as the second input terminal of the logic output unit 1320 and is connected to the output terminal of the first NOR gate Nor1 for receiving the first overflow prevention signal y1;
  • the first OR gate Or1 is configured as: the first input terminal The output terminal of the second NOR gate Nor2 is connected, and the second input terminal serves as the third input terminal of the logic output unit 1320 and is connected to the output terminal of the first AND gate And1 for receiving the second overflow prevention signal y2;
  • the output terminal serves as the logic The output terminal of the output unit 1320 is used to output the sub-target temperature compensation control signal Testmode_DLY ⁇ 0>.
  • the target temperature compensation unit 1110 , the target temperature compensation unit 1111 and the target temperature compensation unit 1112 each include a first NAND gate Nand1 and a selection output unit Select.
  • the following uses the specific circuit structure of the target temperature compensation unit 1110 to exemplify the working principles of each target temperature compensation unit.
  • the first NAND gate Nand1 is configured as follows: the first input terminal serves as the first input terminal of the target temperature compensation unit 1110 and is used to receive the sub-temperature signal Tempcode ⁇ 0>, and the second input terminal serves as The second input terminal of the target temperature compensation unit 1110 is used to receive the temperature coefficient compensation enable signal Testmode_En, and the output terminal outputs the first intermediate sub-temperature signal Ms ⁇ 0>; the selection output unit Select is configured such that the input terminal is connected to the first The output terminal of the NAND gate Nand1 is used to receive the first intermediate temperature signal Ms ⁇ 0>.
  • the control terminal is used as the control terminal of the target temperature compensation unit 111 and is used to receive the initial selection signal En.
  • the output terminal is used as the target temperature compensation unit.
  • the output terminal of 111 is used to output the sub-target temperature compensation signal Temp_out ⁇ 0>; wherein, if the initial selection signal En is high level, the sub-target temperature compensation signal Temp_out ⁇ 0> and the first intermediate sub-temperature signal Ms ⁇ 0> are mutually inverted signals. If the initial selection signal En is low level, the sub-target temperature compensation signal Temp_out ⁇ 0> and the first intermediate sub-temperature signal Ms ⁇ 0> are mutually in-phase signals.
  • the target temperature compensation unit 1111 and the target temperature compensation unit 1112 are similar to the target temperature compensation unit 1110 in circuit structures and similar working principles. It is sufficient to refer to each other and the details will not be described again.
  • the selection output unit Select in the target temperature compensation unit 1110 includes a second inverter Inv2 and a data selector mux1.
  • the input terminal of the second inverter Inv2 is connected to the output terminal of the first NAND gate Nand1; the first terminal of the data selector mux1
  • the input terminal is connected to the output terminal of the second inverter Inv2
  • the second input terminal is connected to the output terminal of the first NAND gate Nand1.
  • the output terminal of the data selector mux1 outputs the sub-target temperature compensation signal Temp_out ⁇ 0>, and the data selector The control end of mux1 is used to receive the initial selection signal En.
  • the initial selection signal En is a high level, such as "1”
  • the sub-target temperature compensation signal Temp_out ⁇ 0> and the first intermediate sub-temperature signal Ms ⁇ 0> are inverse signals of each other; if the initial selection signal En is a low level, For example, "0”, the sub-target temperature compensation signal Temp_out ⁇ 0> and the first intermediate sub-temperature signal Ms ⁇ 0> are in-phase signals with each other.
  • the implementation principles and circuit structures of the target temperature compensation unit 1111 and the target temperature compensation unit 1112 are similar to those of the target temperature compensation unit 1110. Please refer to each other and the details will not be described again.
  • the temperature coefficient control module 14 includes a first XOR gate Xor1 and a second AND gate And2.
  • the first XOR gate Xor1 is configured as: the first input terminal serves as the temperature coefficient control module.
  • the third input terminal of 14 is used to receive the third sub-temperature signal Tempcode ⁇ 2>, and the second input terminal is used as the second input terminal of the temperature coefficient control module 14 and is used to receive the temperature coefficient control signal Testmode_PosEn; the second and The gate And2 is configured as follows: the first input terminal is connected to the output terminal of the first XOR gate Xor1, the second input terminal serves as the first input terminal of the temperature coefficient control module 14 and is used to receive the temperature coefficient compensation enable signal Testmode_En, and the output terminal As the output terminal of the temperature coefficient control module 14 and used to output the initial selection signal En.
  • the adder module 12 includes an adder 1210 , an adder 1211 and an adder 1212 .
  • the carry input terminal of the first-stage adder 1210 serves as the carry input terminal of the adder module 12 and is used to receive The initial carry signal C0, the carry output terminal of the last stage adder 1212 is used as the carry output terminal of the adder module 12, and is used to output the target carry signal Cout; the carry output terminal of each stage adder is connected to the adjacent next stage adder.
  • the carry input terminal; the signal output terminals of the adder 1210, the adder 1211 and the adder 1212 together constitute the first type output terminal of the adder module 12, and are connected to the first type input terminal of the logic output module 13.
  • the signal output terminal outputs the corresponding initial temperature compensation control signal S ⁇ 2:0> and provides it to the logic output module 13; the first input terminals of the adders at all levels together constitute the first type input terminal of the adder module 12 for receiving the initial Control signal Mde ⁇ 2:0>; the second input terminals of the adder 1210, the adder 1211 and the adder 1212 together constitute the second type input terminal of the adder module 12, which is used to receive the target temperature compensation signal Temp_out ⁇ 2:0> .
  • the adders 1210, 1211 and 1212 each include a second XOR gate Xor2, a third XOR gate Xor3, a second NAND gate Nand2, a third Nand3 gate and a fourth Nand4 gate.
  • the second NAND gate Nand2 is configured as follows: the first input terminal receives the sub-initial control signal Mde ⁇ 0>, and the second input terminal is connected to the output terminal of the target temperature compensation unit 1110 for receiving the sub-target temperature compensation.
  • the second XOR gate Xor2 is configured as follows: the first input terminal receives the sub-initial control signal Mde ⁇ 0>, and the second input terminal is connected to the output terminal of the target temperature compensation unit 1110 for receiving the sub-target temperature.
  • the third XOR gate Xor3 is configured as follows: the first input terminal is connected to the output terminal of the second XOR gate Xor2, the second input terminal receives the initial carry signal C0, and the output terminal serves as the signal of the adder 1210 The output terminal provides the sub-temperature signal Tempcode ⁇ 0> to the logic output unit 1320; the third NAND gate Nand3 is configured as: the first input terminal is connected to the output terminal of the second exclusive OR gate Xor2, and the second input terminal receives the initial carry signal.
  • the fourth NAND gate Nand4 is configured as follows: the first input terminal is connected to the output terminal of the second NAND gate Nand2, the second input terminal is connected to the output terminal of the third NAND gate Nand3, and the output terminal serves as the carry of the adder 1210
  • the output terminal also provides the carry signal CO ⁇ 1> to the adder 1211; the adder 1211 and the adder 1212 have similar circuit structures and working principles to the adder 1210, and the details will not be described again.
  • the delay module 20 includes a target delay unit 1, a target delay unit 2, a target delay unit 3, a target logic input unit 210, a target logic input unit 211, and a target logic input unit 212;
  • first The input terminal of the first target delay unit 1 is used to receive the initial delay signal Signal_in;
  • the first target logic input unit 210 is configured as follows: the first input terminal is connected to the input terminal of the first target delay unit 1, and the second input terminal is connected to the input terminal of the first target delay unit 1.
  • the output end and the third input end of one target delay unit 1 are used to receive the first sub-target temperature compensation control signal Testmode_DLY ⁇ 0>;
  • the second target logic input unit 211 is configured as: the first input end is connected to the second The input terminal of the target delay unit 2, the second input terminal is connected to the output terminal of the second target delay unit 2, and the third input terminal is used to receive the second sub-target temperature compensation control signal Testmode_DLY ⁇ 1>;
  • the third target logic input The unit 212 is configured as follows: the first input terminal is connected to the input terminal of the third target delay unit 3, the second input terminal is connected to the output terminal of the third target delay unit 3, and the third input terminal is used to receive the third sub-target temperature. Compensation control signal Testmode_DLY ⁇ 2>.
  • the target logic input unit 210 , the target logic input unit 211 and the target logic input unit 212 each include a second OR gate Or2 and a third AND gate And3.
  • the second OR gate Or2 is configured as follows: the first input terminal serves as the second input terminal of the target logic input unit 210, and the second input terminal serves as the third input terminal of the target logic input unit 21 and is used for Receive the sub-target temperature compensation control signal Testmode_DLY ⁇ 0>; the third AND gate And3 is configured as: the first input terminal serves as the first input terminal of the target logic input unit 210 for receiving the initial delay signal Signal_in, and the second input terminal is connected The output terminal of the second OR gate Or2 serves as the output terminal of the target logic input unit 210 .
  • the second OR gate Or2 is configured as follows: the first input terminal serves as the second input terminal of the target logic input unit 211, and is connected to the output terminal of the second target delay unit 2, and the second input terminal serves as the second input terminal of the target logic input unit 211.
  • the third input terminal of the target logic input unit 211 is used to receive the target temperature compensation control signal Testmode_DLY ⁇ 1>;
  • the third AND gate And3 is configured as: the first input terminal serves as the first input terminal of the target logic input unit 211 and is connected The input terminal of the second target delay unit 2 is connected to the output terminal of the second OR gate Or2, and the output terminal serves as the output terminal of the target logic input unit 211.
  • the second OR gate Or2 is configured as follows: the first input terminal serves as the second input terminal of the target logic input unit 212, and is connected to the output terminal of the third target delay unit 3, and the second input terminal serves as the second input terminal of the target logic input unit 212.
  • the third input terminal of the target logic input unit 212 is used to receive the sub-target temperature compensation control signal Testmode_DLY ⁇ 2>;
  • the third AND gate And3 is configured as: the first input terminal serves as the first input terminal of the target logic input unit 212, The input terminal of the third target delay unit 3 is connected, and the second input terminal is connected to the output terminal of the second OR gate Or2.
  • the output terminal serves as the output terminal of the target logic input unit 212 and is used to output the temperature-compensated target delay signal. Signal_out.
  • the temperature compensation control module 10 is used to generate the target temperature compensation control signal Testmode_DLY ⁇ 2:0>, and the target temperature compensation control signal Testmode_DLY ⁇ 2:0> is used to control the delay module 20, for The signal delay time is compensated for the change caused by the temperature change, and the temperature-compensated target delay signal Signal_out is obtained, so that the actual delay time of the delay circuit 100 reaches the expected value, and the delay circuit 100 is generated according to the temperature signal Tempcode of the real-time environment.
  • the delay time of the target delay signal Signal_out is dynamically compensated to avoid the situation where the delay time of the actually generated target delay signal Signal_out and the required target delay signal Signal_out is significantly different due to temperature changes, thereby improving the stability and accuracy of signal transmission. Improve the performance and reliability of integrated circuits.
  • the initial control The signal Mde ⁇ 2:0> adjusts the delay time to increase.
  • the initial control signal Mde ⁇ 2:0> adjusts the delay time to decrease; the temperature coefficient compensation enable signal Testmode_En can also be set to high level and the temperature coefficient is controlled.
  • the period when the signal Testmode_PosEn is low level is defined as the negative temperature coefficient mode.
  • the initial control signal Mde ⁇ 2:0> adjusts the delay time to decrease.
  • the initial control signal Mde ⁇ 2:0> adjusts Delay time increases. Achieve targeted compensation for the change in delay time due to temperature in positive temperature coefficient mode and negative temperature coefficient mode, meet the needs of a variety of different application scenarios, and improve the performance and application scope of the product.
  • a semiconductor memory 200 includes the delay circuit 100 in any embodiment of the disclosure, configured to operate according to the initial delay signal Signal_in, the initial control signal Mde, the temperature signal Tempcode of the real-time environment and The temperature coefficient control signal Testmode_PosEn generates a temperature-compensated target delay signal Signal_out and provides it to the function module 201, so that the function module 201 triggers a preset target action at the target time to generate the target function.
  • the functional module 201 may include at least one of a mode register, a frequency divider, a microcontroller, and a clock circuit.
  • the temperature compensation control module 10 is used to generate the target temperature compensation control signal Testmode_DLY ⁇ 2:0>, and the target temperature compensation control signal Testmode_DLY ⁇ 2:0> is used to control the delay module 20, the change amount of the signal delay time caused by the temperature change is measured. Compensate to obtain the target delay signal Signal_out after temperature compensation, so that the actual delay time of the delay circuit 100 reaches the expected value, and dynamically compensate the delay time of the target delay signal Signal_out generated by the delay circuit 100 according to the temperature signal Tempcode of the real-time environment. This avoids the situation where the delay time of the actually generated target delay signal Signal_out is significantly different from the required target delay signal Signal_out due to temperature changes. Therefore, the preset target action can be accurately triggered at the target time to generate the target function, improving The stability and accuracy of signal transmission improve the performance and reliability of integrated circuits.

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Abstract

一种延迟电路（100）及半导体存储器，所述延迟电路（100）包括温度补偿控制模块（10）及延迟模块（20），温度补偿控制模块（10）用于根据接收的初始控制信号、实时环境的温度信号、温度系数补偿使能信号及温度系数控制信号，生成目标温度补偿控制信号；延迟模块（20）连接所述温度补偿控制模块（10），用于根据接收的所述目标温度补偿控制信号和初始延迟信号，生成经温度补偿后的目标延迟信号，能够根据温度传感器采集的实时环境的温度信号对延迟电路（100）生成的目标延迟信号的延迟时间进行动态补偿，避免产生因温度变化导致实际生成的目标延迟信号的延迟时间与需求的目标延迟信号的延迟时间相差较大的情况，提高信号传输的稳定性与准确度，提高集成电路的性能及可靠性。

Description

延迟电路及半导体存储器
相关申请的交叉引用
本公开要求于2022年04月29日提交中国专利局、申请号为202210465498.3、申请名称为“延迟电路及半导体存储器”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路领域，特别是涉及一种延迟电路及半导体存储器。
背景技术
随着集成电路技术的快速发展，市场对半导体产品的集成度、信号传输的准确度提出了更高地要求。集成电路内集成的多个电路模块一般需要时钟信号来触发相应的功能响应，一般需要将集成电路的输入时钟信号经过相应的延迟电路产生对应的延迟之后，在目标时刻触发对应的功能响应。
传统的延迟电路中信号传输通路受实时环境的影响，导致实际延迟时间与预设延迟时间存在偏差，影响集成电路工作的稳定性与可靠性。
如果能够减小集成电路中延迟电路受实时环境的影响，无疑将有效提高信号传输的稳定性与准确度，从而提高集成电路的性能及可靠性。
发明内容
根据本公开的各种实施例，提供一种延迟电路及半导体存储器。
根据一些实施例，本公开第一方面提供一种延迟电路，包括温度补偿控制模块及延迟模块，温度补偿控制模块用于根据接收的初始控制信号、实时环境的温度信号、温度系数补偿使能信号及温度系数控制信号，生成目标温度补偿控制信号；延迟模块连接温度补偿控制模块，用于根据接收的目标温度补偿控制信号和初始延迟信号，生成经温度补偿后的目标延迟信号。
根据一些实施例，温度补偿控制模块包括目标温度补偿模块、加法模块及逻辑输出模块，目标温度补偿模块被配置为：第一类型输入端用于接收实时环境的温度信号，第二类型输入端用于接收温度系数补偿使能信号，控制端用于接收初始选择信号，输出端用于输出目标温度补偿信号；加法模块被配置为：第一类型输入端用于接收初始控制信号，第二类型输入端连接目标温度补偿模块的输出端以接收目标温度补偿信号，进位输入端用于接收初始进位信号，第一类型输出端用于输出初始温度补偿控制信号，进位输出端用于输出目标进位信号；逻辑输出模块被配置为：第一类型输入端连接加法模块的第一类型输出端以接收初始温度补偿控制信号，第二类型输入端连接加法模块的进位输出端以接收目标进位信号，第三类型输入端用于接收初始选择信号，对初始温度补偿控制信号、目标进位信号及初始选择信号进行逻辑处理后，经由输出端输出目标温度补偿控制信号。
根据一些实施例，加法模块包括N个级联的加法器，N>1，且N为正整数，每一级加法器的进位输出端连接相邻下一级加法器的进位输入端，第一级加法器的进位输入端作为加法模块的进位输入端且用于接收初始进位信号，最后一级加法器的进位输出端作为加法模块的进位输出端，且用于输出目标进位信号；各级加法器的信号输出端共同构成加法模块的第一类型输出端，且连接逻辑输出模块的第一类型输入端；各级加法器的第一输入端共同构成加法模块的第一类型输入端；各级加法器的第二输入端共同构成加法模块的第二类型输入端。
根据一些实施例，逻辑输出模块包括目标防溢出单元及N个逻辑输出单元，目标防溢出单元被配置为：第一类型输入端作为逻辑输出模块的第三类型输入端以接收初始选择信 号，第二类型输入端作为逻辑输出模块的第二类型输入端且连接最后一级加法器的进位输出端；N个逻辑输出单元中第i个逻辑输出单元的第一输入端连接第i级加法器的信号输出端，每一个逻辑输出单元的第二输入端连接目标防溢出单元的第一输出端，每一个逻辑输出单元的第三输入端连接目标防溢出单元的第二输出端，各逻辑输出单元的输出端共同构成逻辑输出模块的输出端，各逻辑输出单元的第一输入端共同构成逻辑输出模块的第一类型输入端，i∈(1，N]，i为正整数；其中，目标防溢出单元用于防止加法模块的运算结果溢出。
根据一些实施例，目标防溢出单元包括第一或非门及第一与门，第一或非门被配置为：第一输入端用于接收初始选择信号，第二输入端连接最后一级加法器的进位输出端，输出端作为目标防溢出单元的第一输出端，且连接各逻辑输出单元的第二输入端；第一与门被配置为：第一输入端用于接收初始选择信号，第二输入端连接最后一级加法器的进位输出端，输出端作为目标防溢出单元的第二输出端，且连接各逻辑输出单元的第三输入端；其中，第一或非门的第一输入端与第一与门的第一输入端共同构成目标防溢出单元的第一类型输入端，第一或非门的第二输入端与第一与门的第二输入端共同构成目标防溢出单元的第二类型输入端。
根据一些实施例，逻辑输出单元包括第一反相器、第二或非门及第一或门，第一反相器的输入端作为逻辑输出单元的第一输入端；第二或非门被配置为：第一输入端连接第一反相器的输出端，第二输入端作为逻辑输出单元的第二输入端且连接第一或非门的输出端；第一或门被配置为：第一输入端连接第二或非门的输出端，第二输入端作为逻辑输出单元的第三输入端且连接第一与门的输出端，输出端作为逻辑输出单元的输出端。
根据一些实施例，实时环境的温度信号包括N个子温度信号，目标温度补偿信号包括N个子目标温度补偿信号；目标温度补偿模块包括N个目标温度补偿单元；第i个目标温度补偿单元被配置为：第一输入端用于接收第i个子温度信号，第二输入端用于接收温度系数补偿使能信号，控制端用于接收初始选择信号，输出端用于向第i级加法器的第二输入端提供第i个子目标温度补偿信号；i∈(1，N]，i为正整数；每一个目标温度补偿单元的第一输入端共同构成目标温度补偿模块的第一类型输入端，各目标温度补偿单元的第二输入端共同构成目标温度补偿模块的第二类型输入端，各目标温度补偿单元的控制端共同构成目标温度补偿模块的控制端。
根据一些实施例，目标温度补偿单元包括第一与非门及选择输出单元，第一与非门被配置为：第一输入端作为目标温度补偿单元的第一输入端，且用于接收子温度信号，第二输入端作为目标温度补偿单元的第二输入端，且用于接收温度系数补偿使能信号，输出端输出中间子温度信号；选择输出单元被配置为：输入端连接第一与非门的输出端，控制端作为目标温度补偿单元的控制端，且用于接收初始选择信号，输出端作为目标温度补偿单元的输出端，且用于输出子目标温度补偿信号；其中，若初始选择信号为高电平，则子目标温度补偿信号与中间子温度信号互为反相信号，若初始选择信号为低电平，则子目标温度补偿信号与中间子温度信号互为同相信号。
根据一些实施例，温度补偿控制模块还包括温度系数控制模块，温度系数控制模块被配置为：第一输入端用于接收温度系数补偿使能信号、第二输入端用于接收温度系数控制信号，第三输入端用于接收第N个子温度信号，输出端输出初始选择信号；其中，温度系数控制模块的输出端连接目标温度补偿模块的控制端。
根据一些实施例，温度系数控制模块包括第一异或门及第二与门，第一异或门被配置为：第一输入端作为温度系数控制模块的第三输入端，且用于接收第N个子温度信号，第二输入端作为温度系数控制模块的第二输入端，且用于接收温度系数控制信号；第二与门被配置为：第一输入端连接第一异或门的输出端，第二输入端作为温度系数控制模块的第一输入端且用于接收温度系数补偿使能信号，输出端作为温度系数控制模块的输出端且用 于输出初始选择信号。
根据一些实施例，初始选择信号与初始进位信号互为反相信号。
根据一些实施例，初始控制信号包括N个子初始控制信号，第i级加法器的第一输入端用于接收第i个子初始控制信号，i∈(1，N]，i为正整数。
根据一些实施例，目标温度补偿控制信号包括N个子目标温度补偿控制信号，第i个逻辑输出单元用于输出第i个子目标温度补偿控制信号。
根据一些实施例，延迟模块包括N个目标延迟单元及N个目标逻辑输入单元；第一个目标延迟单元的输入端用于接收初始延迟信号；第i个目标逻辑输入单元被配置为：第一输入端连接第i个目标延迟单元的输入端，第二输入端连接第i个目标延迟单元的输出端，第三输入端用于接收第i个子目标温度补偿控制信号；第N个目标逻辑输入单元的输出端作为延迟模块的输出端，且用于输出目标延迟信号；其中，第j个目标延迟单元的输入端连接第j-1个目标逻辑输入单元的输出端，j∈[2，N]，j为正整数。
根据一些实施例，目标逻辑输入单元包括第二或门及第三与门，第二或门被配置为：第一输入端作为目标逻辑输入单元的第二输入端，第二输入端作为目标逻辑输入单元的第三输入端且用于接收子目标温度补偿控制信号；第三与门被配置为：第一输入端作为目标逻辑输入单元的第一输入端，第二输入端连接第二或门的输出端，输出端作为目标逻辑输入单元的输出端。
根据一些实施例，本公开第二方面提供一种半导体存储器，包括任一本公开实施例中的延迟电路。
本公开实施例可以/至少具有以下优点：
在本公开实施例提供的延迟电路及半导体存储器中，利用温度补偿控制模块根据接收的初始控制信号、实时环境的温度信号、温度系数补偿使能信号及温度系数控制信号生成目标温度补偿控制信号，并利用目标温度补偿控制信号控制延迟模块，对信号延迟时间因温度变化导致的变化量进行补偿，得到经温度补偿后的目标延迟信号，使得延迟电路的实际延迟时间达到预期数值，实现根据实时环境的温度信号对延迟电路生成的目标延迟信号进行动态补偿，避免产生因温度变化导致实际生成的目标延迟信号与需求的目标延迟信号相差较大的情况，提高信号传输的稳定性与准确度，提高集成电路的性能及可靠性。
综上，本公开实施例提供的延迟电路及半导体存储器，能够根据实时环境的温度对信号的延迟时间进行动态补偿，避免产生因温度变化导致信号的延迟时间未达到预期数值的情况，提高信号传输的稳定性与准确度，提高集成电路的性能及可靠性。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例技术中的技术方案，下面将对实施例技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-图6为本公开不同实施例中提供的延迟电路的原理示意图；
图7为本公开一实施例中提供的一种延迟电路中温度补偿控制模块的电路示意图；
图8为本公开一实施例中提供的一种半导体存储器的电路示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术 人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
另外，贯穿说明书和跟随的权利要求中所使用的某些术语指代特定元件。本领域的技术人员会理解为，制造商可以用不同的名字指代元件。本文件不想要区分名字不同但是功能相同的元件。在以下的描述和实施例中，术语“包含”和“包括”都是开放式使用的，因此应该解读为“包含，但不限于……”。同样，术语“连接”想要表达间接或直接的电气连接。相应地，如果一个设备被连接到另一个设备上，连接可以通过直接的电气连接完成，或者通过其他设备和连接件的间接电气连接完成。
应当理解，尽管本文可以使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件和另一个元件区分开。例如，在不脱离本公开的范围的情况下，第一元件可以被称为第二元件，并且类似地，第二元件可以被称为第一元件。
请参考图1，在本公开的一些实施例中，提供了一种延迟电路100，包括温度补偿控制模块10及延迟模块20，温度补偿控制模块10用于根据接收的初始控制信号Mde、实时环境的温度信号Tempcode、温度系数补偿使能信号Testmode_En及温度系数控制信号Testmode_PosEn，生成目标温度补偿控制信号Testmode_DLY；延迟模块20连接温度补偿控制模块10，用于根据接收的目标温度补偿控制信号Testmode_DLY和初始延迟信号Signal_in，生成经温度补偿后的目标延迟信号Signal_out。
具体地，请继续参考图1，利用温度补偿控制模块10根据接收的初始控制信号Mde、实时环境的温度信号Tempcode、温度系数补偿使能信号Testmode_En及温度系数控制信号Testmode_PosEn生成目标温度补偿控制信号Testmode_DLY，并利用目标温度补偿控制信号Testmode_DLY控制延迟模块20，对信号延迟时间因温度变化导致的变化量进行补偿，得到经温度补偿后的目标延迟信号Signal_out，使得延迟电路100的实际延迟时间达到预期数值，实现根据实时环境的温度信号Tempcode对延迟电路100生成的目标延迟信号Signal_out的延迟时间进行动态补偿，避免产生因温度变化导致实际生成的目标延迟信号Signal_out的延迟时间与需求的目标延迟信号Signal_out的延迟时间相差较大的情况，提高信号传输的稳定性与准确度，提高集成电路的性能及可靠性。
在一些实施例中，请参考图2，温度补偿控制模块10包括目标温度补偿模块11、加法模块12及逻辑输出模块13，目标温度补偿模块11被配置为：第一类型输入端用于接收实时环境的温度信号Tempcode，第二类型输入端用于接收温度系数补偿使能信号Testmode_En，控制端用于接收初始选择信号En，输出端用于输出目标温度补偿信号Temp_out；加法模块12被配置为：第一类型输入端用于接收初始控制信号Mde，第二类型输入端连接目标温度补偿模块11的输出端以接收目标温度补偿信号Temp_out，进位输入端用于接收初始进位信号C0，第一类型输出端用于输出初始温度补偿控制信号S，进位输出端用于输出目标进位信号Cout；逻辑输出模块13被配置为：第一类型输入端连接加法模块12的第一类型输出端以接收初始温度补偿控制信号S，第二类型输入端连接加法模块12的进位输出端以接收目标进位信号Cout，第三类型输入端用于接收初始选择信号En，对初始温度补偿控制信号S、目标进位信号Cout及初始选择信号En进行逻辑处理后，经由输出端输出目标温度补偿控制信号Testmode_DLY。通过设置目标温度补偿模块11根据接收的实时环境的温度信号Tempcode、温度系数补偿使能信号Testmode_En及初始选择信号En生成经温度补偿后的目标温度补偿信号Temp_out，再利用加法模块12将目标温度补偿信号Temp_out和初始控制信号Mde进行加法处理得到初始温度补偿控制信号S，使得逻辑输出模块13对接收的初始温度补偿控制信号S、目标进位信号Cout及初始选择信号En进行逻辑处理后，输出目标温度补偿控制信号Testmode_DLY，以便于延迟模块20根据接收的目标温度补偿控制信号Testmode_DLY和初始延迟信号Signal_in，生成经温 度补偿后的目标延迟信号Signal_out。可以理解的是，本公开中涉及的信号均由数字信号表示，可以进行二进制运算。
在一些实施例中，请参考图3a，加法模块12包括加法器1210，加法器1210被配置比为：第一输入端用于接收初始控制信号Mde，第二输入端连接目标温度补偿模块11的输出端，以接收目标温度补偿信号Temp_out，进位输入端用于接收初始进位信号C0，信号输出端连接逻辑输出模块13的第一类型输入端，用于向逻辑输出模块13提供初始温度补偿控制信号S，进位输出端用于输出目标进位信号Cout，并提供给逻辑输出模块13。目标温度补偿模块11接收温度传感器采集的实时环境的温度信号Tempcode之后，根据接收的实时环境的温度信号Tempcode、初始选择信号En及温度系数补偿使能信号Testmode_En生成目标温度补偿信号Temp_out；加法器1210根据接收的目标温度补偿信号Temp_out及初始进位信号C0向逻辑输出模块13提供初始温度补偿控制信号S及目标进位信号Cout，使得逻辑输出模块13根据接收的初始温度补偿控制信号S、目标进位信号Cout及初始选择信号En生成目标温度补偿控制信号Testmode_DLY，以便于延迟模块20根据接收的目标温度补偿控制信号Testmode_DLY和初始延迟信号Signal_in，生成经温度补偿后的目标延迟信号Signal_out。
在一些实施例中，请参考图3b，加法模块12包括N个级联的加法器1210、……、加法器121i-1、……及加法器121N-1，i∈(1，N]，i、N均为正整数，N>1；每一级加法器的进位输出端连接相邻下一级加法器的进位输入端，第一级加法器1210的进位输入端作为加法模块12的进位输入端且用于接收初始进位信号C0，最后一级加法器121N-1的进位输出端作为加法模块12的进位输出端，且用于输出目标进位信号Cout；各级加法器的信号输出端共同构成加法模块12的第一类型输出端，且连接逻辑输出模块13的第一类型输入端，各级加法器的信号输出端输出对应的初始温度补偿控制信号S<N-1:0>并提供给逻辑输出模块13；各级加法器的第一输入端共同构成加法模块12的第一类型输入端，用于接收初始控制信号Mde<N-1:0>；各级加法器121的第二输入端共同构成加法模块12的第二类型输入端，用于接收目标温度补偿信号Temp_out<N-1:0>。
在一些实施例中，请继续参考图3b，可以设置初始控制信号Mde包括子初始控制信号Mde<0>、……、子初始控制信号Mde<i-1>、……及子初始控制信号Mde<N-1>在内的共计N个子初始控制信号，初始温度补偿控制信号S包括子初始温度补偿控制信号S<0>、……、子初始温度补偿控制信号S<i-1>、……及子初始温度补偿控制信号S<N-1>在内的共计N个子初始温度补偿控制信号；目标温度补偿信号Temp_out包括子目标温度补偿信号Temp_out<0>、……、子目标温度补偿信号Temp_out<i-1>、……及子目标温度补偿信号Temp_out<N-1>在内的共计N个子目标温度补偿信号；第一级加法器1210的进位输入端用于接收初始进位信号C0，最后一级加法器121N-1的进位输出端用于输出目标进位信号Cout；第i级加法器121i-1的第一输入端用于接收第i个子初始控制信号Mde<i-1>，第二输入端用于接收子目标温度补偿信号Temp_out<i-1>，进位输出端连接相邻下一级第i+1级加法器121i的进位输入端，信号输出端输出对应的子初始温度补偿控制信号S<i-1>，并提供给逻辑输出模块13，i∈(1，N]，i、N均为正整数，N>1。通过设置加法模块12包括与实时环境的温度信号Tempcode中子温度信号的数量相等的加法器，并设置加法器级联，便于利用实时环境的温度信号Tempcode中各子温度信号对初始控制信号的延迟时间进行动态补偿，得到经温度补偿后的目标延迟信号Signal_out，使得延迟电路100的实际延迟时间达到预期数值，避免产生因温度变化导致实际生成的目标延迟信号Signal_out的延迟时间与需求的目标延迟信号Signal_out的延迟时间相差较大的情况，提高信号传输的稳定性与准确度，提高集成电路的性能及可靠性。
在一些实施例中，请参考图4，逻辑输出模块13包括目标防溢出单元131及N个逻辑输出单元，N个逻辑输出单元包括逻辑输出单元1320、……、逻辑输出单元132i-1、…… 及逻辑输出单元132N-1；目标防溢出单元131被配置为：第一类型输入端作为逻辑输出模块13的第三类型输入端，用于接收初始选择信号En，第二类型输入端作为逻辑输出模块13的第二类型输入端且连接最后一级加法器121N-1的进位输出端，用于接收目标进位信号Cout；N个逻辑输出单元中，第i个逻辑输出单元132i-1的第一输入端连接第i级加法器121i-1的信号输出端，用于接收对应的子初始温度补偿控制信号S<i-1>；每一个逻辑输出单元的第二输入端连接目标防溢出单元131的第一输出端，以接收第一防溢出信号y1；每一个逻辑输出单元的第三输入端连接目标防溢出单元131的第二输出端，以接收第二防溢出信号y2；各逻辑输出单元的输出端共同构成逻辑输出模块13的输出端，用于输出目标温度补偿控制信号Testmode_DLY<N-1:0>；各逻辑输出单元的第一输入端共同构成逻辑输出模块13的第一类型输入端，用于接收初始温度补偿控制信号S；i∈(1，N]，i、N均为正整数，N>1；其中，目标防溢出单元131用于防止加法模块12的运算结果溢出。
在一些实施例中，请继续参考图4，可以设置目标温度补偿控制信号Testmode_DLY包括子目标温度补偿控制信号Testmode_DLY<0>、……、子目标温度补偿控制信号Testmode_DLY<i-1>、……及子目标温度补偿控制信号Testmode_DLY<N-1>在内的共计N个子目标温度补偿控制信号，第i个逻辑输出单元132i-1被配置为：第一输入端连接第i级加法器121i-1的信号输出端，用于接收对应的子初始温度补偿控制信号S<i-1>，第二输入端连接目标防溢出单元131的第一输出端，用于接收第一防溢出信号y1，第三输入端连接目标防溢出单元131的第二输出端，用于接收第二防溢出信号y2，输出端用于输出第i个子目标温度补偿控制信号Testmode_DLY<i-1>，i∈(1，N]，i、N均为正整数，N>1。通过设置加法模块12包括与实时环境的温度信号Tempcode中子温度信号的数量相等的加法器，并设置加法器级联，便于利用实时环境的温度信号Tempcode中各子温度信号对初始控制信号的延迟时间进行动态补偿，并设置与加法器一对一的逻辑输出单元，每一逻辑输出单元对接收的第一防溢出信号y1、第二防溢出信号y2及初始温度补偿控制信号S进行逻辑处理后，输出目标温度补偿控制信号Testmode_DLY。
在一些实施例中，请参考图5，实时环境的温度信号Tempcode包括子温度信号Tempcode<0>、……、子温度信号Tempcode<i-1>、……及子温度信号Tempcode<N-1>在内的共计N个子温度信号，目标温度补偿信号Temp_out包括子目标温度补偿信号Temp_out<0>、……、子目标温度补偿信号Temp_out<i-1>、……及子目标温度补偿信号Temp_out<N-1>在内的共计N个子目标温度补偿信号；目标温度补偿模块11包括目标温度补偿单元1110、……、目标温度补偿单元111i-1及目标温度补偿单元111N-1在内的共计N个目标温度补偿单元；第i个目标温度补偿单元111i-1被配置为：第一输入端用于接收第i个子温度信号Tempcode<i-1>，第二输入端用于接收温度系数补偿使能信号Testmode_En，控制端用于接收初始选择信号En，输出端用于向第i级加法器121i-1的第二输入端提供第i个子目标温度补偿信号Temp_out<i-1>；i∈(1，N]，i、N均为正整数，N>1；每一个目标温度补偿单元的第一输入端共同构成目标温度补偿模块11的第一类型输入端，用于接收对应的子温度信号；各目标温度补偿单元的第二输入端共同构成目标温度补偿模块11的第二类型输入端，用于接收温度系数补偿使能信号Testmode_En；各目标温度补偿单元的控制端共同构成目标温度补偿模块的控制端，用于接收初始选择信号En；各目标温度补偿单元的输出端共同构成目标温度补偿模块的输出端，用于输出目标温度补偿信号。通过设置目标温度补偿模块11包括与子温度信号一对一设置的目标温度补偿单元，每一目标温度补偿单元根据接收的子温度信号、温度系数补偿使能信号Testmode_En及初始选择信号En，输出对应的子目标温度补偿信号。
在一些实施例中，请参考图6，温度补偿控制模块还包括温度系数控制模块14，温度系数控制模块14被配置为：第一输入端用于接收温度系数补偿使能信号Testmode_En、 第二输入端用于接收温度系数控制信号Testmode_PosEn，第三输入端用于接收第N个子温度信号Tempcode<N-1>，输出端输出初始选择信号En，i∈(1，N]，i、N均为正整数，N>1；其中，温度系数控制模块14的输出端连接目标温度补偿模块11的控制端。通过设置温度系数控制模块14根据接收的第N个子温度信号Tempcode<N-1>、温度系数补偿使能信号Testmode_En及温度系数控制信号Testmode_PosEn生成初始选择信号En，可以设置初始选择信号En与初始进位信号C0互为反相信号，为加法模块12提供初始进位信号C0，并使得目标防溢出单元131根据初始选择信号En及目标进位信号Cout生成第一防溢出信号y1及第二防溢出信号y2，以防止加法模块12的运算结果溢出。
在一些实施例中，请继续参考图6，可以设置第N个子温度信号Tempcode<N-1>为高电平时表示低温，反之为低电平时表示高温；并设置温度系数补偿使能信号Testmode_En为低电平期间，不对初始控制信号Mde<N-1：0>进行温度系数调节，即不对目标延迟信号的延迟时间进行温度补偿，目标温度补偿控制信号Testmode_DLY<N-1：0>与初始控制信号Mde<N-1：0>对应相等；可以将温度系数补偿使能信号Testmode_En为高电平且温度系数控制信号Testmode_PosEn为高电平期间定义为正温度系数模式，当温度为高温时，需要增加延迟时间，当温度为低温时，需要减少延迟时间；也可以将温度系数补偿使能信号Testmode_En为高电平且温度系数控制信号Testmode_PosEn为低电平期间定义为负温度系数模式，当温度为高温时，需要减少延迟时间，当温度为低温时，需要增加延迟时间；i∈(1，N]，i、N均为正整数，N>1。本公开中通过对初始控制信号Mde<N-1：0>做调节，控制目标延迟信号的延迟时间，实现对正温度系数模式、负温度系数模式下因温度导致延迟时间变化量的针对性补偿，满足多种不同应用场景的需求，提高产品的性能与应用范围。需要说明的是，上述实施例所称高电平、低电平均为相对的概念(即高电平的电压值高于与其对应的低电平的电压值)，不限定高电平的具体电压值，也不限定低电平的具体电压值。并且也并不限定本公开实施例中不同信号线上施加的高电平均相等，本领域技术人员应该理解，根据工艺节点、速度要求及可靠性要求等可自行设置相应高电平和低电平的值。
请注意，上述实施例中关于正温度系数模式或负温度系数模式的定义旨在示意性说明书本公开实施例的具体实现原理，本领域技术人员在公开内容的启示下，可以毫无疑义地将反相信号等效定义。因此，在未付出创造性劳动的前提下，对本公开实施例作出的相同/相似变形，均应当属于本公开的保护范围。
在一些实施例中，可以设置延迟模块包括N个目标延迟单元及N个目标逻辑输入单元；第一个目标延迟单元的输入端用于接收初始延迟信号Signal_in；第i个目标逻辑输入单元被配置为：第一输入端连接第i个目标延迟单元的输入端，第二输入端连接第i个目标延迟单元的输出端，第三输入端用于接收第i个子目标温度补偿控制信号Testmode_DLY<i-1>；第N个目标逻辑输入单元的输出端作为延迟模块的输出端，且用于输出目标延迟信号Signal_out；i∈(1，N]，i、N均为正整数，N>1；其中，第j个目标延迟单元的输入端连接第j-1个目标逻辑输入单元的输出端，j∈[2，N]，j为正整数。可以理解的是，不同目标延迟单元的延迟时间可以不同，第j个目标延迟单元的延迟时间大于第j-1个目标延迟单元的延迟时间，初始控制信号Mde<N-1：0>可以控制对应的目标延迟单元是否对初始延迟信号进行延迟处理。举例说明，当子初始控制信号Mde<0>为高电平，即数字信号“1”时，则第一个目标延迟单元将不对初始延迟信号Signal_in进行第一级延迟操作，反之，当子初始控制信号Mde<0>为低电平，即数字信号“0”时，则第一个目标延迟单元将对初始延迟信号Signal_in进行第一级延迟操作；另外，初始控制信号Mde<N-1：0>表示一个二进制数值，通过增大初始控制信号Mde<N-1：0>，可以减少延迟时间；通过减小初始控制信号Mde<N-1：0>，可以增大延迟时间。通过对初始控制信号Mde<N-1：0>进行温度补偿得到目标温度补偿控制信号Testmode_DLY<N-1：0>，并利用目标温度补偿控制信号Testmode_DLY控制延迟模块，对信号延迟时间因温度变化导致的变 化量进行补偿，得到经温度补偿后的目标延迟信号Signal_out，使得延迟电路的实际延迟时间达到预期数值。
在一些实施例中，请参考图7，以N＝3为例示意性说明本公开实施例的具体实现原理。目标防溢出单元131包括第一或非门Nor1及第一与门And1，第一或非门Nor1被配置为：第一输入端用于接收初始选择信号En，第二输入端连接最后一级加法器1212的进位输出端，输出端作为目标防溢出单元131的第一输出端，且连接逻辑输出单元1320、逻辑输出单元1321及逻辑输出单元1322的第二输入端；第一与门And1被配置为：第一输入端用于接收初始选择信号En，第二输入端连接最后一级加法器1212的进位输出端，输出端作为目标防溢出单元131的第二输出端，且连接逻辑输出单元1320、逻辑输出单元1321及逻辑输出单元1322的第三输入端；其中，第一或非门Nor1的第一输入端与第一与门And1的第一输入端共同构成目标防溢出单元131的第一类型输入端，第一或非门Nor1的第二输入端与第一与门And1的第二输入端共同构成目标防溢出单元131的第二类型输入端。
在一些实施例中，请继续参考图7，逻辑输出单元1320、逻辑输出单元1321及逻辑输出单元1322均包括第一反相器Inv1、第二或非门Nor2及第一或门Or1。如下以逻辑输出单元1320为例来示例性说明逻辑输出单元1320、逻辑输出单元1321及逻辑输出单元1322的电路结构与具体实现原理。逻辑输出单元1320中：第一反相器Inv1的输入端作为逻辑输出单元1320的第一输入端；第二或非门Nor2被配置为：第一输入端连接第一反相器Inv1的输出端，第二输入端作为逻辑输出单元1320的第二输入端且连接第一或非门Nor1的输出端，用于接收第一防溢出信号y1；第一或门Or1被配置为：第一输入端连接第二或非门Nor2的输出端，第二输入端作为逻辑输出单元1320的第三输入端且连接第一与门And1的输出端，用于接收第二防溢出信号y2；输出端作为逻辑输出单元1320的输出端，用于输出子目标温度补偿控制信号Testmode_DLY<0>。类似地，逻辑输出单元1321及逻辑输出单元1322的具体电路结构参见逻辑输出单元1320即可，详细内容不再赘述。
在一些实施例中，请继续参考图7，目标温度补偿单元1110、目标温度补偿单元1111及目标温度补偿单元1112均包括第一与非门Nand1及选择输出单元Select。如下以目标温度补偿单元1110的具体电路结构来示例性说明各目标温度补偿单元的工作原理。目标温度补偿单元1110中：第一与非门Nand1被配置为：第一输入端作为目标温度补偿单元1110的第一输入端，且用于接收子温度信号Tempcode<0>，第二输入端作为目标温度补偿单元1110的第二输入端，且用于接收温度系数补偿使能信号Testmode_En，输出端输出第一中间子温度信号Ms<0>；选择输出单元Select被配置为：输入端连接第一与非门Nand1的输出端，用于接收第一中间子温度信号Ms<0>，控制端作为目标温度补偿单元111的控制端，且用于接收初始选择信号En，输出端作为目标温度补偿单元111的输出端，且用于输出子目标温度补偿信号Temp_out<0>；其中，若初始选择信号En为高电平，则子目标温度补偿信号Temp_out<0>与第一中间子温度信号Ms<0>互为反相信号，若初始选择信号En为低电平，则子目标温度补偿信号Temp_out<0>与第一中间子温度信号Ms<0>互为同相信号。目标温度补偿单元1111及目标温度补偿单元1112与目标温度补偿单元1110的电路结构类似且工作原理相似，互相参见即可，详细内容不再赘述。
在一些实施例中，请继续参考图7，如下以目标温度补偿单元1110的具体电路结构来示例性说明各目标温度补偿单元的工作原理。目标温度补偿单元1110中选择输出单元Select包括第二反相器Inv2及数据选择器mux1，第二反相器Inv2的输入端连接第一与非门Nand1的输出端；数据选择器mux1的第一输入端连接第二反相器Inv2的输出端，且第二输入端连接第一与非门Nand1的输出端，数据选择器mux1的输出端输出子目标温度补偿信号Temp_out<0>，数据选择器mux1的控制端用于接收初始选择信号En。其中，若初始选择信号En为高电平例如“1”，子目标温度补偿信号Temp_out<0>与第一中间子温 度信号Ms<0>互为反相信号；若初始选择信号En为低电平例如“0”，子目标温度补偿信号Temp_out<0>与第一中间子温度信号Ms<0>互为同相信号。目标温度补偿单元1111及目标温度补偿单元1112的实现原理及电路结构与目标温度补偿单元1110的类似，互相参见即可，详细内容不再赘述。
在一些实施例中，请继续参考图7，温度系数控制模块14包括第一异或门Xor1及第二与门And2，第一异或门Xor1被配置为：第一输入端作为温度系数控制模块14的第三输入端，且用于接收第3个子温度信号Tempcode<2>，第二输入端作为温度系数控制模块14的第二输入端，且用于接收温度系数控制信号Testmode_PosEn；第二与门And2被配置为：第一输入端连接第一异或门Xor1的输出端，第二输入端作为温度系数控制模块14的第一输入端且用于接收温度系数补偿使能信号Testmode_En，输出端作为温度系数控制模块14的输出端且用于输出初始选择信号En。
在一些实施例中，请继续参考图7，加法模块12包括加法器1210、加法器1211及加法器1212，第一级加法器1210的进位输入端作为加法模块12的进位输入端且用于接收初始进位信号C0，最后一级加法器1212的进位输出端作为加法模块12的进位输出端，且用于输出目标进位信号Cout；每一级加法器的进位输出端连接相邻下一级加法器的进位输入端；加法器1210、加法器1211及加法器1212的信号输出端共同构成加法模块12的第一类型输出端，且连接逻辑输出模块13的第一类型输入端，各级加法器的信号输出端输出对应的初始温度补偿控制信号S<2:0>并提供给逻辑输出模块13；各级加法器的第一输入端共同构成加法模块12的第一类型输入端，用于接收初始控制信号Mde<2:0>；加法器1210、加法器1211及加法器1212的第二输入端共同构成加法模块12的第二类型输入端，用于接收目标温度补偿信号Temp_out<2:0>。加法器1210、加法器1211及加法器1212均包括第二异或门Xor2、第三异或门Xor3、第二与非门Nand2、第三与非门Nand3及第四与非门Nand4。如下以加法器1210的具体电路结构来示例性说明各加法器的工作原理。加法器1210中：第二与非门Nand2被配置为：第一输入端接收子初始控制信号Mde<0>，第二输入端连接目标温度补偿单元1110的输出端，用于接收子目标温度补偿信号Temp_out<0>；第二异或门Xor2被配置为：第一输入端接收子初始控制信号Mde<0>，第二输入端连接目标温度补偿单元1110的输出端，用于接收子目标温度补偿信号Temp_out<0>，第三异或门Xor3被配置为：第一输入端连接第二异或门Xor2的输出端，第二输入端接收初始进位信号C0，输出端作为加法器1210的信号输出端且向逻辑输出单元1320提供子温度信号Tempcode<0>；第三与非门Nand3被配置为：第一输入端连接第二异或门Xor2的输出端，第二输入端接收初始进位信号C0；第四与非门Nand4被配置为：第一输入端连接第二与非门Nand2的输出端，第二输入端连接第三与非门Nand3的输出端，输出端作为加法器1210的进位输出端且向加法器1211提供进位信号CO<1>；加法器1211及加法器1212与加法器1210的电路结构类似且工作原理相似，详细内容不再赘述。
在一些实施例中，请参考图8，延迟模块20包括目标延迟单元1、目标延迟单元2、目标延迟单元3、目标逻辑输入单元210、目标逻辑输入单元211、目标逻辑输入单元212；第一个目标延迟单元1的输入端用于接收初始延迟信号Signal_in；第1个目标逻辑输入单元210被配置为：第一输入端连接第1个目标延迟单元1的输入端，第二输入端连接第1个目标延迟单元1的输出端，第三输入端用于接收第1个子目标温度补偿控制信号Testmode_DLY<0>；第2个目标逻辑输入单元211被配置为：第一输入端连接第2个目标延迟单元2的输入端，第二输入端连接第2个目标延迟单元2的输出端，第三输入端用于接收第2个子目标温度补偿控制信号Testmode_DLY<1>；第3个目标逻辑输入单元212被配置为：第一输入端连接第3个目标延迟单元3的输入端，第二输入端连接第3个目标延迟单元3的输出端，第三输入端用于接收第3个子目标温度补偿控制信号Testmode_DLY<2>。
在一些实施例中，请继续参考图8，目标逻辑输入单元210、目标逻辑输入单元211及目标逻辑输入单元212均包括第二或门Or2及第三与门And3。目标逻辑输入单元210中，第二或门Or2被配置为：第一输入端作为目标逻辑输入单元210的第二输入端，第二输入端作为目标逻辑输入单元21的第三输入端且用于接收子目标温度补偿控制信号Testmode_DLY<0>；第三与门And3被配置为：第一输入端作为目标逻辑输入单元210的第一输入端，用于接收初始延迟信号Signal_in，第二输入端连接第二或门Or2的输出端，输出端作为目标逻辑输入单元210的输出端。目标逻辑输入单元211中，第二或门Or2被配置为：第一输入端作为目标逻辑输入单元211的第二输入端，且连接第2个目标延迟单元2的输出端，第二输入端作为目标逻辑输入单元211的第三输入端且用于接收目标温度补偿控制信号Testmode_DLY<1>；第三与门And3被配置为：第一输入端作为目标逻辑输入单元211的第一输入端，连接第2个目标延迟单元2的输入端，第二输入端连接第二或门Or2的输出端，输出端作为目标逻辑输入单元211的输出端。目标逻辑输入单元212中，第二或门Or2被配置为：第一输入端作为目标逻辑输入单元212的第二输入端，且连接第3个目标延迟单元3的输出端，第二输入端作为目标逻辑输入单元212的第三输入端且用于接收子目标温度补偿控制信号Testmode_DLY<2>；第三与门And3被配置为：第一输入端作为目标逻辑输入单元212的第一输入端，连接第3个目标延迟单元3的输入端，第二输入端连接第二或门Or2的输出端，输出端作为目标逻辑输入单元212的输出端，且用于输出经温度补偿后的目标延迟信号Signal_out。
在一些实施例中，请继续参考图8，利用温度补偿控制模块10生成目标温度补偿控制信号Testmode_DLY<2:0>，并利用目标温度补偿控制信号Testmode_DLY<2:0>控制延迟模块20，对信号延迟时间因温度变化导致的变化量进行补偿，得到经温度补偿后的目标延迟信号Signal_out，使得延迟电路100的实际延迟时间达到预期数值，实现根据实时环境的温度信号Tempcode对延迟电路100生成的目标延迟信号Signal_out的延迟时间进行动态补偿，避免产生因温度变化导致实际生成的目标延迟信号Signal_out与需求的目标延迟信号Signal_out的延迟时间相差较大的情况，提高信号传输的稳定性与准确度，提高集成电路的性能及可靠性。
在一些实施例中，请继续参考图7、图8及表1，可以设置第3个子温度信号Tempcode<2>为“1”时表示低温且为“0”时表示高温；并设置温度系数补偿使能信号Testmode_En为低电平期间，不对初始控制信号Mde<2：0>进行温度系数调节，即不对目标延迟信号的延迟时间进行温度补偿，目标温度补偿控制信号Testmode_DLY<2：0>与初始控制信号Mde<2：0>对应相等；可以将温度系数补偿使能信号Testmode_En为高电平且温度系数控制信号Testmode_PosEn为高电平期间定义为正温度系数模式，当温度为高温时，初始控制信号Mde<2：0>调节延迟时间增加，当温度为低温时，初始控制信号Mde<2：0>调节延迟时间减少；也可以将温度系数补偿使能信号Testmode_En为高电平且温度系数控制信号Testmode_PosEn为低电平期间定义为负温度系数模式，当温度为高温时，初始控制信号Mde<2：0>调节延迟时间减少，当温度为低温时，初始控制信号Mde<2：0>调节延迟时间增加。实现对正温度系数模式、负温度系数模式下因温度导致延迟时间变化量的针对性补偿，满足多种不同应用场景的需求，提高产品的性能与应用范围。
表1
Figure PCTCN2022092997-appb-000001
在一些实施例中，请继续参考图8，一种半导体存储器200包括任一本公开实施例中 的延迟电路100，用于根据初始延迟信号Signal_in、初始控制信号Mde、实时环境的温度信号Tempcode及温度系数控制信号Testmode_PosEn，生成经温度补偿后的目标延迟信号Signal_out，并提供给功能模块201，使得功能模块201在目标时刻触发预设目标动作以产生目标功能。在一些实施例中，功能模块201可以包括模式寄存器、分频器、微控制器及时钟电路中的至少一种。由于利用温度补偿控制模块10生成目标温度补偿控制信号Testmode_DLY<2：0>，并利用目标温度补偿控制信号Testmode_DLY<2：0>控制延迟模块20，对信号延迟时间因温度变化导致的变化量进行补偿，得到经温度补偿后的目标延迟信号Signal_out，使得延迟电路100的实际延迟时间达到预期数值，实现根据实时环境的温度信号Tempcode对延迟电路100生成的目标延迟信号Signal_out的延迟时间进行动态补偿，避免产生因温度变化导致实际生成的目标延迟信号Signal_out的延迟时间与需求的目标延迟信号Signal_out的延迟时间相差较大的情况，因而能够在目标时刻精准地触发预设目标动作以产生目标功能，提高信号传输的稳定性与准确度，提高集成电路的性能及可靠性。
请注意，上述实施例仅出于说明性目的而不意味对本发明的限制。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种延迟电路，包括：
    温度补偿控制模块，用于根据接收的初始控制信号、实时环境的温度信号、温度系数补偿使能信号及温度系数控制信号，生成目标温度补偿控制信号；
    延迟模块，连接所述温度补偿控制模块，用于根据接收的所述目标温度补偿控制信号和初始延迟信号，生成经温度补偿后的目标延迟信号。
  2. 根据权利要求1所述的延迟电路，其中，所述温度补偿控制模块包括：
    目标温度补偿模块，被配置为：第一类型输入端用于接收所述实时环境的温度信号，第二类型输入端用于接收所述温度系数补偿使能信号，控制端用于接收初始选择信号，输出端用于输出目标温度补偿信号；
    加法模块，被配置为：第一类型输入端用于接收所述初始控制信号，第二类型输入端连接所述目标温度补偿模块的输出端以接收所述目标温度补偿信号，进位输入端用于接收初始进位信号，第一类型输出端用于输出初始温度补偿控制信号，进位输出端用于输出目标进位信号；
    逻辑输出模块，被配置为：第一类型输入端连接所述加法模块的第一类型输出端以接收所述初始温度补偿控制信号，第二类型输入端连接所述加法模块的进位输出端以接收所述目标进位信号，第三类型输入端用于接收初始选择信号，对所述初始温度补偿控制信号、所述目标进位信号及所述初始选择信号进行逻辑处理后，经由输出端输出所述目标温度补偿控制信号。
  3. 根据根据权利要求2所述的延迟电路，其中，所述加法模块包括：
    N个级联的加法器，N>1，且N为正整数，每一级所述加法器的进位输出端连接相邻下一级所述加法器的进位输入端，第一级所述加法器的进位输入端作为所述加法模块的进位输入端且用于接收所述初始进位信号，最后一级所述加法器的进位输出端作为所述加法模块的进位输出端，且用于输出所述目标进位信号；各级所述加法器的信号输出端共同构成所述加法模块的第一类型输出端，且连接所述逻辑输出模块的第一类型输入端；各级所述加法器的第一输入端共同构成所述加法模块的第一类型输入端；各级所述加法器的第二输入端共同构成所述加法模块的第二类型输入端。
  4. 根据权利要求3所述的延迟电路，其中，所述逻辑输出模块包括：
    目标防溢出单元，被配置为：第一类型输入端作为所述逻辑输出模块的第三类型输入端以接收所述初始选择信号，第二类型输入端作为所述逻辑输出模块的第二类型输入端且连接最后一级所述加法器的进位输出端；
    N个逻辑输出单元，第i个所述逻辑输出单元的第一输入端连接第i级所述加法器的信号输出端，每一个所述逻辑输出单元的第二输入端连接所述目标防溢出单元的第一输出端，每一个所述逻辑输出单元的第三输入端连接所述目标防溢出单元的第二输出端，各所述逻辑输出单元的输出端共同构成所述逻辑输出模块的输出端，各所述逻辑输出单元的第一输入端共同构成所述逻辑输出模块的第一类型输入端，i∈(1，N]，i为正整数；
    所述目标防溢出单元用于防止所述加法模块的运算结果溢出。
  5. 根据权利要求4所述的延迟电路，其中，所述目标防溢出单元包括：
    第一或非门，被配置为：第一输入端用于接收所述初始选择信号，第二输入端连接最后一级所述加法器的进位输出端，输出端作为所述目标防溢出单元的第一输出端，且连接各所述逻辑输出单元的第二输入端；
    第一与门，被配置为：第一输入端用于接收所述初始选择信号，第二输入端连接最后一级所述加法器的进位输出端，输出端作为所述目标防溢出单元的第二输出端，且连接各所述逻辑输出单元的第三输入端；
    所述第一或非门的第一输入端与所述第一与门的第一输入端共同构成所述目标防溢 出单元的第一类型输入端，所述第一或非门的第二输入端与所述第一与门的第二输入端共同构成所述目标防溢出单元的第二类型输入端。
  6. 根据权利要求5所述的延迟电路，其中，所述逻辑输出单元包括：
    第一反相器，其输入端作为所述逻辑输出单元的第一输入端；
    第二或非门，被配置为：第一输入端连接所述第一反相器的输出端，第二输入端作为所述逻辑输出单元的第二输入端且连接所述第一或非门的输出端；
    第一或门，被配置为：第一输入端连接所述第二或非门的输出端，第二输入端作为所述逻辑输出单元的第三输入端且连接所述第一与门的输出端，输出端作为所述逻辑输出单元的输出端。
  7. 根据权利要求3所述的延迟电路，其中，所述实时环境的温度信号包括N个子温度信号，所述目标温度补偿信号包括N个子目标温度补偿信号；
    所述目标温度补偿模块包括N个目标温度补偿单元；
    第i个所述目标温度补偿单元被配置为：第一输入端用于接收第i个所述子温度信号，第二输入端用于接收所述温度系数补偿使能信号，控制端用于接收所述初始选择信号，输出端用于向第i级所述加法器的第二输入端提供第i个所述子目标温度补偿信号；i∈(1，N]，i为正整数；
    每一个所述目标温度补偿单元的第一输入端共同构成所述目标温度补偿模块的第一类型输入端，各所述目标温度补偿单元的第二输入端共同构成所述目标温度补偿模块的第二类型输入端，各所述目标温度补偿单元的控制端共同构成所述目标温度补偿模块的控制端。
  8. 根据权利要求7所述的延迟电路，其中，所述目标温度补偿单元包括：
    第一与非门，被配置为：第一输入端作为所述目标温度补偿单元的第一输入端，且用于接收所述子温度信号，第二输入端作为所述目标温度补偿单元的第二输入端，且用于接收所述温度系数补偿使能信号，输出端输出中间子温度信号；
    选择输出单元，被配置为：输入端连接所述第一与非门的输出端，控制端作为所述目标温度补偿单元的控制端，且用于接收所述初始选择信号，输出端作为所述目标温度补偿单元的输出端，且用于输出所述子目标温度补偿信号；
    若所述初始选择信号为高电平，则所述子目标温度补偿信号与所述中间子温度信号互为反相信号，若所述初始选择信号为低电平，则所述子目标温度补偿信号与所述中间子温度信号互为同相信号。
  9. 根据权利要求7所述的延迟电路，其中，所述温度补偿控制模块还包括：
    温度系数控制模块，被配置为：第一输入端用于接收所述温度系数补偿使能信号、第二输入端用于接收所述温度系数控制信号，第三输入端用于接收第N个所述子温度信号，输出端输出所述初始选择信号；
    所述温度系数控制模块的输出端连接所述目标温度补偿模块的控制端。
  10. 根据权利要求9所述的延迟电路，其中，所述温度系数控制模块包括：
    第一异或门，被配置为：第一输入端作为所述温度系数控制模块的第三输入端，且用于接收第N个所述子温度信号，第二输入端作为所述温度系数控制模块的第二输入端，且用于接收所述温度系数控制信号；
    第二与门，被配置为：第一输入端连接所述第一异或门的输出端，第二输入端作为所述温度系数控制模块的第一输入端且用于接收所述温度系数补偿使能信号，输出端作为所述温度系数控制模块的输出端且用于输出所述初始选择信号。
  11. 根据权利要求2-10任一项所述的延迟电路，其中，所述初始选择信号与所述初始进位信号互为反相信号。
  12. 根据权利要求3所述的延迟电路，其中，所述初始控制信号包括N个子初始控制 信号，第i级所述加法器的第一输入端用于接收第i个所述子初始控制信号，i∈(1，N]，i为正整数。
  13. 根据权利要求4所述的延迟电路，其中，所述目标温度补偿控制信号包括N个子目标温度补偿控制信号，第i个所述逻辑输出单元用于输出第i个所述子目标温度补偿控制信号。
  14. 根据权利要求13所述的延迟电路，其中，所述延迟模块包括N个目标延迟单元及N个目标逻辑输入单元；
    第一个所述目标延迟单元的输入端用于接收所述初始延迟信号；
    第i个所述目标逻辑输入单元被配置为：第一输入端连接第i个所述目标延迟单元的输入端，第二输入端连接第i个所述目标延迟单元的输出端，第三输入端用于接收第i个所述子目标温度补偿控制信号；
    第N个所述目标逻辑输入单元的输出端作为所述延迟模块的输出端，且用于输出所述目标延迟信号；其中
    第j个所述目标延迟单元的输入端连接第j-1个所述目标逻辑输入单元的输出端，j∈[2，N]，j为正整数。
  15. 根据权利要求14所述的延迟电路，其中，所述目标逻辑输入单元包括：
    第二或门，被配置为：第一输入端作为所述目标逻辑输入单元的第二输入端，第二输入端作为所述目标逻辑输入单元的第三输入端且用于接收所述子目标温度补偿控制信号；
    第三与门，被配置为：第一输入端作为所述目标逻辑输入单元的第一输入端，第二输入端连接所述第二或门的输出端，输出端作为所述目标逻辑输入单元的输出端。
  16. 一种半导体存储器，包括如权利要求1-15任一项所述的延迟电路。
PCT/CN2022/092997 2022-04-29 2022-05-16 延迟电路及半导体存储器 WO2023206636A1 (zh)

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CN1869615A (zh) * 2005-05-24 2006-11-29 富晶半导体股份有限公司 电子信号的温度补偿装置
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