WO2023206381A1 - 显示背板、显示装置 - Google Patents

显示背板、显示装置 Download PDF

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Publication number
WO2023206381A1
WO2023206381A1 PCT/CN2022/090354 CN2022090354W WO2023206381A1 WO 2023206381 A1 WO2023206381 A1 WO 2023206381A1 CN 2022090354 W CN2022090354 W CN 2022090354W WO 2023206381 A1 WO2023206381 A1 WO 2023206381A1
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WIPO (PCT)
Prior art keywords
light
layer
orthographic projection
area
substrate
Prior art date
Application number
PCT/CN2022/090354
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English (en)
French (fr)
Inventor
岳阳
舒适
姚琪
于勇
李翔
徐传祥
李少辉
李士佩
刘文渠
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/090354 priority Critical patent/WO2023206381A1/zh
Priority to CN202280001032.6A priority patent/CN117356194A/zh
Priority to US18/027,131 priority patent/US20240347543A1/en
Publication of WO2023206381A1 publication Critical patent/WO2023206381A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and specifically relates to a display backplane and a display device.
  • LED Semiconductor light-emitting diode
  • Mini LED sub-millimeter light emitting diode
  • Micro LED Micro Light Emitting Diode
  • Micro LED Displays are mainly used in AR/VR and other fields, and Mini LED displays are mainly used in TV and outdoor display fields.
  • Transparent display is an important personalized display field in display technology. It means that the display device itself has a certain degree of light penetration and can display images in a transparent state. The viewer can not only see the image in the display device, but also See the scene behind the display device, which can be used for outdoor display or public display in open space.
  • the present disclosure provides a display backplane, including a plurality of display units located on a substrate, at least one display unit including a pixel area and a light-transmitting area, the pixel area being configured to display an image, and the light-transmitting area The area is configured to transmit light; the pixel area includes a first wiring layer and a second wiring layer arranged in different layers along the thickness direction of the substrate; and, located on the first wiring layer and the second wiring layer between the first dielectric layer and the second dielectric layer,
  • the ratio of the thickness of the first wiring layer to the thickness of the second wiring layer is greater than 5;
  • the sum of the thickness of the first dielectric layer and the thickness of the second dielectric layer is greater than 3 ⁇ m, and the thickness of the first dielectric layer is less than 2 ⁇ m;
  • the first wiring layer includes a plurality of first wirings, and the first wirings include a first portion extending along a first direction;
  • the second wiring layer includes a plurality of second wirings, the second wirings include a second portion extending along a second direction, and the first direction intersects the second direction.
  • At least one first trace includes at least one of a first scan line, a data signal line, a ground line, a first driving line, and a second driving line.
  • the first portion of at least one first trace includes first edges and second edges opposite to each other along the first direction
  • the pixel area further includes at least one first light-emitting device, at least one second light-emitting device. device and at least one third light-emitting device, orthographic projections of at least one first light-emitting device, at least one second light-emitting device and at least one third light-emitting device on the substrate are located in the area defined by the first edge and the second edge.
  • the first light-emitting device, the second light-emitting device and the third light-emitting device are each one of a sub-millimeter light-emitting diode and a micro light-emitting diode.
  • the pixel area further includes a pixel driving chip configured to provide a driving signal to at least one of the first light-emitting device, the second light-emitting device, and the third light-emitting device.
  • the pixel area further includes a third dielectric layer, a first groove and a second groove are provided in the third dielectric layer, and the first groove is configured to print with the first solder paste connected to at least one of the light-emitting device, the second light-emitting device and the third light-emitting device, and the second groove is configured to print the solder paste connected to the pixel driving chip.
  • the first portion of the at least one first trace includes a first edge and a second edge opposite to each other along the first direction, and the first portion of the at least one first trace is located at an orthographic projection of the substrate.
  • the first dielectric layer is within the orthographic projection of the substrate, and one of the first dielectric layer or the second dielectric layer has a third edge and a fourth edge opposite to each other along the first direction, and the The first edge and the third edge are located on the same side of the first trace, the second edge and the fourth edge are located on the same side of the first trace, and the first edge to the The first vertical distance of the third edge is greater than or equal to 20 ⁇ m, and the second vertical distance from the second edge to the fourth edge is greater than or equal to 20 ⁇ m.
  • the first dielectric layer includes a first strip-shaped region extending along the second direction
  • the second dielectric layer includes a second strip-shaped region extending along the second direction
  • the orthographic projection of the first strip-shaped region on the base coincides with the orthographic projection of the second strip-shaped region on the base;
  • the orthographic projection of the second strip-shaped region on the base is located within the orthographic projection of the first strip-shaped region on the base, and the orthographic projection area of the second strip-shaped region is smaller than the orthographic projection of the first strip-shaped region. area.
  • the second portion of the at least one second trace includes fifth and sixth edges opposite to each other along the second direction, and the second portion of the at least one second trace is on the front side of the substrate.
  • the projection is located within the orthographic projection of the first dielectric layer on the substrate, and one of the first dielectric layer or the second dielectric layer has seventh and eighth edges opposite to each other along the second direction, The fifth edge and the seventh edge are located on the same side of the second direction of the second trace, and the sixth edge and the eighth edge are located on the same side of the second direction of the second trace,
  • the third vertical distance from the fifth edge to the seventh edge is greater than or equal to 20 ⁇ m
  • the fourth vertical distance from the sixth edge to the eighth edge is greater than or equal to 20 ⁇ m.
  • the first dielectric layer includes a third strip-shaped region extending along the first direction
  • the second dielectric layer includes a fourth strip-shaped region extending along the first direction X
  • the third dielectric layer includes a fourth strip-shaped region extending along the first direction X.
  • the orthographic projection of the strip-shaped region on the base is located within the orthographic projection of the fourth strip-shaped region on the base, and the orthographic projection area of the third strip-shaped region is smaller than the orthographic projection area of the fourth strip-shaped region;
  • the orthographic projection of the third strip-shaped area coincides with the orthographic projection of the fourth strip-shaped area
  • the orthographic projection of the fourth strip-shaped region on the base is located within the orthographic projection of the third strip-shaped region on the base, and the orthographic projection area of the fourth strip-shaped region is smaller than the orthographic projection of the third strip-shaped region area.
  • the pixel area further includes a first light-shielding layer and a second light-shielding layer, the first light-shielding layer is located on a side of the first wiring layer close to the substrate, and the second light-shielding layer is located on The side of the second wiring layer away from the substrate;
  • the first light-shielding layer includes a first light-shielding pattern, and the orthographic projection of the first wiring on the substrate is at least partially the same as the orthographic projection of the first light-shielding pattern on the substrate.
  • the second light-shielding layer includes a second light-shielding pattern, and the orthographic projection of the second trace on the substrate at least partially overlaps with the orthographic projection of the second light-shielding pattern on the substrate.
  • the orthographic projection of the first trace on the substrate is located within the orthographic projection of the first light-shielding pattern on the substrate, and the orthographic projection of the second trace on the substrate is located on the second light-shielding pattern. in the orthographic projection of the base.
  • the orthographic projection of the first light-shielding pattern on the substrate and the orthographic projection of the second light-shielding pattern on the substrate coincide with each other.
  • the material of the first light-shielding layer is one of black matrix and molybdenum oxide
  • the material of the second light-shielding layer is one of black matrix and molybdenum oxide
  • the material of the first light-shielding layer is a black matrix
  • a protective layer is provided between the first light-shielding layer and the first wiring layer.
  • a buffer layer is further provided between the first wiring layer and the first light-shielding layer.
  • the material of the first wiring layer is copper, and the first wiring layer includes a seed layer. , the seed layer is in direct contact with the buffer layer.
  • the material of the first light-shielding layer is molybdenum oxide
  • the material of the first wiring layer is copper
  • the first wiring layer is in direct contact with the first light-shielding layer.
  • both the first dielectric layer and the second dielectric layer are organic materials.
  • the pixel area further includes a first inorganic layer located between the first wiring layer and the first dielectric layer, a first inorganic layer located on a side of the second dielectric layer away from the substrate. second inorganic layer and third inorganic layer.
  • the pixel area further includes at least one exhaust hole, at least one exhaust hole is provided in at least one of the second inorganic layer and the third inorganic layer, and at least one exhaust hole
  • the orthographic projection of the hole on the substrate does not overlap with the orthographic projection of the first part of the first trace on the substrate and the orthographic projection of the second part of the second trace on the substrate.
  • the pixel area includes a plurality of exhaust holes, the plurality of exhaust holes are provided on both sides of the first portion of the first trace along the first direction, and/or, a plurality of exhaust holes Holes are provided on both sides of the second portion of the second trace along the second direction.
  • a binding area is further included, the binding area is located on at least one side of the display area, and the orthographic projection of the binding area on the substrate is the same as the orthographic projection of the second dielectric layer on the substrate. No overlap.
  • a fan-out area is further included, the fan-out area is located on at least one side of the display area, the fan-out area includes a base, a first fan-out portion disposed on the base, A first dielectric layer on the side of the first fan-out portion away from the substrate, a second dielectric layer on the side of the first dielectric layer away from the substrate, and a third dielectric layer on the side of the second dielectric layer away from the substrate.
  • Two fan-out parts A first opening is provided in the first dielectric layer.
  • the second fan-out part is connected to the first fan-out part through the first opening to form a fan-out line.
  • the second dielectric layer A second opening is provided in the layer, the orthographic projection of the first opening on the substrate is located in the orthographic projection of the second opening on the substrate, and the area of the orthographic projection of the second opening on the substrate is larger than the first opening The area of the orthographic projection on the base.
  • the fan-out area further includes a third dielectric layer disposed on a side of the second fan-out portion away from the substrate, a third opening is disposed in the third dielectric layer, and the first The front projection of the opening on the base is located in the front projection of the third opening on the base, and the area of the front projection of the third opening on the base is larger than the area of the front projection of the first opening on the base.
  • the present disclosure also provides a display device, including the aforementioned display backplane.
  • Figure 1 is a schematic plan view of a display backplane according to an exemplary embodiment of the present disclosure
  • Figure 2 is a schematic plan view of a display unit in a display backplane according to an exemplary embodiment of the present disclosure
  • Figure 3 is a schematic cross-sectional structural diagram of a display backplane according to an exemplary embodiment of the present disclosure
  • Figure 4 is a schematic diagram 2 of the cross-sectional structure of a display backplane according to an exemplary embodiment of the present disclosure
  • Figure 5 is a cross-sectional view showing the first light-shielding pattern in the backplane according to an exemplary embodiment of the present disclosure
  • Figure 6 is a second cross-sectional view showing the first light-shielding pattern in the backplane according to an exemplary embodiment of the present disclosure
  • Figure 7 is a schematic plan view of the first wiring in a display unit according to an exemplary embodiment of the present disclosure.
  • Figure 8 is a cross-sectional view of the first dielectric layer and the second dielectric layer in a display unit according to an exemplary embodiment of the present disclosure
  • Figure 9 is a second cross-sectional view of the first dielectric layer and the second dielectric layer in a display unit according to an exemplary embodiment of the present disclosure
  • Figure 10 is a cross-sectional view three of the first dielectric layer and the second dielectric layer in a display unit according to an exemplary embodiment of the present disclosure
  • Figure 11 is a schematic plan view of the first trace and the second trace in the backplane according to the related art
  • Figure 12 is a schematic plan view of the second wiring in a display unit according to an exemplary embodiment of the present disclosure.
  • Figure 13 is a schematic plan view of the first wiring and the second wiring in a display unit according to an exemplary embodiment of the present disclosure
  • Figure 14 is a schematic plan view of the exhaust hole in a display unit according to an exemplary embodiment of the present disclosure.
  • FIG. 15 is a cross-sectional view showing a fan-out area in a backplane according to an exemplary embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrical connection includes the case where the constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • Micro LED/Mini LED displays can achieve large-size displays through splicing and can break through size limitations.
  • large-size LED display panels use cross beams or vertical beams to fix multiple boxes.
  • the LED display backplane is set inside the box.
  • the multiple boxes splice multiple LED display backplanes to form a large-size LED display panel.
  • PPI Pigments Per Inch
  • LED display backplanes are miniaturized, arrayed, and thinned using microprocessing technology.
  • the typical size (such as length) of Micro LED can be less than 50 ⁇ m, such as 10 ⁇ m to 50 ⁇ m.
  • Typical dimensions (e.g. length) of Mini LEDs may be approximately 50 ⁇ m to 150 ⁇ m, such as 80 ⁇ m to 120 ⁇ m.
  • FIG. 1 is a schematic plan view of a display backplane according to an exemplary embodiment of the present disclosure.
  • the display backplane may include a display area 100 and a binding area 200 , the display area 100 is configured for transparent display, and the binding area 200 may be located on at least one side of the display area 100 , configured as a bonded flexible circuit board (Flexible Printed Circuit, referred to as FPC).
  • FPC Flexible Printed Circuit
  • the display area 100 may include a substrate and a plurality of regularly arranged display units 300 disposed on the substrate.
  • At least one display unit 300 may include a pixel area 310 and a light-transmitting area 320.
  • the pixel area 310 may include a pixel area 310 and a light-transmitting area 320.
  • a driving circuit and at least one light-emitting diode are provided on the substrate. The light-emitting diode is connected to the driving circuit.
  • the pixel area 310 is configured to display an image.
  • the light-transmitting area 320 is located outside the pixel area 310 in the display unit 300.
  • the light-transmitting area 320 is It is configured to transmit light, so that the display unit 300 can realize image display in a transparent state, that is, transparent display.
  • the area of the pixel area 310 in the display unit 300 may be larger than the area of the light-transmitting area 320 , or the area of the pixel area 310 may be smaller than the area of the light-transmitting area 320 , or the area of the pixel area 310 may be equal to
  • the area of the light-transmitting area 320 is not limited in this disclosure. Generally, the larger the area of the light-transmitting area 320 is, the greater the transmittance of the display unit 300 is, the greater the transmittance of the display backplane is, and the clearer the image seen through the display backplane is.
  • the binding area 200 may be located on one side of the display area 100 in the second direction Y.
  • the binding area 200 may at least include a plurality of binding sub-areas 201 , and the multiple binding sub-areas 201 may be along the first One direction One direction X and the second direction Y are perpendicular.
  • the bonding terminal is configured to be bonded to a flexible circuit board and connected to an external circuit through the flexible circuit board.
  • FIG. 2 is a schematic plan view of a display unit in a display backplane according to an exemplary embodiment of the present disclosure.
  • the pixel area of a display unit may include a driving circuit and a light-emitting diode group 4 arranged on a substrate.
  • the driving circuit may include first traces arranged in different layers along the thickness direction of the substrate. layer, the second wiring layer and the pixel driver chip 3, the light-emitting diode group 4 may include at least one first light-emitting diode, at least one second light-emitting diode and at least one third light-emitting diode, wherein the first light-emitting diode may be a red-emitting diode.
  • the second light-emitting diode can be a blue LED that emits blue light
  • the third light-emitting diode can be a green LED that emits green light.
  • the pixel area of a display unit may include a driving circuit, a light-emitting diode group and a color conversion layer that are stacked on a substrate in sequence.
  • the light-emitting diode group includes a plurality of blue LEDs, and the blue light emitted by the plurality of blue LEDs can excite
  • the color conversion layer causes the color conversion layer to emit predetermined radiated light, for example, red light and green light.
  • the color conversion layer may be made of quantum dots or phosphors.
  • the first wiring layer may include a plurality of first wiring lines 1 , the first wiring lines 1 may include a first portion extending along the second direction Y, and the first wiring line 1 may include a first scan line.
  • VCC1 data signal line DATA, ground line GND, first driving line VGB and second driving line VR.
  • the second wiring layer may include a plurality of second wiring lines 2, the second wiring lines 2 may include a second portion extending along the first direction X, and the second wiring lines 2 may include a second scan line VCC2.
  • the second portion of the second scan line VCC2 may be located on one side of the second direction Y within the display unit.
  • the first part of the first driving line VGB may be located on a side opposite to the first direction X in the display unit, and the first part of the first scanning line VCC1 may be located on a side of the first direction X in the display unit.
  • the second part of the two second scan lines VCC2 defines a display unit row, and the first part of the first driving line VGB and the first part of the first scan line VCC1 define a display unit column.
  • the second parts of the two second scan lines VCC2 intersect with the first parts of the first drive line VGB and the first part of the first scan line VCC1 to define a display unit.
  • the first scan line VCC1 may be connected to the second scan line VCC2 through a via hole.
  • the second scan line VCC2 is configured to provide a scan signal. Since the chip terminal of the bound pixel driving chip 3 is located on the side of the display unit in the second direction Y, the first scan line VCC1 is configured to extend in the first direction X.
  • the second scan line VCC2 is turned to the second direction Y to facilitate connection with the chip terminal.
  • the first driving line VGB may be connected to the blue LED and the green LED respectively, and be configured to provide driving signals to the blue LED and the green LED respectively.
  • the first part of the second driving line VR may be located between the first part of the first driving line VGB and the first part of the ground line GND.
  • the second driving line VR may be connected to the red LED and configured to provide a driving signal to the red LED. . Since the light-emitting characteristics of blue LED and green LED are basically the same, while the light-emitting characteristics of red LED and blue/green LED are different, the blue LED and green LED can be driven by the same first driving line VGB, while the red LED A second drive line VR driver needs to be used separately.
  • the blue LED and the green LED can each be connected to a driving line, which is not limited in this disclosure.
  • the first part of the data signal line DATA and the first part of the ground line GND may be located between the first part of the first driving line VGB and the first part of the first scanning line VCC1, and the pixel driving chip 3 may be located between the data signal line DATA and the ground line GND.
  • the data signal line DATA is configured to provide a data signal to the pixel driving chip 3
  • the ground line GND is configured to provide a ground signal
  • the pixel driving chip 3 is configured to Under the control of the first scan line VCC1 and the second scan line VCC2, drive signals are provided to the first light-emitting device, the second light-emitting device and the third light-emitting device according to the data signal provided by the data signal line DATA to control the first light-emitting device, The second light-emitting device and the third light-emitting device light up.
  • At least one first light-emitting diode, at least one second light-emitting diode, and at least one third light-emitting diode may be sequentially disposed along the second direction Y, and the first portion of the first trace 1 includes a first light-emitting diode along the first direction Y.
  • On the opposite first and second edges of This prevents the light-emitting diode from occupying the space of the light-transmitting area 320, increases the area of the light-transmitting area 320 in the display unit, and improves the light-emitting quality of the light-emitting diode.
  • the first portion of at least one of the ground line GND, the first scan line VCC1, the data signal line DATA, the first drive line, and the VGB second drive line VR includes first opposite first drive lines VR in the first direction X.
  • the edge and the second edge, the orthographic projection of the at least one first light-emitting diode, the at least one second light-emitting diode and the at least one third light-emitting diode on the substrate are located in the area defined by the first edge and the second edge.
  • the first part of the ground line GND includes a first edge and a second edge opposite to each other along the first direction within the area defined by the first edge and the second edge.
  • At least one first light-emitting diode, at least one second light-emitting diode, and at least one third light-emitting diode may be a sub-millimeter light-emitting diode (Mini Light Emitting Diode, Mini LED for short) and a micro light-emitting diode (Micro Light). Emitting Diode, abbreviated as Micro LED).
  • the light-emitting diode LED includes two pins (an anode pin and a cathode pin).
  • the display unit is provided with connection terminals corresponding to the LED pins one-to-one.
  • the connection terminals in the display unit may include: a red positive connection terminal R+ configured to connect to the positive pin of the red LED, and a red negative connection terminal R- configured to connect to the negative pin of the red LED.
  • the blue-light positive connection terminal B+ configured to connect the positive pin of the blue LED
  • the blue-light negative connection terminal B- configured to connect the negative pin of the blue LED
  • the green positive connection terminal G+ configured to connect the positive pin of the green LED
  • the configuration The green negative connection terminal G- is connected to the negative pin of the green LED.
  • the red light positive connection terminal R+ may be connected to the second driving line VR
  • the blue light positive connection terminal B+ may be connected to the first driving line VGB
  • the green light positive connection terminal G+ may be connected to the first driving line VGB.
  • the pixel driving chip 3 may include 6 chip pins.
  • the display unit is provided with chip terminals corresponding to the chip pins, namely: a first chip terminal and a second chip terminal. , the third chip terminal, the fourth chip terminal, the fifth chip terminal and the sixth chip terminal.
  • the first chip terminal may be connected to the red light negative electrode connection terminal R-
  • the second chip terminal may be connected to the blue light negative electrode connection terminal B-
  • the third chip terminal may be connected to the green light negative electrode connection terminal G-.
  • the fourth chip terminal may be connected to the first scan line VCC1
  • the fifth chip terminal may be connected to the data signal line DATA
  • the sixth chip terminal may be connected to the ground line GND.
  • the first scan line VCC1, the data signal line DATA, the ground line GND, and the first and second drive lines VR can be provided on the first wiring layer in the same layer and formed simultaneously through the same process.
  • a connection terminal connected to the light-emitting diode, a plurality of chip terminals connected to the pixel driver chip 3 and the second scanning line VCC2 may be provided on the same layer on the second wiring layer and formed simultaneously through the same process.
  • the aforementioned connection may be a direct connection or a via-hole connection.
  • the plurality of bonding terminals in the bonding area may be disposed on the second wiring layer, disposed on the same layer as the plurality of connection terminals and the plurality of chip terminals of the display unit, and formed simultaneously through the same process.
  • the number of light-emitting diodes in the light-emitting diode group in the display unit may be multiple, such as 4, 5, 6, 8, etc., and the arrangement of the multiple light-emitting diodes may be determined according to the actual situation. settings, this disclosure is not limited here.
  • the first width of the first driving line VGB may be approximately 60 ⁇ m to 80 ⁇ m, for example, may be approximately 70 ⁇ m.
  • the first width of the second driving line VR may be approximately 20 ⁇ m to 40 ⁇ m, for example, may be approximately 30 ⁇ m.
  • the first width of the ground line GND may be approximately 180 ⁇ m to 200 ⁇ m, for example, may be approximately 190 ⁇ m.
  • the first width of the data signal line DATA may be approximately 10 ⁇ m to 30 ⁇ m, for example, may be approximately 20 ⁇ m.
  • the first width of the first scan line VCC1 may be approximately 20 ⁇ m to 40 ⁇ m, for example, may be approximately 30 ⁇ m. Wherein, the first width is the size in the first direction X.
  • the second width of the second scan line VCC2 may be approximately 60 ⁇ m to 80 ⁇ m, for example, may be approximately 70 ⁇ m.
  • the second width is the size in the second direction Y.
  • the first spacing between the first driving line VGB and the second driving line VR may be approximately 35 ⁇ m to 55 ⁇ m, for example, may be approximately 45 ⁇ m.
  • the first spacing between the data signal line DATA and the first scan line VCC1 may be approximately 35 ⁇ m to 55 ⁇ m, for example, may be approximately 45 ⁇ m.
  • the first spacing between the second driving line VR and the ground line GND may be approximately 600 ⁇ m to 800 ⁇ m, for example, may be approximately 690 ⁇ m.
  • the first spacing between the ground line GND and the data signal line DATA may be approximately 600 ⁇ m to 800 ⁇ m, for example, may be approximately 690 ⁇ m.
  • the first distance between the light emitting diode LED and the pixel driving chip 3 may be approximately 100 ⁇ m to 140 ⁇ m, for example, may be approximately 120 ⁇ m.
  • the first spacing is the size in the first direction X.
  • the second spacing between adjacent light-emitting diode LEDs may be approximately 80 ⁇ m to 120 ⁇ m, for example, may be approximately 100 ⁇ m.
  • the second spacing is the size in the second direction Y.
  • the display unit may further include a first light-shielding layer and a second light-shielding layer.
  • the first light-shielding layer is located on a side of the first wiring layer close to the substrate, and the second light-shielding layer is located on a side of the second wiring layer away from the substrate. side.
  • the orthographic projections of the first light-shielding layer and the second light-shielding layer on the substrate at least partially overlap with the orthographic projections of the driving circuit and the light-emitting diode group on the substrate, so as to reduce the visibility of multiple signal lines and improve the display quality of the display backplane. .
  • the first light-shielding layer and the second light-shielding layer (the area where the driving circuit and the light-emitting diode group are located) in the display unit form a component pixel area, which is an opaque area, and is outside the first light-shielding layer and the second light-shielding layer
  • the area is the light-transmitting area 320.
  • the area shown by the dotted line box in Figure 2 is the light-transmitting area 320.
  • the area outside the dotted line box is the area where the first light-shielding layer and the second light-shielding layer are located.
  • Figure 3 is a schematic cross-sectional structure diagram of a display backplane according to an exemplary embodiment of the present disclosure.
  • Figure 3 illustrates the cross-sectional structure of the pixel area 310 and the light-transmitting area 320 in the display area and the binding sub-area 201 in the binding area 200.
  • the pixel area 310 of the display backplane may include a pixel structure layer disposed on the substrate 10
  • the light-transmitting area 320 of the display backplane may include grooves, and the groove bottoms Being the surface of the substrate 10
  • the binding sub-area 201 of the display backplane may include a binding structure layer disposed on the substrate 10 .
  • the pixel structure layer of the pixel area 310 may include: a first light-shielding layer disposed on the substrate 10 , the first light-shielding layer including a third light-shielding pattern 11 , and a first light-shielding layer disposed on a side away from the substrate.
  • the inorganic layer 18 is provided on the second light-shielding layer on the side of the third inorganic layer 18 away from the substrate.
  • the second light-shielding layer includes a fourth light-shielding pattern 19 and is provided on the third dielectric layer 20 on the side of the second light-shielding layer away from the substrate.
  • the light-emitting diode 50 on the side of the third dielectric layer 20 away from the substrate is connected to the anode connection terminal 33 and the cathode connection terminal 34 respectively.
  • the orthographic projection of the third light-shielding pattern 11 on the substrate 10 overlaps with the orthographic projection of the first electrode 31 and the second electrode 32 on the substrate 10 respectively, and the orthographic projection of the fourth light-shielding pattern 19 on the substrate 10 respectively It overlaps with the orthographic projection of the positive connection terminal 33 and the negative connection terminal 34 on the base 10 .
  • a first groove is provided in the third dielectric layer 20, the first groove exposes the positive connection terminal 33 and the negative connection terminal 34, and the first groove is configured to print with the first light-emitting device, Solder paste is used to connect at least one of the second light-emitting device and the third light-emitting device, and the light-emitting diode 50 is connected to the anode connection terminal 33 and the cathode connection terminal 34 respectively through the first groove.
  • the pixel driving chip 3 may include a plurality of chip pins.
  • chip terminals corresponding to the chip pins are provided in the display unit, and the chip terminals may be provided on the second wiring layer.
  • the third dielectric layer 20 is provided with a second groove. The second groove exposes the chip terminals. The second groove is configured to print solder paste connected to the pixel driving chip.
  • the pixel driving chip 3 communicates with the chip terminals through the second groove. connect.
  • the pixel structure layer of the pixel area 310 is removed in the light-transmitting area 320, thereby increasing the light transmittance of the light-transmitting area 320 and improving the display effect of the display backplane.
  • the binding structure layer of the binding sub-region 201 may include: a buffer layer 13 provided on the substrate 10, a first wiring layer provided on the side of the buffer layer 13 away from the substrate, and a first wiring layer.
  • the layer at least includes a first bonding electrode 43 and a second bonding electrode 44, a first inorganic layer 14 disposed on the side of the first wiring layer away from the substrate, and a first dielectric disposed on the side of the first inorganic layer 14 away from the substrate.
  • the wiring layer is away from the third dielectric layer 20 on one side of the substrate.
  • the third dielectric layer 20 is provided with a second groove that exposes the first binding terminal 41 and the second binding terminal 42 .
  • the first dielectric layer 15, the second dielectric layer 16 and the third dielectric layer 20 in the pixel structure layer can use organic materials
  • the buffer layer 13, the first inorganic layer 14, the The second inorganic layer 17 and the third inorganic layer 18 can be made of inorganic materials
  • the first wiring layer and the second wiring layer can be made of conductive metal materials, such as copper.
  • the first dielectric layer 15 in the binding structure layer can use organic materials
  • the buffer layer 13, the first inorganic layer 14, the second inorganic layer 17 and the third inorganic layer 18 can use inorganic materials.
  • the first wiring layer and the second wiring layer can be made of conductive metal material, such as copper.
  • the pixel area 310 adopts two dielectric layers, namely the first dielectric layer 15 and the second dielectric layer 16 .
  • the binding sub-region 201 adopts a dielectric layer, namely the first dielectric layer 15.
  • the orthographic projection of the second dielectric layer 16 on the substrate 10 does not overlap with the orthographic projection of the binding region on the substrate 10.
  • the binding sub-region 201 has There is no second dielectric layer in the fixed structure layer.
  • the thickness of the dielectric layer in the binding sub-region 201 is smaller than the thickness of the dielectric layer in the pixel region 310 .
  • the present disclosure can reduce the step difference of the binding sub-region 201, avoid bonding defects caused by large step differences, improve the quality of the bonding process, and improve the quality of the display backplane. Rate.
  • the buffer layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single-layer structure, or may be a multi-layer structure. layer composite structure.
  • silicon nitride SiN can be used as the buffer layer.
  • the first wiring layer may be made of any metal material, such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), chromium (Cr), and tungsten (W).
  • metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), chromium (Cr), and tungsten (W).
  • metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), chromium (Cr), and tungsten (W).
  • metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), chromium (Cr), and tungsten (W).
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the first wiring layer may include a stacked first sub-layer, a second sub-layer and a third sub-layer.
  • the first sub-layer is disposed on a side of the buffer layer 13 away from the substrate, and the second sub-layer is disposed on the first The sub-layer is on a side away from the substrate, and the third sub-layer is disposed on a side of the second sub-layer away from the substrate.
  • the first sub-layer can be made of molybdenum-niobium alloy MoNb to improve adhesion
  • the second sub-layer can be made of copper Cu to reduce resistance
  • the third sub-layer can be made of MoNb to prevent oxidation to form a stacked structure.
  • MoNb/Cu/MoNb MoNb/Cu/MoNb.
  • the overall thickness of the first wiring layer may be approximately 1.5 ⁇ m to 7 ⁇ m. According to the law of resistance, the larger the cross-sectional area of the trace, the smaller the resistance. Therefore, a thicker first trace layer can reduce the resistance and improve the electrical performance.
  • the substrate may be a hard substrate or a flexible substrate.
  • the hard substrate may be glass or the like
  • the flexible substrate may be polyimide (PI) or the like.
  • the first inorganic layer 14 , the second inorganic layer 17 and the third inorganic layer 18 may all adopt any of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON).
  • silicon oxide SiOx
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • One or more types can be a single-layer structure or a multi-layer composite structure.
  • the first inorganic layer 14 may be silicon nitride Si 3 N 4 .
  • the first dielectric layer 12 , the second dielectric layer 16 and the third dielectric layer 20 may be made of organic materials, such as resin.
  • Figure 4 is a second schematic diagram of the cross-sectional structure of a display backplane according to an exemplary embodiment of the present disclosure.
  • Figure 4 illustrates the cross-sectional structure of the first wiring in the display area.
  • Figure 4 can be a cross-sectional view along the A-A’ direction in Figure 2. In an exemplary embodiment, as shown in FIG.
  • the pixel area 310 of the display backplane may include a wiring structure layer disposed on the substrate 10
  • the wiring structure layer may include: a first light-shielding layer disposed on the substrate 10
  • the first light-shielding layer includes a first light-shielding pattern 21, a protective layer 12 provided on the side of the first light-shielding layer away from the substrate, a buffer layer 13 provided on the side of the protective layer 12 away from the substrate, and a buffer layer 13 provided on the side of the protective layer 12 away from the substrate.
  • the first wiring layer includes at least a plurality of first wirings 1.
  • the first inorganic layer 14 is disposed on the side of the first wiring layer away from the substrate.
  • the first inorganic layer 14 is disposed on the side away from the substrate.
  • the first dielectric layer 15 on the side of the first dielectric layer 15 is provided on the side away from the substrate.
  • the second dielectric layer 16 is provided on the side of the second dielectric layer 16 away from the substrate.
  • the second inorganic layer 17 is provided on the side of the second dielectric layer 16 away from the substrate. 17 is a second wiring layer (not shown in the figure) on the side away from the substrate.
  • the second wiring layer includes a plurality of second wiring lines (not shown in the figure), and is arranged on the side of the second wiring layer away from the substrate.
  • the third inorganic layer 18 is provided with a second light-shielding layer on the side of the third inorganic layer 18 away from the substrate.
  • the second light-shielding layer includes a second light-shielding pattern 22, and the third dielectric layer is provided on the side of the second light-shielding layer away from the substrate. 20.
  • the ratio of the thickness of the first trace 1 in the first trace layer to the thickness of the second trace in the second trace layer is greater than 5; for example, the thickness of the first trace 1 in the first trace layer
  • the thickness of 1 is about 5 ⁇ m to 8 ⁇ m; the thickness of the second trace in the second trace layer is about 0.5 ⁇ m to 1 ⁇ m.
  • the sum of the thickness of the first dielectric layer 15 and the thickness of the second dielectric layer 16 is greater than 3 ⁇ m, so as to reduce the thickness of the first wiring 1 in the first wiring layer and the second wiring layer in the second wiring layer.
  • the thickness of the first dielectric layer 15 is less than 2 ⁇ m to avoid poor binding in the binding area due to the excessive thickness of the first dielectric layer 15 .
  • the orthographic projection of the first trace 1 on the substrate 10 at least partially overlaps the orthographic projection of the first light-shielding pattern 21 on the substrate 10 .
  • the first light-shielding pattern 21 includes a first light-shielding area extending along the first direction Overlap; the orthographic projection of at least one second wiring 2 on the substrate 10 overlaps with the first light-shielding area, and the second light-shielding area of the first light-shielding pattern 21 is located on the side of the first wiring layer close to the substrate 10 and is It is configured to block the ambient light that enters the first trace 1 through the substrate, weaken the visibility of the first trace 1, and improve the display effect of the display backplane; the first light-shielding area of the first light-shielding pattern 21 is located on the first trace.
  • the side of the line layer close to the substrate 10 is configured to block the ambient light incident on the second trace 2 through the substrate, reduce the visibility of the second trace 2, and improve the display effect of the display backplane
  • the orthographic projection of the second trace on the substrate 10 and the orthographic projection of the second light shielding pattern 22 on the substrate 10 at least partially overlap.
  • the second light-shielding pattern 22 includes a third light-shielding area extending along the first direction Overlap; the orthographic projection of at least one second wiring 2 on the substrate 10 overlaps with the third light-shielding area, and the fourth light-shielding area of the second light-shielding pattern 22 is located on the side of the second wiring layer away from the substrate 10 and is It is configured to block the ambient light incident on the first trace 1, weaken the visibility of the first trace 1, and improve the display effect of the display backplane; the third light shielding area of the second light shielding pattern 22 is located away from the second trace layer One side of the substrate 10 is configured to block the ambient light incident on the second trace 2, reduce the visibility of the second trace 2, and improve the display effect of the display backplane.
  • the orthographic projection of the first trace 1 on the substrate 10 is located within the orthographic projection of the second light-shielding area of the first light-shielding pattern 21 on the substrate 10 , and is located in the fourth light-shielding area of the second light-shielding pattern 22 The area is within the orthographic projection on the substrate 10 , so that the first trace 1 is completely blocked by the first light-shielding pattern 21 and the second light-shielding pattern 22 , thereby achieving double-sided shielding of the first trace 1 .
  • the orthographic projection of the second trace 2 on the substrate 10 is located within the orthographic projection of the first light-shielding area of the first light-shielding pattern 21 on the substrate 10 , and is located in the third light-shielding area of the second light-shielding pattern 22 The area is within the orthographic projection on the substrate 10 , so that the second trace 2 is completely blocked by the first light-shielding pattern 21 and the second light-shielding pattern 22 , thereby achieving double-sided shielding of the second trace 2 .
  • the orthographic projection of the first light-shielding pattern 21 on the substrate 10 and the orthographic projection of the second light-shielding pattern 22 on the substrate 10 coincide with each other.
  • the orthographic projection of the first light-shielding area of the first light-shielding pattern 21 on the substrate 10 coincides with the orthographic projection of the third light-shielding area of the second light-shielding pattern 22 on the substrate 10 .
  • the orthographic projection of the second light-shielding area of the first light-shielding pattern 21 on the substrate 10 coincides with the orthographic projection of the fourth light-shielding area of the second light-shielding pattern 22 on the substrate 10 .
  • the first trace 1 and the second trace 2 are blocked by the first light-shielding pattern 21 on the side close to the substrate 10, and the first trace 1 and the second trace 2 are blocked by the second light-shielding pattern on the side away from the substrate 10. 22 blocks light to achieve double-sided blocking of the first trace and the second trace.
  • the first trace and the second trace will have strong reflection under ambient light, which will affect the display effect of the display backplane.
  • Table 1 shows the display effect of a display backplane using a single-sided light-shielding layer.
  • Table 2 shows the display effect of a display backplane using a double-sided light shielding layer according to an embodiment of the present disclosure.
  • Table 3 shows the display effects of reflectivity and color gamut of a display backplane using a double-sided light shielding layer according to an embodiment of the present disclosure.
  • Table 1 shows the display effect of a display backplane using a single-sided light-shielding layer.
  • Table 2 shows the display effect of a display backplane using a double-sided light shielding layer.
  • Table 3 shows the reflectivity and color gamut display effects of a display backplane using a double-sided light shielding layer.
  • the material of both the first light-shielding layer and the second light-shielding layer may be one of black matrix and molybdenum oxide.
  • the first light-shielding layer and the second light-shielding layer may also be made of other light-shielding materials, preferably light-shielding materials that can block visible light.
  • At least one of the first light-shielding layer and the second light-shielding layer may adopt amorphous silicon.
  • FIG. 5 is a cross-sectional view showing the first light-shielding pattern in the backplane according to an exemplary embodiment of the present disclosure.
  • the first light-shielding pattern 21 of the first light-shielding layer may be a black matrix, and the first light-shielding pattern 21 of the first light-shielding layer and the first wiring 1 of the first wiring layer A protective layer 12 and a buffer layer 13 are provided between them.
  • the buffer layer 13 is located on the side of the protective layer 12 away from the substrate 10 .
  • the first wiring 1 of the first wiring layer may be made of copper.
  • the first wiring 1 of the first wiring layer may include a seed layer.
  • the seed layer of the first wiring 1 of the first wiring layer may be connected to the buffer layer 13 direct contact.
  • the buffer layer 13 and the protective layer 12 can prevent the seed layer from falling off and ensure the stability of the black matrix.
  • the protective layer 12 may be made of organic material, such as resin.
  • FIG. 6 is a second cross-sectional view showing the first light-shielding pattern in the backplane according to an exemplary embodiment of the present disclosure.
  • the first light-shielding pattern 21 of the first light-shielding layer may use molybdenum oxide.
  • the first wiring 1 can be made of copper, and the first light-shielding pattern can be in direct contact with the first wiring 1 , simplify the process and reduce production costs.
  • the second light-shielding pattern 22 since there is a step difference between the second light-shielding pattern 22 and the substrate 10 of the light-transmitting area 320 , and the step difference is generally greater than 10 ⁇ m, the second light-shielding pattern 22 is easily transparent during preparation. A large area of residue occurs at the step difference of the area 320, which reduces the light transmittance of the light-transmitting area 320 and affects the light transmittance of the display backplane.
  • the display backplane of the embodiment of the present disclosure increases the development time of the second light-shielding pattern 22 and reduces the residual area of the second light-shielding pattern 22 at the step of the light-transmitting area 320, thereby improving the light transmittance of the display backplane.
  • FIG. 7 is a schematic plan view of a first wiring in a display unit according to an exemplary embodiment of the present disclosure.
  • the first part of at least one first trace 1 in a display unit includes a first edge 61 and a second edge 62 opposite along the first direction X.
  • the orthographic projection of the first part of the trace 1 on the substrate is located within the orthographic projection of the first dielectric layer 15 on the substrate.
  • the orthographic projection of the first dielectric layer 15 on the substrate is located within the orthographic projection of the second dielectric layer 16 on the substrate.
  • the second dielectric layer 16 has a third edge 63 and a fourth edge 64 opposite along the first direction X.
  • the first edge 61 and the third edge 63 are located on the same side of the first direction of the first trace 1 .
  • the second edge 62 and The fourth edge 64 is located on the same side of the first direction X of the first trace 1, and the first vertical distance L1 from the first edge 61 to the third edge 63 is greater than or equal to 20 ⁇ m.
  • the first vertical distance L1 is approximately 20 ⁇ m to 30 ⁇ m.
  • the second vertical distance L2 from the second edge 62 to the fourth edge 64 is greater than or equal to 20 ⁇ m.
  • the second vertical distance L2 is approximately 20 ⁇ m to 30 ⁇ m.
  • the first vertical distance L1 and the second vertical distance L2 are vertical distances in the first direction X respectively.
  • the first dielectric layer has third and fourth edges opposite to each other along the first direction X, the first edge and the third edge are located on the same side of the first trace in the first direction X, and the second edge and The fourth edge is located on the same side of the first direction X of the first trace, and the first vertical distance L1 from the first edge to the third edge is greater than or equal to 20 ⁇ m.
  • the first vertical distance L1 from the first edge to the third edge is approximately 20 ⁇ m to 30 ⁇ m.
  • the second vertical distance L2 from the second edge to the fourth edge is greater than or equal to 20 ⁇ m.
  • the second vertical distance L2 is approximately 20 ⁇ m to 30 ⁇ m.
  • the first vertical distance L1 and the second vertical distance L2 are vertical distances in the first direction X respectively.
  • the embodiment of the present disclosure shows that the backplane reduces the third vertical distance L1 by forming a first vertical distance L1 between the first edge 61 and the third edge 63 and forming a second vertical distance L2 between the second edge 62 and the fourth edge 64 .
  • the step difference between the two light-shielding patterns 22 and the base 10 of the light-transmitting area 320 reduces the remaining area of the second light-shielding pattern 22 at the step difference of the light-transmitting area 320 and improves the light transmittance of the display backplane.
  • the first dielectric layer 15 includes a first strip-shaped region extending along the second direction Y
  • the second dielectric layer 16 includes a second strip-shaped region extending along the second direction Y.
  • the orthographic projection of the first strip-shaped region on the base is located within the orthographic projection of the second strip-shaped region on the base, and the orthographic projection area of the first strip-shaped region is smaller than the orthographic projection area of the second strip-shaped region.
  • the second strip-shaped area includes a first side wall and a second side wall.
  • the first side wall includes a first inclined surface 71 , a second inclined surface 72 and a first boss surface 73 .
  • the first inclined surface 71 and the second inclined surface 72 connected through the first boss surface 73 .
  • the second side wall includes a third inclined surface 74 , a fourth inclined surface 75 and a second boss surface 76 .
  • the third inclined surface 74 and the fourth inclined surface 75 are connected by the second boss surface 76 .
  • FIG. 9 is a second cross-sectional view of the first dielectric layer and the second dielectric layer in a display unit according to an exemplary embodiment of the present disclosure.
  • the orthographic projection of the first strip-shaped region on the substrate is located within the orthographic projection of the second strip-shaped region on the substrate, and the orthographic projection area of the first strip-shaped region is smaller than that of the second strip-shaped region.
  • the second strip-shaped area includes a first side wall 77 and a second side wall 78. Both the first side wall 77 and the second side wall 78 have inclined surfaces.
  • FIG. 10 is a cross-sectional view of the first dielectric layer and the second dielectric layer in a display unit according to an exemplary embodiment of the present disclosure.
  • the orthographic projection of the second strip-shaped region on the base is located within the orthographic projection of the first strip-shaped region on the base, and the orthographic projection area of the second strip-shaped region is smaller than that of the first strip-shaped region.
  • the second strip-shaped area includes a first side wall 77 and a second side wall 78.
  • the first strip-shaped area includes a third side wall 79 and a fourth side wall 80.
  • the first side wall 77 and the third side wall 79 are located along the first path.
  • the second side wall 78 and the fourth side wall 80 are located on the same side of the first line 1.
  • the surface of the first side wall 77 and the surface of the third side wall 79 form an inclined surface.
  • the surface of wall 78 and the surface of fourth side wall 80 form an inclined surface.
  • the orthographic projection of the second strip-shaped area may also coincide with the orthographic projection of the first strip-shaped area, which will not be described in detail here.
  • FIG. 11 is a schematic plan view showing the first trace and the second trace in the backplane according to the related art.
  • the first trace 1 in the related art display backplane includes a first portion extending along the second direction Y
  • the second trace 2 includes a second portion extending along the first direction X. part. Since there is a large step difference between the second part of the second trace 2 and the substrate 10 of the light-transmitting area 320 , when the second trace 2 is being prepared, the second trace 2 is prone to edge edges at the step difference of the light-transmitting area 320 . A remains a extending in the second direction Y, and the remaining a may easily cause a short circuit in the adjacent second trace 2 .
  • FIG. 12 is a schematic plan view of the second wiring in a display unit according to an exemplary embodiment of the present disclosure.
  • the second portion of at least one second trace 2 in a display unit includes fifth edges 65 and sixth edges 66 opposite along the second direction Y.
  • At least one The orthographic projection of the second part of the second trace 2 on the substrate is located within the orthographic projection of the first dielectric layer 15 on the substrate.
  • the orthographic projection of the first dielectric layer 15 on the substrate is located within the orthographic projection of the second dielectric layer 16 on the substrate.
  • the second dielectric layer 16 has a seventh edge 67 and an eighth edge 68 opposite along the second direction Y.
  • the fifth edge 65 and the seventh edge 67 are located on the same side of the second trace 2 in the second direction Y.
  • the eighth edge 68 is located on the same side of the second direction Y of the second trace 2, and the third vertical distance L3 from the fifth edge 65 to the seventh edge 67 is greater than or equal to 20 ⁇ m.
  • the third vertical distance L3 is approximately 20 ⁇ m to 30 ⁇ m.
  • the fourth vertical distance L4 from the sixth edge 66 to the eighth edge 68 is greater than or equal to 20 ⁇ m.
  • the third vertical distance L3 is approximately 20 ⁇ m to 30 ⁇ m.
  • the third vertical distance L3 and the fourth vertical distance L4 are respectively the vertical distances in the second direction Y.
  • the first dielectric layer has seventh and eighth edges opposite to each other along the second direction Y, the fifth edge and the seventh edge are located on the same side of the second trace in the second direction Y, and the sixth edge and The eighth edge is located on the same side of the second direction Y of the second trace, and the third vertical distance L3 from the fifth edge to the seventh edge is greater than or equal to 20 ⁇ m.
  • the third vertical distance L3 is approximately 20 ⁇ m to 30 ⁇ m.
  • the fourth vertical distance L4 from the sixth edge to the eighth edge is greater than or equal to 20 ⁇ m.
  • the third vertical distance L3 is approximately 20 ⁇ m to 30 ⁇ m.
  • the first dielectric layer 15 includes a third strip-shaped region extending along the first direction X
  • the second dielectric layer 16 includes a fourth strip-shaped region extending along the first direction X
  • the third strip-shaped region The orthographic projection on the base is located within the orthographic projection of the fourth strip-shaped region on the base, and the orthographic projection area of the third strip-shaped region is smaller than the orthographic projection area of the fourth strip-shaped region.
  • the first dielectric layer includes a third strip-shaped region extending along the first direction X
  • the second dielectric layer includes a fourth strip-shaped region extending along the first direction The orthographic projections of the fourth strip area overlap.
  • the first dielectric layer includes a third strip-shaped region extending along the first direction X
  • the second dielectric layer includes a fourth strip-shaped region extending along the first direction X
  • the fourth strip-shaped region is located on the substrate.
  • the orthographic projection is located within the orthographic projection of the third strip-shaped region on the base, and the orthographic projection area of the fourth strip-shaped region is smaller than the orthographic projection area of the third strip-shaped region.
  • the embodiment of the present disclosure shows that the backplane reduces the third vertical distance L3 by forming a third vertical distance L3 between the fifth edge 65 and the seventh edge 67 , and forming a fourth vertical distance L4 between the sixth edge 66 and the eighth edge 68 .
  • the step difference between the two light-shielding patterns 22 and the base 10 of the light-transmitting area 320 reduces the remaining area of the second light-shielding pattern 22 at the step difference of the light-transmitting area 320 and improves the light transmittance of the display backplane.
  • FIG. 13 is a schematic plan view of the first wiring and the second wiring in a display unit according to an exemplary embodiment of the present disclosure.
  • the embodiment of the present disclosure shows that when the second wiring 2 is prepared on the backplane, the residual b of the second wiring 2 in the light-transmitting area 320 is formed in the first dielectric layer 15 or the second dielectric layer 16 edge of one, thereby preventing the residual b from causing a short circuit between adjacent second traces 2.
  • the pixel area of the display unit of the exemplary embodiment of the present disclosure further includes at least one exhaust hole 90 , and the exhaust hole 90 includes a first sub-exhaust hole and a second sub-row.
  • the first sub-exhaust hole is arranged in the second inorganic layer 17, and the first sub-exhaust hole penetrates the second inorganic layer 17 in the thickness direction of the second inorganic layer 17; the second sub-exhaust hole is arranged in the third inorganic layer 17.
  • the second sub-exhaust hole penetrates the third inorganic layer 18 in the thickness direction of the third inorganic layer 18; the orthographic projection of a first sub-exhaust hole on the base and the orthographic projection of a second sub-exhaust hole on the base At least partially overlap to form one exhaust hole 90, and the area of the orthogonal projection of the first sub-exhaust hole on the base is smaller than the area of the orthogonal projection of the second sub-exhaust hole on the base.
  • the back plate can discharge the water vapor in the first dielectric layer and the second dielectric layer through the exhaust hole 90 to prevent the membrane from bursting.
  • FIG. 14 is a schematic plan view of an exhaust hole in a display unit according to an exemplary embodiment of the present disclosure.
  • the display unit of the exemplary embodiment of the present disclosure includes a plurality of exhaust holes 90 , and the plurality of exhaust holes 90 are respectively provided in the first part of the first trace 1 along the first direction.
  • a plurality of exhaust holes 90 are arranged at intervals along the second direction Y.
  • the orthographic projection of the plurality of exhaust holes 90 on the substrate does not overlap with the orthographic projection of the first trace 1 on the substrate.
  • the orthographic projection of the first sub-exhaust hole and the second sub-exhaust hole in the exhaust hole 90 on the base may be a regular or irregular shape such as a rectangle, a circle, an ellipse, a rhombus, a polygon, or the like.
  • the orthographic projection of the first sub-exhaust hole and the second sub-exhaust hole in the exhaust hole 90 on the base may be a rectangle.
  • the vertical distance between the edge of the first sub-exhaust hole in the exhaust hole 90 close to the side of the first trace 1 in the first direction X and the edge of the first trace 1 is about 1 ⁇ m to 5 ⁇ m.
  • the exhaust The vertical distance between the edge of the first sub-exhaust hole in the hole 90 close to the side of the first trace 1 in the first direction X and the edge of the first trace 1 is about 4 ⁇ m.
  • the vertical distance between the edges of the second sub-exhaust holes in the adjacent exhaust holes 90 in the second direction Y is about 100 ⁇ m to 200 ⁇ m.
  • the second sub-row in the adjacent exhaust holes 90 in the second direction Y The vertical distance between the pore edges is approximately 150 ⁇ m.
  • the vertical distance between the two edges of the first sub-exhaust hole in the exhaust hole 90 in the first direction X is about 5 ⁇ m to 10 ⁇ m.
  • the first sub-exhaust hole in the exhaust hole 90 is in the first direction X
  • the vertical distance between the edges on both sides is approximately 9 ⁇ m.
  • the vertical distance between the two edges of the second sub-exhaust hole in the exhaust hole 90 in the first direction X is about 10 ⁇ m to 20 ⁇ m.
  • the second sub-exhaust hole in the exhaust hole 90 is in the first direction X.
  • the vertical distance between the edges on both sides is approximately 11 ⁇ m.
  • the display unit of the exemplary embodiment of the present disclosure includes a plurality of exhaust holes.
  • the plurality of exhaust holes are provided on both sides of the second portion of the second trace along the second direction Y and are provided on A plurality of exhaust holes on both sides of the second part are arranged at intervals along the first direction X.
  • the orthographic projection of the plurality of exhaust holes on the substrate does not overlap with the orthographic projection of the second trace on the substrate.
  • FIG. 15 is a cross-sectional view showing a fan-out area in a backplane according to an exemplary embodiment of the present disclosure.
  • the display unit of the exemplary embodiment of the present disclosure further includes a fan-out area, the fan-out area is located between the display area and the binding area, and the fan-out area includes a plurality of fan-out lines 3 , a plurality of fanout lines 3 are configured to connect the first wiring of the display area in a fanout wiring manner.
  • the fan-out area includes a protective layer 12 provided on the substrate 10 , a buffer layer 13 provided on the side of the protective layer 12 away from the substrate 10 , a first wiring layer provided on the side of the buffer layer 13 away from the substrate 10 , and a first wiring layer.
  • the layer includes a plurality of first fan-out portions 301, a first dielectric layer 15 provided on the side of the first wiring layer away from the substrate 10, a second dielectric layer 16 provided on the side of the first dielectric layer 15 away from the substrate 10, and
  • the second inorganic layer 17 is provided on the side of the second dielectric layer 16 away from the substrate 10 , and the second wiring layer is provided on the side of the second inorganic layer 17 away from the substrate 10 .
  • the second wiring layer includes a plurality of second fan-out portions. 302.
  • the third dielectric layer 20 is provided on the side of the second wiring layer away from the substrate 10, wherein the first dielectric layer 15 is provided with a plurality of first openings 151, and the plurality of first openings 151 are connected with a plurality of first fans.
  • the fan-out parts 301 correspond to each other one by one, and the first opening 151 exposes the corresponding first fan-out part 301.
  • a second fan-out part 302 is connected to a first fan-out part 301 through a first opening 151 to form a fan-out part 301.
  • a second opening 161 is provided in the second dielectric layer 16 , the plurality of first openings 151 is located in the orthographic projection of the substrate 10 , and the second opening 161 is located in the orthographic projection of the substrate 10 .
  • the orthographic projection area is greater than the sum of the orthographic projection areas of the plurality of first openings 151 on the substrate 10 .
  • a third opening 201 is provided in the third dielectric layer 20 .
  • the plurality of first openings 151 is located in the orthographic projection of the substrate 10 .
  • the third opening 201 is located in the orthographic projection of the substrate 10 .
  • the area of the front projection is greater than the sum of the areas of the front projection of the plurality of first openings 151 on the substrate 10 , thereby reducing the step difference between the first fan-out part 301 and the second fan-out part 302 of the fan-out area.
  • the present disclosure also provides a display device, including the display backplane of the foregoing exemplary embodiment.
  • the display device can be any product or component with a display function such as a mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame or navigator.

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Abstract

一种显示背板、显示装置。显示背板包括位于基底(10)上的多个显示单元(300)，至少一个显示单元(300)包括像素区(310)和透光区(320)，像素区(310)被配置为进行图像显示，透光区(320)被配置为透过光线；像素区(310)包括沿基底(10)厚度方向异层设置的第一走线层和第二走线层；以及，位于第一走线层和第二走线层之间的第一介质层(15)和第二介质层(16)，其中，第一走线层的厚度与第二走线层的厚度之比大于5；第一介质层(15)的厚度与第二介质层(16)的厚度之和大于3μm，第一介质层(15)的厚度小于2μm。

Description

显示背板、显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示背板、显示装置。
背景技术
半导体发光二极管(Light Emitting Diode，简称LED)技术发展了近三十年，从最初的固态照明电源到显示领域的背光源再到LED显示屏，为其更广泛的应用提供了坚实的基础。随着芯片制作及封装技术的发展，次毫米发光二极管(Mini Light Emitting Diode，简称Mini LED)显示和微型发光二极管(Micro Light Emitting Diode，简称Micro LED)显示逐渐成为显示技术的一个热点，Micro LED显示主要应用在AR/VR等领域、Mini LED显示主要应用在TV及户外显示等领域。
目前，LED显示逐渐应用于透明显示中。透明显示是显示技术一个重要的个性化显示领域，是指显示装置本身具有一定程度的光穿透性，能够在透明状态下进行图像显示，观看者不仅可以看到显示装置中的影像，而且可以看到显示装置背后的景象，可用于户外显示或者开阔空间的公共场所显示。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示背板，包括位于基底上的多个显示单元，至少一个显示单元包括像素区和透光区，所述像素区被配置为进行图像显示，所述透光区被配置为透过光线；所述像素区包括沿基底厚度方向异层设置的第一走线层和第二走线层；以及，位于所述第一走线层和所述第二走线层之间的第一介质层和第二介质层，
其中，所述第一走线层的厚度与所述第二走线层的厚度之比大于5；
所述第一介质层的厚度与所述第二介质层的厚度之和大于3μm,所述第一介质层的厚度小于2μm；
所述第一走线层包括多根第一走线，所述第一走线包括沿第一方向延伸的第一部分；
所述第二走线层包括多根第二走线，所述第二走线包括沿第二方向延伸的第二部分，所述第一方向与所述第二方向交叉。
在示例性实施方式中，至少一根第一走线包括第一扫描线、数据信号线、接地线、第一驱动线和第二驱动线中的至少一种。
在示例性实施方式中，至少一根第一走线的第一部分包括沿第一方向相对的第一边沿和第二边沿，所述像素区还包括至少一个第一发光器件、至少一个第二发光器件以及至少一个第三发光器件，至少一个第一发光器件、至少一个第二发光器件和至少一个第三发光器件在基底的正投影均位于所述第一边沿和所述第二边沿限定的区域内。
在示例性实施方式中，所述第一发光器件、所述第二发光器件和所述第三发光器件均为次毫米发光二极管和微型发光二极管中的一种。
在示例性实施方式中，所述像素区还包括像素驱动芯片，所述像素驱动芯片被配置为向第一发光器件、第二发光器件以及第三发光器件中至少一者提供驱动信号。
在示例性实施方式中，所述像素区还包括第三介质层，所述第三介质层中设置有第一凹槽和第二凹槽，所述第一凹槽被配置为印刷与第一发光器件、第二发光器件以及第三发光器件中至少一者连接的锡膏，所述第二凹槽被配置为印刷与所述像素驱动芯片连接的锡膏。
在示例性实施方式中，至少一根第一走线的第一部分包括沿所述第一方向相对的第一边沿和第二边沿，至少一根第一走线的第一部分在基底的正投影位于所述第一介质层在基底的正投影内，所述第一介质层或所述第二介质层中的一者，具有沿所述第一方向相对的第三边沿和第四边沿，所述第一边沿和所述第三边沿位于所述第一走线的同一侧，所述第二边沿和所述第四边沿位于所述第一走线的同一侧，所述第一边沿到所述第三边沿的第一垂直距 离大于等于20μm，所述第二边沿到所述第四边沿的第二垂直距离大于等于20μm。
在示例性实施方式中，所述第一介质层包括沿所述第二方向延伸的第一条状区域，所述第二介质层包括沿所述第二方向延伸的第二条状区域，所述第一条状区域在基底的正投影位于所述第二条状区域在基底的正投影内，且所述第一条状区域正投影面积小于所述第二条状区域正投影面积；
或者，所述第一条状区域在基底的正投影与所述第二条状区域在基底的正投影重合；
或者，所述第二条状区域在基底的正投影位于所述第一条状区域在基底的正投影内，且所述第二条状区域正投影面积小于所述第一条状区域正投影面积。
在示例性实施方式中，至少一根第二走线的第二部分包括沿所述第二方向相对的第五边沿和第六边沿，至少一根第二走线的第二部分在基底的正投影位于所述第一介质层在基底的正投影内，所述第一介质层或所述第二介质层中的一者，具有沿所述第二方向相对的第七边沿和第八边沿，所述第五边沿和所述第七边沿位于所述第二走线第二方向的同一侧，所述第六边沿和所述第八边沿位于所述第二走线第二方向的同一侧，所述第五边沿到所述第七边沿的第三垂直距离大于等于20μm，所述第六边沿到所述第八边沿的第四垂直距离大于等于20μm。
在示例性实施方式中，所述第一介质层包括沿第一方向延伸的第三条状区域，所述第二介质层包括沿第一方向X延伸的第四条状区域，所述第三条状区域在基底的正投影位于所述第四条状区域在基底的正投影内，且所述第三条状区域正投影面积小于所述第四条状区域正投影面积；
或者，所述第三条状区域正投影与所述第四条状区域正投影重合；
或者，所述第四条状区域在基底的正投影位于所述第三条状区域在基底的正投影内，且所述第四条状区域正投影面积小于所述第三条状区域正投影面积。
在示例性实施方式中，所述像素区还包括第一遮光层和第二遮光层，所 述第一遮光层位于所述第一走线层靠近基底的一侧，所述第二遮光层位于所述第二走线层远离基底的一侧；所述第一遮光层包括第一遮光图案，所述第一走线在基底的正投影与所述第一遮光图案在基底的正投影至少部分交叠；所述第二遮光层包括第二遮光图案，所述第二走线在基底的正投影与所述第二遮光图案在基底的正投影至少部分交叠。
在示例性实施方式中，所述第一走线在基底的正投影位于所述第一遮光图案在基底的正投影内，所述第二走线在基底的正投影位于所述第二遮光图案在基底的正投影内。
在示例性实施方式中，所述第一遮光图案在基底的正投影和所述第二遮光图案在基底的正投影重合。
在示例性实施方式中，所述第一遮光层的材料为黑矩阵和氧化钼中的一种，所述第二遮光层的材料为黑矩阵和氧化钼中的一种。
在示例性实施方式中，所述第一遮光层的材料为黑矩阵，所述第一遮光层与所述第一走线层之间设置保护层。
在示例性实施方式中，所述第一走线层与所述第一遮光层之间还设置有缓冲层，所述第一走线层材料为铜，所述第一走线层包括种子层，所述种子层与所述缓冲层直接接触。
在示例性实施方式中，所述第一遮光层的材料为氧化钼，所述第一走线层材料为铜，所述第一走线层与所述第一遮光层直接接触。
在示例性实施方式中，所述第一介质层和所述第二介质层均为有机材料。
在示例性实施方式中，所述像素区还包括位于所述第一走线层与所述第一介质层之间的第一无机层、位于所述第二介质层远离所述基底一侧的第二无机层和第三无机层。
在示例性实施方式中，所述像素区还包括至少一个排气孔，至少一个排气孔设置在所述第二无机层和所述第三无机层中的至少一者，且至少一个排气孔在基底的正投影均与所述第一走线的第一部分在基底的正投影和所述第二走线的第二部分在基底的正投影不交叠。
在示例性实施方式中，所述像素区包括多个排气孔，多个排气孔分设于所述第一走线的第一部分沿第一方向的两侧，和/或，多个排气孔分设于所述第二走线的第二部分沿第二方向的两侧。
在示例性实施方式中，还包括绑定区，所述绑定区位于所述显示区的至少一侧，所述绑定区在基底的正投影与所述第二介质层在基底的正投影不交叠。
在示例性实施方式中，还包括扇出区，所述扇出区位于所述显示区的至少一侧，所述扇出区包括基底，设置在所述基底上的第一扇出部分，设置在所述第一扇出部分远离基底一侧的第一介质层，设置在所述第一介质层远离基底一侧的第二介质层，设置在所述第二介质层远离基底一侧的第二扇出部分，所述第一介质层中设置有第一开口，所述第二扇出部分通过所述第一开口与所述第一扇出部分连接，形成扇出线，所述第二介质层中设置有第二开口，所述第一开口在基底的正投影位于所述第二开口在基底的正投影中，且所述第二开口在基底的正投影的面积大于所述第一开口在基底的正投影的面积。
在示例性实施方式中，所述扇出区还包括设置在所述第二扇出部分远离基底一侧的第三介质层，所述第三介质层中设置有第三开口，所述第一开口在基底的正投影位于所述第三开口在基底的正投影中，且所述第三开口在基底的正投影的面积大于所述第一开口在基底的正投影的面积。
另一方面，本公开还提供了一种显示装置，包括前述的显示背板。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本公开示例性实施例一种显示背板的平面结构示意图；
图2为本公开示例性实施例显示背板中一个显示单元的平面结构示意图；
图3为本公开示例性实施例一种显示背板的剖面结构示意图一；
图4为本公开示例性实施例一种显示背板的剖面结构示意图二；
图5为本公开示例性实施例显示背板中第一遮光图案的剖视图一；
图6为本公开示例性实施例显示背板中第一遮光图案的剖视图二；
图7为本公开示例性实施例一个显示单元中第一走线的平面结构示意图；
图8为本公开示例性实施例一个显示单元中第一介质层和第二介质层的剖视图一；
图9为本公开示例性实施例一个显示单元中第一介质层和第二介质层的剖视图二；
图10为本公开示例性实施例一个显示单元中第一介质层和第二介质层的剖视图三；
图11为相关技术显示背板中第一走线和第二走线的平面结构示意图；
图12为本公开示例性实施例一个显示单元中第二走线的平面结构示意图；
图13为本公开示例性实施例一个显示单元中第一走线和第二走线的平面结构示意图；
图14为本公开示例性实施例一个显示单元中排气孔的平面结构示意图；
图15为本公开示例性实施例显示背板中扇出区的剖视图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接 在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
目前，虽然显示市场以液晶显示(Liquid Crystal Display，简称LCD)和有机发光二极管显示(Organic Light Emitting Diode，简称OLED)两种技术为主，但受基底尺寸、制备设备和工艺等限制，LCD和OLED均难以实现大尺寸显示。相比之下，Micro LED/Mini LED显示可以通过拼接方式实现大尺寸显示，能够突破尺寸限制。通常，大尺寸LED显示面板是利用横梁或竖梁固定多个箱体，LED显示背板设置在箱体内，多个箱体将多个LED显示背板拼接形成大尺寸LED显示面板。由于LED具有自发光、广视角、快速响应、结构简单、体积小、轻薄、节能、高效、长寿、光线清晰等优点，因而大尺寸LED显示面板能够实现高分辨率(Pixels Per Inch，简称PPI)。
LED显示背板是用微缩制程技术进行微缩化、阵列化、薄膜化，通常，Micro LED的典型尺寸(例如长度)可以小于50μm，例如10μm至50μm。Mini LED的典型尺寸(例如长度)可以约为50μm至150μm，例如80μm至120μm。通过将LED批量转移到显示背板上，并配合驱动设计，实现每个LED可寻址、可单独驱动点亮。
图1为本公开示例性实施例一种显示背板的平面结构示意图。如图1所示，在示例性实施方式中，显示背板可以包括显示区域100和绑定区域200， 显示区域100被配置为进行透明显示，绑定区域200可以位于显示区域100的至少一侧，被配置为绑定柔性电路板(Flexible Printed Circuit，简称FPC)。
在示例性实施方式中，显示区域100可以包括基底以及设置在基底上的多个规则排布的显示单元300，至少一个显示单元300可以包括像素区310和透光区320，像素区310包括设置在基底上的驱动电路和至少一个发光二极管，发光二极管与驱动电路连接，像素区310被配置为进行图像显示，透光区320位于显示单元300中像素区310的以外区域，透光区320被配置为透过光线，使得显示单元300能够实现透明状态下的图像显示，即透明显示。
在示例性实施方式中，显示单元300中像素区310的面积可以大于透光区320的面积，或者，像素区310的面积可以小于透光区320的面积，或者，像素区310的面积可以等于透光区320的面积，本公开在此不做限定。通常，透光区320的面积越大，显示单元300的透过率越大，显示背板的透过率越大，透过显示背板看到的图像越清晰。
在示例性实施方式中，绑定区域200可以位于显示区域100第二方向Y的一侧，绑定区域200可以至少包括多个绑定子区201，多个绑定子区201可以沿着第一方向X依次设置，每个绑定子区201可以设置至少一个绑定端子，绑定端子通过引线与显示单元中的驱动电路连接，第一方向X和第二方向Y交叉，示例的，第一方向X和第二方向Y垂直。在示例性实施方式中，绑定端子被配置为与柔性电路板绑定连接，通过柔性电路板与外部电路连接。
图2为本公开示例性实施例显示背板中一个显示单元的平面结构示意图。如图2所示，在示例性实施方式中，一个显示单元的像素区可以包括设置在基底上的驱动电路和发光二极管组4，驱动电路可以包括沿基底厚度方向异层设置的第一走线层、第二走线层以及像素驱动芯片3，发光二极管组4可以包括至少一个第一发光二极管、至少一个第二发光二极管以及至少一个第三发光二极管，其中，第一发光二极管可以为出射红光的红光LED，第二发光二极管可以为出射蓝光的蓝光LED，第三发光二极管可以为出射绿光的绿光LED。
在一些实施例中，一个显示单元的像素区可以包括依次层叠设置在基底 上的驱动电路、发光二极管组以及色转换层，发光二极管组包括多个蓝光LED，多个蓝光LED发出的蓝光能够激发色转换层，使色转换层出射预定颜射的光线，例如，红光和绿光。其中，色转换层的材料可以为量子点或荧光粉。
在示例性实施方式中，第一走线层可以包括多根第一走线1，第一走线1可以包括沿第二方向Y延伸的第一部分，第一走线1可以包括第一扫描线VCC1、数据信号线DATA、接地线GND、第一驱动线VGB和第二驱动线VR。第二走线层可以包括多根第二走线2，第二走线2包括沿第一方向X延伸的第二部分，第二走线2可以包括第二扫描线VCC2。
在示例性实施方式中，第二扫描线VCC2的第二部分可以位于显示单元内第二方向Y的一侧。第一驱动线VGB的第一部分可以位于显示单元内第一方向X的反方向的一侧，第一扫描线VCC1的第一部分可以位于显示单元内第一方向X的一侧。在示例性实施方式中，可以认为两条第二扫描线VCC2的第二部分限定了一个显示单元行，第一驱动线VGB的第一部分和第一扫描线VCC1的第一部分限定了一个显示单元列，两条第二扫描线VCC2的第二部分与第一驱动线VGB的第一部分和第一扫描线VCC1的第一部分相互交叉，限定了一个显示单元。
在示例性实施方式中，第一扫描线VCC1可以通过过孔与第二扫描线VCC2连接。第二扫描线VCC2被配置为提供扫描信号，由于绑定像素驱动芯片3的芯片端子位于显示单元第二方向Y上的侧边，因而第一扫描线VCC1被配置为将第一方向X延伸的第二扫描线VCC2转到第二方向Y，便于与芯片端子连接。
在示例性实施方式中，第一驱动线VGB可以分别与蓝光LED和绿光LED连接，被配置为分别向蓝光LED和绿光LED提供驱动信号。第二驱动线VR的第一部分可以位于第一驱动线VGB的第一部分与接地线GND的第一部分之间，第二驱动线VR可以与红光LED连接，被配置为向红光LED提供驱动信号。由于蓝光LED和绿光LED的发光特性基本相同，而红光LED与蓝光/绿光LED的发光特性不同，因而蓝光LED和绿光LED可以使用同一条第一驱动线VGB驱动，而红光LED需要单独使用一条第二驱动线VR 驱动。在示例性实施方式中，蓝光LED和绿光LED可以分别连接一条驱动线，本公开在此不做限定。
在示例性实施方式中，数据信号线DATA的第一部分和接地线GND的第一部分可以位于第一驱动线VGB的第一部分和第一扫描线VCC1的第一部分之间，像素驱动芯片3可以位于数据信号线DATA的第一部分和接地线GND的第一部分之间，数据信号线DATA被配置为向像素驱动芯片3提供数据信号，接地线GND被配置为提供接地信号，像素驱动芯片3被配置为在第一扫描线VCC1和第二扫描线VCC2的控制下，根据数据信号线DATA提供的数据信号，向第一发光器件、第二发光器件以及第三发光器件提供驱动信号，控制第一发光器件、第二发光器件以及第三发光器件点亮。
在示例性实施方式中，至少一个第一发光二极管、至少一个第二发光二极管以及至少一个第三发光二极管可以沿着第二方向Y依次设置，第一走线1的第一部分包括沿第一方向X相对的第一边沿和第二边沿，至少一个第一发光二极管、至少一个第二发光二极管以及至少一个第三发光二极管在基底的正投影均位于第一边沿和第二边沿限定的区域内，避免发光二极管占用透光区320的空间，提供显示单元内透光区320的面积，提升发光二极管的发光质量。
在示例性实施方式中，接地线GND、第一扫描线VCC1、数据信号线DATA、第一驱动线和VGB第二驱动线VR中至少一者的第一部分包括沿第一方向X相对的第一边沿和第二边沿，至少一个第一发光二极管、至少一个第二发光二极管以及至少一个第三发光二极管在基底的正投影位于第一边沿和第二边沿限定的区域内。例如，接地线GND的第一部分包括沿第一方向X相对的第一边沿和第二边沿，至少一个第一发光二极管、至少一个第二发光二极管以及至少一个第三发光二极管在基底的正投影位于第一边沿和第二边沿限定的区域内。
在示例性实施方式中，至少一个第一发光二极管、至少一个第二发光二极管以及至少一个第三发光二极管可以为次毫米发光二极管(Mini Light Emitting Diode，简称Mini LED)和微型发光二极管(Micro Light Emitting Diode，简称Micro LED)中的一种。
在示例性实施方式中，发光二极管LED包括两个引脚(正极引脚和负极引脚)，相应地，显示单元内设置有与LED引脚一一对应的连接端子。在示例性实施方式中，显示单元内的连接端子可以包括：配置为连接红光LED正极引脚的红光正极连接端子R+、配置为连接红光LED负极引脚的红光负极连接端子R-、配置为连接蓝光LED正极引脚的蓝光正极连接端子B+、配置为连接蓝光LED负极引脚的蓝光负极连接端子B-、配置为连接绿光LED正极引脚的绿光正极连接端子G+和配置为连接绿光LED负极引脚的绿光负极连接端子G-。在示例性实施方式中，红光正极连接端子R+可以与第二驱动线VR连接，蓝光正极连接端子B+可以与第一驱动线VGB连接，绿光正极连接端子G+可以与第一驱动线VGB连接。
在示例性实施方式中，像素驱动芯片3可以包括6个芯片引脚，相应地，显示单元内设置有与芯片引脚一一对应的芯片端子，分别为：第一芯片端子、第二芯片端子、第三芯片端子、第四芯片端子、第五芯片端子和第六芯片端子。在示例性实施方式中，第一芯片端子可以与红光负极连接端子R-连接，第二芯片端子可以与蓝光负极连接端子B-连接，第三芯片端子可以与绿光负极连接端子G-连接，第四芯片端子可以与第一扫描线VCC1连接，第五芯片端子可以与数据信号线DATA连接，第六芯片端子可以与接地线GND连接。
在示例性实施方式中，第一扫描线VCC1、数据信号线DATA、接地线GND、第一驱动第二驱动线VR可以同层设置于第一走线层，且通过同一次工艺同时形成，多个连接发光二极管的连接端子、多个连接像素驱动芯片3的芯片端子和第二扫描线VCC2可以同层设置于第二走线层，且通过同一次工艺同时形成。前述的连接可以是直接连接，或者是通过过孔连接。
在示例性实施方式中，绑定区域的多个绑定端子可以设置在第二走线层，与显示单元的多个连接端子和多个芯片端子同层设置，且通过同一次工艺同时形成。
在示例性实施方式中，显示单元中发光二极管组中发光二极管的数量可以为多个，如4个、5个、6个、8个等，多个发光二极管的排布方式可以根据实际情况来设置，本公开在此不做限定。
在示例性实施方式中，第一驱动线VGB的第一宽度可以约为60μm至80μm，例如可以约为70μm。第二驱动线VR的第一宽度可以约为20μm至40μm，例如可以约为30μm。接地线GND的第一宽度可以约为180μm至200μm，例如可以约为190μm。数据信号线DATA的第一宽度可以约为10μm至30μm，例如可以约为20μm。第一扫描线VCC1的第一宽度可以约为20μm至40μm，例如可以约为30μm。其中，第一宽度是第一方向X的尺寸。
在示例性实施方式中，第二扫描线VCC2的第二宽度可以约为60μm至80μm，例如可以约为70μm。其中，第二宽度是第二方向Y的尺寸。
在示例性实施方式中，第一驱动线VGB与第二驱动线VR之间的第一间距可以约为35μm至55μm，例如可以约为45μm。数据信号线DATA与第一扫描线VCC1之间的第一间距可以约为35μm至55μm，例如可以约为45μm。第二驱动线VR与接地线GND之间的第一间距可以约为600μm至800μm，例如可以约为690μm。接地线GND与数据信号线DATA之间的第一间距可以约为600μm至800μm，例如可以约为690μm。发光二极管LED与像素驱动芯片3之间的第一间距可以约为100μm至140μm，例如可以约为120μm。其中，第一间距是第一方向X的尺寸。
在示例性实施方式中，沿着第二方向Y依次设置的三个发光二极管LED中，相邻发光二极管LED之间的第二间距可以约为80μm至120μm，例如可以约为100μm。其中，第二间距是第二方向Y的尺寸。
在示例性实施方式中，显示单元还可以包括第一遮光层和第二遮光层，第一遮光层位于第一走线层靠近基底一侧，第二遮光层位于第二走线层远离基底一侧。第一遮光层和第二遮光层在基底的正投影均与驱动电路和发光二极管组在基底的正投影至少部分交叠，以减弱多条信号线的可视度，提升显示背板的显示质量。
在示例性实施方式中，显示单元内第一遮光层和第二遮光层(驱动电路和发光二极管组所在区域)形成组成像素区，为不透光区域，第一遮光层和第二遮光层以外区域为透光区320，图2中虚线框所示区域为透光区320，虚线框以外区域为第一遮光层和第二遮光层所在区域。
图3为本公开示例性实施例一种显示背板的剖面结构示意图一，图3示意了显示区域中像素区310和透光区320以及绑定区域200中绑定子区201的剖面结构。如图3所示，在示例性实施方式中，显示背板的像素区310可以包括设置在基底10上的像素结构层，显示背板的透光区320可以包括开槽，开槽的槽底为基底10的表面，显示背板的绑定子区201可以包括设置在基底10上的绑定结构层。
在示例性实施方式中，像素区310的像素结构层可以包括：设置在基底10上的第一遮光层，第一遮光层包括第三遮光图案11，设置在第一遮光层远离基底一侧的保护层12，设置在保护层12远离基底一侧的缓冲层13，设置在缓冲层13远离基底一侧的第一走线层，第一走线层至少包括第一电极31和第二电极32，设置在第一走线层远离基底一侧的第一无机层14，设置在第一无机层14远离基底一侧的第一介质层15，设置在第一介质层15远离基底一侧的第二介质层16，设置在第二介质层16远离基底一侧的第二无机层17，设置在第二无机层17远离基底一侧的第二走线层，第二走线层至少包括正极连接端子33和负极连接端子34，正极连接端子33通过过孔与第一电极31连接，负极连接端子34通过过孔与第二电极32连接，设置在第二走线层远离基底一侧的第三无机层18，设置在第三无机层18远离基底一侧的第二遮光层，第二遮光层包括第四遮光图案19，设置在第二遮光层远离基底一侧的第三介质层20，设置在第三介质层20远离基底一侧的发光二极管50，发光二极管50分别与正极连接端子33和负极连接端子34连接。
在示例性实施方式中，第三遮光图案11在基底10的正投影分别与第一电极31和第二电极32在基底10的正投影交叠，第四遮光图案19在基底10的正投影分别与正极连接端子33和负极连接端子34在基底10的正投影交叠。
在示例性实施方式中，第三介质层20中设置有第一凹槽，第一凹槽将正极连接端子33和负极连接端子34暴露，第一凹槽被配置为印刷与第一发光器件、第二发光器件以及第三发光器件中至少一者连接的锡膏，发光二极管50通过第一凹槽分别与正极连接端子33和负极连接端子34连接。
在示例性实施方式中，像素驱动芯片3可以包括多个芯片引脚，相应地，显示单元内设置有与芯片引脚一一对应的芯片端子，芯片端子可以设置在第 二走线层。第三介质层20中设置有第二凹槽，第二凹槽将芯片端子暴露，第二凹槽配置为印刷与像素驱动芯片连接的锡膏，像素驱动芯片3通过第二凹槽与芯片端子连接。
在示例性实施方式中，像素区310的像素结构层在透光区320被去除，提高透光区320的透光率，提升显示背板的显示效果。
在示例性实施方式中，绑定子区201的绑定结构层可以包括：设置在基底10上的缓冲层13，设置在缓冲层13远离基底一侧的第一走线层，第一走线层至少包括第一绑定电极43和第二绑定电极44，设置在第一走线层远离基底一侧的第一无机层14，设置在第一无机层14远离基底一侧的第一介质层15，设置在第一介质层15远离基底一侧的第二无机层17，设置在第二无机层17远离基底一侧的第二走线层，第二走线层至少包括第一绑定端子41和第二绑定端子42，第一绑定端子41通过过孔与第一绑定电极43连接，第二绑定端子42通过过孔与第二绑定电极44连接，设置在第二走线层远离基底一侧的第三介质层20，第三介质层20上设置有暴露出第一绑定端子41和第二绑定端子42的第二凹槽。
在示例性实施方式中，在像素区310，像素结构层中的第一介质层15、第二介质层16和第三介质层20可以采用有机材料，缓冲层13、第一无机层14、第二无机层17和第三无机层18可以采用无机材料，第一走线层和第二走线层可以采用导电金属材质，比如铜材质。在绑定子区201，绑定结构层中的第一介质层15可以采用有机材料，缓冲层13、第一无机层14、第二无机层17和第三无机层18可以采用无机材料，第一走线层和第二走线层可以采用导电金属材质，比如铜材质。
在示例性实施方式中，像素区310采用两层介质层，即第一介质层15和第二介质层16。绑定子区201采用一层介质层，即第一介质层15，第二介质层16在基底10的正投影与绑定区在基底10的正投影不交叠，绑定子区201的绑定结构层中没有设置第二介质层。绑定子区201中介质层的厚度小于像素区310介质层的厚度。本公开通过减小绑定子区201介质层的厚度，可以减小绑定子区201的段差，避免因较大段差导致的绑定不良，可以提高绑定工艺质量，提高显示背板的良品率。
在示例性实施方式中，缓冲层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层结构，或者可以是多层复合结构。例如，缓冲层可以采用氮化硅SiN。
在示例性实施方式中，第一走线层可以采用金属材料，如铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)、铬(Cr)和钨(W)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者可以是多层复合结构，如MoNb/Cu/MoNb等。例如，第一走线层可以包括叠设的第一子层、第二子层和第三子层，第一子层设置在缓冲层13远离基底的一侧，第二子层设置在第一子层远离基底的一侧，第三子层设置在第二子层远离基底的一侧。第一子层可以采用钼铌合金MoNb，用于提高粘附力，第二子层可以采用铜Cu，用于降低电阻，第三子层可以采用MoNb，用于防氧化，形成叠层结构的MoNb/Cu/MoNb。
在示例性实施方式中，第一走线层的整体厚度可以约为1.5μm至7μm。根据电阻定律，走线的横截面积越大，电阻越小，因而较厚的第一走线层可以减小电阻，提高电学性能。
在示例性实施方式中，基底可以采用硬质基底或柔性基底，硬质基底可以是玻璃等，柔性基底可以是聚酰亚胺(PI)等。
在示例性实施方式中，第一无机层14、第二无机层17和第三无机层18均可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层结构，或者可以是多层复合结构。例如，第一无机层14可以采用氮化硅Si 3N 4。
在示例性实施方式中，第一介质层12、第二介质层16和第三介质层20可以采用有机材料，如树脂等。
图4为本公开示例性实施例一种显示背板的剖面结构示意图二，图4示意了显示区域中第一走线的剖面结构，图4可以为图2中A-A’方向的剖视图。在示例性实施方式中，如图4所示，显示背板的像素区310可以包括设置在基底10上的走线结构层，走线结构层可以包括：设置在基底10上的第一遮光层，第一遮光层包括第一遮光图案21，设置在第一遮光层远离基底一侧的 保护层12，设置在保护层12远离基底一侧的缓冲层13，设置在缓冲层13远离基底一侧的第一走线层，第一走线层至少包括多根第一走线1，设置在第一走线层远离基底一侧的第一无机层14，设置在第一无机层14远离基底一侧的第一介质层15，设置在第一介质层15远离基底一侧的第二介质层16，设置在第二介质层16远离基底一侧的第二无机层17，设置在第二无机层17远离基底一侧的第二走线层(图中未示出)，第二走线层包括多根第二走线(图中未示出)，设置在第二走线层远离基底一侧的第三无机层18，设置在第三无机层18远离基底一侧的第二遮光层，第二遮光层包括第二遮光图案22，设置在第二遮光层远离基底一侧的第三介质层20。
在示例性实施方式中，第一走线层中第一走线1的厚度与第二走线层中第二走线的厚度之比大于5；例如，第一走线层中第一走线1的厚度约为5μm至8μm；第二走线层中第二走线的厚度约为0.5μm至1μm。
在示例性实施方式中，第一介质层15的厚度与第二介质层16的厚度之和大于3μm，以减小第一走线层中第一走线1与第二走线层中第二走线之间的电容负载；由于绑定区上仅覆盖第一介质层15，没有覆盖第二介质层16，为了保证绑定区的绑定效果，需要减小第一介质层15的厚度，例如，第一介质层15的厚度小于2μm，以避免发生由于第一介质层15过厚导致绑定区出现绑定不良的情况。
在示例性实施方式中，第一走线1在基底10上的正投影与第一遮光图案21在基底10上的正投影至少部分交叠。第一遮光图案21包括沿第一方向X延伸的第一遮光区域和沿第二方向Y延伸的第二遮光区域，至少一根第一走线1在基底10上的正投影与第二遮光区域交叠；至少一根第二走线2在基底10上的正投影与第一遮光区域交叠，第一遮光图案21的第二遮光区域位于第一走线层靠近基底10的一侧，被配置为遮挡透过基底射入第一走线1的环境光，减弱第一走线1的可视度，提升显示背板的显示效果；第一遮光图案21的第一遮光区域位于第一走线层靠近基底10的一侧，被配置为遮挡透过基底射入第二走线2的环境光，减弱第二走线2的可视度，提升显示背板的显示效果。
在示例性实施方式中，第二走线在基底10上的正投影与第二遮光图案 22在基底10上的正投影至少部分交叠。第二遮光图案22包括沿第一方向X延伸的第三遮光区域和沿第二方向Y延伸的第四遮光区域，至少一根第一走线1在基底10上的正投影与第四遮光区域交叠；至少一根第二走线2在基底10上的正投影与第三遮光区域交叠，第二遮光图案22的第四遮光区域位于第二走线层远离基底10的一侧，被配置为遮挡射入第一走线1的环境光，减弱第一走线1的可视度，提升显示背板的显示效果；第二遮光图案22的第三遮光区域位于第二走线层远离基底10的一侧，被配置为遮挡射入第二走线2的环境光，减弱第二走线2的可视度，提升显示背板的显示效果。
在示例性实施方式中，第一走线1在基底10上的正投影位于第一遮光图案21的第二遮光区域在基底10上的正投影内，以及位于第二遮光图案22的第四遮光区域在基底10上的正投影内，使第一走线1完全被第一遮光图案21和第二遮光图案22遮挡，实现第一走线1的双面遮挡。
在示例性实施方式中，第二走线2在基底10上的正投影位于第一遮光图案21的第一遮光区域在基底10上的正投影内，以及位于第二遮光图案22的第三遮光区域在基底10上的正投影内，使第二走线2完全被第一遮光图案21和第二遮光图案22遮挡，实现第二走线2的双面遮挡。
在示例性实施方式中，第一遮光图案21在基底10上的正投影和第二遮光图案22在基底10上的正投影重合。第一遮光图案21的第一遮光区域在基底10上的正投影与第二遮光图案22的第三遮光区域在基底10上的正投影重合。第一遮光图案21的第二遮光区域在基底10上的正投影与第二遮光图案22的第四遮光区域在基底10上的正投影重合。使第一走线1和第二走线2在靠近基底10一侧均被第一遮光图案21遮挡光线，第一走线1和第二走线在远离基底10一侧均被第二遮光图案22遮挡光线，实现第一走线和第二走线的双面遮挡。
第一走线和第二走线在环境光下会有较强的反光现象，影响显示背板的显示效果。表1为采用单面遮光层的显示背板的显示效果。表2为本公开实施例采用双面遮光层的显示背板的显示效果。表3为本公开实施例采用双面遮光层的显示背板的反射率和色域的显示效果。
表1 为采用单面遮光层的显示背板的显示效果
Figure PCTCN2022090354-appb-000001
表2 为采用双面遮光层的显示背板的显示效果
Figure PCTCN2022090354-appb-000002
表3 为采用双面遮光层的显示背板的反射率和色域的显示效果
Figure PCTCN2022090354-appb-000003
由表1、表2和表3可知，采用单面遮光层的显示背板的反射率可以达到30％；采用双面遮光层的显示背板的反射率可以降低到23％。且采用双面遮光层的显示背板的反射率和色域均有提升。
在示例性实施方式中，第一遮光层和第二遮光层的材料均可以采用黑矩阵和氧化钼中的一种。
在示例性实施方式中，第一遮光层和第二遮光层的材料也可以采用其他遮光材料，优选可阻隔可见光的遮光材料。
在示例性实施方式中，第一遮光层和第二遮光层的至少一个可以采用非晶硅。
图5为本公开示例性实施例显示背板中第一遮光图案的剖视图一。在示例性实施方式中，如图5所示，第一遮光层的第一遮光图案21可以采用黑矩阵，第一遮光层的第一遮光图案21与第一走线层的第一走线1之间设置有保护层12以及缓冲层13。缓冲层13位于保护层12远离基底10一侧。第一走线层的第一走线1可以采用铜材质，第一走线层的第一走线1包括种子层，第一走线层的第一走线1的种子层可以与缓冲层13直接接触。缓冲层13和保护层12能够防止种子层脱落，保证黑矩阵的稳固。其中，保护层12可以采用有机材质，例如，树脂。
图6为本公开示例性实施例显示背板中第一遮光图案的剖视图二。在示例性实施方式中，如图6所示，第一遮光层的第一遮光图案21可以采用氧化钼。第一遮光图案21与第一走线层的第一走线1之间不设置保护层以及缓冲层，第一走线1可以采用铜材质，第一遮光图案可以与第一走线1直接接触，简化工艺，降低制作成本。
在示例性实施方式中，如图4所示，由于第二遮光图案22与透光区320的基底10之间存在段差，段差一般大于10μm，第二遮光图案22在制备时，容易在透光区320的段差处发生大面积残留，降低透光区320的透光率，影响显示背板的透光率。本公开实施例显示背板通过增加第二遮光图案22的显影时间，减少第二遮光图案22在透光区320段差处的残留面积，提高显示背板的透光率。
图7为本公开示例性实施例一个显示单元中第一走线的平面结构示意图。在示例性实施方式中，如图7所示，一个显示单元中至少一根第一走线1的第一部分包括沿第一方向X相对的第一边沿61和第二边沿62，至少一根第一走线1的第一部分在基底的正投影位于第一介质层15在基底的正投影内。第一介质层15在基底的正投影位于第二介质层16在基底的正投影内。第二 介质层16具有沿第一方向X相对的第三边沿63和第四边沿64，第一边沿61和第三边沿63位于第一走线1第一方向的同一侧，第二边沿62和第四边沿64位于第一走线1第一方向X的同一侧，第一边沿61到第三边沿63的第一垂直距离L1大于等于20μm。比如，第一垂直距离L1约为20μm至30μm。第二边沿62到第四边沿64的第二垂直距离L2大于等于20μm。比如，第二垂直距离L2约为20μm至30μm。其中，第一垂直距离L1和第二垂直距离L2分别为第一方向X的垂直距离。
在一些实施例中，第一介质层具有沿第一方向X相对的第三边沿和第四边沿，第一边沿和第三边沿位于第一走线第一方向X的同一侧，第二边沿和第四边沿位于第一走线第一方向X的同一侧，第一边沿到第三边沿的第一垂直距离L1大于等于20μm。比如，第一边沿到第三边沿的第一垂直距离L1约为20μm至30μm。第二边沿到第四边沿的第二垂直距离L2大于等于20μm。比如，第二垂直距离L2约为20μm至30μm。其中，第一垂直距离L1和第二垂直距离L2分别为第一方向X的垂直距离。
本公开实施例显示背板通过将第一边沿61到第三边沿63之间形成第一垂直距离L1，以及将第二边沿62到第四边沿64之间形成第二垂直距离L2，减小第二遮光图案22与透光区320的基底10之间的段差，从而减少第二遮光图案22在透光区320段差处的残留面积，提高显示背板的透光率。
图8为本公开示例性实施例一个显示单元中第一介质层和第二介质层的剖视图一。在示例性实施方式中，如图8所示，第一介质层15包括沿第二方向Y延伸的第一条状区域，第二介质层16包括沿第二方向Y延伸的第二条状区域，第一条状区域在基底的正投影位于第二条状区域在基底的正投影内，且第一条状区域正投影面积小于第二条状区域正投影面积。第二条状区域包括第一侧壁和第二侧壁，第一侧壁包括第一倾斜表面71、第二倾斜表面72以及第一凸台面73，第一倾斜表面71和第二倾斜表面72通过第一凸台面73连接。第二侧壁包括第三倾斜表面74、第四倾斜表面75以及第二凸台面76，第三倾斜表面74和第四倾斜表面75通过第二凸台面76连接。
图9为本公开示例性实施例一个显示单元中第一介质层和第二介质层的剖视图二。在示例性实施方式中，如图9所示，第一条状区域在基底的正投 影位于第二条状区域在基底的正投影内，且第一条状区域正投影面积小于第二条状区域正投影面积。第二条状区域包括第一侧壁77和第二侧壁78，第一侧壁77和第二侧壁78均具有倾斜设置的表面。
图10为本公开示例性实施例一个显示单元中第一介质层和第二介质层的剖视图三。在示例性实施方式中，如图10所示，第二条状区域在基底的正投影位于第一条状区域在基底的正投影内，且第二条状区域正投影面积小于第一条状区域正投影面积。第二条状区域包括第一侧壁77和第二侧壁78，第一条状区域第三侧壁79和第四侧壁80，第一侧壁77和第三侧壁79位于第一走线1的同一侧，第二侧壁78和第四侧壁80位于第一走线1的同一侧，第一侧壁77的表面和第三侧壁79的表面构成一倾斜表面，第二侧壁78的表面和第四侧壁80的表面构成一倾斜表面。
在一些实施例中，第二条状区域正投影也可以与第一条状区域正投影重合，本公开在此不再赘述。
图11为相关技术显示背板中第一走线和第二走线的平面结构示意图。在示例性实施方式中，如图11所示，相关技术显示背板中第一走线1包括沿第二方向Y延伸的第一部分，第二走线2包括沿第一方向X延伸的第二部分。由于第二走线2的第二部分与透光区320的基底10之间存在较大段差，第二走线2在制备时，第二走线2容易在透光区320的段差处发生沿着第二方向Y延伸残留a，残留a容易造成相邻的第二走线2短路。
图12为本公开示例性实施例一个显示单元中第二走线的平面结构示意图。在示例性实施方式中，如图12所示，一个显示单元中至少一根第二走线2的第二部分包括沿第二方向Y相对的第五边沿65和第六边沿66，至少一根第二走线2的第二部分在基底的正投影位于第一介质层15在基底的正投影内。第一介质层15在基底的正投影位于第二介质层16在基底的正投影内。第二介质层16具有沿第二方向Y相对的第七边沿67和第八边沿68，第五边沿65和第七边沿67位于第二走线2第二方向Y的同一侧，第六边沿66和第八边沿68位于第二走线2第二方向Y的同一侧，第五边沿65到第七边沿67的第三垂直距离L3大于等于20μm。比如，第三垂直距离L3约为20μm至30μm。第六边沿66到第八边沿68的第四垂直距离L4大于等于20μ m。比如，第三垂直距离L3约为20μm至30μm。其中，三垂直距离L3和第四垂直距离L4分别为第二方向Y的垂直距离。
在一些实施例中，第一介质层具有沿第二方向Y相对的第七边沿和第八边沿，第五边沿和第七边沿位于第二走线第二方向Y的同一侧，第六边沿和第八边沿位于第二走线第二方向Y的同一侧，第五边沿到第七边沿的第三垂直距离L3大于等于20μm。比如，第三垂直距离L3约为20μm至30μm。第六边沿到第八边沿的第四垂直距离L4大于等于20μm。比如，第三垂直距离L3约为20μm至30μm。
在示例性实施方式中，第一介质层15包括沿第一方向X延伸的第三条状区域，第二介质层16包括沿第一方向X延伸的第四条状区域，第三条状区域在基底的正投影位于第四条状区域在基底的正投影内，且第三条状区域正投影面积小于第四条状区域正投影面积。
在一些实施例中，第一介质层包括沿第一方向X延伸的第三条状区域，第二介质层包括沿第一方向X延伸的第四条状区域，第三条状区域正投影与第四条状区域正投影重合。
在一些实施例中，第一介质层包括沿第一方向X延伸的第三条状区域，第二介质层包括沿第一方向X延伸的第四条状区域，第四条状区域在基底的正投影位于第三条状区域在基底的正投影内，且第四条状区域正投影面积小于第三条状区域正投影面积。
本公开实施例显示背板通过将第五边沿65到第七边沿67之间形成第三垂直距离L3，以及将第六边沿66到第八边沿68之间形成第四垂直距离L4，减小第二遮光图案22与透光区320的基底10之间的段差，从而减少第二遮光图案22在透光区320段差处的残留面积，提高显示背板的透光率。
图13为本公开示例性实施例一个显示单元中第一走线和第二走线的平面结构示意图。如图13所示，本公开实施例显示背板在制备第二走线2时，第二走线2在透光区320段差的残留b形成在第一介质层15或第二介质层16中一个的边缘，从而避免残留b导致相邻第二走线2之间发生短路。
在示例性实施方式中，如图4所示，本公开示例性实施例的显示单元的 像素区还包括至少一个排气孔90，排气孔90包括第一子排气孔和第二子排气孔，第一子排气孔设置在第二无机层17，第一子排气孔在第二无机层17的厚度方向贯穿第二无机层17；第二子排气孔设置在第三无机层18，第二子排气孔在第三无机层18的厚度方向贯穿第三无机层18；一个第一子排气孔在基底的正投影与一个第二子排气孔在基底的正投影至少部分交叠，形成一个排气孔90，且第一子排气孔在基底的正投影的面积小于第二子排气孔在基底的正投影面积。
在本公开实施例显示背板中，由于无机材料层密闭性较好，有机材料层中的水汽会被无机材料层密封在里面。在显示背板制备工艺中，高温工艺会使有机材料层中的水气无法排出。本公开实施例显示背板通过排气孔90能够将第一介质层和第二介质层中的水汽排出，防止爆膜的情况发生。
图14为本公开示例性实施例一个显示单元中排气孔的平面结构示意图。在示例性实施方式中，如图14所示，本公开示例性实施例的显示单元包括多个排气孔90，多个排气孔90分设于第一走线1的第一部分沿第一方向X的两侧，且设于第一部分两侧的多个排气孔90沿第二方向Y间隔排布。多个排气孔90在基底的正投影均与第一走线1在基底的正投影不交叠。
在示例性实施方式中，排气孔90中第一子排气孔和第二子排气孔在基底的正投影可以为矩形、圆形、椭圆形、菱形、多边形等规则或不规则形状。
在示例性实施方式中，排气孔90中第一子排气孔和第二子排气孔在基底的正投影可以为矩形。排气孔90中第一子排气孔在第一方向X上靠近第一走线1一侧的边缘至第一走线1的边缘之间的垂直距离约为1μm至5μm，例如，排气孔90中第一子排气孔在第一方向X上靠近第一走线1一侧的边缘至第一走线1的边缘之间的垂直距离约为4μm。在第二方向Y上相邻的排气孔90中第二子排气孔边缘的垂直距离约为100μm至200μm，例如，在第二方向Y上相邻的排气孔90中第二子排气孔边缘的垂直距离约为150μm。排气孔90中第一子排气孔在第一方向X上的两侧边缘之间的垂直距离约为5μm至10μm，例如，排气孔90中第一子排气孔在第一方向X上的两侧边缘之间的垂直距离约为9μm。排气孔90中第二子排气孔在第一方向X上的两侧边缘之间的垂直距离约为10μm至20μm，例如，排气孔90中 第二子排气孔在第一方向X上的两侧边缘之间的垂直距离约为11μm。
在示例性实施方式中，本公开示例性实施例的显示单元包括多个排气孔，多个排气孔分设于第二走线的第二部分沿第二方向Y的两侧，且设于第二部分两侧的多个排气孔沿第一方向X间隔排布。多个排气孔在基底的正投影均与第二走线在基底的正投影不交叠。
图15为本公开示例性实施例显示背板中扇出区的剖视图。在示例性实施方式中，如图15所示，本公开示例性实施例的显示单元还包括扇出区，扇出区位于显示区与绑定区之间，扇出区包括多个扇出线3，多个扇出线3被配置为以扇出(Fanout)走线方式连接显示区的第一走线。扇出区包括设置在基底10上的保护层12，设置在保护层12远离基底10一侧的缓冲层13，设置在缓冲层13远离基底10一侧的第一走线层，第一走线层包括多个第一扇出部分301，设置在第一走线层远离基底10一侧的第一介质层15，设置在第一介质层15远离基底10一侧的第二介质层16，设置在第二介质层16远离基底10一侧的第二无机层17，设置在第二无机层17远离基底10一侧的第二走线层，第二走线层包括多个第二扇出部分302，设置在第二走线层远离基底10一侧的第三介质层20，其中，第一介质层15中设置有多个第一开口151，多个第一开口151与多个第一扇出部分301一一对应，且第一开口151将与其对应的第一扇出部分301暴露，一个第二扇出部分302通过一个第一开口151与一个第一扇出部分301连接，形成一个扇出线3。第二介质层16中设置有一个第二开口161，多个第一开口151在基底10的正投影位于一个第二开口161在基底10的正投影中，且一个第二开口161在基底10的正投影的面积大于多个第一开口151在基底10的正投影的面积之和。第三介质层20中设置有一个第三开口201，多个第一开口151在基底10的正投影位于一个第三开口201在基底10的正投影中，且一个第三开口201在基底10的正投影的面积大于多个第一开口151在基底10的正投影的面积之和，从而以降低扇出区的第一扇出部分301与第二扇出部分302之间的段差。
本公开还提供了一种显示装置，包括前述示例性实施例的显示背板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (25)

  1. 一种显示背板，包括位于基底上的多个显示单元，至少一个显示单元包括像素区和透光区，所述像素区被配置为进行图像显示，所述透光区被配置为透过光线；所述像素区包括沿基底厚度方向异层设置的第一走线层和第二走线层；以及，位于所述第一走线层和所述第二走线层之间的第一介质层和第二介质层，
    其中，所述第一走线层的厚度与所述第二走线层的厚度之比大于5；
    所述第一介质层的厚度与所述第二介质层的厚度之和大于3μm,所述第一介质层的厚度小于2μm；
    所述第一走线层包括多根第一走线，所述第一走线包括沿第一方向延伸的第一部分；
    所述第二走线层包括多根第二走线，所述第二走线包括沿第二方向延伸的第二部分，所述第一方向与所述第二方向交叉。
  2. 根据权利要求1所述的显示背板，其中，至少一根第一走线包括第一扫描线、数据信号线、接地线、第一驱动线和第二驱动线中的至少一种。
  3. 根据权利要求1所述的显示背板，其中，至少一根第一走线的第一部分包括沿第一方向相对的第一边沿和第二边沿，所述像素区还包括至少一个第一发光器件、至少一个第二发光器件以及至少一个第三发光器件，至少一个第一发光器件、至少一个第二发光器件和至少一个第三发光器件在基底的正投影均位于所述第一边沿和所述第二边沿限定的区域内。
  4. 根据权利要求3所述的显示背板，其中，所述第一发光器件、所述第二发光器件和所述第三发光器件均为次毫米发光二极管和微型发光二极管中的一种。
  5. 根据权利要求3所述的显示背板，其中，所述像素区还包括像素驱动芯片，所述像素驱动芯片被配置为向第一发光器件、第二发光器件以及第三发光器件中至少一者提供驱动信号。
  6. 根据权利要求5所述的显示背板，其中，所述像素区还包括第三介质 层，所述第三介质层中设置有第一凹槽和第二凹槽，所述第一凹槽被配置为印刷与第一发光器件、第二发光器件以及第三发光器件中至少一者连接的锡膏，所述第二凹槽被配置为印刷与所述像素驱动芯片连接的锡膏。
  7. 根据权利要求1所述的显示背板，其中，至少一根第一走线的第一部分包括沿所述第一方向相对的第一边沿和第二边沿，至少一根第一走线的第一部分在基底的正投影位于所述第一介质层在基底的正投影内，所述第一介质层或所述第二介质层中的一者，具有沿所述第一方向相对的第三边沿和第四边沿，所述第一边沿和所述第三边沿位于所述第一走线的同一侧，所述第二边沿和所述第四边沿位于所述第一走线的同一侧，所述第一边沿到所述第三边沿的第一垂直距离大于等于20μm，所述第二边沿到所述第四边沿的第二垂直距离大于等于20μm。
  8. 根据权利要求7所述的显示背板，其中，所述第一介质层包括沿所述第二方向延伸的第一条状区域，所述第二介质层包括沿所述第二方向延伸的第二条状区域，所述第一条状区域在基底的正投影位于所述第二条状区域在基底的正投影内，且所述第一条状区域正投影面积小于所述第二条状区域正投影面积；
    或者，所述第一条状区域在基底的正投影与所述第二条状区域在基底的正投影重合；
    或者，所述第二条状区域在基底的正投影位于所述第一条状区域在基底的正投影内，且所述第二条状区域正投影面积小于所述第一条状区域正投影面积。
  9. 根据权利要求1所述的显示背板，其中，至少一根第二走线的第二部分包括沿所述第二方向相对的第五边沿和第六边沿，至少一根第二走线的第二部分在基底的正投影位于所述第一介质层在基底的正投影内，所述第一介质层或所述第二介质层中的一者，具有沿所述第二方向相对的第七边沿和第八边沿，所述第五边沿和所述第七边沿位于所述第二走线第二方向的同一侧，所述第六边沿和所述第八边沿位于所述第二走线第二方向的同一侧，所述第五边沿到所述第七边沿的第三垂直距离大于等于20μm，所述第六边沿到所 述第八边沿的第四垂直距离大于等于20μm。
  10. 根据权利要求9所述的显示背板，其中，所述第一介质层包括沿第一方向延伸的第三条状区域，所述第二介质层包括沿第一方向X延伸的第四条状区域，所述第三条状区域在基底的正投影位于所述第四条状区域在基底的正投影内，且所述第三条状区域正投影面积小于所述第四条状区域正投影面积；
    或者，所述第三条状区域正投影与所述第四条状区域正投影重合；
    或者，所述第四条状区域在基底的正投影位于所述第三条状区域在基底的正投影内，且所述第四条状区域正投影面积小于所述第三条状区域正投影面积。
  11. 根据权利要求1所述的显示背板，其中，所述像素区还包括第一遮光层和第二遮光层，所述第一遮光层位于所述第一走线层靠近基底的一侧，所述第二遮光层位于所述第二走线层远离基底的一侧；所述第一遮光层包括第一遮光图案，所述第一走线在基底的正投影与所述第一遮光图案在基底的正投影至少部分交叠；所述第二遮光层包括第二遮光图案，所述第二走线在基底的正投影与所述第二遮光图案在基底的正投影至少部分交叠。
  12. 根据权利要求11所述的显示背板，其中，所述第一走线在基底的正投影位于所述第一遮光图案在基底的正投影内，所述第二走线在基底的正投影位于所述第二遮光图案在基底的正投影内。
  13. 根据权利要求12所述的显示背板，其中，所述第一遮光图案在基底的正投影和所述第二遮光图案在基底的正投影重合。
  14. 根据权利要求11所述的显示背板，其中，所述第一遮光层的材料为黑矩阵和氧化钼中的一种，所述第二遮光层的材料为黑矩阵和氧化钼中的一种。
  15. 根据权利要求14所述的显示背板，其中，所述第一遮光层的材料为黑矩阵，所述第一遮光层与所述第一走线层之间设置保护层。
  16. 根据权利要求15所述的显示背板，其中，所述第一走线层与所述第 一遮光层之间还设置有缓冲层，所述第一走线层材料为铜，所述第一走线层包括种子层，所述种子层与所述缓冲层直接接触。
  17. 根据权利要求14所述的显示背板，其中，所述第一遮光层的材料为氧化钼，所述第一走线层材料为铜，所述第一走线层与所述第一遮光层直接接触。
  18. 根据权利要求1所述的显示背板，其中，所述第一介质层和所述第二介质层均为有机材料。
  19. 根据权利要求18所述的显示背板，其中，所述像素区还包括位于所述第一走线层与所述第一介质层之间的第一无机层、位于所述第二介质层远离所述基底一侧的第二无机层和第三无机层。
  20. 根据权利要求19所述的显示背板，其中，所述像素区还包括至少一个排气孔，至少一个排气孔设置在所述第二无机层和所述第三无机层中的至少一者，且至少一个排气孔在基底的正投影均与所述第一走线的第一部分在基底的正投影和所述第二走线的第二部分在基底的正投影不交叠。
  21. 根据权利要求20所述的显示背板，其中，所述像素区包括多个排气孔，多个排气孔分设于所述第一走线的第一部分沿第一方向的两侧，和/或，多个排气孔分设于所述第二走线的第二部分沿第二方向的两侧。
  22. 根据权利要求1所述的显示背板，还包括绑定区，所述绑定区位于所述显示区的至少一侧，所述绑定区在基底的正投影与所述第二介质层在基底的正投影不交叠。
  23. 根据权利要求1所述的显示背板，还包括扇出区，所述扇出区位于所述显示区的至少一侧，所述扇出区包括基底，设置在所述基底上的第一扇出部分，设置在所述第一扇出部分远离基底一侧的第一介质层，设置在所述第一介质层远离基底一侧的第二介质层，设置在所述第二介质层远离基底一侧的第二扇出部分，所述第一介质层中设置有第一开口，所述第二扇出部分通过所述第一开口与所述第一扇出部分连接，形成扇出线，所述第二介质层中设置有第二开口，所述第一开口在基底的正投影位于所述第二开口在基底的正投影中，且所述第二开口在基底的正投影的面积大于所述第一开口在基 底的正投影的面积。
  24. 根据权利要求23所述的显示背板，其中，所述扇出区还包括设置在所述第二扇出部分远离基底一侧的第三介质层，所述第三介质层中设置有第三开口，所述第一开口在基底的正投影位于所述第三开口在基底的正投影中，且所述第三开口在基底的正投影的面积大于所述第一开口在基底的正投影的面积。
  25. 一种显示装置，包括权利要求1至24任一所述的显示背板。
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018055815A (ja) * 2016-09-26 2018-04-05 パイオニア株式会社 発光装置
CN108305881A (zh) * 2018-03-23 2018-07-20 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、显示装置
CN110112146A (zh) * 2019-05-17 2019-08-09 京东方科技集团股份有限公司 一种阵列基板、其制备方法及显示面板
CN110265454A (zh) * 2019-06-25 2019-09-20 上海天马微电子有限公司 一种显示面板、其制作方法及显示装置
CN110767738A (zh) * 2019-11-22 2020-02-07 京东方科技集团股份有限公司 显示装置、显示面板及其制造方法
CN112271206A (zh) * 2020-11-09 2021-01-26 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN113327958A (zh) * 2020-02-28 2021-08-31 三星显示有限公司 显示装置及制造显示装置的方法
US20220085122A1 (en) * 2019-12-03 2022-03-17 Shanghai Tianma Micro-electronics Co., Ltd. Display panel and display device
US20220131111A1 (en) * 2020-10-28 2022-04-28 Samsung Display Co., Ltd. Display apparatus

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018055815A (ja) * 2016-09-26 2018-04-05 パイオニア株式会社 発光装置
CN108305881A (zh) * 2018-03-23 2018-07-20 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、显示装置
CN110112146A (zh) * 2019-05-17 2019-08-09 京东方科技集团股份有限公司 一种阵列基板、其制备方法及显示面板
CN110265454A (zh) * 2019-06-25 2019-09-20 上海天马微电子有限公司 一种显示面板、其制作方法及显示装置
CN110767738A (zh) * 2019-11-22 2020-02-07 京东方科技集团股份有限公司 显示装置、显示面板及其制造方法
US20220085122A1 (en) * 2019-12-03 2022-03-17 Shanghai Tianma Micro-electronics Co., Ltd. Display panel and display device
CN113327958A (zh) * 2020-02-28 2021-08-31 三星显示有限公司 显示装置及制造显示装置的方法
US20220131111A1 (en) * 2020-10-28 2022-04-28 Samsung Display Co., Ltd. Display apparatus
CN112271206A (zh) * 2020-11-09 2021-01-26 武汉华星光电半导体显示技术有限公司 显示面板及显示装置

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