WO2023206328A9 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023206328A9
WO2023206328A9 PCT/CN2022/090169 CN2022090169W WO2023206328A9 WO 2023206328 A9 WO2023206328 A9 WO 2023206328A9 CN 2022090169 W CN2022090169 W CN 2022090169W WO 2023206328 A9 WO2023206328 A9 WO 2023206328A9
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Prior art keywords
substrate
display
display substrate
pixel
layer
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PCT/CN2022/090169
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English (en)
French (fr)
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WO2023206328A1 (zh
Inventor
杨薇
黄洪涛
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京东方科技集团股份有限公司
南京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 南京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000970.4A priority Critical patent/CN117321498A/zh
Priority to PCT/CN2022/090169 priority patent/WO2023206328A1/zh
Publication of WO2023206328A1 publication Critical patent/WO2023206328A1/zh
Publication of WO2023206328A9 publication Critical patent/WO2023206328A9/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application belongs to the field of display technology, and specifically relates to a display substrate and a display device.
  • the top-gate self-aligned thin film transistor has a small parasitic capacitance because there is no overlapping area between the gate and the drain-source electrode.
  • OLED organic electroluminescent diode
  • LCD liquid crystal display
  • top-gate self-aligned oxide thin film transistors because oxide thin film transistors are sensitive to light, in order to achieve stable device characteristics, it is usually necessary to separately design a metal light-shielding layer that can block the semiconductor layer.
  • the metal light-shielding layer The area depends on the actual need for stable oxide properties, and its occupied area is usually larger.
  • the structure containing a metal light-shielding layer has a great impact on the pixel aperture ratio. If the thin film transistor structure in the pixel is poorly designed, it is easy to cause pixel The opening ratio will decrease, affecting product performance.
  • This application aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a display device.
  • an embodiment of the present application provides a display substrate, wherein the display substrate includes: a substrate, gate scanning lines and data signal lines arranged crosswise on the substrate, and gate scanning lines located on the gate scanning line. and pixel units in the area defined by the data signal lines;
  • the pixel unit has a pixel display area and a driving device area disposed on one side of the pixel display area; the gate scanning line penetrates the driving device area, and a part of the gate scanning line faces the pixel
  • the display area is bent to form a bent portion;
  • the pixel unit includes: a plurality of thin film transistors disposed in the driving device area; the thin film transistors include: a semiconductor layer located on the substrate;
  • the length direction of the bent portion intersects the length direction of the semiconductor layer, and the orthographic projection of the bent portion on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate;
  • the portion where the semiconductor layer overlaps the bent portion forms a channel; the portion where the bent portion overlaps the semiconductor layer serves as a gate electrode of the thin film transistor.
  • the angle between the length direction of the bending portion and the extension direction of the gate scanning line is 30 degrees to 60 degrees.
  • the angle between the length direction of the bent portion and the length direction of the semiconductor layer is 60 degrees to 90 degrees.
  • the semiconductor layer further includes: a source electrode and a drain electrode respectively provided at both ends of the channel;
  • the source electrode and the drain electrode are both formed by conductorization.
  • the display substrate further includes: an interlayer insulating layer located on a side of the source electrode and the drain electrode facing away from the substrate;
  • the drain electrode is electrically connected to the data signal line through a via hole penetrating the interlayer insulating layer.
  • the display substrate further includes: a first passivation layer, a second passivation layer and a pixel electrode located on the interlayer insulating layer and arranged in sequence in a direction away from the substrate;
  • the source electrode is electrically connected to the pixel electrode through a via hole penetrating the interlayer insulating layer, the first passivation layer and the second passivation layer.
  • the display substrate further includes: a common electrode located between the first passivation layer and the second passivation layer;
  • the orthographic projection of the common electrode on the substrate at least partially overlaps the orthographic projection of the pixel electrode on the substrate.
  • the display substrate further includes: a planarization layer located between the first passivation layer and the second passivation layer;
  • the source electrode is electrically connected to the pixel electrode through a via hole penetrating the interlayer insulating layer, the first passivation layer, the planarization layer and the second passivation layer.
  • the display substrate further includes: a common electrode located between the planarization layer and the second passivation layer;
  • the orthographic projection of the common electrode on the substrate at least partially overlaps the orthographic projection of the pixel electrode on the common electrode on the substrate.
  • the display substrate further includes: a common electrode located on a side of the second passivation layer facing away from the substrate;
  • An orthographic projection of the common electrode on the substrate at least partially overlaps an orthographic projection of the pixel electrode on the substrate.
  • the display substrate further includes: a light-shielding layer located between the substrate and the channel;
  • the orthographic projection of the channel on the substrate falls within the orthographic projection of the light shielding layer on the substrate.
  • embodiments of the present application provide a display device, wherein the display device includes the display substrate provided as above.
  • Figure 1 is a schematic structural diagram of an exemplary display substrate
  • Figure 2 is a schematic structural diagram of a pixel unit in the display substrate shown in Figure 1;
  • Figure 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a pixel unit in the display substrate shown in Figure 3;
  • Figure 5 is a schematic cross-sectional structural diagram of the pixel unit shown in Figure 4 along the A-A’ direction;
  • Figure 6 is another structural schematic diagram of the pixel unit in the display substrate shown in Figure 3;
  • Figure 7 is a schematic cross-sectional structural diagram of the pixel unit shown in Figure 6 along the B-B’ direction;
  • Figure 8 is another structural schematic diagram of the pixel unit in the display substrate shown in Figure 3;
  • the driving device area is located on the lower side of the pixel display area.
  • the pixel unit 104 includes a plurality of thin film transistors 105 disposed in a driving device area. For ease of illustration, only the structure of one thin film transistor 105 is shown in FIG. 2 . The structures of other thin film transistors 105 are similar and will not be described in detail.
  • the display substrate also includes: a pixel electrode 106 located on the side of the drain electrode 1055 facing away from the substrate 101 .
  • the source electrode 1054 of the thin film transistor 105 may be electrically connected to the pixel electrode 106 .
  • the light-shielding layer 1051 can block the channel 1052a of the semiconductor layer 102 to prevent the light incident from the direction of the substrate 101 from irradiating the channel 1052a of the semiconductor layer 102, thereby improving the stability of the thin film transistor 105.
  • the area of the light-shielding layer 1051 Depending on the actual need for stable oxide properties, its occupied area is usually larger.
  • BM black matrix
  • the gate scanning line 102 and the data signal line 103 can use thinner line widths to reduce the area they occupy, but the area occupied by the thin film transistor 105 is still large.
  • the total length of the thin film transistor 105 in the second direction is 21 microns
  • the total length in the first direction is the length between the two adjacent data signal lines 103 .
  • the area of the black matrix blocks the thin film transistor 105 and reduces the effective display area in the pixel unit. Therefore, it is easy to cause the pixel aperture ratio in the display substrate to decrease, resulting in a decrease in light transmittance and affecting the display effect of the display substrate.
  • embodiments of the present application provide a display substrate and a display device.
  • the display substrate and display device provided by embodiments of the present application will be described in further detail below with reference to the drawings and specific implementation modes.
  • an embodiment of the present application provides a display substrate.
  • Figure 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present application. As shown in Figure 3, the display substrate includes: a base 101, an intersection located on the base 101 The gate scanning line 102 and the data signal line 103 are provided, and the pixel unit 104 is located in the area defined by the gate scanning line 102 and the data signal line 103.
  • the folded portion 102a; the pixel unit 104 includes: a plurality of thin film transistors 105 provided in the driving device area; the thin film transistor 105 includes: a semiconductor layer 1052 located on the substrate 101; the length direction of the folded portion 102a intersects the length direction of the semiconductor layer 1052 , and the orthographic projection of the bent portion 102a on the substrate 101 at least partially overlaps with the orthographic projection of the semiconductor layer 1052 on the substrate 101; the overlapping portion of the semiconductor layer 1052 and the bent portion 102a forms a channel 1052a; the bent portion 102a
  • the portion overlapping the semiconductor layer 1052 serves as the gate electrode 1053 of the thin film transistor 105 .
  • the substrate 101 can be made of rigid materials such as glass, which can improve the carrying capacity of other film layers on the substrate 101 .
  • the substrate 101 can also be made of flexible materials such as polyimide (PI), which can improve the overall bending and tensile resistance of the metal oxide thin film transistor and avoid bending, stretching, and twisting processes.
  • PI polyimide
  • the stress generated in the substrate 101 causes the substrate 101 to break, resulting in poor circuit breaking.
  • the material of the substrate 101 can be reasonably selected according to actual needs to ensure that the metal oxide thin film transistor has good performance.
  • the data signal line 103 can be made of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), and chromium (Cr). It is made of at least one material, which can form a single-layer structure made of a single material.
  • the gate scanning line 102 is a single-layer structure made of aluminum (Al). Of course, it can also be formed of multiple different materials.
  • the multi-layer structure is made, for example, a three-layer structure composed of molybdenum (Mo), aluminum (Al), and molybdenum (Mo).
  • the data signal line 103 may pass through the driving device area to provide data signals to the thin film transistors in the driving device area.
  • the semiconductor layer 1052 may be made of at least one of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc oxide (IZO), indium tin oxide (ITO), and indium tin zinc oxide (ITZO). Made of a kind of material, which are all metal oxides with higher mobility, to ensure that the overall metal oxide thin film transistor has higher mobility.
  • the channel 1052a of the semiconductor layer 1052 may be disposed in a central region thereof. The channel 1052a of the semiconductor layer 1052 can be turned on driven by the gate scanning signal input by the gate 1053 to transmit the data signal input by the data signal line 103.
  • the gate scanning lines 102 can generally extend along the horizontal direction (ie, the first direction shown in FIG. 4 ), and the data signal lines 103 can extend along the vertical direction (ie, the first direction shown in FIG. 4 ).
  • second direction in which a partial area of the gate scanning line 102 is bent toward the direction of the pixel display area (ie, the third direction shown in FIG. 4 ) to form a bent portion 102a.
  • the formed bent portion 102a is shown in FIG. 4
  • the third direction is the length direction of the bent portion 102a, and the length direction forms a certain angle with the horizontal direction.
  • the semiconductor layer 1052 can extend along the fourth direction shown in Figure 4,
  • the fourth direction is the length direction of the semiconductor layer 1052 .
  • the longitudinal direction of the semiconductor layer 1052 intersects the longitudinal direction of the bent portion 102a, where the portion where the semiconductor layer 1052 overlaps the bent portion 102a forms the channel 1052a, and the portion where the bent portion 102a overlaps the semiconductor layer 1052 serves as a thin film Gate 1053 of transistor 105 .
  • both the gate electrode 1053 and the channel 1052a of the thin film transistor 105 can be closer to the pixel display area, so the total length of the thin film transistor 105 in the second direction can be reduced.
  • the thin film transistor 105 The total length of the thin film transistor 105 in the second direction can be reduced from the original 21 microns to 16 microns. It can be seen that the area occupied by the thin film transistor 105 can be reduced to the original 16/21, and there is no need to use a larger area black matrix for the thin film transistor. 105 is blocked to increase the effective display area in the pixel unit, thereby increasing the pixel aperture ratio of the display substrate, increasing the light transmittance of the display substrate, and thereby improving the display effect of the display substrate.
  • the angle between the third direction and the first direction or the second direction is only an example, and the angle can be set according to actual needs.
  • the angle between the fourth direction and the first direction or the second direction is only an example, and the angle can also be set according to actual needs.
  • the angle between the length direction of the bent portion 102a and the extension direction of the gate scanning line 102 is 30 degrees to 60 degrees.
  • the bending portion 102a can be bent toward the pixel display area at a certain angle.
  • the bending angle can be 30 degrees to 60 degrees to ensure that the formed gate electrode 1053 and channel 1052a can be directed toward the pixel display area. Therefore, the total length of the thin film transistor 105 in the second direction can be reduced, so that the area occupied by the thin film transistor 105 can be significantly reduced, and there is no need to use a larger area of black matrix to block the thin film transistor 105, thereby increasing the number of pixels.
  • the effective display area in the unit can thereby increase the pixel aperture ratio of the display substrate, increase the light transmittance of the display substrate, and thereby improve the display effect of the display substrate. It should be noted here that the bending angle cannot be too small.
  • the bending angle of the bending portion 102a can be specifically 45 degrees, which not only improves the pixel aperture ratio of the display substrate, but also reduces the process difficulty of the gate scanning line 102 and saves preparation costs.
  • the angle between the length direction of the bent portion 102a and the length direction of the semiconductor layer 1052 is 60 degrees to 90 degrees.
  • the bent portion 102a and the semiconductor layer 1052 may at least partially overlap, and the angle between their length directions may range from 60 degrees to 90 degrees.
  • the angle between the bending portion 102a and the length direction of the channel 1052a is small, for example, 60 degrees, the overlapping area between the bending portion 102a and the semiconductor layer 1052 can be increased, thereby improving the groove in the semiconductor layer 1052.
  • the length and width of the track 1052a are increased to improve the mobility of the thin film transistor 105.
  • the angle between the bent portion 102a and the channel 1052a is relatively large, such as 90 degrees, the difficulty of the manufacturing process can be reduced and the manufacturing cost can be saved.
  • the angle between the bent portion 102a and the length direction of the semiconductor layer 1052 may be 90 degrees.
  • the semiconductor layer 1052 further includes: a source electrode 1054 and a drain electrode 1055 respectively disposed at both ends of the channel 1052a; both the source electrode 1054 and the drain electrode 1055 are formed by conductorization.
  • heavy doping can be used to make the ion concentration at both ends of the semiconductor layer 1052 greater than the ion concentration of the central channel 1052.
  • the two ends of the semiconductor layer 1052 can be conductive to form the source electrode 1054 and the drain electrode. 1055.
  • hydrogen (H 2 ) or helium (He) plus argon (Ar) plasma gas can be used to perform plasma treatment on the area where the central channel 1052 of the semiconductor layer 1052 is located.
  • the source electrode 1054 and the drain electrode 1055 are formed by direct conduction from both ends of the semiconductor layer 1052, it is not necessary to use a separate metal layer to prepare the source electrode 1054 and the drain electrode 1055 of the thin film transistor 105, thereby reducing the area occupied by the thin film transistor 105. , which can increase the pixel aperture ratio of the display substrate, increase the light transmittance of the display substrate, and thereby improve the display performance of the display product.
  • the number of film layers in the thin film transistor 105 can be reduced, thereby reducing the thickness of the thin film transistor 105, and at the same time, the number of separate layers can be reduced. Process steps of the source electrode 1054 and the drain electrode 1055 to save process costs.
  • the display substrate further includes: an interlayer insulating layer 107 located on the side of the source electrode 1054 and the drain electrode 1055 facing away from the substrate 101 ; the drain electrode 1055 passes through a via hole penetrating the interlayer insulating layer 107 Electrically connected to the data signal line 103.
  • the interlayer insulating layer 107 can short-circuit the source electrode 1054 and the drain electrode 1055 of the thin film transistor and other film layers above it, thereby improving the stability of the thin film transistor.
  • the interlayer insulating layer 107 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO 2 ). It can form a single-layer structure made of a single material, or can also be formed of a variety of different materials. Made of multi-layer structure.
  • the drain electrode 1055 can be electrically connected to the data signal line 103 through a via hole penetrating the interlayer insulating layer 107.
  • the gate electrode 1052 When the gate electrode 1052 inputs a gate scanning signal, the source electrode 1054 and the drain electrode 1055 are turned on, and the data signal line 103 transmits data. The signal can be transmitted to the source electrode 1054 through the drain electrode 1055 to realize the transmission of the data signal.
  • the display substrate further includes: a first passivation layer 108 , a second passivation layer 109 and a pixel electrode 106 located on the interlayer insulating layer 107 and arranged in sequence in a direction away from the substrate 101 ;
  • the source electrode 1054 is electrically connected to the pixel electrode 106 through a via hole penetrating the interlayer insulating layer 107, the first passivation layer 108 and the second passivation layer 109.
  • Both the first passivation layer 108 and the second passivation layer 109 can be made of at least one material selected from silicon nitride (SiN) and silicon oxide (SiO 2 ), which can form a single-layer structure made of a single material. , it is also possible to form multi-layer structures made of a variety of different materials.
  • the pixel electrode 106 can be made of a transparent conductive material such as indium tin oxide (ITO) to prevent the pixel electrode 106 from blocking light and improve the overall light transmittance of the display substrate.
  • the source electrode 1054 can be electrically connected to the pixel electrode 106 through a via hole penetrating the interlayer insulating layer 107, the first passivation layer 108 and the second passivation layer 109.
  • the data signal can be The data signal on the line 103 is transmitted to the pixel electrode 106 to realize the transmission of the data signal.
  • no other film layer (such as a planarization layer, etc.) is provided between the first passivation layer 108 and the second passivation layer 109, so it is not necessary to make via holes penetrate too many film layers to reduce the risk of The size of the via hole can therefore reduce the size of the thin film transistor 105 and the area it occupies, thereby increasing the pixel aperture ratio of the display substrate, increasing the light transmittance of the display substrate, and thus improving the display performance of the display product.
  • the display substrate further includes: a common electrode 110 located between the first passivation layer 108 and the second passivation layer 109 ; an orthographic projection of the common electrode 110 on the substrate 101 and a pixel The orthographic projections of the electrodes 106 on the substrate 101 at least partially overlap.
  • the common electrode 110 can be made of transparent conductive materials such as indium tin oxide (ITO) to prevent the common electrode 110 from blocking light and improve the overall light transmittance of the display substrate.
  • ITO indium tin oxide
  • the gate scan signal transmitted by the gate scan line 102 can be transmitted to the gate electrode 1053 of the thin film transistor 105 to control the source electrode 1054 and the drain electrode 1055 to be turned on, so that the data signal on the data signal line 103 is transmitted to The pixel electrode 106, and with the cooperation of the common signal transmitted by the common electrode 110, a driving electric field is formed between the pixel electrode 106 and the common electrode 110 to control the deflection of the liquid crystal molecules in the liquid crystal layer, so that the light in the backlight module is transmitted through the liquid crystal layer. passed to achieve the display function.
  • ITO indium tin oxide
  • FIG. 6 is another schematic structural diagram of the pixel unit in the display substrate shown in FIG. 3
  • FIG. 7 is a schematic cross-sectional structural diagram of the pixel unit shown in FIG. 6 along the BB′ direction.
  • the display substrate also includes: a planarization layer 111 located between the first passivation layer 108 and the second passivation layer 109; the source electrode 1054 passes through the interlayer insulating layer 107, the first The passivation layer 108 , the planarization layer 111 and the via holes of the second passivation layer 109 are electrically connected to the pixel electrode 106 .
  • the planarization layer 111 can be made of organic materials such as acrylic, resin, polyimide or benzocyclobutene, which can be selected according to actual needs.
  • a planarization layer 111 is provided between the first passivation layer 108 and the second passivation layer 109 .
  • the planarization layer 111 can planarize the surface of the film layer formed by the thin film transistor 105 so that the surface of the thin film transistor 105 is
  • the other film layers can have a relatively flat lamination plane to ensure the flatness of the lamination.
  • the distance between the source electrode 1054 and other conductive film layers in the thin film transistor 105 can be increased to avoid the distance between the source electrode 1054 or the drain electrode 1055 and other conductive film layers thereon. Produce parasitic capacitance.
  • Fig. 8 is another schematic structural diagram of the pixel unit in the display substrate shown in Fig. 3
  • Fig. 9 is a schematic cross-sectional structural diagram of the pixel unit shown in Fig. 8 along the CC' direction, as shown in
  • the display substrate also includes: a common electrode 110 located on the side of the second passivation layer 109 facing away from the substrate 101; the orthographic projection of the common electrode 110 on the substrate 101 is the same as the orthogonal projection of the pixel electrode 106 on the substrate 101. The projections at least partially overlap.
  • the structure shown in FIG. 9 is different from the structures shown in FIGS. 5 and 7 in that the common electrode 110 can be disposed on the side of the second passivation layer 109 facing away from the substrate 101 .
  • the common electrode 110 is usually disposed on the entire surface.
  • the common electrode 110 since the common electrode 110 is disposed at a position close to the pixel electrode 106 and the substrate 101 , there is a gap between the pixel electrode 106 and the thin film transistor 105 .
  • a via hole needs to be drilled so that the via hole penetrates the common electrode 110.
  • FIG. 9 is different from the structures shown in FIGS. 5 and 7 in that the common electrode 110 can be disposed on the side of the second passivation layer 109 facing away from the substrate 101 .
  • the common electrode 110 is usually disposed on the entire surface.
  • the common electrode 110 since the common electrode 110 is disposed at a position close to the pixel electrode 106 and the substrate 101 , there is a gap between the pixel electrode 106 and the thin film transistor
  • the common electrode 110 is farther away from the substrate 101 than the pixel electrode 106 , and the via hole between the pixel electrode 106 and the source electrode 1054 does not need to penetrate the common electrode 110 to reduce the size of the via hole, so it can By reducing the size of the thin film transistor 105 and the area it occupies, the pixel aperture ratio of the display substrate can be increased, the light transmittance of the display substrate can be increased, and the display performance of the display product can be improved.
  • the display substrate further includes: a light-shielding layer 1051 located between the substrate 101 and the channel 1052a; the orthographic projection of the channel 1052a on the substrate 101 falls on the light-shielding layer 1051. within the orthographic projection on base 101.
  • the light shielding layer 1051 can be made of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo) and chromium (Cr). Made of at least one material, it can form a single-layer structure made of a single material.
  • the light-shielding layer 1051 is a single-layer structure made of aluminum (Al). Of course, it can also form a single-layer structure made of multiple different materials. Multi-layer structure, for example, a three-layer structure composed of molybdenum (Mo), aluminum (Al), and molybdenum (Mo).
  • the light-shielding layer 1051 can block the channel 1052a of the semiconductor layer 102 to prevent light incident from the direction of the substrate 101 from irradiating the channel 1052a of the semiconductor layer 102, thereby improving the stability of the thin film transistor 105.
  • FIGS 10a to 10k are schematic diagrams of the intermediate structure of the display substrate in various process stages provided by the embodiment of the present application. The following will be combined with the accompanying drawings, taking the structure of the display substrate shown in Figures 6 and 7 as an example to provide a detailed description of the display substrate provided by the embodiment of the present application. The preparation process of the display substrate is described in further detail.
  • a first metal layer is formed on the substrate 101, and the first metal layer is patterned to form the light-shielding layer 1051 of the thin film transistor 105.
  • a first insulating layer is formed on the light-shielding layer 1051.
  • the first insulating layer can be used as a buffer layer.
  • the buffer layer can be made of at least one material selected from silicon nitride, silicon oxide, and silicon oxynitride. become.
  • a semiconductor layer 1052 is formed on the first insulating layer.
  • the semiconductor layer 1052 can be made of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc oxide (IZO), indium It is made of at least one material selected from tin oxide (ITO) and indium tin zinc oxide (ITZO).
  • the semiconductor layer 1052 may be divided into a channel region, a source region, and a drain region.
  • a second insulating layer is formed on the semiconductor layer 1052.
  • the second insulating layer may be a gate insulating layer.
  • the gate insulating layer may be made of at least one of silicon nitride, silicon oxide, and silicon oxynitride. Made of materials.
  • a second metal layer is formed on the second insulating layer.
  • the second metal layer may be the gate scanning line 102 and the gate electrode 1053 of the thin film transistor 105 .
  • plasma process gas is used, and the gate 1053 is used as a mask plate to perform a conductive treatment on the portion of the semiconductor layer 1052 that is not blocked by the gate 1053, that is, the source region and the drain region, so that the semiconductor layer
  • the source and drain regions of 1052 are conductive to form the source 1054 and drain 1055 of the thin film transistor 105 .
  • a third insulating layer is formed on the second metal layer.
  • the third insulating layer may be an interlayer insulating layer 107.
  • the interlayer insulating layer 107 may be made of silicon nitride, silicon oxide, or silicon oxynitride. made of at least one material.
  • the third insulating layer is patterned to expose the source electrode 1054 and the drain electrode 1055 in the semiconductor layer 1052 .
  • a third metal layer is formed on the third insulating layer at a position where the drain electrode 1055 is exposed.
  • the third metal layer may be the data signal line 103 .
  • the data signal line 103 may be electrically connected to the drain electrode 1055 to input the data signal to the drain electrode 1055 .
  • a fourth insulating layer and a fifth insulating layer are formed on the third metal layer.
  • the fourth insulating layer may be specifically the first passivation layer 108
  • the fifth insulating layer may be specifically the planarization layer 111 .
  • the first passivation layer 108 can be made of at least one material selected from silicon nitride, silicon oxide, and silicon oxynitride.
  • the planarization layer 111 can be made of acrylic, resin, polyimide, or benzocyclobutene. Made of organic materials.
  • a common electrode 110 is formed on the fifth insulating layer.
  • the common electrode 110 can be made of transparent materials such as indium tin oxide (ITO).
  • a sixth insulating layer is formed on the common electrode 110.
  • the sixth insulating layer can be specifically a second passivation layer 109.
  • the second passivation layer 109 can be made of silicon nitride, silicon oxide, or silicon oxynitride. made of at least one of the materials.
  • the pixel electrode 106 is formed on the sixth insulating layer, so that the pixel electrode 106 is electrically connected to the source electrode 1054 through a via hole penetrating the interlayer insulating layer, the first passivation layer 108 and the second passivation layer 109 .
  • inventions of the present application provide a display device.
  • the display device includes the display substrate provided in any of the above embodiments.
  • the display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital
  • the implementation principles and beneficial effects of any products or components with display functions such as photo frames and navigators are the same as those of the above-mentioned display substrate, and will not be described again here.

Abstract

本申请提供一种显示基板及显示装置，属于显示技术领域，其可解决现有的显示基板的像素开口率较低的问题。本申请提供的显示基板包括：基底、位于基底上交叉设置的栅极扫描线和数据信号线、及位于栅极扫描线和数据信号线限定区域中的像素单元；像素单元具有像素显示区及设置于像素显示区一侧的驱动器件区；栅极扫描线贯穿驱动器件区，且栅极扫描线的部分区域向像素显示区弯折形成弯折部；像素单元包括：设置于驱动器件区的多个薄膜晶体管；薄膜晶体管包括：位于基底上的半导体层；弯折部的长度方向与半导体层的长度方向相交；半导体层与弯折部交叠的部分形成沟道；弯折部与半导体层交叠的部分用作薄膜晶体管的栅极。

Description

显示基板及显示装置 技术领域
本申请属于显示技术领域，具体涉及一种显示基板及显示装置。
背景技术
顶栅自对准薄膜晶体管由于栅极和漏源电极不存在交叠区域，其寄生电容小，运用到显示面板的像素电路中，栅极扫描线和数据信号线上的信号延迟低，像素充放电速度快，在高分辨率的有机电致发光二极管(Organic Light-Emitting Diode，OLED)显示基板和液晶显示(Liquid Crystal Display，LCD)显示基板的显示方面具有明显优势。
然而，对于顶栅自对准的氧化物薄膜晶体管而言，因氧化物薄膜晶体管对光照敏感，为实现稳定的器件特性，通常需要单独设计对半导体层有遮挡作用的金属遮光层，金属遮光层面积取决于实际氧化物特性稳定的需求，其占用面积通常较大。当顶栅自对准氧化物薄膜晶体管应用于LCD显示面板的像素中时，含有金属遮光层的结构对像素开口率的影响非常大，若像素中的薄膜晶体管结构设计不佳，则容易导致像素开口率会下降，影响产品性能。
发明内容
本申请旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及显示装置。
第一方面，本申请实施例提供了一种显示基板，其中，所述显示基板包括：基底、位于所述基底上交叉设置的栅极扫描线和数据信号线、及位于所述栅极扫描线和所述数据信号线限定区域中的像素单元；
所述像素单元具有像素显示区及设置于所述像素显示区一侧的驱动器 件区；所述栅极扫描线贯穿所述驱动器件区，且所述栅极扫描线的部分区域向所述像素显示区弯折形成弯折部；
所述像素单元包括：设置于所述驱动器件区的多个薄膜晶体管；所述薄膜晶体管包括：位于所述基底上的半导体层；
所述弯折部的长度方向与所述半导体层的长度方向相交，且所述弯折部在所述基底上的正投影与所述半导体层在所述基底上的正投影至少部分交叠；
所述半导体层与所述弯折部交叠的部分形成沟道；所述弯折部与所述半导体层交叠的部分用作所述薄膜晶体管的栅极。
可选地，所述弯折部的长度方向与所述栅极扫描线的延伸方向之间的夹角为30度至60度。
可选地，所述弯折部的长度方向与所述半导体层的长度方向之间的夹角为60度至90度。
可选地，所述半导体层还包括：分别设置于所述沟道两端的源极和漏极；
所述源极和所述漏极均经过导体化形成。
可选地，所述显示基板还包括：位于所述源极和所述漏极背离所述基底一侧的层间绝缘层；
所述漏极通过贯穿所述层间绝缘层的过孔与所述数据信号线电连接。
可选地，所述显示基板还包括：位于所述层间绝缘层上沿着背离所述基底方向依次设置的第一钝化层、第二钝化层及像素电极；
所述源极通过贯穿所述层间绝缘层、所述第一钝化层和所述第二钝化层的过孔与所述像素电极电连接。
可选地，所述显示基板还包括：位于所述第一钝化层和所述第二钝化层之间的公共电极；
所述公共电极在所述基底上的正投影与所述像素电极在所述基底上的 正投影至少部分交叠。
可选地，所述显示基板还包括：位于所述第一钝化层和所述第二钝化层之间的平坦化层；
所述源极通过贯穿所述层间绝缘层、所述第一钝化层、所述平坦化层和所述第二钝化层的过孔与所述像素电极电连接。
可选地，所述显示基板还包括：位于所述平坦化层与所述第二钝化层之间的公共电极；
所述公共电极在所述基底上的正投影与所述像素电极在所述公共电极在所述基底上的正投影至少部分交叠。
可选地，所述显示基板还包括：位于所述第二钝化层背离所述基底一侧的公共电极；
所述公共电极在所述基底上的正投影与所述像素电极在所述基底上的正投影至少部分交叠。
可选地，所述显示基板还包括：位于所述基底与所述沟道之间的遮光层；
所述沟道在所述基底上的正投影落在所述遮光层在所述基底上的正投影内。
第二方面，本申请实施例提供了一种显示装置，其中，所述显示装置包括如上述提供的显示基板。
附图说明
图1为一种示例性的显示基板的结构示意图；
图2为图1所示的显示基板中的像素单元的结构示意图；
图3为本申请实施例提供的一种显示基板的结构示意图；
图4为图3所示的显示基板中的像素单元的一种结构示意图；
图5为图4所示的像素单元沿A-A’方向上的截面结构示意图；
图6为图3所示的显示基板中的像素单元的另一种结构示意图；
图7为图6所示的像素单元沿B-B’方向上的截面结构示意图；
图8为图3所示的显示基板中的像素单元的又一种结构示意图；
图9为图8所示的像素单元沿C-C’方向上的截面结构示意图；
图10a至图10k为本申请实施例提供的显示基板在各个工艺阶段的中间结构示意图。
具体实施方式
为使本领域技术人员更好地理解本申请的技术方案，下面结合附图和具体实施方式对本申请作进一步详细描述。
除非另外定义，本申请使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本申请实施例中的所采用的晶体管可以为薄膜晶体管，也可以为场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的，其中的一者为源极时，另一者即为漏极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型，当采用P型晶体管时，栅极输入低电平信号时，源漏极导通；当采用N型晶体管时，栅极输入高电 平信号时，源漏极导通。在本申请实施例及之后的描述中，显示基板中的薄膜晶体管可以为P型晶体管，也可以为N型晶体管，具体类型可以根据实际需要进行设置。
图1为一种示例性的显示基板的结构示意图，如图1所示，该显示基板包括：基底101、位于基底101上交叉设置的栅极扫描线102和数据信号线103、及位于栅极扫描线102和数据信号线103限定区域中的像素单元104。图2为图1所示的显示基板中的像素单元的结构示意图，如图2所示，该像素单元104具有像素显示区及设置于像素显示区一侧的驱动器件区。其中，驱动器件区可以位于像素显示区的上侧，也可以位于像素显示区的下侧，在本申请实施例及之后的描述中将以驱动器件区在像素显示区的下侧为例进行说明。像素单元104包括：设置于驱动器件区的多个薄膜晶体管105。为了便于展示，图2中仅示出了其中的一个薄膜晶体管105的结构，其他薄膜晶体管105的结构与其类似，将不再进行详细描述。
如图2所示，该薄膜晶体管105包括：位于所述基底101上的遮光层1051、位于遮光层1051背离基底101一侧的半导体层1052。栅极扫描线102可以沿着水平方向(即图2所示的第一方向)延伸，并贯穿驱动器件区，同时，半导体层1052可以沿着垂直方向(即如图2所示的第二方向)延伸，半导体层1052的长度方向(即图2所示的第二方向)与栅极扫描线102的延伸方向(即图2所示的第一方向)垂直相交，半导体层1052与栅极扫描线102交叠的部分形成沟道1052a，并且栅极扫描线102与半导体层1052交叠的部分可以用作薄膜晶体管105的栅极1053。源极1054和漏极1055位于栅极1053背离基底101的一侧，可以理解的是，在薄膜晶体管105中相邻的两个导电层中，还是设置有其他绝缘层，例如缓冲层、栅极绝缘层、层间绝缘层、平坦化层、钝化层等，其在图2中均未示出。源极1054和漏极1055分别通过贯穿其与半导体层1052之间的绝缘层的过孔与半导体层1052的两 端电连接。
继续参照图2，显示基板中还包括：位于漏极1055背离基底101一侧的像素电极106，薄膜晶体管105的源极1054可以与像素电极106电连接。在实际应用中，栅极扫描线102传输的栅极扫描信号可以传输至薄膜晶体管105的栅极1053，以控制源极1054和漏极1055导通，使得数据信号线103上的数据信号传输至像素电极106，并且在公共电极(图中未示出)传输的公共信号的配合下，控制液晶层中的液晶分子偏转，使得背光单元中的光线由液晶层透过，以实现显示功能。
同时，遮光层1051可以对半导体层102的沟道1052a进行遮挡，以防止由基底101方向入射的光线照射至半导体层102的沟道1052a，从而提高薄膜晶体管105的稳定性，遮光层1051的面积取决于实际氧化物特性稳定的需求，其占用面积通常较大。
显示基板在与彩膜基板、背光单元等组件构成显示面板时，需要利用黑矩阵(black matrix，BM)对显示基板中的栅极扫描线102、数据信号线103、薄膜晶体管105等器件进行遮挡，以避免对背光单元的光线造成遮挡。在实际应用中，栅极扫描线102和数据信号线103可以采用更细的线宽来减少其所占用的面积，但是薄膜晶体管105所占用的面积依然较大，例如在16寸像素单元中，如图2所示，薄膜晶体管105在第二方向上的总长度为21微米，在第一方向上的总长度为相邻的两条数据信号线103之间的长度，这样，需要使用较大面积的黑矩阵对薄膜晶体管105进行遮挡，减小了像素单元中的有效显示面积，因此容易导致显示基板中的像素开口率下降，从而造成透光率降低，影响显示基板的显示效果。
为了至少解决上述的技术问题之一，本申请实施例提供了一种显示基板及显示装置，下面将结合附图及具体实施方式对本申请实施例提供的显示基板及显示装置进行进一步详细描述。
第一方面，本申请实施例提供了一种显示基板，图3为本申请实施例提供的一种显示基板的结构示意图，如图3所示，显示基板包括：基底101、位于基底101上交叉设置的栅极扫描线102和数据信号线103、及位于栅极扫描线102和数据信号线103限定区域中的像素单元104。
图4为图3所示的显示基板中的像素单元的一种结构示意图，图5为图4所示的像素单元沿A-A’方向上的一种截面结构示意图，如图4和图5所示，像素单元104具有像素显示区及设置于像素显示区一侧的驱动器件区；栅极扫描线102贯穿驱动器件区，且栅极扫描线102的部分区域向像素显示区弯折形成弯折部102a；像素单元104包括：设置于驱动器件区的多个薄膜晶体管105；薄膜晶体管105包括：位于基底101上的半导体层1052；弯折部102a的长度方向与半导体层1052的长度方向相交，且弯折部102a在基底101上的正投影与半导体层1052在基底101上的正投影至少部分交叠；半导体层1052与弯折部102a交叠的部分形成沟道1052a；弯折部102a与半导体层1052交叠的部分用作薄膜晶体管105的栅极1053。
基底101可以采用玻璃等刚性材料制成，可以提高基底101对其上的其他膜层的承载能力。当然，基底101还可以采用聚酰亚胺(polyimide，PI)等柔性材料制成，可以提高金属氧化物薄膜晶体管整体的抗弯折、抗拉伸性能，避免在弯折、拉伸、扭曲过程中产生的应力使得基底101发生断裂，造成断路不良。在实际应用中，可以根据实际需要，合理选择基底101的材料，以保证金属氧化物薄膜晶体管具有良好的性能。
栅极1053与栅极扫描线102为一体成型结构，并且栅极1053为栅极扫描线102的一部分，可以采用金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铂(Pt)、钯(Pd)、铝(Al)、钼(Mo)以及铬(Cr)中的至少一种材料制成，其可以形成由单一材料制成的单层结构，例如，栅极扫描线102为铝(Al)构成的单层结构，当然，其也可以形成有多重不同材料制成的多层结构，例如，钼(Mo)、铝(Al)、 钼(Mo)构成的三层结构。栅极扫描线102可以贯穿驱动器件区，以向驱动器件区的薄膜晶体管提供栅极扫描信号。
数据信号线103可以采用金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铂(Pt)、钯(Pd)、铝(Al)、钼(Mo)以及铬(Cr)中的至少一种材料制成，其可以形成由单一材料制成的单层结构，例如，栅极扫描线102为铝(Al)构成的单层结构，当然，其也可以形成有多重不同材料制成的多层结构，例如，钼(Mo)、铝(Al)、钼(Mo)构成的三层结构。数据信号线103可以贯穿驱动器件区，以向驱动器件区的薄膜晶体管提供数据信号。
半导体层1052可以采用铟镓锌氧化物(IGZO)，铟镓锡氧化物(IGTO)，铟锌氧化物(IZO)，铟锡氧化物(ITO)以及铟锡锌氧化物(ITZO)中的至少一种材料制成，其均为具有较高迁移率的金属氧化物，以保证金属氧化物薄膜晶体管整体具有较高的迁移率。半导体层1052的沟道1052a可以设置于其中心区域。半导体层1052的沟道1052a可以在栅极1053输入的栅极扫描信号的驱动下导通，以传输数据信号线103输入的数据信号。
本申请实施例提供的显示基板中，栅极扫描线102总体可以沿着水平方向(即图4所示的第一方向)延伸，数据信号线103可以沿着垂直方向(即图4所示的第二方向)延伸，其中栅极扫描线102的部分区域向像素显示区方向(即图4所示的第三方向)进行弯折形成弯折部102a，所形成的弯折部102a图4所示的第三方向延伸，第三方向即为弯折部102a的长度方向，其长度方向与水平方向呈一定夹角，相应地，半导体层1052可以沿着图4所示的第四方向延伸，第四方向即为半导体层1052的长度方向。半导体层1052的长度方向与弯折部102a的长度方向相交，其中，半导体层1052与弯折部102a交叠的部分形成沟道1052a，弯折部102a与半导体层1052交叠的部分用作薄膜晶体管105的栅极1053。这样，薄膜晶体管105的栅极1053及沟道1052a均可以向像素显示区方向靠近，因此可以减少薄膜晶体管105整体 在第二方向上的总长度，例如图4所示的显示基板中，薄膜晶体管105在第二方向上的总长度可以由原来的21微米减少为16微米，可见，薄膜晶体管105所占用的面积可以降低为原来的16/21，可以不必采用较大面积的黑矩阵对薄膜晶体管105进行遮挡，增大了像素单元中的有效显示面积，从而可以提高显示基板的像素开口率，提升显示基板的透光率，进而提升显示基板的显示效果。
在此需要说明的是，第三方向与第一方向或第二方向之间的夹角仅为示例性的，其角度是可以根据实际需要进行设置的。同样地，第四方向与第一方向或第二方向之间的夹角也仅为示例性的，其角度也是可以根据实际需要进行设置的。
在一些实施例中，弯折部102a的长度方向与栅极扫描线102的延伸方向之间的夹角为30度至60度。
弯折部102a可以以一定的角度向像素显示区进行弯折，具体地其弯折角度可以为30度至60度，以保证所形成的栅极1053及沟道1052a均可以向像素显示区方向靠近，因此可以减少薄膜晶体管105整体在第二方向上的总长度，使得薄膜晶体管105所占用的面积可以明显减少，可以不必采用较大面积的黑矩阵对薄膜晶体管105进行遮挡，增大了像素单元中的有效显示面积，从而可以提高显示基板的像素开口率，提升显示基板的透光率，进而提升显示基板的显示效果。在此需要说明的是，该弯折角度不可以过小，若弯折的角度过小，所形成的栅极1053箱像素显示区方向靠近的距离也较小，不能起到明显减少薄膜晶体管105整体在第二方向上的总长度的作用。优选地，弯折部102a的弯折角度具体可以为45度，在提高显示基板的像素开口率的同时，降低栅极扫描线102的工艺难度，节约制备成本。
在一些实施例中，弯折部102a的长度方向与半导体层1052的长度方向之间的夹角为60度至90度。
弯折部102a与半导体层1052可以至少部分交叠，并且二者的长度方向之间的夹角可以为60度至90度。当弯折部102a与沟道1052a长度方向之间的夹角较小时，例如60度，可以增大弯折部102a与半导体层1052之间的交叠面积，从而可以提高半导体层1052中的沟道1052a的长度及宽度，以提高薄膜晶体管105的迁移率。当弯折部102a与沟道1052a之间的夹角较大时，例如90度，在制备过程中，可以降低制备工艺难度，节约制备成本。例如，弯折部102a与半导体层1052的长度方向之间的夹角可以为90度。
在一些实施例中，半导体层1052还包括：分别设置于沟道1052a两端的源极1054和漏极1055；源极1054和漏极1055均经过导体化形成。
在实际应用中，可以通过重掺杂的方式，使得半导体层1052两端的离子浓度大于中心的沟道1052的离子浓度，这样半导体层1052的两端可以导体化，以形成源极1054和漏极1055。具体地，可以采用氢气(H 2)或氦气(He)加氩气(Ar)等离子气体对半导体层1052的中心沟道1052所在区域进行等离子处理。由于源极1054和漏极1055由半导体层1052的两端直接导体化形成，可以不必采用单独的金属层来制备薄膜晶体管105的源极1054和漏极1055，以减少薄膜晶体管105所占用的面积，从而可以提高显示基板的像素开口率，提升显示基板的透光率，进而提升显示产品的显示性能。另一方面，由于不必采用单独的金属层来制备薄膜晶体管105的源极1054和漏极1055，可以减小薄膜晶体管105中膜层的数量，从而降低薄膜晶体管105的厚度，同时可以减少单独形成源极1054和漏极1055的工艺步骤，以节约工艺成本。
在一些实施例中，如图5所示，显示基板还包括：位于源极1054和漏极1055背离基底101一侧的层间绝缘层107；漏极1055通过贯穿层间绝缘层107的过孔与数据信号线103电连接。
层间绝缘层107可以对薄膜晶体管的源极1054和漏极1055及其上方的 其他膜层之间短路，从而提升薄膜晶体管的稳定性。层间绝缘层107可以采用氮化硅(SiN)、氧化硅(SiO 2)中的至少一种材料制成，其可以形成由单一材料制成的单层结构，也可以形成由多种不同材料制成的多层结构。漏极1055可以通过贯穿层间绝缘层107的过孔与数据信号线103电连接，在栅极1052输入栅极扫描信号时，源极1054和漏极1055导通，数据信号线103传输的数据信号可以通过漏极1055传输至源极1054，以实现数据信号的传输。
在一些实施例中，如图5所示，显示基板还包括：位于层间绝缘层107上沿着背离基底101方向依次设置的第一钝化层108、第二钝化层109及像素电极106；源极1054通过贯穿层间绝缘层107、第一钝化层108和第二钝化层109的过孔与像素电极106电连接。
第一钝化层108和第二钝化层109均可以采用氮化硅(SiN)、氧化硅(SiO 2)中的至少一种材料制成，其可以形成由单一材料制成的单层结构，也可以形成由多种不同材料制成的多层结构。像素电极106可以采用铟锡氧化物(ITO)等透明导电材料，以避免像素电极106对光线的遮挡，提高显示基板整体的透光率。源极1054可以通过贯穿层间绝缘层107、第一钝化层108和第二钝化层109的过孔与像素电极106电连接，源极1054与漏极1055导通后，可以使得数据信号线103上的数据信号传输至像素电极106，以实现数据信号的传输。在本申请实施例中，第一钝化层108和第二钝化层109之间未设置其他膜层(例如平坦化层等)，可以不必使得过孔贯穿过多的膜层，以减小过孔的尺寸，因此可以减少薄膜晶体管105的尺寸及其所占用的面积，从而可以提高显示基板的像素开口率，提升显示基板的透光率，进而提升显示产品的显示性能。
在一些实施例中，如图5所示，显示基板还包括：位于第一钝化层108和第二钝化层109之间的公共电极110；公共电极110在基底101上的正投影与像素电极106在基底101上的正投影至少部分交叠。
公共电极110可以采用铟锡氧化物(ITO)等透明导电材料，以避免公共电极110对光线的遮挡，提高显示基板整体的透光率。在实际应用中，栅极扫描线102传输的栅极扫描信号可以传输至薄膜晶体管105的栅极1053，以控制源极1054和漏极1055导通，使得数据信号线103上的数据信号传输至像素电极106，并且在公共电极110传输的公共信号的配合下，像素电极106与公共电极110之间形成驱动电场，控制液晶层中的液晶分子偏转，使得背光模组中的光线由液晶层透过，以实现显示功能。
在一些实施例中，图6为图3所示的显示基板中的像素单元的另一种结构示意图，图7为图6所示的像素单元沿B-B’方向上的一种截面结构示意图，如图6和图7所示，显示基板还包括：位于第一钝化层108和第二钝化层109之间的平坦化层111；源极1054通过贯穿层间绝缘层107、第一钝化层108、平坦化层111和第二钝化层109的过孔与像素电极106电连接。
平坦化层111可以采用亚克力、树脂、聚酰亚胺或苯并环丁烯等有机材料制成，具体可以根据实际需要进行选择。在第一钝化层108和第二钝化层109之间设置有平坦化层111，平坦化层111可以对薄膜晶体管105所形成的膜层的表面进行平坦化处理，使得薄膜晶体管105之上的其他膜层可以具有较为平整的贴合平面，保证贴合的平整度。并且，由于平坦化层111的存在，可以使得薄膜晶体管105中的源极1054与其他的导电膜层之间的距离增大，避免源极1054或漏极1055与其上的其他导电膜层之间产生寄生电容。
在一些实施例中，图8为图3所示的显示基板中的像素单元的又一种结构示意图，图9为图8所示的像素单元沿C-C’方向上的截面结构示意图，如图8和图9所示，显示基板还包括：位于第二钝化层109背离基底101一侧的公共电极110；公共电极110在基底101上的正投影与像素电极106在基底101上的正投影至少部分交叠。
图9所示的结构与图5及图7所示的结构不同之处在于，公共电极110 可以设置在第二钝化层109背离基底101的一侧。在实际应用中，公共电极110通常为整面设置，在图5和图7所示的结构中，由于公共电极110设置在像素电极106靠近基底101的位置，在像素电极106与薄膜晶体管105的源极1054连接时需要打过孔，使得过孔贯穿公共电极110。在图9所示的结构中，公共电极110较像素电极106更远离基底101，像素电极106与源极1054之间的过孔可以不必贯穿公共电极110，以减小过孔的尺寸，因此可以减少薄膜晶体管105的尺寸及其所占用的面积，从而可以提高显示基板的像素开口率，提升显示基板的透光率，进而提升显示产品的显示性能。
在一些实施例中，如图4至图9所示，显示基板还包括：位于基底101与沟道1052a之间的遮光层1051；沟道1052a在基底101上的正投影落在遮光层1051在基底101上的正投影内。
遮光层1051可以采用金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铂(Pt)、钯(Pd)、铝(Al)、钼(Mo)以及铬(Cr)中的至少一种材料制成，其可以形成由单一材料制成的单层结构，例如，遮光层1051为铝(Al)构成的单层结构，当然，其也可以形成有多重不同材料制成的多层结构，例如，钼(Mo)、铝(Al)、钼(Mo)构成的三层结构。遮光层1051可以对半导体层102的沟道1052a进行遮挡，以防止由基底101方向入射的光线照射至半导体层102的沟道1052a，从而提高薄膜晶体管105的稳定性。
图10a至图10k为本申请实施例提供的显示基板在各个工艺阶段的中间结构示意图，下面将结合附图，以图6和图7所示的显示基板的结构为例，对本申请实施例提供的显示基板的制备工艺进行进一步详细描述。
如图10a所示，在基底101上形成第一金属层，并对第一金属层进行图案化，形成薄膜晶体管105的遮光层1051。
如图10b所示，在遮光层1051上形成第一绝缘层，第一绝缘层具体可以为作缓冲层，该缓冲层可以采用氮化硅、氧化硅、氮氧化硅中的至少一种 材料制成。
如图10c所示，在第一绝缘层上形成半导体层1052，该半导体层1052可以采用铟镓锌氧化物(IGZO)，铟镓锡氧化物(IGTO)，铟锌氧化物(IZO)，铟锡氧化物(ITO)以及铟锡锌氧化物(ITZO)中的至少一种材料制成。可以将半导体层1052划分为沟道区、源极区和漏极区。
如图10d所示，在半导体层1052上形成第二绝缘层，第二绝缘层具体可以为栅极绝缘层，该栅极绝缘层可以采用氮化硅、氧化硅、氮氧化硅中的至少一种材料制成。在第二绝缘层上形成第二金属层，第二金属层可以为栅极扫描线102和薄膜晶体管105的栅极1053。
如图10e所示，利用等离子工艺气体，以栅极1053为掩膜板，对半导体层1052中未被栅极1053遮挡的部分，即源极区和漏极区进行导体化处理，使得半导体层1052的源极区和漏极区导体化，以形成薄膜晶体管105的源极1054和漏极1055。
如图10f所示，在第二金属层上形成第三绝缘层，第三绝缘层具体可以为层间绝缘层107，该层间绝缘层107可以采用氮化硅、氧化硅、氮氧化硅中的至少一种材料制成。对第三绝缘层进行图案化处理，以露出半导体层1052中的源极1054和漏极1055。
如图10g所示，在第三绝缘层上露出漏极1055的位置形成第三金属层，第三金属层可以为数据信号线103。数据信号线103可以与漏极1055电连接，以将数据信号输入至漏极1055。
如图10h所示，在第三金属层上形成第四绝缘层、第五绝缘层。第四绝缘层具体可以为第一钝化层108，第五绝缘层具体可以为平坦化层111。该第一钝化层108可以采用氮化硅、氧化硅、氮氧化硅中的至少一种材料制成，该平坦化层111可以采用亚克力、树脂、聚酰亚胺或苯并环丁烯等有机材料制成。
如图10i所示，在第五绝缘层上形成公共电极110，公共电极110可以采用铟锡氧化物(ITO)等透明材料制成。
如图10j所示，在公共电极110上形成第六绝缘层，第六绝缘层具体可以为第二钝化层109，该第二钝化层109可以采用氮化硅、氧化硅、氮氧化硅中的至少一种材料制成。
如图10k所示，在第六绝缘层上形成像素电极106，使得像素电极106通过贯穿层间绝缘层、第一钝化层108和第二钝化层109的过孔与源极1054电连接。
第二方面，本申请实施例提供了一种显示装置，该显示装置包括如上述任一实施例提供的显示基板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，其实现原理及有益效果与上述的显示基板的实现原理及有益效果相同，在此不再进行赘述。
可以理解的是，以上实施方式仅仅是为了说明本申请的原理而采用的示例性实施方式，然而本申请并不局限于此。对于本领域内的普通技术人员而言，在不脱离本申请的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本申请的保护范围。

Claims (12)

  1. 一种显示基板，其中，所述显示基板包括：基底、位于所述基底上交叉设置的栅极扫描线和数据信号线、及位于所述栅极扫描线和所述数据信号线限定区域中的像素单元；
    所述像素单元具有像素显示区及设置于所述像素显示区一侧的驱动器件区；所述栅极扫描线贯穿所述驱动器件区，且所述栅极扫描线的部分区域向所述像素显示区弯折形成弯折部；
    所述像素单元包括：设置于所述驱动器件区的多个薄膜晶体管；所述薄膜晶体管包括：位于所述基底上的半导体层；
    所述弯折部的长度方向与所述半导体层的长度方向相交，且所述弯折部在所述基底上的正投影与所述半导体层在所述基底上的正投影至少部分交叠；
    所述半导体层与所述弯折部交叠的部分形成沟道；所述弯折部与所述半导体层交叠的部分用作所述薄膜晶体管的栅极。
  2. 根据权利要求1所述的显示基板，其中，所述弯折部的长度方向与所述栅极扫描线的延伸方向之间的夹角为30度至60度。
  3. 根据权利要求2所述的显示基板，其中，所述弯折部的长度方向与所述半导体层的长度方向之间的夹角为60度至90度。
  4. 根据权利要求1所述的显示基板，其中，所述半导体层还包括：分别设置于所述沟道两端的源极和漏极；
    所述源极和所述漏极均经过导体化形成。
  5. 根据权利要求4所述的显示基板，其中，所述显示基板还包括：位于所述源极和所述漏极背离所述基底一侧的层间绝缘层；
    所述漏极通过贯穿所述层间绝缘层的过孔与所述数据信号线电连接。
  6. 根据权利要求5所述的显示基板，其中，所述显示基板还包括：位于所述层间绝缘层上沿着背离所述基底方向依次设置的第一钝化层、第二钝 化层及像素电极；
    所述源极通过贯穿所述层间绝缘层、所述第一钝化层和所述第二钝化层的过孔与所述像素电极电连接。
  7. 根据权利要求6所述的显示基板，其中，所述显示基板还包括：位于所述第一钝化层和所述第二钝化层之间的公共电极；
    所述公共电极在所述基底上的正投影与所述像素电极在所述基底上的正投影至少部分交叠。
  8. 根据权利要求6所述的显示基板，其中，所述显示基板还包括：位于所述第一钝化层和所述第二钝化层之间的平坦化层；
    所述源极通过贯穿所述层间绝缘层、所述第一钝化层、所述平坦化层和所述第二钝化层的过孔与所述像素电极电连接。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板还包括：位于所述平坦化层与所述第二钝化层之间的公共电极；
    所述公共电极在所述基底上的正投影与所述像素电极在所述公共电极在所述基底上的正投影至少部分交叠。
  10. 根据权利要求6或8所述的显示基板，其中，所述显示基板还包括：位于所述第二钝化层背离所述基底一侧的公共电极；
    所述公共电极在所述基底上的正投影与所述像素电极在所述基底上的正投影至少部分交叠。
  11. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：位于所述基底与所述沟道之间的遮光层；
    所述沟道在所述基底上的正投影落在所述遮光层在所述基底上的正投影内。
  12. 一种显示装置，其中，所述显示装置包括如权利要求1至11任一项所述的显示基板。
PCT/CN2022/090169 2022-04-29 2022-04-29 显示基板及显示装置 WO2023206328A1 (zh)

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