WO2023206295A1 - 阵列基板及其制作方法、液晶显示面板和显示装置 - Google Patents

阵列基板及其制作方法、液晶显示面板和显示装置 Download PDF

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Publication number
WO2023206295A1
WO2023206295A1 PCT/CN2022/090087 CN2022090087W WO2023206295A1 WO 2023206295 A1 WO2023206295 A1 WO 2023206295A1 CN 2022090087 W CN2022090087 W CN 2022090087W WO 2023206295 A1 WO2023206295 A1 WO 2023206295A1
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Prior art keywords
film transistor
thin film
electrode
line
orthographic projection
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PCT/CN2022/090087
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English (en)
French (fr)
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肖锋
八木敏文
罗艳梅
杨桂冬
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京东方科技集团股份有限公司
成都京东方显示科技有限公司
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Priority to CN202280001008.2A priority Critical patent/CN117321499A/zh
Priority to PCT/CN2022/090087 priority patent/WO2023206295A1/zh
Publication of WO2023206295A1 publication Critical patent/WO2023206295A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to the field of display devices, and in particular to an array substrate and a manufacturing method thereof, a liquid crystal display panel and a display device.
  • LCD Liquid crystal display
  • parasitic capacitances between gate lines and some structures there are parasitic capacitances between gate lines and some structures.
  • some pixel electrodes are connected to multiple thin film transistors, and the connection lines between these thin film transistors and pixel electrodes have parasitic capacitances between the gate lines. These parasitic capacitances will have adverse effects on the LCD panel and are not conducive to improving the display effect of the LCD panel.
  • Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, a liquid crystal display panel and a display device, which can reduce parasitic capacitance and help improve display effects.
  • the technical solutions are as follows:
  • an embodiment of the present disclosure provides an array substrate, which includes a base substrate, a signal line, and a plurality of first pixel units;
  • the signal line is located on the bearing surface of the base substrate and includes a gate line, a data line and a discharge line that are insulated from each other.
  • the gate line extends along a first direction
  • the data line extends along a second direction
  • the discharge line The wires extend along a third direction, both the first direction and the third direction intersect the second direction, and the gate lines and the data lines intersect with each other to define a plurality of sub-pixel regions;
  • the first pixel unit includes a first pixel electrode, a first thin film transistor, a second thin film transistor and a first connection line. A plurality of the first pixel electrodes are respectively located in the plurality of sub-pixel regions.
  • the first thin film The orthographic projections of the transistor and the second thin film transistor on the carrying surface at least partially overlap with the orthographic projection of the gate line on the carrying surface;
  • the control electrode of the first thin film transistor and the control electrode of the second thin film transistor are both electrically connected to the gate line, and the first electrode of the first thin film transistor is electrically connected to the data line.
  • the second electrode of the first thin film transistor and the first electrode of the second thin film transistor are both electrically connected to the first pixel electrode through the first connection line.
  • the second electrode of the second thin film transistor is connected to the first electrode of the second thin film transistor.
  • the above-mentioned discharge wires are electrically connected.
  • the orthographic projection of the first connection line on the bearing surface is located outside the orthographic projection of the grid line on the bearing surface; or,
  • the first connecting line includes connected overlapping segments and connecting segments
  • the orthographic projection of the overlapping section on the bearing surface is located within the orthographic projection of the grid line on the carrying surface, and the overlapping section is perpendicular to the first direction, and the overlapping section is in contact with the first film.
  • the second electrode of the transistor is electrically connected to the first electrode of the second thin film transistor;
  • the orthographic projection of the connecting section on the carrying surface is located outside the orthographic projection of the grid line on the carrying surface, and the connecting section is electrically connected to the first pixel electrode.
  • the first connection line is in the same layer as at least one of the second electrode of the first thin film transistor, the first electrode of the second thin film transistor, the data line, and the discharge line.
  • the active layer of the first thin film transistor is connected to the active layer of the second thin film transistor, and the second electrode of the first thin film transistor is multiplexed as the first electrode of the second thin film transistor.
  • the arrangement direction of the first pole and the second pole of the first thin film transistor is the same as the arrangement direction of the first pole and the second pole of the second thin film transistor.
  • the first electrode and the second electrode of the first thin film transistor are arranged along the first direction;
  • the first pixel unit also includes a second connection line.
  • the first electrode of the first thin film transistor is electrically connected to the data line through the second connection line.
  • the second connection line is on the carrying surface.
  • the orthographic projection of is located at least partially outside the orthographic projection of the grid line on the bearing surface.
  • the first electrode and the second electrode of the first thin film transistor are arranged along the second direction;
  • the first pixel unit also includes a third connection line.
  • the second electrode of the second thin film transistor is electrically connected to the discharge line through the third connection line.
  • the third connection line is on the bearing surface.
  • the orthographic projection of the grid line is located within the orthographic projection of the grid line on the bearing surface, or is at least partially located outside the orthographic projection of the grid line on the bearing surface.
  • the first electrode and the second electrode of the first thin film transistor are arranged along the second direction, and the first electrode and the second electrode of the second thin film transistor are arranged along the first direction.
  • the gate line includes a connected main body part and a branch part, an orthographic projection of the first thin film transistor on the carrying surface at least partially overlaps an orthographic projection of the main body part on the carrying surface, and the first thin film transistor is A control electrode of a thin film transistor is electrically connected to the main body;
  • the orthographic projection of the second thin film transistor on the carrying surface and the orthographic projection of the branch part on the carrying surface at least partially overlap, and the control electrode of the second thin film transistor is electrically connected to the branch part.
  • the gate lines include main gate lines and auxiliary gate lines;
  • the orthographic projection of the second thin film transistor on the carrying surface at least partially overlaps the orthographic projection of the auxiliary gate line on the carrying surface, and the control electrode of the second thin film transistor is electrically connected to the auxiliary gate line. .
  • the first pixel electrode includes a connected first part and a second part, the first part and the second part are arranged along the second direction, and in the first direction, the first part and said second part are mutually offset.
  • the array substrate further includes a plurality of second pixel units, the second pixel unit includes a second pixel electrode and a third thin film transistor, and the plurality of second pixel electrodes are located in the plurality of sub-pixel regions. , and in the second direction, the second pixel electrode and the first pixel electrode are alternately distributed;
  • the first electrode of the third thin film transistor is electrically connected to the data line
  • the second electrode of the third thin film transistor is electrically connected to the first pixel electrode
  • the control electrode of the third thin film transistor is electrically connected to the data line.
  • the gate lines are electrically connected.
  • the channel region of the first thin film transistor has a length of 4 ⁇ m to 5 ⁇ m and a width of 5 ⁇ m to 15 ⁇ m;
  • the channel region of the second thin film transistor has a length of 8 ⁇ m to 14 ⁇ m and a width of 3 ⁇ m to 4 ⁇ m;
  • the length and width of the channel region of the third thin film transistor are respectively the same as the length and width of the channel region of the first thin film transistor.
  • embodiments of the present disclosure also provide a method for manufacturing an array substrate, which method includes:
  • a grid line is formed on the bearing surface of the base substrate, and the grid line extends along the first direction;
  • a first thin film transistor and a second thin film transistor are formed on the bearing surface of the base substrate.
  • the orthographic projections of the first thin film transistor and the second thin film transistor on the bearing surface are aligned with the gate lines.
  • the orthographic projections of the carrying surface at least partially overlap, and the control electrode of the first thin film transistor and the control electrode of the second thin film transistor are both electrically connected to the gate line;
  • Data lines, discharge lines and first connection lines are formed on the bearing surface of the base substrate.
  • the data lines extend along the second direction
  • the discharge lines extend along the third direction
  • the second direction and the The third directions all intersect the first direction
  • the gate lines and the data lines cross each other to define a plurality of sub-pixel regions
  • the data lines are electrically connected to the first pole of the first thin film transistor, so
  • the discharge line is electrically connected to the second electrode of the second thin film transistor
  • the first connection line is electrically connected to the second electrode of the first thin film transistor and the first electrode of the second thin film transistor;
  • a plurality of first pixel electrodes are formed on the carrying surface of the base substrate.
  • the plurality of first pixel electrodes are respectively located in the plurality of sub-pixel regions.
  • the first pixel electrodes are electrically connected to the first connection lines. sexual connection to form a plurality of first pixel units on the carrying surface of the base substrate.
  • embodiments of the present disclosure also provide a liquid crystal display panel, which includes a color filter substrate, a liquid crystal layer, and an array substrate as described in the first aspect.
  • the color filter substrate is opposite to the array substrate.
  • the liquid crystal layer is located between the color filter substrate and the array substrate.
  • embodiments of the present disclosure further provide a display device, which includes a backlight source and the liquid crystal display panel described in the third aspect, where the backlight source is located on a side of the array substrate away from the color filter substrate.
  • the second electrode of the first thin film transistor and the first electrode of the second thin film transistor are both electrically connected to the first pixel electrode through the first connection line, so that There is no need to connect the second electrode of the first thin film transistor and the first electrode of the second thin film transistor to the first pixel electrode through a connecting line respectively, which can reduce the arrangement of one connecting line, thereby reducing the risk of overlapping of the connecting line and the gate line.
  • the total area reduces the parasitic capacitance, which is beneficial to improving the display effect of the liquid crystal display panel.
  • Figure 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • Figure 2 is an enlarged schematic diagram of the dotted line in Figure 1;
  • Figure 3 is an enlarged schematic diagram of the dotted line in Figure 2;
  • Figure 4 is a partially enlarged schematic diagram of Figure 3;
  • Figure 5 is a schematic diagram of alignment in a liquid crystal display panel provided by an embodiment of the present disclosure.
  • Figure 6 is an equivalent circuit diagram of a liquid crystal display panel provided by an embodiment of the present disclosure.
  • Figure 7 is a cross-sectional view at the dotted line M in Figure 4.
  • Figure 8 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • Figure 13 is a flow chart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a liquid crystal display panel provided by an embodiment of the present disclosure.
  • Words such as “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up”, “Down”, “Left”, “Right”, etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • the LCD panel has a certain viewing angle, and a relatively normal picture can be observed within the viewing angle range.
  • a problem of color distortion under different viewing angles especially at large viewing angles.
  • liquid crystal display panels in order to avoid the problem of color distortion in large viewing angles of liquid crystal display panels, liquid crystal display panels usually adopt a multi-domain vertical alignment (VA) display mode, and the pixel structure is a multi-domain pixel structure.
  • VA vertical alignment
  • the pixel structure is a multi-domain pixel structure.
  • discharge lines are provided.
  • some pixel electrodes are also connected to the discharge lines through thin film transistors.
  • this part of the pixel electrode is connected to at least two thin film transistors, and the two thin film transistors are connected to the pixels through connecting lines.
  • the electrodes are connected, resulting in a large overlap between the connecting line and the gate, resulting in a large parasitic capacitance, which affects the improvement of the display effect of the liquid crystal display panel.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate includes a base substrate 10 and signal lines 20 .
  • Figure 2 is an enlarged schematic diagram of the dotted line in Figure 1.
  • Figure 3 is an enlarged schematic diagram of the dotted line in Figure 2.
  • the array substrate also includes a plurality of pixel units, where the pixel units include pixel electrodes 30 and thin film transistors.
  • the base substrate 10 has two opposite surfaces, one of which is a bearing surface.
  • the signal lines 20 , the pixel electrodes 30 and the thin film transistors are all located on the bearing surface of the base substrate 10 .
  • What is referred to here as "located on the load-bearing surface of the substrate substrate 10" includes not only being directly distributed on the load-bearing surface and in direct contact with the load-bearing surface, but also including having other structures between it and the load-bearing surface and being separated by other structures. , there is no direct contact with the load-bearing surface.
  • the signal line 20 is located on the carrying surface of the base substrate 10 and includes gate lines 21 and data lines 22 that are insulated from each other.
  • the gate line 21 extends along the first direction X
  • the data line 22 extends along the second direction Y.
  • the first direction X and the second direction Y are both parallel to the bearing surface, and the first direction X and the second direction Y intersect.
  • the first direction X and the second direction Y are perpendicular to each other, or the first direction X and the second direction Y form an acute angle.
  • the multiple gate lines 21 , data lines 22 and pixel electrodes 30 may be multiple gate lines 21 , data lines 22 and pixel electrodes 30 .
  • the multiple gate lines 21 and the multiple data lines 22 define multiple sub-pixel areas on the bearing surface, and two pixel electrodes are distributed in each sub-pixel area. .
  • the plurality of pixel electrodes 30 include a first pixel electrode 31 and a second pixel electrode 32 .
  • a first pixel electrode 31 located in one sub-pixel region and a second pixel electrode 32 located in the other sub-pixel region are shown.
  • the first pixel electrode 31 is located on one side of the gate line 21
  • the second pixel electrode 32 is located on the other side of the gate line 21 .
  • the signal line 20 also includes a discharge line 23.
  • the discharge line 23 extends along a third direction Z.
  • the third direction Z is parallel to the bearing surface and intersects the second direction Y.
  • the third direction Z is perpendicular to the first direction X.
  • the third direction Z may also be at an acute angle to the first direction X.
  • FIG. 4 is a partially enlarged schematic diagram of FIG. 3 .
  • the thin film transistor includes a first thin film transistor T1 and a second thin film transistor T2.
  • the orthographic projections of the first thin film transistor T1 and the second thin film transistor T2 on the carrying surface at least partially overlap with the orthographic projection of the gate line 21 on the carrying surface.
  • the first thin film transistor T1 as an example, at least part of the overlap includes that the orthographic projection of the first thin film transistor T1 on the carrying surface is all located within the orthographic projection of the gate line 21 on the carrying surface, and also includes the orthographic projection of the first thin film transistor T1 on the carrying surface.
  • Part of the orthographic projection is located within the orthographic projection of the grid line 21 on the bearing surface, and the other part is located outside the orthographic projection of the grid line 21 on the bearing surface.
  • the orthographic projection of a part of the second electrode of the first thin film transistor T1 on the supporting surface is located outside the orthographic projection of the gate line 21 on the supporting surface
  • the orthographic projection of a part of the first electrode of the second thin film transistor T2 on the supporting surface is located outside the orthographic projection of the gate line 21 on the supporting surface.
  • the grid line 21 is outside the orthographic projection of the bearing surface.
  • the control electrode of the first thin film transistor T1 and the control electrode of the second thin film transistor T2 are both electrically connected to the gate line 21 .
  • the first electrode T11 of the first thin film transistor T1 is electrically connected to the data line 22 .
  • the second electrode T12 and the first electrode T21 of the second thin film transistor T2 are both electrically connected to the first pixel electrode 31 through the first connection line 41 , and the second electrode T22 of the second thin film transistor T2 is electrically connected to the discharge line 23 .
  • the first electrode of the thin film transistor is one of the source electrode and the drain electrode of the thin film transistor, and the second electrode of the thin film transistor is the other of the source electrode and the drain electrode of the thin film transistor.
  • the electrical connection referred to here refers to a cooperative relationship that can form an electrical path.
  • the control electrode of the first thin film transistor T1 is electrically connected to the gate line 21, which means that an electrical path can be formed between the control electrode of the first thin film transistor T1 and the gate line 21.
  • the electrical signal can Acting on the control electrode of the first thin film transistor T1.
  • the plurality of pixel units includes a plurality of first pixel units and a plurality of second pixel units.
  • the first pixel unit includes a first pixel electrode 31, a first thin film transistor T1, a second thin film transistor T2, and a first connection line 41;
  • the second pixel unit includes a second pixel electrode 32 and a third thin film transistor T3.
  • the first pixel electrodes 31 of the first pixel unit and the second pixel electrodes 32 of the second pixel unit are alternately distributed.
  • the second electrode T12 of the first thin film transistor T1 and the first electrode T21 of the second thin film transistor T2 are connected to the first pixel through the first connection line 41.
  • the electrode 31 is electrically connected, so there is no need to connect the second electrode T12 of the first thin film transistor T1 and the first electrode T21 of the second thin film transistor T2 to the first pixel electrode 31 through connecting lines respectively, which can reduce the layout of one connecting line. , thereby reducing the total area of overlap between the connecting line and the gate line 21, reducing the parasitic capacitance, which is beneficial to improving the display effect of the liquid crystal display panel.
  • the first connection line 41 partially overlaps with the grid line 21 , that is, the orthographic projection of the first connection line 41 on the bearing surface is located in the orthographic projection of the grid line 21 on the bearing surface.
  • the first connection line 41 includes connected overlapping sections 411 and connecting sections 412 .
  • the orthographic projection of the overlapping section 411 on the carrying surface is located within the orthographic projection of the grid line 21 on the carrying surface, and the overlapping section 411 is perpendicular to the first direction X.
  • the overlapping section 411 is connected to the second electrode T12 of the first thin film transistor T1 and the first electrode T21 of the second thin film transistor T2.
  • the orthographic projection of the connecting section 412 on the carrying surface is located outside the orthographic projection of the gate line 21 on the carrying surface, and the connecting section 412 is connected to the first pixel electrode 31 .
  • the overlapping section 411 is strip-shaped, and the overlapping section 411 is perpendicular to the first direction X, that is, the length direction or width direction of the overlapping section 411 is perpendicular to the first direction X.
  • the orthographic projection of the overlapping section 411 on the carrying surface overlaps with the orthographic projection of the grid line 21 on the carrying surface, which will generate parasitic capacitance.
  • the orthographic projection of the first connecting line 41 on the bearing surface may also be located outside the orthographic projection of the grid line 21 on the bearing surface, which is equivalent to the length of the overlapping section 411 being 0.
  • the first connection line 41 is in the same layer as at least one of the second electrode T12 of the first thin film transistor T1 , the first electrode T21 of the second thin film transistor T2 , the data line 22 and the discharge line 23 .
  • the same layer referred to here includes but is not limited to being located on the same surface of the same structure, formed in the same process step, and formed from the same film layer.
  • the first connection line 41 and the second electrode T12 of the first thin film transistor T1 are in the same layer, which may mean that the first connection line 41 and the second electrode T12 of the first thin film transistor T1 are formed in the same patterning process.
  • Using the same layer arrangement can save the number of patterning processes and help reduce the total thickness of the array substrate.
  • At least two of the first connection line 41 , the second electrode T12 of the first thin film transistor T1 , the first electrode T21 of the second thin film transistor T2 , the data line 22 , and the discharge line 23 are in the same layer.
  • the first connection line 41, the second electrode T12 of the first thin film transistor T1, the first electrode T21 of the second thin film transistor T2, the data line 22, and the discharge line 23 are all in the same layer and are made of the same film layer. Formed through the same patterning process.
  • Thin film transistors usually include an active layer, a control electrode, a source electrode and a drain electrode.
  • the active layer T10 of the first thin film transistor T1 and the active layer T20 of the second thin film transistor T2 are connected.
  • the second electrode T12 of the first thin film transistor T1 is multiplexed as the first electrode T21 of the second thin film transistor T2. That is, the active layers of the two thin film transistors are a whole, and the second electrode T12 of the first thin film transistor T1 and the first electrode T21 of the second thin film transistor T2 are a whole.
  • the second electrode T12 of the first thin film transistor T1 and the first electrode T21 of the second thin film transistor T2 are integrated to further reduce the parasitic capacitance between the first thin film transistor T1 and the gate line 21, thereby further improving the display effect of the liquid crystal display panel.
  • the area where the picture is displayed is generally the area where the pixel electrode is located, and the area where the thin film transistor is located does not display.
  • the second electrode T12 of the first thin film transistor T1 is multiplexed as the second electrode of the second thin film transistor T2.
  • the first electrode T21 can also reduce the area occupied by the third thin film transistor T3 and the first thin film transistor T1 on the base substrate 10, leaving a larger space for arranging the pixel electrode, which is beneficial to improving the aperture ratio of the pixel.
  • Spacers are usually provided in liquid crystal display panels.
  • the spacers and thin film transistors are located in the area outside the pixel electrodes, which reduces the area occupied by the thin film transistors on the base substrate 10 and makes the spacers larger. Arrange the space to facilitate the installation of spacers.
  • the first thin film transistor T1 and the second thin film transistor T2 are arranged between the data line 22 and the discharge line 23, and the spacer may be arranged on a side of the discharge line 23 away from the second thin film transistor T2.
  • the array substrate further includes spacers 40 .
  • the spacer 40 is located on the side of the discharge line 23 away from the thin film transistor, and the spacer 40 is distributed on both sides of the gate line 21 .
  • the spacers 40 can increase the height of a local area, so that the area above the grid line 21 between the two spacers 40 is recessed, which can provide space for arranging spacers.
  • the spacers 40 can be used to remove spacers from the spacers.
  • the two sides of the spacer provide support and limitation to prevent the spacer from deforming to both sides of the grid line 21 .
  • the cushion block 40 may have a single-layer structure or a multi-layer structure.
  • each layer in the cushion block 40 can be on the same layer as other structures.
  • a part of the spacer 40 can be in the same layer as the active layer.
  • a part of the material can remain in the area where the spacer 40 needs to be formed to form a part of the spacer 40 .
  • the other part of the spacer 40 can be in the same layer as the first electrode, the second electrode, and the first connection line 41 of the thin film transistor.
  • the spacer 40 can be formed in the area where the spacer 40 needs to be formed. A portion of the material remains to form a part of the cushion block 40 . In this way, by forming the residue of material in the same area, the thickness of the area gradually increases to form the cushion block 40 .
  • the arrangement direction of the first electrode T11 and the second electrode T12 of the first thin film transistor T1 is the same as the arrangement direction of the first electrode T21 and the second electrode T22 of the second thin film transistor T2 .
  • the direction of the thin film transistor refers to the arrangement direction of the first electrode and the second electrode of the thin film transistor.
  • the thin film transistor with different directions referred to here refers to the thin film transistor with the first electrode and the second electrode arranged in different directions.
  • the direction of the first thin film transistor T1 is adjusted The direction is the same as that of the second thin film transistor T2, which is beneficial to reducing the characteristic difference between the first thin film transistor T1 and the second thin film transistor T2.
  • the first pole T11 and the second pole T12 of the first thin film transistor T1 are arranged along the first direction X.
  • the directions of the first thin film transistor T1 and the second thin film transistor T2 are both along the first direction X, which is beneficial to the arrangement of the second pole T22 of the second thin film transistor T2.
  • the first thin film transistor T1 and the second thin film transistor T2 are arranged between the data line 22 and the discharge line 23.
  • the second electrode T22 of the second thin film transistor T2 needs to be connected to the discharge line 23.
  • the direction is consistent with the arrangement direction of the two electrodes of the second thin film transistor T2, and the first electrode T11 and the second electrode T12 of the first thin film transistor T1 are arranged along the first direction X, so the second electrode T22 of the second thin film transistor T2 is aligned with
  • the distance between the discharge lines 23 can be set very small, which is beneficial to reducing the parasitic capacitance generated between the second electrode T22 of the second thin film transistor T2 and the gate line 21 .
  • a part of the discharge line 23 is reused as the second electrode T22 of the second thin film transistor T2, which can further reduce the parasitic capacitance and help improve the display effect of the liquid crystal display panel.
  • the first pixel unit of the array substrate also includes a second connection line 42 .
  • the first electrode T11 of the first thin film transistor T1 is electrically connected to the data line 22 through the second connection line 42 .
  • the orthographic projection of the second connecting line 42 on the carrying surface is at least partially located outside the orthographic projection of the grid line 21 on the carrying surface.
  • connection line 42 Since at least part of the second connection line 42 does not overlap with the grid line 21 , that is, at least part of the orthographic projection of the second connection line 42 on the bearing surface is located outside the orthographic projection of the grid line 21 on the bearing surface, thus reducing the second The parasitic capacitance between the connection line 42 and the gate line 21 is conducive to further improving the display effect of the liquid crystal display panel.
  • the second connection line 42 does not overlap with the gate line 21 , that is, the orthographic projection of the second connection line 42 on the load-bearing surface is entirely outside the orthographic projection of the gate line 21 on the load-bearing surface, so as to further reduce the parasitic capacitance.
  • the second connection line 42 may be on the same layer as the first electrode T11 of the first thin film transistor T1 to save processes and also help reduce the thickness of the base substrate.
  • the second pixel unit includes a second pixel electrode 32 and a third thin film transistor T3.
  • the first pixel electrode 31 and the second pixel electrode 32 are respectively located on both sides of the gate line 21 .
  • the third thin film transistor T3 connects the second pixel electrode 32 and the data line 22 .
  • the first electrode T31 of the third thin film transistor T3 is electrically connected to the data line 22
  • the second electrode T32 of the third thin film transistor T3 is electrically connected to the first pixel electrode 31
  • the control electrode of the third thin film transistor T3 is electrically connected to the gate line 21 Electrical connection.
  • the third thin film transistor T3 is used to control the connection between the second pixel electrode 32 and the data line 22 .
  • the second pixel electrode 32 and the first pixel electrode 31 are electrically connected to the data line 22 through a thin film transistor respectively
  • the first pixel electrode 31 is also electrically connected to the discharge line 23 through the second thin film transistor T2
  • the discharge line 23 is connected to A signal line that can provide a voltage close to the common voltage, for example, a signal line that can provide a voltage of 7.7V.
  • There is a difference in voltage between the common electrodes Combined with the difference in orientation of liquid crystal molecules in the areas corresponding to the second pixel electrode 32 and the first pixel electrode 31 in the liquid crystal display panel, a multi-domain liquid crystal display effect can be obtained.
  • FIG. 5 is a schematic diagram of alignment in a liquid crystal display panel provided by an embodiment of the present disclosure.
  • the black arrow in the figure indicates the alignment direction of the array substrate in the liquid crystal display panel
  • the white arrow indicates the alignment direction of the color filter substrate in the liquid crystal display panel
  • the ellipse indicates the liquid crystal molecules.
  • the liquid crystal molecules in the areas where the first pixel electrode 31 and the second pixel electrode 32 are located respectively exhibit four alignment directions.
  • the difference between the voltage between the first pixel electrode 31 and the common electrode and the voltage between the second pixel electrode 32 and the common electrode makes the liquid crystal display panel equivalent to an 8-domain liquid crystal display effect, making the liquid crystal display panel have a lower color shift and better display effect.
  • the pixel electrode includes two parts that are mutually offset in the first direction X.
  • the first pixel electrode 31 includes a connected first part 311 and a second part 312.
  • the first part 311 and the second part 312 are arranged along the second direction Y. In the first direction Each of the two sides of is not collinear.
  • the first part 311 is offset to the right by a certain distance relative to the second part 312 .
  • the orientation of liquid crystal molecules located at the edge of the pixel electrode is relatively chaotic. When the liquid crystal display panel displays, dark lines will be formed in these areas.
  • a second pixel electrode is roughly shown with a dotted line.
  • the dark pattern area 30a corresponding to 32 has the same shape. This will lead to a reduction in the aperture ratio and affect the display effect.
  • the active layer T30 of the third thin film transistor T3 may be connected to the active layer T10 of the first thin film transistor T1.
  • the first electrode T11 of the first thin film transistor T1 is multiplexed as the first electrode T31 of the third thin film transistor T3. That is, the active layers of the two thin film transistors are a whole, and the first electrode T11 of the first thin film transistor T1 and the first electrode T31 of the third thin film transistor T3 are a whole. This can further reduce the parasitic capacitance between the first electrode T31 of the third thin film transistor T3 and the gate line 21, thereby further improving the display effect of the liquid crystal display panel.
  • the first, second and third thin film transistors T1, T2 and T3 are located between the data line 22 and the discharge line 23.
  • the active layer T30 of the third thin film transistor T3, the active layer T10 of the first thin film transistor T1, and the active layer T20 of the second thin film transistor T2 are connected in sequence to form a stripe shape.
  • the length of the channel region of the first thin film transistor T1 is 4 ⁇ m ⁇ 5 ⁇ m, such as 4.4 ⁇ m, and the width is 5 ⁇ m ⁇ 15 ⁇ m, such as 10 ⁇ m.
  • the length direction of the channel region of the first thin film transistor T1 is the arrangement direction of the first electrode T11 and the second electrode T12 of the first thin film transistor T1.
  • the width direction of the channel region of the first thin film transistor T1 is perpendicular to the length direction.
  • the length of the channel region of the second thin film transistor T2 is 8 ⁇ m to 14 ⁇ m, for example, 10 ⁇ m; the width of the channel region of the second thin film transistor T2 is 3 ⁇ m to 4 ⁇ m, for example, 3.4 ⁇ m. Changing the length of the channel region of the second thin film transistor T2 can change the difference between the voltage between the first pixel electrode 31 and the common electrode and the voltage between the second pixel electrode 32 and the common electrode.
  • the length of the channel region of the third thin film transistor T3 is the same as the length of the channel region of the first thin film transistor T1
  • the width of the channel region of the third thin film transistor T3 is the same as the width of the channel region of the first thin film transistor T1.
  • the directions of the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are consistent.
  • the second electrode T32 of the third thin film transistor T3, the first electrode T31 of the third thin film transistor T3, and the first electrode T31 of the first thin film transistor T1 The diode T12 and the second pole T22 of the second thin film transistor T2 are arranged in sequence along the first direction X.
  • the first electrode T11 of the first thin film transistor T1 is multiplexed as the first electrode T31 of the third thin film transistor T3, and the second electrode T12 of the first thin film transistor T1 is multiplexed as the first electrode T21 of the second thin film transistor T2.
  • the discharge line A part of 23 is multiplexed as the second electrode T22 of the second thin film transistor T2.
  • a part of the gate line 21 is reused as a control electrode of the first thin film transistor T1, another part of the gate line 21 is reused as a control electrode of the second thin film transistor T2, and a part of the gate line 21 is reused as a third thin film transistor. Control electrode of transistor T3.
  • the first thin film transistor T1 , the second thin film transistor T2 and the third thin film transistor T3 are distributed on one side of the discharge line 23 .
  • the width of the gate line 21 on both sides of the discharge line 23 is different.
  • the line width of the gate line 21 is smaller.
  • the line width of the gate line 21 is smaller. The larger the width, the better to further reduce the parasitic capacitance and improve the display effect of the liquid crystal display panel.
  • FIG. 6 is an equivalent circuit diagram of a liquid crystal display panel provided by an embodiment of the present disclosure.
  • This liquid crystal display panel has an array substrate as shown in FIG. 4 .
  • V com in the figure represents the common voltage, and the arrow indicates that this end is connected to the common voltage line, or other signal lines that can provide a voltage similar to or equal to the public voltage.
  • in the liquid crystal display panel there is a first liquid crystal capacitor C 1 between the second electrode T12 of the first thin film transistor T1 and the common voltage line, and the first electrode T11 of the second thin film transistor T2 is connected to the common voltage line.
  • first storage capacitor C 2 between the lines, and there are a second liquid crystal capacitor C 3 and a second storage capacitor C 4 between the second pole T32 of the third thin film transistor T1 and the common voltage line.
  • One of the two plates of the first liquid crystal capacitor C 1 may be the first pixel electrode 31 and the other may be a common electrode.
  • One of the two plates of the first storage capacitor C 2 may be the first pixel electrode 31 , and the other may be the first storage capacitor plate 24 .
  • One of the two plates of the second liquid crystal capacitor C 3 may be the second pixel electrode 32 and the other may be a common electrode.
  • One of the two plates of the second storage capacitor C 4 may be the second pixel electrode 32 , and the other may be the second storage capacitor plate 25 .
  • Both the first storage capacitor plate 24 and the second storage capacitor plate 25 may be in the same layer as the gate line 21 .
  • the first storage capacitor plate 24 and the second storage capacitor plate 25 are respectively connected to the common voltage line.
  • the potential of the first pixel electrode 31 is equal to the potential between the first thin film transistor T1 and the second thin film transistor T2, for example, the potential of the second electrode T12 of the first thin film transistor T1 or the first electrode T21 of the second thin film transistor T2. potentials are equal.
  • the potential of the second pixel electrode 32 is equal to the potential of the data line 22 .
  • the first storage capacitor plate 24 and the second storage capacitor plate 25 between two adjacent gate lines 21 may be connected.
  • FIG. 7 is a cross-sectional view taken along the dotted line M in FIG. 4 .
  • the base substrate is provided with a gate line 21 , a first storage capacitor plate 24 and a second storage capacitor plate 25 on the bearing surface of the array substrate 10 .
  • a first insulating layer 101 is provided on the gate line 21 , the first storage capacitor plate 24 and the second storage capacitor plate 25 .
  • An active layer, such as the active layer T10 of the first thin film transistor T1 is located on the first insulating layer 101.
  • a second insulating layer 102 is provided on the active layer, and the second insulating layer 102 has via holes.
  • the first electrode and the second electrode of the thin film transistor for example, the first electrodes T11 and T12 of the first thin film transistor T1 are located on the second insulating layer 102 and are respectively connected to the active layer T10 of the first thin film transistor T1 through via holes.
  • the first connection line 41 is also located on the second insulation layer 102 .
  • a third insulating layer 103 is provided on the first connection line 41.
  • the third insulating layer 103 has a via hole 50.
  • the pixel electrode, such as the first pixel electrode 31, is located on the third insulating layer 103 and is connected to the first insulating layer through the via hole 50. Connected to line 41.
  • the first pixel electrode 31 and the first storage capacitor plate 24 form a first storage capacitor C 2 .
  • the structure shown in FIG. 7 is only an example. In other examples, some or all of the structures shown in FIG. 7 may be included, and other structures not shown in FIG. 7 may also be included.
  • the second insulating layer 102 shown in FIG. 7 may not be included, that is, the first and second electrodes of the thin film transistor and the first connection line 41 are directly formed on the active layer and the first insulating layer 101 .
  • FIG. 8 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 8 , in the array substrate, the first electrode T11 and the second electrode T12 of the first thin film transistor T1 are arranged along the second direction Y.
  • the directions of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are consistent and are all along the second direction Y.
  • the second electrode T32 of the third thin film transistor T3, the first electrode T31 of the third thin film transistor T3, the second electrode T12 of the first thin film transistor T1, and the second electrode T22 of the second thin film transistor T2 are arranged in sequence along the second direction Y.
  • the first electrode T11 of the first thin film transistor T1 is multiplexed as the first electrode T31 of the third thin film transistor T3, and the second electrode T12 of the first thin film transistor T1 is multiplexed as the first electrode T21 of the second thin film transistor T2.
  • the array substrate with this structure reduces the space occupied by the thin film transistor in the first direction X, which is conducive to setting the size of the pixel electrode smaller in the first direction X. Therefore, a larger number of pixel electrodes can be arranged in the first direction X to improve the resolution of the liquid crystal display device.
  • the first pixel unit of the array substrate further includes a third connection line 43 , and the second electrode T22 of the second thin film transistor T2 is electrically connected to the discharge line 23 through the third connection line 43 .
  • the third connecting line 43 is provided to connect the second thin film transistor T2 to the discharge line 23.
  • the second pole T22 of T2 is connected to the discharge line 23 .
  • the third connection line 43 may be on the same layer as the second electrode T22 of the second thin film transistor T2 and the discharge line 23 to save processes and also help reduce the thickness of the base substrate.
  • the orthographic projection of the third connection line 43 on the bearing surface is located within the orthographic projection of the grid line 21 on the bearing surface.
  • FIG. 9 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 9 , the difference between this array substrate and the array substrate shown in FIG. 8 is that the orthographic projection of the third connection line 43 on the carrying surface is at least partially located outside the orthographic projection of the grid line 21 on the carrying surface.
  • the overlapping area of the third connection line 43 and the gate line 21 is smaller, and the parasitic capacitance between the third connection line 43 and the gate line 21 is smaller, which is beneficial to Further improve the display effect of the LCD panel.
  • the orthographic projection of the second electrode T22 of the second thin film transistor T2 on the carrying surface and the orthographic projection of the second electrode T32 of the third thin film transistor T3 on the carrying surface are both partially located on the orthographic projection of the gate line 21 on the carrying surface. In addition, this can further reduce the parasitic capacitance between the gate line 21 and the thin film transistor.
  • the direction of the first thin film transistor T1 and the second thin film transistor T2 may also be along other directions, such as a direction that has a non-zero included angle with both the first direction X and the second direction Y.
  • the direction is at an angle of 45° to the first direction X.
  • FIG. 10 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the first electrode T11 and the second electrode T12 of the first thin film transistor T1 are arranged along the second direction Y
  • the first electrode T21 and the second electrode T22 of the second thin film transistor T2 are arranged along the second direction Y.
  • the second electrode T12 of the first thin film transistor T1 is connected to the first electrode T21 of the second thin film transistor T2 and the first connection line 41 is connected to the first electrode T21 of the second thin film transistor T2.
  • the orthographic projection of the first connection line 41 on the carrying surface may be completely located outside the orthographic projection of the gate line 21 on the carrying surface, so as to further reduce the parasitic capacitance.
  • the grid line 21 includes a main body part 211 and a branch part 212 that are connected.
  • the orthographic projection of the first thin film transistor T1 on the carrying surface at least partially overlaps with the orthographic projection of the main body part 211 on the carrying surface, and the control electrode of the first thin film transistor T1 is connected to the main body part 211 .
  • the orthographic projection of the second thin film transistor T2 on the carrying surface at least partially overlaps with the orthographic projection of the branch portion 212 on the carrying surface, and the control electrode of the second thin film transistor T2 is connected to the branch portion 212 .
  • the first thin film transistor T1 and the third thin film transistor T3 are oriented along the second direction Y.
  • the direction of the second thin film transistor T2 is along the first direction X, which can facilitate the connection between the second electrode T22 of the second thin film transistor T2 and the discharge line 23 .
  • a part of the discharge line 23 can be reused as the second electrode T22 of the second thin film transistor T2 to further reduce the parasitic capacitance and improve the display effect of the liquid crystal display panel.
  • FIG. 11 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure. As shown in Figure 11, the difference between this array substrate and the array substrate shown in Figure 10 is that the orthographic projection of the second electrode T12 of the first thin film transistor T1 on the bearing surface, and the second electrode T32 of the third thin film transistor T3 on the bearing surface. The orthographic projection of the surface is partially located outside the orthographic projection of the gate line 21 on the carrying surface, which can further reduce the parasitic capacitance between the gate line 21 and the thin film transistor.
  • FIG. 12 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the first electrode T11 and the second electrode T12 of the first thin film transistor T1 are arranged along the second direction Y
  • the first electrode T21 and the second electrode T22 of the second thin film transistor T2 are arranged along the first direction Y.
  • the second electrode T12 of the first thin film transistor T1 is electrically connected to the first electrode T21 of the second thin film transistor T2
  • the first connection line 41 is electrically connected to the first electrode T21 of the second thin film transistor T2.
  • the gate line 21 includes a main gate line 213 and an auxiliary gate line 214 .
  • the orthographic projection of the first thin film transistor T1 on the carrying surface at least partially overlaps with the orthographic projection of the main gate line 213 on the carrying surface.
  • the control electrode of the first thin film transistor T1 is connected to the main gate line 214.
  • the gate lines 213 are electrically connected.
  • the orthographic projection of the second thin film transistor T2 on the carrying surface at least partially overlaps with the orthographic projection of the auxiliary gate line 214 on the carrying surface, and the control electrode of the second thin film transistor T2 is electrically connected to the auxiliary gate line 214.
  • the main gate line 213 and the auxiliary gate line 214 can be used to input the same or different control signals.
  • the main gate line 213 is used to input the control signal to control the on/off of the first thin film transistor T1 and the third thin film transistor T3.
  • the auxiliary gate line 214 is used to input a control signal to control on/off of the second thin film transistor T2.
  • FIG. 13 is a flow chart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure. This method is used to produce any of the array substrates shown in Figures 1 to 12. The method includes:
  • step S11 the array substrate 10 is provided.
  • step S12 gate lines 21 are formed on the bearing surface of the base substrate 10 .
  • the grid line 21 extends along the first direction X, and the first direction X is parallel to the carrying surface.
  • step S13 the first thin film transistor T1 and the second thin film transistor T2 are formed on the carrying surface of the base substrate 10 .
  • the orthographic projection of the first thin film transistor T1 and the second thin film transistor T2 on the carrying surface at least partially overlaps with the orthographic projection of the gate line 21 on the carrying surface, and the control electrode of the first thin film transistor T1 and the second thin film transistor T2
  • the control electrodes are all electrically connected to the gate line 21 .
  • step S14 the data lines 22 , the discharge lines 23 and the first connection lines 41 are formed on the bearing surface of the base substrate 10 .
  • the data line 22 extends along the second direction Y, and the discharge line 23 extends along the third direction Z.
  • the second direction Y and the third direction Z are both parallel to the bearing surface, and the second direction Y intersects the first direction X.
  • the gate lines 21 and the data lines 22 cross each other to define a plurality of sub-pixel regions.
  • the data line 22 is electrically connected to the first electrode T11 of the first thin film transistor T1
  • the discharge line 23 is electrically connected to the second electrode T22 of the second thin film transistor T2
  • the first connection line 41 is electrically connected to the second electrode T11 of the first thin film transistor T1.
  • the electrode T12 and the first electrode T21 of the second thin film transistor T2 are electrically connected.
  • step S15 the first pixel electrode 31 is formed on the carrying surface of the base substrate 10.
  • the first pixel electrode 31 is located on one side of the gate line 21 .
  • the plurality of first pixel electrodes 31 are respectively located in a plurality of sub-pixel regions.
  • the first pixel electrode 31 is electrically connected to the first connection line 41 to connect the base substrate 10 to the first pixel electrode 31 .
  • a plurality of first pixel units are formed on the carrying surface.
  • the second electrode T12 of the first thin film transistor T1 and the first electrode T21 of the second thin film transistor T2 are connected to the first pixel through the first connection line 41.
  • the electrode 31 is electrically connected, so there is no need to connect the second electrode T12 of the first thin film transistor T1 and the first electrode T21 of the second thin film transistor T2 to the first pixel electrode 31 through connecting lines respectively, which can reduce the layout of one connecting line. , thereby reducing the total area of overlap between the connecting line and the gate line 21, reducing the parasitic capacitance, which is beneficial to improving the display effect of the liquid crystal display panel.
  • an insulating layer is also formed on the carrying surface to insulate some structures from each other, such as the gate lines 21, the data lines 22 and the discharge lines 23 from each other.
  • a first insulating layer 101 is formed on the carrying surface, and the first insulating layer 101 at least covers the gate lines 21 .
  • the first thin film transistor T1 , the second thin film transistor T2 and the third thin film transistor T3 can be fabricated together.
  • the active layers of the third thin film transistor T3, the first thin film transistor T1 and the second thin film transistor T2 can be formed on the first insulating layer 101. These three thin film transistors The active layers can be connected or not.
  • the active layers of these three thin film transistors are connected as a whole.
  • a second insulating layer 102 is formed on the bearing surface, and the second insulating layer 102 at least covers the active layer.
  • Vias may also be formed on the second insulating layer 102 so that subsequently formed structures can be connected to the active layer through the vias.
  • the first electrode T31 and the second electrode T32 of the third thin film transistor T3, the first electrode T11 and the second electrode T12 of the first thin film transistor T1, and the first electrode of the second thin film transistor T2 are formed on the second insulating layer 102. T21 and the second pole T22.
  • the first electrode T31 and the second electrode T32 of the third thin film transistor T3, the first electrode T11 and the second electrode T12 of the first thin film transistor T1, the second electrode The first pole T21 and the second pole T22 of the transistor T2, the first connection line 41, the data line 22, the discharge line 23, the second connection line 42, and the third connection line 43 can all be formed together, for example, from the same film layer through the same Formed by secondary patterning process.
  • the second insulating layer 102 can also be omitted, and the first pole, the second pole, and the first connection line 41 of the thin film transistor can be directly formed on the active layer and the first insulating layer 101 to further save the process and reduce the cost.
  • the thickness of the array substrate can also be omitted, and the first pole, the second pole, and the first connection line 41 of the thin film transistor can be directly formed on the active layer and the first insulating layer 101 to further save the process and reduce the cost.
  • a third insulating layer 103 may also be formed on the thin film transistor.
  • the third insulating layer 103 has a through hole 50 to facilitate subsequent formation of the pixel electrode, for example, the first pixel electrode 31 is connected to the first connection line 41 .
  • FIG. 14 is a schematic structural diagram of a liquid crystal display panel provided by an embodiment of the present disclosure.
  • the liquid crystal display panel includes a color filter substrate 300 , a liquid crystal layer 200 and any array substrate 100 shown in FIGS. 1 to 12 .
  • the color filter substrate 300 and the array substrate 100 are arranged oppositely, and the liquid crystal layer 200 is located between the color filter substrate 300 and the array substrate 100 .
  • the color filter substrate 300 includes a transparent substrate 301, a color filter layer 302 located on one side of the transparent substrate 301, and a common electrode 303 located on the color filter layer 302.
  • An embodiment of the present disclosure also provides a display device, which includes a backlight and a liquid crystal display panel as shown in FIG. 14 .
  • the backlight is located on a side of the array substrate 100 away from the color filter substrate 300 .
  • the display device may be, but is not limited to, a mobile phone, a notebook computer, a tablet computer, a monitor, a navigator, or a digital camera.

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Abstract

本公开提供了一种阵列基板及其制作方法、液晶显示面板和显示装置，属于显示装置领域。该阵列基板包括衬底基板、栅线、数据线、放电线、第一像素电极、第一薄膜晶体管、第二薄膜晶体管和第一连接线；第一薄膜晶体管的控制极和第二薄膜晶体管的控制极均与栅线相连，第一薄膜晶体管的第一极与数据线相连，第一薄膜晶体管的第二极和第二薄膜晶体管的第一极均通过第一连接线与第一像素电极相连，第二薄膜晶体管的第二极与放电线相连。从而不需要将第一薄膜晶体管的第二极和第二薄膜晶体管的第一极分别通过连接线连接到第一像素电极，能够减少一个连接线的布置，从而减小连接线与栅线重叠的总面积，降低寄生电容，有利于提高液晶显示面板的显示效果。

Description

阵列基板及其制作方法、液晶显示面板和显示装置 技术领域
本公开涉及显示装置领域，特别涉及一种阵列基板及其制作方法、液晶显示面板和显示装置。
背景技术
液晶显示面板(liquid crystal display，LCD)由于其耗电量较低被广泛应用于大尺寸的显示装置中。
在液晶显示面板中，栅线与一些结构之间存在寄生电容，例如部分像素电极分别与多个薄膜晶体管相连，这些薄膜晶体管与像素电极之间的连接线就与栅线之间存在寄生电容。这些寄生电容会对液晶显示面板产生不良影响，不利于液晶显示面板显示效果的提升。
发明内容
本公开实施例提供了一种阵列基板及其制作方法、液晶显示面板和显示装置，能够减小寄生电容，有利于提高显示效果。所述技术方案如下：
第一方面，本公开实施例提供了一种阵列基板，所述阵列基板包括衬底基板、信号线和多个第一像素单元；
所述信号线位于所述衬底基板的承载面，包括相互绝缘的栅线、数据线和放电线，所述栅线沿第一方向延伸，所述数据线沿第二方向延伸，所述放电线沿第三方向延伸，所述第一方向和所述第三方向均与所述第二方向相交，所述栅线和所述数据线相互交叉限定出多个子像素区域；
所述第一像素单元包括第一像素电极、第一薄膜晶体管、第二薄膜晶体管和第一连接线，多个所述第一像素电极分别位于所述多个子像素区域中，所述第一薄膜晶体管和所述第二薄膜晶体管在所述承载面上的正投影均与所述栅线在所述承载面的正投影至少部分重叠；
所述第一薄膜晶体管的控制极和所述第二薄膜晶体管的控制极均与所述栅线电性连接，所述第一薄膜晶体管的第一极与所述数据线电性连接，所述第一 薄膜晶体管的第二极和所述第二薄膜晶体管的第一极均通过所述第一连接线与所述第一像素电极电性连接，所述第二薄膜晶体管的第二极与所述放电线电性连接。
可选地，所述第一连接线在所述承载面的正投影位于所述栅线在所述承载面的正投影外；或者，
所述第一连接线包括相连的重叠段和连接段；
所述重叠段在所述承载面的正投影位于所述栅线在所述承载面的正投影内，且所述重叠段与所述第一方向垂直，所述重叠段与所述第一薄膜晶体管的第二极和所述第二薄膜晶体管的第一极电性连接；
所述连接段在所述承载面的正投影位于所述栅线在所述承载面的正投影外，所述连接段与所述第一像素电极电性连接。
可选地，所述第一连接线与所述第一薄膜晶体管的第二极、所述第二薄膜晶体管的第一极、所述数据线和所述放电线中的至少一种同层。
可选地，所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层相连，所述第一薄膜晶体管的第二极复用为所述第二薄膜晶体管的第一极。
可选地，所述第一薄膜晶体管的第一极和第二极的排列方向、与所述第二薄膜晶体管的第一极和第二极的排列方向相同。
可选地，所述第一薄膜晶体管的第一极和第二极沿所述第一方向排列；
所述第一像素单元还包括第二连接线，所述第一薄膜晶体管的第一极通过所述第二连接线与所述数据线电性连接，所述第二连接线在所述承载面的正投影至少部分位于所述栅线在所述承载面的正投影外。
可选地，所述第一薄膜晶体管的第一极和第二极沿所述第二方向排列；
所述第一像素单元还包括第三连接线，所述第二薄膜晶体管的第二极通过所述第三连接线与所述放电线电性连接，所述第三连接线在所述承载面的正投影位于所述栅线在所述承载面的正投影内，或至少部分位于所述栅线在所述承载面的正投影外。
可选地，所述第一薄膜晶体管的第一极和第二极沿所述第二方向排列，所述第二薄膜晶体管的第一极和第二极沿所述第一方向排列。
可选地，所述栅线包括相连的主体部和分支部，所第一薄膜晶体管在所述承载面的正投影与所述主体部在所述承载面的正投影至少部分重叠，所述第一 薄膜晶体管的控制极与所述主体部电性连接；
所述第二薄膜晶体管在所述承载面的正投影与所述分支部在所述承载面的正投影至少部分重叠，所述第二薄膜晶体管的控制极与所述分支部电性连接。
可选地，所述栅线包括主栅线和辅助栅线；
所述主栅线和所述辅助栅线之间具有间隙，所述第一薄膜晶体管在所述承载面的正投影与所述主栅线在所述承载面的正投影至少部分重叠，所述第一薄膜晶体管的控制极与所述主栅线电性连接；
所述第二薄膜晶体管在所述承载面的正投影与所述辅助栅线在所述承载面的正投影至少部分重叠，所述第二薄膜晶体管的控制极与所述辅助栅线电性连接。
可选地，所述第一像素电极包括相连的第一部分和第二部分，所述第一部分和所述第二部分沿所述第二方向排列，在所述第一方向上，所述第一部分和所述第二部分相互错位。
可选地，所述阵列基板还包括多个第二像素单元，所述第二像素单元包括第二像素电极和第三薄膜晶体管，多个所述第二像素电极位于所述多个子像素区域中，且在所述第二方向上，所述第二像素电极和所述第一像素电极交替分布；
所述第三薄膜晶体管的第一极与所述数据线电性连接，所述第三薄膜晶体管的第二极与所述第一像素电极电性连接，所述第三薄膜晶体管的控制极与所述栅线电性连接。
可选地，所述第一薄膜晶体管的沟道区的长度为4μm～5μm，宽度为5μm～15μm；
所述第二薄膜晶体管的沟道区的长度为8μm～14μm，宽度为3μm～4μm；
所述第三薄膜晶体管的沟道区的长度和宽度与所述第一薄膜晶体管的沟道区的长度和宽度分别相同。
第二方面，本公开实施例还提供了一种阵列基板的制作方法，该方法包括：
提供衬底基板；
在所述衬底基板的承载面上形成栅线，所述栅线沿第一方向延伸；
在所述衬底基板的承载面上形成第一薄膜晶体管和第二薄膜晶体管，所述 第一薄膜晶体管和所述第二薄膜晶体管在所述承载面上的正投影均与所述栅线在所述承载面的正投影至少部分重叠，且所述第一薄膜晶体管的控制极和所述第二薄膜晶体管的控制极均与所述栅线电性连接；
在所述衬底基板的承载面上形成数据线、放电线和第一连接线，所述数据线沿第二方向延伸，所述放电线沿第三方向延伸，所述第二方向和所述第三方向均与所述第一方向相交，所述栅线和所述数据线相互交叉限定出多个子像素区域，所述数据线与所述第一薄膜晶体管的第一极电性连接，所述放电线与所述第二薄膜晶体管的第二极电性连接，所述第一连接线与所述第一薄膜晶体管的第二极、所述第二薄膜晶体管的第一极电性连接；
在所述衬底基板的承载面上形成多个第一像素电极，多个所述第一像素电极分别位于所述多个子像素区域中，所述第一像素电极与所述第一连接线电性连接，以在所述衬底基板的承载面上形成多个第一像素单元。
第三方面，本公开实施例还提供了一种液晶显示面板，该液晶显示面板包括彩膜基板、液晶层和如第一方面所述的阵列基板，所述彩膜基板与所述阵列基板相对布置，所述液晶层位于所述彩膜基板和所述阵列基板之间。
第四方面，本公开实施例还提供了一种显示装置，该显示装置包括背光源和第三方面所述的液晶显示面板，所述背光源位于阵列基板远离彩膜基板的一侧。
本公开实施例提供的技术方案带来的有益效果至少包括：
本公开实施例提供的阵列基板中，通过设置第一连接线，第一薄膜晶体管的第二极和第二薄膜晶体管的第一极均通过第一连接线与第一像素电极电性连接，从而不需要将第一薄膜晶体管的第二极和第二薄膜晶体管的第一极分别通过连接线连接到第一像素电极，能够减少一个连接线的布置，从而减小了连接线与栅线重叠的总面积，降低了寄生电容，有利于提高液晶显示面板的显示效果。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所 需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种阵列基板的结构示意图；
图2是图1中虚线处的放大示意图；
图3是图2中虚线处的放大示意图；
图4是图3的局部放大示意图；
图5是本公开实施例提供的一种液晶显示面板中的配向示意图；
图6是本公开实施例提供的一种液晶显示面板的等效电路图；
图7是图4中虚线M处的截面图；
图8是本公开实施例提供的一种阵列基板的结构示意图；
图9是本公开实施例提供的一种阵列基板的结构示意图；
图10是本公开实施例提供的一种阵列基板的结构示意图；
图11是本公开实施例提供的一种阵列基板的结构示意图；
图12是本公开实施例提供的一种阵列基板的结构示意图；
图13是本公开实施例提供的一种阵列基板的制作方法流程图；
图14是本公开实施例提供的一种液晶显示面板的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、 “下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
液晶显示面板具有一定的可视角度，在视角范围内都能够观察到较正常的画面。但是在不同视角下，尤其是大视角下，存在颜色失真的问题。相关技术中，为避免液晶显示面板的大视角颜色失真的问题，液晶显示面板通常采用多畴(domain)垂直配向(vertical alignment，VA)的显示模式，像素结构为多畴像素结构。例如通过设置八畴像素结构，能够大大降低颜色失真的问题，提高液晶显示面板的显示效果。在八畴像素结构中，设置有放电线。部分像素电极除了与数据线之间通过薄膜晶体管相连外，还要通过薄膜晶体管与放电线相连，也就是说这部分像素电极至少连接有两个薄膜晶体管，两个薄膜晶体管分别通过连接线与像素电极相连，使得连接线与栅极之间具有较大的重叠，产生较大的寄生电容，影响液晶显示面板显示效果的提升。
图1是本公开实施例提供的一种阵列基板的结构示意图。如图1所示，该阵列基板包括衬底基板10和信号线20。图2是图1中虚线处的放大示意图。图3是图2中虚线处的放大示意图。如图2和图3所示，该阵列基板还包括多个像素单元，其中像素单元包括像素电极30和薄膜晶体管。
衬底基板10具有相反的两个表面，其中一个表面为承载面，信号线20、像素电极30和薄膜晶体管均位于衬底基板10的承载面上。这里所指的“位于衬底基板10的承载面上”，既包括直接分布在承载面，与承载面直接接触的情况，也包括与承载面之间还具有其他结构，被其他结构所隔开，与承载面并无直接接触的情况。
信号线20位于衬底基板10的承载面，包括相互绝缘的栅线21和数据线22。栅线21沿第一方向X延伸，数据线22沿第二方向Y延伸。第一方向X和第二方向Y均平行于承载面，且第一方向X和第二方向Y相交。例如，第一方向X与第二方向Y相互垂直，或是第一方向X与第二方向Y呈锐角。
栅线21、数据线22和像素电极30均可以有多个，多个栅线21和多个数据线22在承载面上限定出多个子像素区域，每个子像素区域中分布有两个像素电极。
如图3所示，多个像素电极30包括第一像素电极31和第二像素电极32。在图3中，示出了在第二方向Y上相邻的两个子像素区域中，位于一个子像素 区域中的第一像素电极31和位于另一个子像素区域中的第二像素电极32。该第一像素电极31位于栅线21的一侧，该第二像素电极32位于栅线21的另一侧。
信号线20还包括放电线23，放电线23沿第三方向Z延伸，第三方向Z平行于承载面，且与第二方向Y相交。作为示例，本公开实施例中，第三方向Z与第一方向X垂直。在其他示例中，第三方向Z也可以第一方向X呈锐角。放电线23也可以有多个，多个放电线23和多个数据线21在第一方向X上交替间隔分布。
图4是图3的局部放大示意图。如图4所示，薄膜晶体管包括第一薄膜晶体管T1和第二薄膜晶体管T2。第一薄膜晶体管T1和第二薄膜晶体管T2在承载面上的正投影均与栅线21在承载面的正投影至少部分重叠。以第一薄膜晶体管T1为例，至少部分重叠包括第一薄膜晶体管T1在承载面上的正投影全部位于栅线21在承载面的正投影内，也包括第一薄膜晶体管T1在承载面上的正投影有一部分位于栅线21在承载面的正投影内，另一部分位于栅线21在承载面的正投影外。例如第一薄膜晶体管T1的第二极的一部分在承载面上的正投影位于栅线21在承载面的正投影外，第二薄膜晶体管T2的第一极的一部分在承载面上的正投影位于栅线21在承载面的正投影外。
第一薄膜晶体管T1的控制极和第二薄膜晶体管T2的控制极均与栅线21电性连接，第一薄膜晶体管T1的第一极T11与数据线22电性连接，第一薄膜晶体管T1的第二极T12和第二薄膜晶体管T2的第一极T21均通过第一连接线41与第一像素电极31电性连接，第二薄膜晶体管T2的第二极T22与放电线23电性连接。薄膜晶体管的第一极为薄膜晶体管的源极和漏极中的一个，薄膜晶体管的第二极为薄膜晶体管的源极和漏极中的另一个。这里所指的电性连接是指能够形成电通路的配合关系。例如，第一薄膜晶体管T1的控制极与栅线21电性连接，是指第一薄膜晶体管T1的控制极与栅线21之间能够形成电通路，栅线21加载电信号时，电信号能够作用到第一薄膜晶体管T1的控制极。
多个像素单元包括多个第一像素单元和多个第二像素单元。第一像素单元包括第一像素电极31、第一薄膜晶体管T1、第二薄膜晶体管T2和第一连接线41；第二像素单元包括第二像素电极32和第三薄膜晶体管T3。在第二方向Y上，第一像素单元的第一像素电极31和第二像素单元的第二像素电极32交替分布。
本公开实施例提供的阵列基板中，通过设置第一连接线41，第一薄膜晶体管T1的第二极T12和第二薄膜晶体管T2的第一极T21均通过第一连接线41与第一像素电极31电性连接，从而不需要将第一薄膜晶体管T1的第二极T12和第二薄膜晶体管T2的第一极T21分别通过连接线连接到第一像素电极31，能够减少一个连接线的布置，从而减小了连接线与栅线21重叠的总面积，降低了寄生电容，有利于提高液晶显示面板的显示效果。
如图4所示，第一连接线41与栅线21之间部分重叠，即第一连接线41在承载面的正投影部分位于栅线21在承载面的正投影中。
本公开实施例中，第一连接线41包括相连的重叠段411和连接段412。重叠段411在承载面的正投影位于栅线21在承载面的正投影内，且重叠段411与第一方向X垂直。重叠段411与第一薄膜晶体管T1的第二极T12和第二薄膜晶体管T2的第一极T21相连。连接段412在承载面的正投影位于栅线21在承载面的正投影外，连接段412与第一像素电极31相连。
重叠段411呈条状，重叠段411与第一方向X垂直，即重叠段411的长度方向或宽度方向与第一方向X垂直。
重叠段411在承载面的正投影与栅线21在承载面的正投影存在重叠，会产生寄生电容。通过将重叠段411设置成与第一方向X垂直的形式，以尽量减小重叠段411的长度，有利于进一步减小寄生电容，进一步提高液晶显示面板的显示效果。
在其他示例中，第一连接线41在承载面的正投影也可以位于栅线21在承载面的正投影外，也就相当于重叠段411的长度为0。通过使第一连接线41与栅线21不重叠，以进一步减小第一连接线41与栅线21之间的寄生电容。
可选地，第一连接线41与第一薄膜晶体管T1的第二极T12、第二薄膜晶体管T2的第一极T21、数据线22和放电线23中的至少一种同层。
这里所指的同层包括但不限于位于同一结构的同一表面、在同一工艺步骤中形成、由同一膜层形成。例如第一连接线41与第一薄膜晶体管T1的第二极T12同层，可以指第一连接线41与第一薄膜晶体管T1的第二极T12在同一次构图工艺中形成。
采用同层布置能够节省构图工艺的次数，并且有利于降低阵列基板的总厚度。
在一些示例中，第一连接线41、第一薄膜晶体管T1的第二极T12、第二薄膜晶体管T2的第一极T21、数据线22、放电线23中的至少两种同层。
在本公开实施例中，第一连接线41、第一薄膜晶体管T1的第二极T12、第二薄膜晶体管T2的第一极T21、数据线22、放电线23均同层，由同一膜层通过同一次构图工艺形成。
薄膜晶体管通常包括有源层、控制极、源极和漏极。在本公开实施例中，如图4所示，第一薄膜晶体管T1的有源层T10和第二薄膜晶体管T2的有源层T20相连。第一薄膜晶体管T1的第二极T12复用为第二薄膜晶体管T2的第一极T21。即两个薄膜晶体管的有源层为一个整体，第一薄膜晶体管T1的第二极T12和第二薄膜晶体管T2的第一极T21为一个整体。
第一薄膜晶体管T1的第二极T12和第二薄膜晶体管T2的第一极T21为一个整体能够进一步减小与栅线21之间的寄生电容，从而进一步提升液晶显示面板的显示效果。
在液晶显示面板中，进行画面显示的区域一般是像素电极所在的区域，而薄膜晶体管所在的区域并不进行显示，将第一薄膜晶体管T1的第二极T12复用为第二薄膜晶体管T2的第一极T21，还能够减小第三薄膜晶体管T3和第一薄膜晶体管T1在衬底基板10上占据的面积，能够留出更大的空间布置像素电极，有利于提升像素的开口率。在液晶显示面板中通常还设置有隔垫物，隔垫物和薄膜晶体管都位于像素电极之外的区域，减小薄膜晶体管在衬底基板10上占据的面积，使得隔垫物也有更大的空间进行布置，方便隔垫物的设置。
例如，第一薄膜晶体管T1和第二薄膜晶体管T2布置在数据线22和放电线23之间，隔垫物可以布置在放电线23远离第二薄膜晶体管T2的一侧。
可选地，如图3所示，该阵列基板还包括垫块40。垫块40位于放电线23远离薄膜晶体管的一侧，垫块40分布在栅线21的两侧。垫块40能够起到增加局部区域的高度的作用，从而使栅线21上方位于两个垫块40之间的区域呈凹陷状，可以提供布置隔垫物的空间，利用垫块40从隔垫物的两侧提供支撑和限位，避免隔垫物向栅线21的两侧变形。
该垫块40可以为单层结构，也可以为多层结构。当垫块40为多层结构时，垫块40中的各层可以分别与其他结构同层。例如，垫块40的一部分可以与有源层同层，在制作各薄膜晶体管的有源层时，在构图工艺中，可以在需要形成 垫块40的区域残留一部分材料，形成垫块40的一部分。垫块40的另一部分可以与薄膜晶体管的第一极、第二极、第一连接线41等同层，在制作第一连接线41时，在构图工艺中，可以在需要形成垫块40的区域残留一部分材料，形成垫块40的一部分，这样通过在同一个区域形成材料的残留，使该区域的厚度逐渐增大，形成垫块40。
如图4所示，第一薄膜晶体管T1的第一极T11和第二极T12的排列方向、与第二薄膜晶体管T2的第一极T21和第二极T22的排列方向相同。
在同一个阵列基板上，不同的薄膜晶体管之间，由于工艺的影响，薄膜晶体管的特性可能会存在一定的差异，尤其是方向不同的薄膜晶体管，差异会更大。薄膜晶体管的方向是指薄膜晶体管的第一极和第二极的排列方向，这里所指的方向不同的薄膜晶体管是指第一极和第二极的排列方向不相同的薄膜晶体管。
例如在构图工艺中，在进行曝光时，如果采用拼接曝光，在平行于承载面的方向上会存在一定的误差，并且在不同方向上的误差也难以准确控制。在进行刻蚀时，不同方向上的刻蚀速度存在差异，会影响不同方向上的刻蚀量。
本公开实施例中，通过将第一薄膜晶体管T1的两极(即第一极和第二极)的排列方向和第二薄膜晶体管T2的两极的排列方向保持一致，使第一薄膜晶体管T1的方向和第二薄膜晶体管T2的方向相同，有利于减小第一薄膜晶体管T1和第二薄膜晶体管T2的特性差异。
作为示例，如图4所示，第一薄膜晶体管T1的第一极T11和第二极T12沿第一方向X排列。
也就是说，第一薄膜晶体管T1和第二薄膜晶体管T2的方向均沿第一方向X，这有利于第二薄膜晶体管T2的第二极T22的设置。第一薄膜晶体管T1和第二薄膜晶体管T2布置在数据线22和放电线23之间，第二薄膜晶体管T2的第二极T22需要连接至放电线23，由于第一薄膜晶体管T1的两极的排列方向和第二薄膜晶体管T2的两极的排列方向保持一致，而第一薄膜晶体管T1的第一极T11和第二极T12沿第一方向X排列，因此第二薄膜晶体管T2的第二极T22与放电线23之间的距离可以设置的很小，有利于减小第二薄膜晶体管T2的第二极T22与栅线21之间产生的寄生电容。
在本示例中，放电线23的一部分复用为第二薄膜晶体管T2的第二极T22， 这样能够进一步降低寄生电容，有利于提高液晶显示面板的显示效果。
如图4所示，该阵列基板的第一像素单元还包括第二连接线42。第一薄膜晶体管T1的第一极T11通过第二连接线42与数据线22电性连接。第二连接线42在承载面的正投影至少部分位于栅线21在承载面的正投影外。
由于第二连接线42至少有部分与栅线21不重叠，也就是第二连接线42至少有部分在承载面的正投影位于栅线21在承载面的正投影外，因此减小了第二连接线42与栅线21之间的寄生电容，有利于进一步提高液晶显示面板的显示效果。
在一些示例中，第二连接线42与栅线21不重叠，即第二连接线42在承载面的正投影全部位于栅线21在承载面的正投影外，以进一步减小寄生电容。
可选地，第二连接线42可以与第一薄膜晶体管T1的第一极T11同层，以节省工艺，并且还有利于降低衬底基板的厚度。
如图4所示，第二像素单元包括第二像素电极32和第三薄膜晶体管T3。第一像素电极31和第二像素电极32分别位于栅线21的两侧。第三薄膜晶体管T3连接第二像素电极32和数据线22。第三薄膜晶体管T3的第一极T31与数据线22电性连接，第三薄膜晶体管T3的第二极T32与第一像素电极31电性连接，第三薄膜晶体管T3的控制极与栅线21电性连接。
第三薄膜晶体管T3用于控制第二像素电极32与数据线22之间的通断。虽然第二像素电极32和第一像素电极31分别通过薄膜晶体管与数据线22电性连接，但第一像素电极31还通过第二薄膜晶体管T2与放电线23电性连接，放电线23连接至能够提供与公共电压相近的电压的信号线，例如能提供7.7V电压的信号线，这使得，在液晶显示面板中，第一像素电极31与公共电极之间的电压与第二像素电极32与公共电极之间的电压具有差异。再结合液晶显示面板中，第二像素电极32和第一像素电极31所对应区域的液晶分子的取向的不同，能够得到多畴的液晶显示效果。
例如，图5是本公开实施例提供的一种液晶显示面板中的配向示意图。图中的黑色箭头示意液晶显示面板中的阵列基板的配向方向，白色箭头示意液晶显示面板中的彩膜基板的配向方向，椭圆示意液晶分子。如图5所示，在液晶显示面板中，通过配向，使第一像素电极31和第二像素电极32所在区域的液晶分子分别呈现4种配向方向。第一像素电极31与公共电极之间的电压和第二 像素电极32与公共电极之间的电压具有差异，就使得液晶显示面板等效为8畴的液晶显示效果，使液晶显示面板具有较低的色偏，显示效果更好。
如图5所示，像素电极包括在第一方向X上相互错位的两部分。以图5中所示的第一像素电极31为例，该第一像素电极31包括相连的第一部分311和第二部分312，第一部分311和第二部分312沿第二方向Y排列。在第一方向X上，第一部分311和第二部分312相互错位，即第一部分311在第一方向上相对的两条侧边中的每一条，与第二部分312在第一方向X上相对的两条侧边中的每一条，均不共线。在图5中，第一部分311相对于第二部分312向右侧错开一段距离。在多畴像素结构中，位于像素电极边缘的液晶分子取向比较混乱，液晶显示面板在进行显示时，在这些区域会形成暗纹，例如图5中，以虚线大致示出了一个第二像素电极32所对应的暗纹区域30a。第一像素电极32所对应的暗纹区域与第二像素电极32所对应的暗纹区域30a形状相同。这会导致开口率降低，影响显示效果，通过将像素电极设置成相互错位的两部分，有利于提高像素的开口率，以提升显示效果。
如图4所示，第三薄膜晶体管T3的有源层T30可以与第一薄膜晶体管T1的有源层T10相连。第一薄膜晶体管T1的第一极T11复用为第三薄膜晶体管T3的第一极T31。即两个薄膜晶体管的有源层为一个整体，第一薄膜晶体管T1的第一极T11和第三薄膜晶体管T3的第一极T31为一个整体。这样能进一步减小第三薄膜晶体管T3的第一极T31与栅线21之间的寄生电容，从而进一步提升液晶显示面板的显示效果。
在本示例中，第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3位于数据线22和放电线23之间。第三薄膜晶体管T3的有源层T30、第一薄膜晶体管T1的有源层T10和第二薄膜晶体管T2的有源层T20依次相连呈条状。
在一些示例中，第一薄膜晶体管T1的沟道区的长度为4μm～5μm，例如4.4μm；宽度为5μm～15μm，例如10μm。第一薄膜晶体管T1的沟道区的长度方向为第一薄膜晶体管T1的第一极T11和第二极T12的排列方向，第一薄膜晶体管T1的沟道区的宽度方向与长度方向垂直。
第二薄膜晶体管T2的沟道区的长度为8μm～14μm，例如10μm；第二薄膜晶体管T2的沟道区的宽度为3μm～4μm，例如3.4μm。改变第二薄膜晶体管T2的沟道区的长度，能够改变第一像素电极31与公共电极之间的电压和第二像素 电极32与公共电极之间的电压的差异。
第三薄膜晶体管T3的沟道区的长度与第一薄膜晶体管T1的沟道区的长度相同，第三薄膜晶体管T3的沟道区的宽度与第一薄膜晶体管T1的沟道区的宽度相同。
第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3的方向一致，第三薄膜晶体管T3的第二极T32、第三薄膜晶体管T3的第一极T31、第一薄膜晶体管T1的第二极T12、第二薄膜晶体管T2的第二极T22沿第一方向X依次排列。第一薄膜晶体管T1的第一极T11复用为第三薄膜晶体管T3的第一极T31，第一薄膜晶体管T1的第二极T12复用为第二薄膜晶体管T2的第一极T21，放电线23的一部分复用为第二薄膜晶体管T2的第二极T22。栅线21上的一部分复用为第一薄膜晶体管T1的控制极，栅线21上的另一部分复用为第二薄膜晶体管T2的控制极，栅线21上还有一部分复用为第三薄膜晶体管T3的控制极。
如图3和图4所示，第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3分布在放电线23的一侧。栅线21在放电线23两侧的线宽不同，在放电线23靠近薄膜晶体管的一侧，栅线21的线宽较小，在放电线23远离薄膜晶体管的一侧，栅线21的线宽较大，这样有利于进一步减小寄生电容，提升液晶显示面板的显示效果。
图6是本公开实施例提供的一种液晶显示面板的等效电路图。该液晶显示面板具有如图4所示的阵列基板。图中的V com表示公共电压，箭头表示该端连接至公共电压线，或是能够提供与公共电压大小相近或相等的电压的其他信号线。如图6所示，在液晶显示面板中，在第一薄膜晶体管T1的第二极T12与公共电压线之间有第一液晶电容C 1，第二薄膜晶体管T2的第一极T11与公共电压线之间有第一存储电容C 2，在第三薄膜晶体管T1的第二极T32与公共电压线之间有第二液晶电容C 3和第二存储电容C 4。第一液晶电容C 1的两块极板中的一块可以是第一像素电极31，另一块可以是公共电极。第一存储电容C 2的两块极板中的一块可以是第一像素电极31，另一块可以是第一存储电容极板24。第二液晶电容C 3的两块极板中的一块可以是第二像素电极32，另一块可以是公共电极。第二存储电容C 4的两块极板中的一块可以是第二像素电极32，另一块可以是第二存储电容极板25。第一存储电容极板24和第二存储电容极板25均可以与栅线21同层。第一存储电容极板24和第二存储电容极板25分别连接至 公共电压线。第一像素电极31的电位与第一薄膜晶体管T1和第二薄膜晶体管T2之间的电位相等，例如与第一薄膜晶体管T1的第二极T12的电位或第二薄膜晶体管T2的第一极T21的电位相等。第二像素电极32的电位与数据线22的电位相等。
参照图2所示，相邻两条栅线21之间的第一存储电容极板24和第二存储电容极板25可以相连。
图7是图4中虚线M处的截面图。如图7所示，该衬底基板在阵列基板10的承载面上设置有栅线21、第一存储电容极板24和第二存储电容极板25。在有栅线21、第一存储电容极板24和第二存储电容极板25上设置有第一绝缘层101。有源层，例如第一薄膜晶体管T1的有源层T10位于第一绝缘层101上。在有源层上设置有第二绝缘层102，第二绝缘层102上具有过孔。薄膜晶体管的第一极和第二极，例如第一薄膜晶体管T1的第一极T11和T12位于第二绝缘层102上，且分别通过过孔与第一薄膜晶体管T1的有源层T10相连。第一连接线41也位于第二绝缘层102上。第一连接线41上设置有第三绝缘层103，第三绝缘层103具有过孔50，像素电极，例如第一像素电极31位于第三绝缘层103上，并通过过孔50与第一连接线41相连。第一像素电极31与第一存储电容极板24构成第一存储电容C 2。
图7所示结构仅为一种示例，在其他示例中，可以包括图7所示的部分或全部结构，并且还可以包括未在图7中示出的其他结构。例如在一些示例中，可以不包括图7所示的第二绝缘层102，即薄膜晶体管的第一极和第二极、第一连接线41直接形成在有源层和第一绝缘层101上。
图8是本公开实施例提供的一种阵列基板的结构示意图。如图8所示，在该阵列基板中，第一薄膜晶体管T1的第一极T11和第二极T12沿第二方向Y排列。
在该阵列基板中，第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3的方向一致，均沿第二方向Y。第三薄膜晶体管T3的第二极T32、第三薄膜晶体管T3的第一极T31、第一薄膜晶体管T1的第二极T12、第二薄膜晶体管T2的第二极T22沿第二方向Y依次排列。第一薄膜晶体管T1的第一极T11复用为第三薄膜晶体管T3的第一极T31，第一薄膜晶体管T1的第二极T12复用为第二薄膜晶体管T2的第一极T21。
该结构的阵列基板，相比于图4所示阵列基板，减小了薄膜晶体管在第一方向X上占据的空间，有利于在第一方向X上，将像素电极的尺寸设置的更小，从而能够在第一方向X上布置更多数量的像素电极，以提高液晶显示装置的分辨率。
如图8所示，该阵列基板的第一像素单元还包括第三连接线43，第二薄膜晶体管T2的第二极T22通过第三连接线43与放电线23电性连接。
由于第二薄膜晶体管T2的方向沿第二方向Y，因此第二薄膜晶体管T2的第二极T22与放电线23之间具有一定的间距，通过设置第三连接线43，以将第二薄膜晶体管T2的第二极T22连接至放电线23。
可选地，第三连接线43可以与第二薄膜晶体管T2的第二极T22同层、放电线23同层，以节省工艺，并且还有利于降低衬底基板的厚度。
在本示例中，第三连接线43在承载面的正投影位于栅线21在承载面的正投影内。
在图8所示阵列基板中，第三连接线43在承载面的正投影位于栅线21在承载面的正投影内。图9是本公开实施例提供的一种阵列基板的结构示意图。如图9所示，该阵列基板与图8所示的阵列基板的区别在于，第三连接线43在承载面的正投影至少部分位于栅线21在承载面的正投影外。
相比于图8所示的衬底基板，图9中，第三连接线43与栅线21重叠的面积更小，第三连接线43与栅线21之间的寄生电容更小，有利于进一步提高液晶显示面板的显示效果。
在本示例中，第二薄膜晶体管T2的第二极T22在承载面的正投影、第三薄膜晶体管T3的第二极T32在承载面的正投影均部分位于栅线21在承载面的正投影外，这样能够进一步减小栅线21与薄膜晶体管之间的寄生电容。
在另一些示例中，第一薄膜晶体管T1和第二薄膜晶体管T2的方向还可以沿其他方向，例如与第一方向X和第二方向Y均呈非零夹角的方向。例如与第一方向X均呈45°夹角的方向。
图10是本公开实施例提供的一种阵列基板的结构示意图。如图10所示，该阵列基板中，第一薄膜晶体管T1的第一极T11和第二极T12沿第二方向Y排列，第二薄膜晶体管T2的第一极T21和第二极T22沿第一方向X排列。即第一薄膜晶体管T1和第三薄膜晶体管T3的方向一致，均沿第二方向Y，第二 薄膜晶体管T2的方向沿第一方向X。
该示例中，第一薄膜晶体管T1的第二极T12与第二薄膜晶体管T2的第一极T21相连，第一连接线41与第二薄膜晶体管T2的第一极T21相连。第一连接线41在承载面的正投影可以完全位于栅线21在承载面的正投影外，以进一步减小寄生电容。
如图10所示，该栅线21包括相连的主体部211和分支部212。所第一薄膜晶体管T1在承载面的正投影与主体部211在承载面的正投影至少部分重叠，第一薄膜晶体管T1的控制极与主体部211相连。第二薄膜晶体管T2在承载面的正投影与分支部212在承载面的正投影至少部分重叠，第二薄膜晶体管T2的控制极与分支部212相连。
在该示例中，第一薄膜晶体管T1和第三薄膜晶体管T3的方向沿第二方向Y，相比于图4所示的阵列基板，能够减小薄膜晶体管在第一方向X所占据的空间。而第二薄膜晶体管T2的方向沿第一方向X，能够方便第二薄膜晶体管T2的第二极T22与放电线23的连接。例如，使放电线23的一部分能够复用为第二薄膜晶体管T2的第二极T22，以进一步减小寄生电容，提高液晶显示面板的显示效果。
图11是本公开实施例提供的一种阵列基板的结构示意图。如图11所示，该阵列基板与图10所示的阵列基板的区别在于，第一薄膜晶体管T1的第二极T12在承载面的正投影、第三薄膜晶体管T3的第二极T32在承载面的正投影均部分位于栅线21在承载面的正投影外，这样能够进一步减小栅线21与薄膜晶体管之间的寄生电容。
图12是本公开实施例提供的一种阵列基板的结构示意图。如图12所示，该示例中，第一薄膜晶体管T1的第一极T11和第二极T12沿第二方向Y排列，第二薄膜晶体管T2的第一极T21和第二极T22沿第一方向X排列。第一薄膜晶体管T1的第二极T12与第二薄膜晶体管T2的第一极T21电性连接，第一连接线41与第二薄膜晶体管T2的第一极T21电性连接。
如图12所示，该栅线21包括主栅线213和辅助栅线214。主栅线213和辅助栅线214之间具有间隙，第一薄膜晶体管T1在承载面的正投影与主栅线213在承载面的正投影至少部分重叠，第一薄膜晶体管T1的控制极与主栅线213电性连接。第二薄膜晶体管T2在承载面的正投影与辅助栅线214在承载面的正投 影至少部分重叠，第二薄膜晶体管T2的控制极与辅助栅线214电性连接。
主栅线213和辅助栅线214可以用于输入相同或不同的控制信号，主栅线213用于输入控制信号，以控制第一薄膜晶体管T1和第三薄膜晶体管T3的通断。辅助栅线214用于输入控制信号，以控制第二薄膜晶体管T2的通断。通过设置主栅线213和辅助栅线214，能够减小薄膜晶体管与主栅线213之间的寄生电容，也有利于提高液晶显示面板的显示效果。
图13是本公开实施例提供的一种阵列基板的制作方法流程图。该方法用于制作图1～图12所示的任一种阵列基板。该方法包括：
在步骤S11中，提供阵列基板10。
在步骤S12中，在衬底基板10的承载面上形成栅线21。
其中，栅线21沿第一方向X延伸，第一方向X平行于承载面。
在步骤S13中，在衬底基板10的承载面上形成第一薄膜晶体管T1和第二薄膜晶体管T2。
其中，第一薄膜晶体管T1和第二薄膜晶体管T2在承载面上的正投影均与栅线21在承载面的正投影至少部分重叠，且第一薄膜晶体管T1的控制极和第二薄膜晶体管T2的控制极均与栅线21电性连接。
在步骤S14中，在衬底基板10的承载面上形成数据线22、放电线23和第一连接线41。
其中，数据线22沿第二方向Y延伸，放电线23沿第三方向Z延伸，第二方向Y和第三方向Z均平行于承载面，且第二方向Y与第一方向X相交。栅线21和数据线22相互交叉限定出多个子像素区域。数据线22与第一薄膜晶体管T1的第一极T11电性连接，放电线23与第二薄膜晶体管T2的第二极T22电性连接，第一连接线41与第一薄膜晶体管T1的第二极T12、第二薄膜晶体管T2的第一极T21电性连接。
在步骤S15中，在衬底基板10的承载面上形成第一像素电极31。
该第一像素电极31位于栅线21的一侧，多个第一像素电极31分别位于多个子像素区域中，第一像素电极31与第一连接线41电性连接，以在衬底基板10的承载面上形成多个第一像素单元。
本公开实施例提供的阵列基板中，通过设置第一连接线41，第一薄膜晶体 管T1的第二极T12和第二薄膜晶体管T2的第一极T21均通过第一连接线41与第一像素电极31电性连接，从而不需要将第一薄膜晶体管T1的第二极T12和第二薄膜晶体管T2的第一极T21分别通过连接线连接到第一像素电极31，能够减少一个连接线的布置，从而减小了连接线与栅线21重叠的总面积，降低了寄生电容，有利于提高液晶显示面板的显示效果。
需要说明的是，在制作该阵列基板时，还在承载面上形成有绝缘层，以使部分结构之间相互绝缘，例如使栅线21、数据线22和放电线23相互绝缘。
例如图7所示，在形成栅线21后，在承载面上形成有第一绝缘层101，第一绝缘层101至少覆盖栅线21。
对于图3～图12所示的阵列基板，第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3可以一同进行制作。示例性地，步骤S13中进行薄膜晶体管的制作时，可以在第一绝缘层101上形成第三薄膜晶体管T3、第一薄膜晶体管T1和第二薄膜晶体管T2的有源层，这3个薄膜晶体管的有源层可以相连，也可以不相连。
以图4所示的阵列基板为例，结合图7，这3个薄膜晶体管的有源层相连为一个整体。接着在承载面上形成第二绝缘层102，第二绝缘层102至少覆盖有源层。第二绝缘层102上还可以形成过孔，以使后续形成的结构能够通过过孔与有源层形成连接。然后在第二绝缘层102上形成第三薄膜晶体管T3的第一极T31和第二极T32、第一薄膜晶体管T1的第一极T11和第二极T12、第二薄膜晶体管T2的第一极T21和第二极T22。
在一些示例中，为了节省工艺，降低阵列基板的厚度，第三薄膜晶体管T3的第一极T31和第二极T32、第一薄膜晶体管T1的第一极T11和第二极T12、第二薄膜晶体管T2的第一极T21和第二极T22、第一连接线41、数据线22、放电线23、第二连接线42、第三连接线43均可以一同形成，例如由同一膜层通过同一次构图工艺形成。
在一些示例中，还可以省略第二绝缘层102，将薄膜晶体管的第一极和第二极、第一连接线41直接形成在有源层和第一绝缘层101上，进一步节省工艺，降低阵列基板的厚度。
在形成薄膜晶体管后，还可以在薄膜晶体管上形成第三绝缘层103，第三绝缘层103具有通孔50，以方便后续形成的像素电极，例如第一像素电极31与第 一连接线41相连。
本公开实施例还提供了一种液晶显示面板，图14是本公开实施例提供的一种液晶显示面板的结构示意图。如图14所示，该液晶显示面板包括彩膜基板300、液晶层200和如图1～图12所示的任一种阵列基板100。例如图14所示，彩膜基板300与阵列基板100相对布置，液晶层200位于彩膜基板300和阵列基板100之间。
彩膜基板300包括透明基板301、位于透明基板301的一侧的彩膜层302、位于彩膜层302上的公共电极303。
本公开实施例还提供了一种显示装置，该显示装置包括背光源和如图14所示的液晶显示面板。背光源位于阵列基板100远离彩膜基板300的一侧。
该显示装置可以是，但不限于是手机、笔记本电脑、平板电脑、显示器、导航仪、数码相机。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种阵列基板，其特征在于，包括衬底基板(10)、信号线(20)和多个第一像素单元；
    所述信号线(20)位于所述衬底基板(10)的承载面，包括相互绝缘的栅线(21)、数据线(22)和放电线(23)，所述栅线(21)沿第一方向(X)延伸，所述数据线(22)沿第二方向(Y)延伸，所述放电线(23)沿第三方向(Z)延伸，所述第一方向(X)和所述第三方向(Z)均与所述第二方向(Y)相交，所述栅线(21)和所述数据线(22)相互交叉限定出多个子像素区域；
    所述第一像素单元包括第一像素电极(31)、第一薄膜晶体管(T1)、第二薄膜晶体管(T2)和第一连接线(41)，多个所述第一像素电极(31)分别位于所述多个子像素区域中，所述第一薄膜晶体管(T1)和所述第二薄膜晶体管(T2)在所述承载面上的正投影均与所述栅线(21)在所述承载面的正投影至少部分重叠；
    所述第一薄膜晶体管(T1)的控制极和所述第二薄膜晶体管(T2)的控制极均与所述栅线(21)电性连接，所述第一薄膜晶体管(T1)的第一极(T11)与所述数据线(22)电性连接，所述第一薄膜晶体管(T1)的第二极(T12)和所述第二薄膜晶体管(T2)的第一极(T21)均通过所述第一连接线(41)与所述第一像素电极(31)电性连接，所述第二薄膜晶体管(T2)的第二极(T22)与所述放电线(23)电性连接。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述第一连接线(41)在所述承载面的正投影位于所述栅线(21)在所述承载面的正投影外；或者，
    所述第一连接线(41)包括相连的重叠段(411)和连接段(412)；
    所述重叠段(411)在所述承载面的正投影位于所述栅线(21)在所述承载面的正投影内，且所述重叠段(411)与所述第一方向(X)垂直，所述重叠段(411)与所述第一薄膜晶体管(T1)的第二极(T12)和所述第二薄膜晶体管(T2)的第一极(T21)电性连接；
    所述连接段(412)在所述承载面的正投影位于所述栅线(21)在所述承载面的正投影外，所述连接段(412)与所述第一像素电极(31)电性连接。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述第一连接线(41)与所述第一薄膜晶体管(T1)的第二极(T12)、所述第二薄膜晶体管(T2)的第一极(T21)、所述数据线(22)和所述放电线(23)中的至少一种同层。
  4. 根据权利要求1所述的阵列基板，其特征在于，所述第一薄膜晶体管(T1)的有源层(T10)和所述第二薄膜晶体管(T2)的有源层(T20)相连，所述第一薄膜晶体管(T1)的第二极(T12)复用为所述第二薄膜晶体管(T2)的第一极(T21)。
  5. 根据权利要求1～4任一项所述的阵列基板，其特征在于，所述第一薄膜晶体管(T1)的第一极(T11)和第二极(T12)的排列方向、与所述第二薄膜晶体管(T2)的第一极(T21)和第二极(T22)的排列方向相同。
  6. 根据权利要求5所述的阵列基板，其特征在于，所述第一薄膜晶体管(T1)的第一极(T11)和第二极(T12)沿所述第一方向(X)排列；
    所述第一像素单元还包括第二连接线(42)，所述第一薄膜晶体管(T1)的第一极(T11)通过所述第二连接线(42)与所述数据线(22)电性连接，所述第二连接线(42)在所述承载面的正投影至少部分位于所述栅线(21)在所述承载面的正投影外。
  7. 根据权利要求5所述的阵列基板，其特征在于，所述第一薄膜晶体管(T1)的第一极(T11)和第二极(T12)沿所述第二方向(Y)排列；
    所述第一像素单元还包括第三连接线(43)，所述第二薄膜晶体管(T2)的第二极(T22)通过所述第三连接线(43)与所述放电线(23)电性连接，所述第三连接线(43)在所述承载面的正投影位于所述栅线(21)在所述承载面的正投影内，或至少部分位于所述栅线(21)在所述承载面的正投影外。
  8. 根据权利要求1～4任一项所述的阵列基板，其特征在于，所述第一薄膜晶体管(T1)的第一极(T11)和第二极(T12)沿所述第二方向(Y)排列， 所述第二薄膜晶体管(T2)的第一极(T21)和第二极(T22)沿所述第一方向(X)排列。
  9. 根据权利要求8所述的阵列基板，其特征在于，所述栅线(21)包括相连的主体部(211)和分支部(212)，所第一薄膜晶体管(T1)在所述承载面的正投影与所述主体部(211)在所述承载面的正投影至少部分重叠，所述第一薄膜晶体管(T1)的控制极与所述主体部(211)电性连接；
    所述第二薄膜晶体管(T2)在所述承载面的正投影与所述分支部(212)在所述承载面的正投影至少部分重叠，所述第二薄膜晶体管(T2)的控制极与所述分支部(212)电性连接。
  10. 根据权利要求8所述的阵列基板，其特征在于，所述栅线(21)包括主栅线(213)和辅助栅线(214)；
    所述主栅线(213)和所述辅助栅线(214)之间具有间隙，所述第一薄膜晶体管(T1)在所述承载面的正投影与所述主栅线(213)在所述承载面的正投影至少部分重叠，所述第一薄膜晶体管(T1)的控制极与所述主栅线(213)电性连接；
    所述第二薄膜晶体管(T2)在所述承载面的正投影与所述辅助栅线(214)在所述承载面的正投影至少部分重叠，所述第二薄膜晶体管(T2)的控制极与所述辅助栅线(214)电性连接。
  11. 根据权利要求1～4、6～7和9～10任一项所述的阵列基板，其特征在于，所述第一像素电极(31)包括相连的第一部分(311)和第二部分(312)，所述第一部分(311)和所述第二部分(312)沿所述第二方向(Y)排列，在所述第一方向(X)上，所述第一部分(311)和所述第二部分(312)相互错位。
  12. 根据权利要求1～4、6～7和9～10任一项所述的阵列基板，其特征在于，还包括多个第二像素单元，所述第二像素单元包括第二像素电极(32)和第三薄膜晶体管(T3)，多个所述第二像素电极(32)位于所述多个子像素区域中，且在所述第二方向(Y)上，所述第二像素电极(32)和所述第一像素电极(31) 交替分布；
    所述第三薄膜晶体管(T3)的第一极(T31)与所述数据线(22)电性连接，所述第三薄膜晶体管(T3)的第二极(T32)与所述第一像素电极(31)电性连接，所述第三薄膜晶体管(T3)的控制极与所述栅线(21)电性连接。
  13. 根据权利要求12所述的阵列基板，其特征在于，
    所述第一薄膜晶体管(T1)的沟道区的长度为4μm～5μm，宽度为5μm～15μm；
    所述第二薄膜晶体管(T2)的沟道区的长度为8μm～14μm，宽度为3μm～4μm；
    所述第三薄膜晶体管(T3)的沟道区的长度和宽度与所述第一薄膜晶体管(T1)的沟道区的长度和宽度分别相同。
  14. 一种阵列基板的制作方法，其特征在于，所述方法包括：
    提供衬底基板(10)；
    在所述衬底基板(10)的承载面上形成栅线(21)，所述栅线(21)沿第一方向(X)延伸；
    在所述衬底基板(10)的承载面上形成第一薄膜晶体管(T1)和第二薄膜晶体管(T2)，所述第一薄膜晶体管(T1)和所述第二薄膜晶体管(T2)在所述承载面上的正投影均与所述栅线(21)在所述承载面的正投影至少部分重叠，且所述第一薄膜晶体管(T1)的控制极和所述第二薄膜晶体管(T2)的控制极均与所述栅线(21)电性连接；
    在所述衬底基板(10)的承载面上形成数据线(22)、放电线(23)和第一连接线(41)，所述数据线(22)沿第二方向(Y)延伸，所述放电线(23)沿第三方向(Z)延伸，所述第二方向(Y)和所述第三方向(Z)均与所述第一方向(X)相交，所述栅线(21)和所述数据线(22)相互交叉限定出多个子像素区域，所述数据线(22)与所述第一薄膜晶体管(T1)的第一极(T11)电性连接，所述放电线(23)与所述第二薄膜晶体管(T2)的第二极(T22)电性连接，所述第一连接线(41)与所述第一薄膜晶体管(T1)的第二极(T12)、所述第二薄膜晶体管(T2)的第一极(T21)电性连接；
    在所述衬底基板(10)的承载面上形成多个第一像素电极(31)，多个所述第一像素电极(31)分别位于所述多个子像素区域中，所述第一像素电极(31) 与所述第一连接线(41)电性连接，以在所述衬底基板(10)的承载面上形成多个第一像素单元。
  15. 一种液晶显示面板，其特征在于，所述液晶显示面板包括彩膜基板(300)、液晶层(200)和如权利要求1～13任一项所述的阵列基板(100)，所述彩膜基板(300)与所述阵列基板(100)相对布置，所述液晶层(200)位于所述彩膜基板(300)和所述阵列基板(100)之间。
  16. 一种显示装置，其特征在于，所述显示装置包括背光源和如权利要求15所述的液晶显示面板，所述背光源位于阵列基板(100)远离彩膜基板(300)的一侧。
PCT/CN2022/090087 2022-04-28 2022-04-28 阵列基板及其制作方法、液晶显示面板和显示装置 WO2023206295A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102402087A (zh) * 2011-07-06 2012-04-04 友达光电股份有限公司 像素结构、主动元件阵列基板以及平面显示面板
US20160291383A1 (en) * 2015-03-31 2016-10-06 Samsung Display Co., Ltd. Liquid crystal display device including switching element with floating terminal
CN113311624A (zh) * 2021-04-06 2021-08-27 Tcl华星光电技术有限公司 一种阵列基板及显示面板
CN113534561A (zh) * 2020-04-21 2021-10-22 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN114280861A (zh) * 2020-09-27 2022-04-05 京东方科技集团股份有限公司 阵列基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102402087A (zh) * 2011-07-06 2012-04-04 友达光电股份有限公司 像素结构、主动元件阵列基板以及平面显示面板
US20160291383A1 (en) * 2015-03-31 2016-10-06 Samsung Display Co., Ltd. Liquid crystal display device including switching element with floating terminal
CN113534561A (zh) * 2020-04-21 2021-10-22 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN114280861A (zh) * 2020-09-27 2022-04-05 京东方科技集团股份有限公司 阵列基板及显示装置
CN113311624A (zh) * 2021-04-06 2021-08-27 Tcl华星光电技术有限公司 一种阵列基板及显示面板

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