WO2023206283A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023206283A1
WO2023206283A1 PCT/CN2022/090049 CN2022090049W WO2023206283A1 WO 2023206283 A1 WO2023206283 A1 WO 2023206283A1 CN 2022090049 W CN2022090049 W CN 2022090049W WO 2023206283 A1 WO2023206283 A1 WO 2023206283A1
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WO
WIPO (PCT)
Prior art keywords
touch
layer
pin
metal layer
organic layer
Prior art date
Application number
PCT/CN2022/090049
Other languages
English (en)
French (fr)
Inventor
仝可蒙
胡明
樊聪
何帆
董向丹
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/090049 priority Critical patent/WO2023206283A1/zh
Priority to CN202280001010.XA priority patent/CN117377937A/zh
Publication of WO2023206283A1 publication Critical patent/WO2023206283A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/047—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the FMLOC (Flexible Metal Layer on Cell) process can integrate the display module and the touch module, thereby effectively reducing the thickness and cost of the display panel.
  • FMLOC Flexible Metal Layer on Cell
  • the purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art, provide a display panel and a display device, and reduce short circuit defects between touch traces.
  • a display panel including a base substrate, a driving layer, a pixel layer and a touch layer that are stacked in sequence; in a peripheral area of the display panel, the driving layer is provided with a touch lead feet and a touch transfer line connected to the touch pin; the touch layer includes a touch organic layer and a touch metal layer buried in the touch organic layer, and the touch metal layer forms There are touch channels and touch traces connected to the touch channels;
  • the touch organic layer exposes the touch pins, and the end of the touch transfer line away from the touch pins extends between the touch organic layer and the base substrate ;
  • the touch trace does not protrude from the touch organic layer, and the touch trace is electrically connected to the end of the touch transfer line away from the touch pin through a via hole.
  • the touch organic layer includes a first touch organic layer, a second touch organic layer and a third touch organic layer sequentially stacked on a side of the pixel layer away from the base substrate.
  • Organic layer; the touch metal layer includes a first touch metal layer sandwiched between the first touch organic layer and the second touch organic layer, and includes a first touch metal layer sandwiched between the second touch organic layer and the second touch organic layer. a second touch metal layer between the touch control organic layer and the third touch control organic layer.
  • the second touch metal layer and the first touch metal layer form the touch channel;
  • the touch wiring includes a first touch channel connected to the same touch channel.
  • Touch traces and second touch traces, the first touch traces are located on the first touch metal layer, and the second touch traces are located on the second touch metal layer;
  • One end of the first touch trace away from the touch channel is electrically connected to the touch transfer line through a via hole, and one end of the second touch trace away from the touch channel is electrically connected to the third touch transfer line through a via hole.
  • the driving layer is provided with a common voltage bus between the touch pin and the display area of the display panel.
  • the common voltage bus is used to load a common voltage to the pixel layer. Voltage;
  • the via hole between the touch transfer line and the touch trace is located between the common voltage bus and the touch pin.
  • the driving layer includes a source-drain metal layer and a passivation layer used to protect the source-drain metal layer;
  • the touch transfer line is located on the source-drain metal layer; the portion of the touch transfer line between the touch pin and the touch organic layer is covered by the passivation layer.
  • the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer sequentially stacked on one side of the base substrate, and the passivation layer is located on the between the first source and drain metal layer and the second source and drain metal layer;
  • the touch transfer wire is located on the first source-drain metal layer; the second source-drain metal layer includes a transfer metal part corresponding to each touch transfer wire, and the touch transfer wire is away from the touch switch.
  • the end of the control pin is connected to the corresponding transfer metal part;
  • the end of the touch trace away from the touch channel is connected to the touch transfer line through the transfer metal part.
  • the transfer metal part overlaps an end of the touch transfer wire away from the touch pin; the touch transfer wire does not overlap with the transfer metal.
  • Part of the passivation layer is covered by the passivation layer.
  • the touch metal layer further includes a pin protection part corresponding to each touch pin, and the pin protection part overlaps with the corresponding touch pin. And electrically connected; there is a gap between the pin protection part and the edge of the touch organic layer.
  • the orthographic projection of the touch pin on the base substrate is located within the orthographic projection of the pin protection portion on the base substrate.
  • the touch organic layer includes a first touch organic layer, a second touch organic layer and a third touch organic layer sequentially stacked on a side of the pixel layer away from the base substrate.
  • Organic layer; the touch metal layer includes a first touch metal layer sandwiched between the first touch organic layer and the second touch organic layer, and includes a first touch metal layer sandwiched between the second touch organic layer and the second touch organic layer. a second touch metal layer between the touch control organic layer and the third touch control organic layer;
  • the pin protection part includes a first pin protection part located on the first touch metal layer and a second pin protection part located on the second touch metal layer;
  • the orthographic projection of the touch pin on the base substrate is within the orthographic projection of the first pin protection part on the base substrate; the first pin protection part is on the substrate.
  • the orthographic projection on the base substrate is within the orthographic projection of the second lead protection portion on the base substrate.
  • no second touch organic layer is provided between the first pin protection part and the second pin protection part; the first pin protection part and the touch The first touch organic layer is not provided between the pins.
  • the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer sequentially stacked on one side of the base substrate, and the passivation layer is located on the between the first source-drain metal layer and the second source-drain metal layer; the touch pin and the touch transfer line are located in the first source-drain metal layer;
  • the second source-drain metal layer includes a laminated metal portion corresponding to each touch pin, and the laminated metal portion overlaps and is electrically connected to the corresponding touch pin.
  • the orthographic projection of the touch pin on the base substrate is located within the orthographic projection of the laminated metal part on the base substrate.
  • the driving layer further includes a planarization layer located on a side of the second source-drain metal layer away from the base substrate;
  • the planarization layer covers a gap between the boundary of the laminated metal part and the touch organic layer.
  • the touch organic layer covers a portion of the touch transfer line and is directly formed on a surface of the planarization layer away from the base substrate.
  • the touch metal layer further includes a pin protection part corresponding to each touch pin, and the pin protection part is connected to the corresponding one through the laminated metal part.
  • the touch pins are arranged overlappingly and electrically connected;
  • the touch metal layer further includes a pin protection part corresponding to each touch pin, and the pin protection part is connected to the corresponding one through the laminated metal part.
  • the touch pins are arranged overlappingly and electrically connected;
  • the orthographic projection of the laminated metal part on the base substrate is located within the orthographic projection of the lead protection part on the base substrate.
  • the display panel further includes a thin film encapsulation layer located between the pixel layer and the touch layer.
  • the thin film encapsulation layer includes an alternately stacked inorganic encapsulation layer and an organic encapsulation layer.
  • the thin film encapsulation layer includes at least one organic encapsulation layer and at least two inorganic encapsulation layers.
  • a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a touch metal layer in an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display panel adjacent to the pin area in the related art.
  • FIG. 7 is a schematic structural diagram of a display panel adjacent to the pin area in the related art.
  • FIG. 8 is a schematic structural diagram of a display panel near the pin area in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a display panel near the pin area in an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of each layer of metal on the touch pin in an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display panel near the pin area in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the structural layer A is located on the side of the structural layer B facing away from the base substrate. It can be understood that the structural layer A is formed on the side of the structural layer B facing away from the base substrate.
  • part of the structure of structural layer A may also be located at the same physical height of structural layer B or lower than the physical height of structural layer B, where the base substrate is the height reference.
  • the display panel PNL in the embodiment of the present disclosure includes a base substrate BP, a driving layer FA, a pixel layer FB and a touch layer TT that are stacked in sequence.
  • the pixel layer FB is provided with sub-pixels for display
  • the driving layer FA is provided with a pixel driving circuit PDC for driving the sub-pixels
  • the touch layer TT is provided with a touch channel TS for realizing touch.
  • the substrate substrate BP may be a flexible substrate substrate, and its material may include a flexible organic material, such as one or more polyimide layers.
  • the display panel PNL of the present disclosure can be a flexible display panel PNL or a bendable display panel PNL.
  • the display panel can be applied to a bendable display device or a polygonal display device, such as a bendable mobile phone or a bendable display device. Four sides song in mobile phone.
  • the display panel PNL may also be a rigid display panel PNL.
  • the substrate BP may be made of inorganic materials such as glass and metal, or may be made of high-hardness organic materials.
  • FIG. 2 is a partial structural diagram of the display panel PNL in an embodiment of the present disclosure.
  • the driving layer FA is provided with a pixel driving circuit PDC for driving sub-pixels.
  • any pixel driving circuit PDC may include a transistor and a storage capacitor.
  • the transistor can be a thin film transistor, and the thin film transistor can be selected from a top gate thin film transistor, a bottom gate thin film transistor, or a double gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low temperature polysilicon.
  • the types of any two transistors may be the same or different.
  • some transistors may be N-type transistors and some transistors may be P-type transistors.
  • the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some of the transistors may be Metal oxide semiconductor materials.
  • the thin film transistors are low temperature polysilicon transistors. In other embodiments of the present disclosure, some thin film transistors are low temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.
  • the driving layer FA may include a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, etc. stacked between the base substrate BP and the pixel layer FB.
  • Each thin film transistor and storage capacitor can be formed by a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD and other film layers. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the semiconductor layer SEMI can be used to form the channel region of the transistor; the gate layer can be used to form gate layer wiring such as scanning wiring, reset control wiring, and emission control wiring, and can also be used to form the transistor.
  • the gate can also be used to form part or all of the electrode plates of the storage capacitor; the source-drain metal layer can be used to form source-drain metal layer traces such as data voltage traces and drive voltage traces, and can also be used to form the storage capacitor. Part of the electrode plate.
  • the driving layer FA may include a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD and a source-drain metal layer SD that are stacked in sequence.
  • the thin film transistor thus formed is a top layer. Gate thin film transistor.
  • the driving layer FA may include a gate layer GT, a gate insulating layer GI, a semiconductor layer SEMI, an interlayer dielectric layer ILD and a source-drain metal layer SD that are stacked in sequence.
  • the thin film transistor thus formed It is a bottom gate thin film transistor.
  • the gate layer may be one layer, or may be provided as two or three layers as needed.
  • the gate layer GT may include a first gate layer and a second gate layer
  • the gate insulating layer GI may include a first gate insulating layer for isolating the semiconductor layer SEMI and the first gate layer. , and including a second gate insulating layer for isolating the first gate layer and the second gate layer.
  • the driving layer FA may include a semiconductor layer SEMI, a first gate insulating layer, a first gate layer, a second gate insulating layer, and a second gate layer that are sequentially stacked on one side of the base substrate BP.
  • the gate layer GT may include a first gate layer and a second gate layer, and the semiconductor layer SEMI may be sandwiched between the first gate layer and the second gate layer; the gate insulating layer GI A first gate insulating layer for isolating the semiconductor layer SEMI and the first gate electrode layer may be included, and a second gate insulating layer may be included for isolating the second gate electrode layer and the semiconductor layer SEMI.
  • the driving layer FA may include a first gate layer, a first gate insulating layer, a semiconductor layer SEMI, a second gate insulating layer, and a second gate layer that are sequentially stacked on one side of the base substrate BP.
  • the semiconductor layer SEMI may include a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer; the gate layer includes a first gate layer and a second gate layer, and the gate insulating layer includes first to third gate electrodes. Insulation.
  • the driving layer FA may include a low-temperature polysilicon semiconductor layer, a first gate insulating layer, a first gate insulating layer, a second gate insulating layer, a metal oxide semiconductor layer, and a third gate that are sequentially stacked on one side of the base substrate BP.
  • the semiconductor layer SEMI may include a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer; the gate layer includes first to third gate layers, and the gate insulating layer includes first to third gate insulating layers.
  • the driving layer FA may include a low-temperature polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, an insulating buffer layer, a second gate layer, and a second gate insulating layer that are sequentially stacked on one side of the base substrate BP. , a metal oxide semiconductor layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer ILD and a source-drain metal layer SD.
  • the source and drain metal layers may be one layer, or may be provided as two or three layers as needed.
  • the source-drain metal layer may include a first source-drain metal layer and a second source-drain metal layer sequentially stacked on a side of the interlayer dielectric layer ILD away from the base substrate, and the first source-drain metal layer and the second An insulating layer, such as a passivation layer and/or a planarization layer, may be sandwiched between the source and drain metal layers.
  • the source-drain metal layer may include a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially stacked on the side of the interlayer dielectric layer ILD away from the base substrate;
  • An insulating layer such as a passivation layer and/or a resin layer, may be sandwiched between the first source-drain metal layer and the second source-drain metal layer; the second source-drain metal layer and the third source-drain metal layer may be sandwiched
  • An insulating layer is interposed, for example, a passivation layer and/or a planarization layer is interposed.
  • the driving layer FA may also include a passivation layer, and the passivation layer may be provided on the surface of the source and drain metal layer SD away from the base substrate BP, so as to protect the source and drain metal layer SD.
  • the driving layer FA may also include a buffer material layer Buff disposed between the base substrate BP and the semiconductor layer SEMI, and the semiconductor layer SEMI, the gate layer GT, etc. are located on a side of the buffer material layer away from the base substrate BP. side.
  • the buffer material layer may be made of inorganic insulating materials such as silicon oxide and silicon nitride.
  • the buffer material layer may be one layer of inorganic material, or may be multiple layers of laminated inorganic material layers.
  • the driving layer FA may also include a planarization layer located between the source-drain metal layer SD and the pixel layer FB, and the planarization layer may provide a planarized surface for the pixel electrode.
  • the material of the planarization layer PLN may be an organic material.
  • FIG. 2 only illustrates one way of the driving layer FA of the display panel PNL according to the embodiment of the present disclosure.
  • the source-drain metal layer SD includes a first source-drain metal layer SD1 and a second source-drain metal layer SD2; a passivation layer is sandwiched between the first source-drain metal layer SD1 and the second source-drain metal layer SD2
  • the passivation layer PVX and the first planarization layer PLN1 are provided with a second planarization layer PLN2 on the side of the second source-drain metal layer SD2 away from the base substrate BP.
  • the driving layer FA of the display panel PNL according to the embodiment of the present disclosure can also adopt other structures.
  • the source-drain metal layer SD may include one or more metal layers stacked in a stack, and the metal layer may be a metal elemental layer or an alloy layer.
  • the source-drain metal layer SD (for example, the first source-drain metal layer SD1 or the second source-drain metal layer SD2) may include three layers of metal layers such as titanium, aluminum, and titanium that are stacked.
  • the source-drain metal layer SD (for example, the first source-drain metal layer SD1 or the second source-drain metal layer SD2) may include a stacked molybdenum-niobium alloy layer/copper layer/molybdenum-niobium alloy layer.
  • the pixel layer FB may be provided with a light-emitting element electrically connected to the pixel driving circuit PDC, and the light-emitting element may serve as a sub-pixel sub-pixel PIX of the display panel PNL.
  • the pixel layer FB is provided with light-emitting elements distributed in an array, and each light-emitting element emits light under the control of the pixel driving circuit PDC.
  • the light-emitting element may be an organic electroluminescent diode (OLED), a polymer organic electroluminescent diode (PLED), a micro-light emitting diode (Micro LED), or a quantum dot-organic electroluminescent diode (QD-OLED). , quantum dot light-emitting diodes (QLED) or other types of light-emitting components.
  • OLED organic electroluminescent diode
  • PLED polymer organic electroluminescent diode
  • Micro LED micro-light emitting diode
  • QD-OLED quantum dot-organic electroluminescent diode
  • QLED quantum dot light-emitting diodes
  • the display panel PNL is an OLED display panel PNL.
  • the pixel layer FB may be disposed on a side of the driving layer FA away from the base substrate BP, and may include a pixel electrode layer AND, a pixel definition layer PDL, a support pillar layer PS, and an organic light-emitting functional layer EL that are stacked in sequence. and common electrode layer COML.
  • the pixel electrode layer AND has multiple pixel electrodes in the display area of the display panel PNL;
  • the pixel definition layer PDL has multiple through pixel openings in the display area that are arranged in one-to-one correspondence with the multiple pixel electrodes, and any one pixel opening exposes the corresponding at least part of the pixel electrode.
  • the support pillar layer PS includes a plurality of support pillars in the display area, and the support pillars are located on the surface of the pixel definition layer PDL away from the base substrate BP to support the fine metal mask (FMM) during the evaporation process.
  • the organic light-emitting functional layer EL at least covers the pixel electrode exposed by the pixel definition layer PDL.
  • the organic light-emitting functional layer EL may include an organic electroluminescent material layer, and may include one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer. Or multiple.
  • Each film layer of the organic light-emitting functional layer EL can be prepared through an evaporation process, and a fine metal mask or an open mask can be used to define the pattern of each film layer during evaporation.
  • the common electrode layer COML can cover the organic light-emitting functional layer EL in the display area. In this way, the pixel electrode, the common electrode layer COML and the organic light-emitting functional layer EL located between the pixel electrode and the common electrode layer COML form an organic electroluminescent diode, and any organic electroluminescent diode can be used as a sub-pixel of the display panel PNL.
  • the pixel layer FB may also include a light extraction layer located on a side of the common electrode layer COML away from the base substrate BP to enhance the light extraction efficiency of the organic light emitting diode.
  • the display panel PNL may further include a thin film encapsulation layer TFE.
  • the thin film encapsulation layer TFE is provided on the surface of the pixel layer FB away from the base substrate BP, and may include alternately stacked inorganic encapsulation layers and organic encapsulation layers.
  • the touch layer TT is disposed on the side of the thin film encapsulation layer TFE away from the base substrate BP.
  • the inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting functional layer EL and causing material degradation.
  • the edge of the inorganic encapsulation layer may be located in the peripheral area.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.
  • FIG 3 illustrates a schematic structural diagram of the thin film encapsulation layer TFE in one embodiment.
  • the thin film encapsulation layer TFE includes an alternately stacked inorganic encapsulation layer and an organic encapsulation layer.
  • the organic encapsulation layer is sandwiched between two adjacent inorganic encapsulation layers.
  • the film layers closest to the base substrate and farthest from the base substrate are both inorganic encapsulation layers; the edge of the inorganic encapsulation layer exceeds the edge of the organic encapsulation layer, so that the organic encapsulation layer is sealed by the inorganic encapsulation layer.
  • the thin film encapsulation layer includes at least one organic encapsulation layer and at least two inorganic encapsulation layers.
  • the thin film encapsulation layer TFE includes at least two organic encapsulation layers, and includes at least three inorganic encapsulation layers.
  • the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1 , a first organic encapsulation layer IJP1 , a second inorganic encapsulation layer CVD2 , and a second organic encapsulation layer sequentially stacked on the side of the pixel layer FB away from the base substrate BP.
  • Encapsulation layer IJP2 third inorganic encapsulation layer CVD3.
  • the stress distribution of the display panel PNL during bending can be adjusted, and it can cooperate with the touch layer TT to meet the needs of the display panel PNL when bending at large angles. Stress requirements during folding.
  • the touch layer TT includes a touch organic layer OC and a touch metal layer TM buried in the touch organic layer OC.
  • the touch metal layer TM is formed with a touch channel TS and a touch channel TS.
  • the touch channel TS is connected to the touch trace TSW.
  • the touch channel TS can generate a touch signal in response to the touch of a touch object such as a finger, and the touch signal can be transmitted to the control module through the touch wire TSW to locate the touch position.
  • a touch object such as a finger
  • the touch metal layer TM in the touch layer TT is buried in the touch organic layer OC, which makes the organic content in the touch layer TT high, thereby making the display panel PNL It has greater flexibility and bending ability, which is conducive to achieving large-angle bending.
  • the stress distribution of the display panel PNL when bent at a large angle can be adjusted, such as adjusting the maximum stress and neutral layer of the display panel PNL when bent at a large angle, etc. , thereby meeting the stress requirements of the display panel PNL when it is bent at a large angle.
  • the touch organic layer OC includes a first touch organic layer OC1 and a second touch organic layer OC1 which are sequentially stacked on the side of the pixel layer FB away from the base substrate BP.
  • the touch metal layer TM includes a first touch organic layer OC1 and a second touch organic layer OC2 sandwiched between the first touch organic layer OC1 and the second touch organic layer OC2.
  • the touch metal layer TMA includes a second touch metal layer TMB sandwiched between the second touch organic layer OC2 and the third touch organic layer OC3.
  • the touch metal layer TM has two layers of metal, which facilitates the formation of two touch channels TS with intersecting directions.
  • the touch metal layer TM may include one or more metal layers stacked in a stack, and the metal layer may be a metal elemental layer or an alloy layer.
  • the touch metal layer TM eg, the first touch metal layer TMA or the second touch metal layer TMB
  • the touch metal layer TM may include three metal layers such as titanium, aluminum, and titanium that are stacked.
  • the touch metal layer TM eg, the first touch metal layer TMA or the second touch metal layer TMB
  • the material of at least one layer of the touch organic layer OC is optical glue, such as at least one layer of the first touch organic layer OC1, the second touch organic layer OC2, and the third touch organic layer OC3.
  • optical glue such as at least one layer of the first touch organic layer OC1, the second touch organic layer OC2, and the third touch organic layer OC3.
  • a low-temperature process can be used.
  • the materials of the first touch organic layer OC1, the second touch organic layer OC2, and the third touch organic layer OC3 are all optical glue.
  • FIG. 4 illustrates a schematic structural diagram of the touch metal layer TM in an embodiment of the present disclosure.
  • the touch metal layer TM of the touch layer TT is formed with a plurality of touch channels TS.
  • These touch channels TS include a plurality of second signal channels extending along the second direction DH (see Figure 5).
  • Rx intersects a plurality of first signal channels Tx extending along the first direction DV (see FIG. 5 );
  • the second direction DH intersects the first direction DV.
  • one of the second direction DH and the first direction DV is the row direction (the direction in which the scanning lines extend) of the display panel PNL, and the other is the column direction (the direction in which the data voltage lines extend).
  • the second direction DH is the row direction of the display panel PNL
  • the first direction DV is the column direction of the display panel PNL.
  • the second signal channel Rx has a plurality of second signal electrodes RxP arranged sequentially along the second direction DH on the second touch metal layer TMB; two adjacent second signal electrodes The RxPs are electrically connected through the connection portion RxB located in the second touch metal layer TMB; the first signal channel Tx has a plurality of first signal electrodes TxP arranged sequentially along the first direction DV in the second touch metal layer TMB, and A plurality of bridge portions TxB are provided on the first touch metal layer TMA, and two adjacent first signal electrodes TxP are electrically connected through the bridge portions TxB.
  • the bridge portion TxB and the connection portion RxB partially overlap, so that the second signal channel Rx remains continuous in the second touch metal layer TMB, and the first signal The channel Tx is bridged by the first touch metal layer TMA.
  • Each first signal channel Tx and each second signal channel Rx define a plurality of touch positioning areas distributed in an array.
  • the touch capacitance is formed by mutual capacitance between the first signal channel Tx and the second signal channel Rx in the touch positioning area.
  • the capacitance value of the touch capacitor in the touch positioning area will change in response to the touch object (such as a finger), thereby causing the first signal channel Tx and the second signal channel Rx through the touch positioning area to generate Touch signal.
  • the touch position can be determined.
  • the display panel PNL may include a display area AA and a peripheral area BB located on at least one side of the display area AA.
  • the peripheral area BB surrounds the display area AA.
  • a sub-pixel PIX and a pixel driving circuit PDC that drives the sub-pixel PIX are provided, so that the display panel PNL displays a picture in the display area AA.
  • the driving layer FA is provided with a driving voltage bus VDDB for applying a driving voltage to the display area AA and a common voltage bus VSSB for applying a common voltage to the display area AA.
  • the touch trace TSW connected to the touch channel TS may also be at least partially disposed in the peripheral area BB, for example, completely disposed in the peripheral area BB.
  • the peripheral area BB is provided with a pin area PADA
  • the driving layer FA is provided with pins bound and connected to the control module in the pin area PADA.
  • the driving voltage bus VDDB includes a driving voltage access line VDDBA and a driving voltage distribution line VDDBB between the pin area PADA and the display area AA.
  • the display area AA is provided with a driving voltage for loading the pixel driving circuit PDC. Drive voltage trace VDDL.
  • the common voltage bus VSSB may include a common voltage access line VSSBA connected to a common voltage pin located in the pin area PADA, and a common voltage overlap located on both sides of the display area AA (both sides in the row direction).
  • the width of the common voltage access line VSSBA is smaller than the width of the common voltage transfer line VSSBB; when routing, the touch trace TSW can be located on the common voltage bus VSSB to reduce the noise from the display panel. PNL crosstalk improves the accuracy of touch signals.
  • the touch trace TSW can cross the range of the common voltage transfer line VSSBB and extend into the pin area PADA to facilitate the connection of the touch pin PAD located in the pin area PADA.
  • the touch signal generated by the touch channel TS can be transmitted to the touch pin PAD through the touch trace TSW; when each pin in the pin area PADA is connected to the control module, for example, through a flexible circuit board and the control module When the circuit board of the module is connected, the touch signal on the touch channel TS can be transmitted to the control module.
  • the touch trace TSW includes a first touch trace TSWA and a second touch trace TSWB connected to the same touch channel TS.
  • the touch trace TSWA is located on the first touch metal layer TMA
  • the second touch trace TSWB is located on the second touch metal layer TMB.
  • One end of the second touch trace TSWB away from the touch channel TS is connected to the first touch trace TSWA through a via hole.
  • the touch trace TSW includes two sub- traces arranged in parallel, which can reduce the impedance of the touch trace TSW and ensure effective transmission of touch signals.
  • first touch trace TSWA and the second touch trace TSWB are basically the same, so that they overlap each other.
  • One or more additional connection vias may be provided as needed between the first touch trace TSWA and the second touch trace TSWB, so that the first touch trace TSWA and the second touch trace TSWB The connection is more reliable and provides mutual backup, improving the stability of touch wiring TSW.
  • the touch trace TSW can only be provided in the second touch metal layer TMB; the touch trace The TSW can extend out of the third touch organic layer OC3 and be connected to the touch pin PAD.
  • the second touch organic layer OC2 and the first touch organic layer OC1 under the second touch metal layer TMB on the side close to the base substrate BP
  • the second touch The slope at the edge OC2L of the organic layer is relatively large.
  • the second touch metal layer TMB When the second touch metal layer TMB is patterned to form the touch trace TSW, it is easy to form the edge OC2L of the second touch organic layer (for example, in the area EA in Figure 7) There are conductive material residues, which makes short circuits easily occur between the touch traces TSW.
  • the touch organic layer OC exposes the touch pin PAD, and the touch transfer line TRW is away from the end of the touch pin PAD. Extends between the touch organic layer OC and the base substrate BP; the touch trace TSW does not extend out of the touch organic layer OC, and the touch trace TSW passes through the via hole and The end of the touch transfer wire TRW is electrically connected. In this way, in the display panel PNL according to the embodiment of the present disclosure, the touch trace TSW is not directly connected to the touch pin PAD, but is transferred to the touch pin PAD through the touch transfer line TRW located on the driving layer FA.
  • the second touch organic layer OC2 covers the edge of the first touch organic layer OC1, which can reduce the slope of the second touch organic layer OC2 near its edge, thereby reducing the second There is a risk that the touch trace TSWB may be short-circuited near the edge of the second touch organic layer OC2.
  • the edge OC3L of the third touch organic layer OC3 and the edge OC1L of the first touch organic layer OC1 may be flush, which makes the third touch organic layer OC3 and the edge OC1L of the first touch organic layer OC1 flush.
  • the touch organic layer OC1 can share a mask, thereby reducing the manufacturing cost of the display panel.
  • one end of the first touch trace TSWA away from the touch channel TS is electrically connected to the touch transfer line TRW through a via hole, and the second One end of the touch trace TSWB away from the touch channel TS is connected to the first touch trace TSWA through a via hole.
  • the driving layer FA is provided with a common voltage bus VSSB between the touch pin PAD and the display area AA of the display panel PNL (for example, in FIG. 9
  • the common voltage transfer line VSSBB) the common voltage bus VSSB is used to load a common voltage to the pixel layer FB; the via hole between the touch transfer line TRW and the touch trace TSW is located in the Between the common voltage bus VSSB and the touch pin PAD. In this way, the touch trace TSW can obtain as much shielding protection as possible from the common voltage bus VSSB.
  • the touch transfer line TRW is located in the source-drain metal layer SD; the touch transfer line TRW is between the touch pin PAD and the touch organic layer OC. is covered by the passivation layer PVX; further, the edge of the part of the touch transfer line TRW between the touch pin PAD and the touch organic layer OC is covered by the passivation layer PVX .
  • the source-drain metal layer SD includes a first source-drain metal layer SD1 and a second source-drain metal layer SD2 stacked in sequence.
  • the first source-drain metal layer SD1 and the second source-drain metal layer SD2 are stacked in sequence.
  • a passivation layer PVX is sandwiched between the source and drain metal layers SD2.
  • the touch transfer line TRW is provided on the first source-drain metal layer SD1; the part of the touch transfer line TRW between the touch pin PAD and the touch organic layer OC is covered by the passivation layer PVX; In particular, the edge of the portion of the touch transfer line TRW between the touch pin PAD and the touch organic layer OC is covered by the passivation layer PVX.
  • the touch transfer line TRW is protected by the passivation layer PVX; during the patterning process of the first touch metal layer TMA and the second touch metal layer TMB through etching, the touch transfer line TRW will not cause the touch transfer line TRW to The part between the touch pin PAD and the touch organic layer OC is corroded, especially the edge of the touch transfer line TRW can be avoided from being corroded.
  • the second source-drain metal layer SD2 includes a transfer metal portion TRM corresponding to each touch transfer line TRW, and the touch transfer line TRW is far away from the touch transfer line TRW.
  • the end of the touch pin PAD is connected to the corresponding transfer metal part TRM; the end of the touch trace TSW away from the touch channel TS passes through the transfer metal part TRM and the Touch adapter cable TRW connection.
  • the transfer metal portion TRM can protect the touch transfer line TRW on the one hand, and can reduce the step difference between the first touch metal layer TMA and the touch transfer line TRW on the other hand to prevent the first touch trace TSWA from being The via connected to the transfer metal part TRM is disconnected.
  • the transfer metal part TRM overlaps the end of the touch transfer wire TRW away from the touch pin PAD; the touch transfer wire TRW
  • the portion that is not overlapped with the transfer metal portion TRM is covered by the passivation layer PVX.
  • the touch transfer line TRW can be protected by the passivation layer PVX and the second source-drain metal layer SD2, and the touch transfer line TRW is protected during the patterning process of the first touch metal layer TMA and the second touch metal layer TMB. Corrosion of TRW.
  • the passivation layer PVX covers the edge of the touch transfer line TRW to prevent undercutting of the touch transfer line TRW.
  • the second source-drain metal layer SD2 includes a laminated metal part PADM corresponding to each touch pin PAD, and the laminated metal part PADM is connected to the corresponding touch pin PAD.
  • the control pins PAD overlap and are electrically connected.
  • the laminated metal part PADM can protect the touch pin PAD.
  • the orthographic projection of the touch pin PAD on the base substrate BP is located within the orthographic projection of the laminated metal part PADM on the base substrate BP.
  • the passivation layer PVX covers the edge of the touch pin PAD and has one or more opening grooves that expose a partial surface of the touch pin PAD.
  • the line PADML in Figure 10 represents the edge of the laminated metal part PADM located in the second source-drain metal layer SD2; according to the example of Figure 10, the laminated metal part PADM covers each opening groove and covers each edge of the touch pin PAD. . In this way, the laminated metal part PADM and the touch pin PAD are connected through the open groove, and the second source-drain metal layer SD2 will not cause undercutting of the edge of the touch pin PAD during the etching process.
  • the touch metal layer TM also includes a pin protection part PADC corresponding to each touch pin PAD, and the pin protection part PADC is in contact with the corresponding touch pin PAD.
  • the touch pins PAD are overlapped and electrically connected; there is a gap between the pin protection part PADC and the edge of the touch organic layer OC.
  • the pin protection part PADC can protect the touch pin PAD and reduce corrosion to the touch pin PAD.
  • there is a gap between the pin protection part PADC and the edge of the touch organic layer OC which makes the touch metal layer TM discontinuous at the edge of the touch organic layer OC.
  • the orthographic projection of the touch pin PAD on the base substrate BP is located within the orthographic projection of the pin protection part PADC on the base substrate BP; that is, the pin protection part PADC can Completely covers the touch pin PAD.
  • the pin protection part PADC includes a first pin protection part PADCA located on the first touch metal layer TMA and a first pin protection part PADCA located on the second touch metal layer TMB.
  • the second pin protection part is PADCB.
  • the line PADCAL illustrates the edge of the first pin protection part PADCA
  • the line PADCBL illustrates the edge of the second pin protection part PADCB.
  • the touch pin PAD is on the lining.
  • the orthographic projection on the base substrate BP is within the orthographic projection of the first pin protection part PADCA on the base substrate BP; the orthogonal projection of the first pin protection part PADCA on the base substrate BP Projection is within the orthographic projection of the second pin protection part PADCB on the base substrate BP.
  • the orthographic projection of the touch pin PAD on the base substrate BP is within the orthographic projection of the laminated metal part PADM on the base substrate BP; the laminated metal part The orthographic projection of PADM on the base substrate BP is within the orthographic projection of the first pin protection part PADCA on the base substrate BP.
  • the laminated metal part PADM covers the edge of the touch pin PAD; when the second source-drain metal layer SD2 is patterned by etching, the side walls of the touch pin PAD can be prevented from being side-etched.
  • the first pin protection part PADCA covers the edge of the laminated metal part PADM; when the first touch metal layer TMA is patterned by etching, it can prevent the side walls of the touch pin PAD and the laminated metal part PADM from being Lateral erosion.
  • the second pin protection part PADCB covers the edge of the first pin protection part PADCA; when the second touch metal layer TMB is patterned by etching, the touch pin PAD, the laminated metal part PADM and the third pin protection part PADM can be avoided.
  • the side wall of one pin protection part PADCA was undercut.
  • the second touch organic layer OC2 is not provided between the first pin protection part PADCA and the second pin protection part PADCB; the first pin protection part PADCA
  • the first touch organic layer OC1 is not disposed between the touch pin PAD and the touch pin PAD.
  • the touch organic layer OC may not extend into the pin area PADA. This avoids the touch organic layer OC using a low-temperature process from conflicting with the high temperature during bonding, and avoids the touch organic layer OC in the pin area PADA from causing defects during bonding.
  • the adhesion between the touch organic layer OC and the material of the driving layer FA is weak
  • this arrangement can also reduce the risk of film peeling.
  • at least one film layer in the touch organic layer OC such as the first touch organic layer OC1 and the second touch organic layer OC2
  • these film layers need to be set relatively thick; if these film layers also extend to the lead In the foot area PADA, these film layers need to open through holes to electrically connect the metal on the upper and lower layers; then thicker film layers need to open larger through holes, which affects the arrangement density of the pins.
  • the metal layer is prone to breakage.
  • the touch organic layer OC may also be provided in at least part of the pin area PADA.
  • the driving layer FA further includes a planarization layer PLN located on the side of the second source-drain metal layer SD2 away from the base substrate BP; the planarization layer PLN covers all The gap between the boundary of the laminated metal part PADM and the touch organic layer OC.
  • the touch organic layer OC can be raised at the boundary of the touch organic layer OC, and the step difference of the touch organic layer OC near the boundary can be reduced, thereby reducing the distance between the first touch metal layer TMA and the second touch metal layer.
  • the risk of conductive material residues when layer TMB is patterned near the boundary for example, the risk of short circuits between different first touch traces TSWA can be reduced, and the risk of short circuits between different second touch traces TSWB can be reduced.
  • the risk of short circuit is reduced, the risk of short circuit between adjacent first pin protection parts PADCA is reduced, and the risk of short circuit between the second pin protection parts PADCB is reduced.
  • the touch organic layer OC covers a portion of the touch transfer line TRW and is directly formed on the surface of the planarization layer PLN away from the base substrate BP.
  • the display panel PNL is provided with a second planarization layer PLN2 between the second source-drain metal layer SD2 and the pixel layer FB.
  • the second planarization layer PLN2 covers the boundary of the touch organic layer OC and the stacked metal portion. Gap between PADM. Near the boundary of the touch organic layer OC, the touch organic layer OC is directly disposed on the upper surface of the second planarization layer PLN2. The portion of the pin protection part PADC close to the touch organic layer OC overlaps the second planarization layer PLN2.
  • An embodiment of the present disclosure also provides a display device, which includes any of the display panels PNL described in the above display panel embodiments.
  • the display device may be a smartphone screen, a smart watch screen, or other types of display devices. Since the display device has any one of the display panels PNL described in the above embodiments of the display panel PNL, it has the same beneficial effects, which will not be described in detail here.

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Abstract

一种显示面板(PNL)和显示装置。显示面板(PNL)包括依次层叠设置的衬底基板(BP)、驱动层(FA)、像素层(FB)和触控层(TT)；在显示面板(PNL)的外围区(BB)，驱动层(FA)设置有触控引脚(PAD)和与触控引脚(PAD)连接的触控转接线(TRW)；触控层(TT)包括触控有机层(OC)和填埋于触控有机层(OC)中的触控金属层(TM)，触控金属层(TM)形成有触控通道(TS)和与触控通道(TS)连接的触控走线(TSW)；其中，触控有机层(OC)暴露触控引脚(PAD)，且触控转接线(TRW)远离触控引脚(PAD)的端部伸入至触控有机层(OC)与衬底基板(BP)之间；触控走线(TSW)不伸出触控有机层(OC)，且触控走线(TSW)通过过孔与触控转接线(TRW)的端部电连接。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板和显示装置。
背景技术
FMLOC(Flexible Metal Layer on Cell)工艺可以使得显示模组和触控模组合一，进而有效降低显示面板的厚度和成本。然而，采用FMLOC工艺的显示面板中，触控走线之间短路易发生短路不良。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板和显示装置，降低触控走线之间的短路不良。
根据本公开的一个方面，提供一种显示面板，包括依次层叠设置的衬底基板、驱动层、像素层和触控层；在所述显示面板的外围区，所述驱动层设置有触控引脚和与所述触控引脚连接的触控转接线；所述触控层包括触控有机层和填埋于所述触控有机层中的触控金属层，所述触控金属层形成有触控通道和与所述触控通道连接的触控走线；
其中，所述触控有机层暴露所述触控引脚，且所述触控转接线远离所述触控引脚的端部伸入至所述触控有机层与所述衬底基板之间；
所述触控走线不伸出所述触控有机层，且所述触控走线通过过孔与所述触控转接线远离所述触控引脚的端部电连接。
根据本公开的一种实施方式，所述触控有机层包括在所述像素层远离所述衬底基板一侧依次层叠的第一触控有机层、第二触控有机层和第三触控有机层；所述触控金属层包括夹设于所述第一触控有机层和所述第二触控有机层之间的第一触控金属层，以及包括夹设于所述第二触控有机层和 所述第三触控有机层之间的第二触控金属层。
根据本公开的一种实施方式，所述第二触控金属层和所述第一触控金属层形成有所述触控通道；所述触控走线包括连接于同一触控通道的第一触控走线和第二触控走线，所述第一触控走线位于所述第一触控金属层，所述第二触控走线位于所述第二触控金属层；所述第一触控走线远离所述触控通道的一端通过过孔与所述触控转接线电连接，所述第二触控走线远离所述触控通道的一端通过过孔与所述第一触控走线连接。
根据本公开的一种实施方式，所述驱动层在所述触控引脚与所述显示面板的显示区之间设置有公共电压总线，所述公共电压总线用于向所述像素层加载公共电压；
所述触控转接线与所述触控走线之间的过孔，位于所述公共电压总线与所述触控引脚之间。
根据本公开的一种实施方式，所述驱动层包括源漏金属层和用于保护所述源漏金属层的钝化层；
所述触控转接线位于所述源漏金属层；所述触控转接线在所述触控引脚和所述触控有机层之间的部分被所述钝化层覆盖。
根据本公开的一种实施方式，所述源漏金属层包括依次层叠设置于所述衬底基板一侧的第一源漏金属层和第二源漏金属层，所述钝化层位于所述第一源漏金属层和所述第二源漏金属层之间；
所述触控转接线位于所述第一源漏金属层；所述第二源漏金属层包括与各个触控转接线一一对应的转接金属部，所述触控转接线远离所述触控引脚的端部与对应的所述转接金属部连接；
所述触控走线远离所述触控通道的端部，通过所述转接金属部与所述触控转接线连接。
根据本公开的一种实施方式，所述转接金属部搭接于所述触控转接线远离所述触控引脚的端部；所述触控转接线未搭接有所述转接金属部的部分，被所述钝化层覆盖。
根据本公开的一种实施方式，所述触控金属层还包括与各个触控引脚一一对应的引脚保护部，所述引脚保护部与对应的所述触控引脚交叠设置且电连接；所述引脚保护部与所述触控有机层的边缘之间具有间隙。
根据本公开的一种实施方式，所述触控引脚在所述衬底基板上的正投影，位于所述引脚保护部在所述衬底基板上的正投影内。
根据本公开的一种实施方式，所述触控有机层包括在所述像素层远离所述衬底基板一侧依次层叠的第一触控有机层、第二触控有机层和第三触控有机层；所述触控金属层包括夹设于所述第一触控有机层和所述第二触控有机层之间的第一触控金属层，以及包括夹设于所述第二触控有机层和所述第三触控有机层之间的第二触控金属层；
所述引脚保护部包括位于所述第一触控金属层的第一引脚保护部和位于所述第二触控金属层的第二引脚保护部；
所述触控引脚在所述衬底基板上的正投影，在所述第一引脚保护部在所述衬底基板上的正投影内；所述第一引脚保护部在所述衬底基板上的正投影，在所述第二引脚保护部在所述衬底基板上的正投影内。
根据本公开的一种实施方式，所述第一引脚保护部与所述第二引脚保护部之间不设置第二触控有机层；所述第一引脚保护部与所述触控引脚之间不设置第一触控有机层。
根据本公开的一种实施方式，所述源漏金属层包括依次层叠设置于所述衬底基板一侧的第一源漏金属层和第二源漏金属层，所述钝化层位于所述第一源漏金属层和所述第二源漏金属层之间；所述触控引脚和所述触控转接线位于所述第一源漏金属层；
所述第二源漏金属层包括与各个触控引脚一一对应的叠层金属部，所述叠层金属部与对应的所述触控引脚交叠且电连接。
根据本公开的一种实施方式，所述触控引脚在所述衬底基板上的正投影，位于所述叠层金属部在所述衬底基板上的正投影内。
根据本公开的一种实施方式，所述驱动层还包括位于所述第二源漏金属层远离所述衬底基板一侧的平坦化层；
所述平坦化层覆盖所述叠层金属部与所述触控有机层的边界之间的间隙。
根据本公开的一种实施方式，所述触控有机层覆盖所述触控转接线的部分，直接形成于所述平坦化层远离所述衬底基板的表面。
根据本公开的一种实施方式，所述触控金属层还包括与各个触控引脚 一一对应的引脚保护部，所述引脚保护部通过所述叠层金属部与对应的所述触控引脚交叠设置且电连接；
所述引脚保护部与所述触控有机层的边缘之间具有间隙，且所述引脚保护部靠近所述触控有机层的部分搭接于所述平坦化层上。
根据本公开的一种实施方式，所述触控金属层还包括与各个触控引脚一一对应的引脚保护部，所述引脚保护部通过所述叠层金属部与对应的所述触控引脚交叠设置且电连接；
其中，所述叠层金属部在所述衬底基板上的正投影，位于所述引脚保护部在所述衬底基板上的正投影内。
根据本公开的一种实施方式，所述显示面板还包括位于所述像素层与所述触控层之间的薄膜封装层，所述薄膜封装层包括交替层叠设置的无机封装层和有机封装层，所述薄膜封装层包括至少一层有机封装层和至少两层无机封装层。
根据本公开的另一个方面，提供一种显示装置，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种实施方式中，显示面板的结构示意图。
图2为本公开一种实施方式中，显示面板的结构示意图。
图3为本公开一种实施方式中，显示面板的结构示意图。
图4为本公开一种实施方式中，触控金属层的结构示意图。
图5为本公开一种实施方式中，显示面板的结构示意图。
图6为相关技术中，显示面板在临近引脚区的结构示意图。
图7为相关技术中，显示面板在临近引脚区的结构示意图。
图8为本公开一种实施方式中，显示面板在临近引脚区的结构示意图。
图9为本公开一种实施方式中，显示面板在临近引脚区的结构示意图。
图10为本公开一种实施方式中，触控引脚上各层金属的结构示意图。
图11为本公开一种实施方式中，显示面板在临近引脚区的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
结构层A位于结构层B背离衬底基板的一侧，可以理解为，结构层A在结构层B背离衬底基板的一侧形成。当结构层B为图案化结构时，结构层A的部分结构也可以位于结构层B的同一物理高度或低于结构层B的物理高度，其中，衬底基板为高度基准。
本公开提供一种显示面板。参见图1，本公开实施方式中显示面板PNL 包括依次层叠设置的衬底基板BP、驱动层FA、像素层FB和触控层TT。其中，像素层FB设置有用于显示的子像素，驱动层FA设置有用于驱动子像素的像素驱动电路PDC，触控层TT设置有用于实现触控的触控通道TS。
在本公开的一些实施方式中，衬底基板BP可以为柔性衬底基板，其材料可以包括柔性的有机材料，例如可以包括一层或者多层聚酰亚胺层。这样，本公开的显示面板PNL可以为柔性显示面板PNL或者可弯折显示面板PNL，该显示面板可以应用于可弯折显示装置或者多边曲显示装置中，例如应用于可弯折手机或者应用于四边曲手机中。当然的，在本公开的其他实施方式中，显示面板PNL也可以为刚性显示面板PNL，此时衬底基板BP可以选择玻璃、金属等无机材料，或者选择高硬度的有机材料。
图2为本公开实施方式中显示面板PNL的一种局部结构示意图。参见图1和图2，驱动层FA设置有用于驱动子像素的像素驱动电路PDC。在驱动层FA中，任意一个像素驱动电路PDC可以包括有晶体管和存储电容。进一步地，晶体管可以为薄膜晶体管，薄膜晶体管可以选自顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。
可以理解的是，像素驱动电路PDC中的各个晶体管中，任意两个晶体管之间的类型可以相同或者不相同。示例性地，在一种实施方式中，在一个像素驱动电路PDC中，部分晶体管可以为N型晶体管且部分晶体管可以为P型晶体管。再示例性地，在本公开的另一种实施方式中，在一个像素驱动电路PDC中，部分晶体管的有源层的材料可以为低温多晶硅半导体材料，且部分晶体管的有源层的材料可以为金属氧化物半导体材料。在本公开的一些实施方式中，薄膜晶体管均为低温多晶硅晶体管。在本公开的另外一些实施方式中，部分薄膜晶体管为低温多晶硅晶体管，部分薄膜晶体管为金属氧化物晶体管。
可选地，驱动层FA可以包括层叠于衬底基板BP和像素层FB之间的 半导体层SEMI、栅极绝缘层GI、栅极层GT、层间电介质层ILD和源漏金属层SD等。各个薄膜晶体管和存储电容可以由半导体层SEMI、栅极绝缘层GI、栅极层GT、层间电介质层ILD、源漏金属层SD等膜层形成。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。进一步地，半导体层SEMI可以用于形成晶体管的沟道区；栅极层可以用于形成扫描走线、复位控制走线、发光控制走线等栅极层走线，也可以用于形成晶体管的栅极，还可以用于形成存储电容的部分或者全部电极板；源漏金属层可以用于形成数据电压走线、驱动电压走线等源漏金属层走线，也可以用于形成存储电容的部分电极板。
在一种示例中，驱动层FA可以包括依次层叠设置的半导体层SEMI、栅极绝缘层GI、栅极层GT、层间电介质层ILD和源漏金属层SD，如此所形成的薄膜晶体管为顶栅型薄膜晶体管。
在另一种示例中，在驱动层FA可以包括依次层叠设置的栅极层GT、栅极绝缘层GI、半导体层SEMI、层间电介质层ILD和源漏金属层SD，如此所形成的薄膜晶体管为底栅型薄膜晶体管。
在本公开实施方式的显示面板PNL中，栅极层可以为一层，也可以根据需要设置为两层或者三层。在一种示例中，栅极层GT可以包括第一栅极层和第二栅极层，栅极绝缘层GI可以包括用于隔离半导体层SEMI和第一栅极层的第一栅极绝缘层，以及包括用于隔离第一栅极层和第二栅极层的第二栅极绝缘层。举例而言，驱动层FA可以包括依次层叠设置于衬底基板BP一侧的半导体层SEMI、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层ILD和源漏金属层SD。在一种示例中，栅极层GT可以包括第一栅极层和第二栅极层，半导体层SEMI可以夹设于第一栅极层和第二栅极层之间；栅极绝缘层GI可以包括用于隔离半导体层SEMI和第一栅极层的第一栅极绝缘层，以及包括用于隔离第二栅极层和半导体层SEMI的第二栅极绝缘层。举例而言，驱动层FA可以包括依次层叠设置于衬底基板BP一侧的第一栅极层、第一栅极绝缘层、半导体层SEMI、第二栅极绝缘层、第二栅极层、层间电介质层ILD和源漏金属层SD。这样，可以形成具有双栅结构的晶体管。在一种示例中，半导体层SEMI可以包括低温多晶硅半导体层和金属氧化物半导体层； 栅极层包括第一栅极层和第二栅极层，栅极绝缘层包括第一至第三栅极绝缘层。驱动层FA可以包括依次层叠设置于衬底基板BP一侧的低温多晶硅半导体层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、金属氧化物半导体层、第三栅极绝缘层、第二栅极层、层间电介质层ILD和源漏金属层SD。在一种示例中，半导体层SEMI可以包括低温多晶硅半导体层和金属氧化物半导体层；栅极层包括第一至第三栅极层，栅极绝缘层包括第一至第三栅极绝缘层。驱动层FA可以包括依次层叠设置于衬底基板BP一侧的低温多晶硅半导体层、第一栅极绝缘层、第一栅极层、绝缘缓冲层、第二栅极层、第二栅极绝缘层、金属氧化物半导体层、第三栅极绝缘层、第三栅极层、层间电介质层ILD和源漏金属层SD。
在本公开实施方式的显示面板PNL中，源漏金属层可以为一层，也可以根据需要设置为两层或者三层。在一种示例中，源漏金属层可以包括依次层叠于层间电介质层ILD远离衬底基板一侧的第一源漏金属层和第二源漏金属层，第一源漏金属层和第二源漏金属层之间可以夹设有绝缘层，例如夹设有钝化层和/或平坦化层。在另一种示例中，源漏金属层可以包括依次层叠于层间电介质层ILD远离衬底基板一侧的第一源漏金属层、第二源漏金属层、第三源漏金属层；第一源漏金属层和第二源漏金属层之间可以夹设有绝缘层，例如夹设有钝化层和/或树脂层；第二源漏金属层和第三源漏金属层之间可以夹设有绝缘层，例如夹设有钝化层和/或平坦化层。
可选地，驱动层FA还可以包括有钝化层，钝化层可以设于源漏金属层SD远离衬底基板BP的表面，以便保护源漏金属层SD。
可选地，驱动层FA还可以包括设于衬底基板BP与半导体层SEMI之间的缓冲材料层Buff，且半导体层SEMI、栅极层GT等均位于缓冲材料层远离衬底基板BP的一侧。缓冲材料层的材料可以为氧化硅、氮化硅等无机绝缘材料。缓冲材料层可以为一层无机材料层，也可以为多层层叠的无机材料层。
可选地，驱动层FA还可以包括位于源漏金属层SD和像素层FB之间的平坦化层，平坦化层可以为像素电极提供平坦化表面。可选地，平坦化层平坦化层PLN的材料可以为有机材料。
图2仅仅示例了本公开实施方式的显示面板PNL的驱动层FA的一种 方式。在该示例中，源漏金属层SD包括第一源漏金属层SD1和第二源漏金属层SD2；第一源漏金属层SD1和第二源漏金属层SD2之间夹设有钝化层钝化层PVX和第一平坦化层PLN1，在第二源漏金属层SD2远离所述衬底基板BP的一侧设置有第二平坦化层PLN2。可以理解的是，本公开实施方式的显示面板PNL的驱动层FA还可以采用其他结构。
在本公开的一种实施方式中，源漏金属层SD可以包括层叠设置的一层或者多层金属层，金属层可以金属单质层或者合金层。举例而言，在一种示例中，源漏金属层SD(例如第一源漏金属层SD1或者第二源漏金属层SD2)可以包括层叠设置的钛铝钛等三层金属层。在另一种示例中，源漏金属层SD(例如第一源漏金属层SD1或者第二源漏金属层SD2)可以包括层叠设置的钼铌合金层/铜层/钼铌合金层。
参见图1，像素层FB可以设置有与像素驱动电路PDC对应电连接的发光元件，发光元件可以作为显示面板PNL的子像素子像素PIX。如此，像素层FB设置有阵列分布的发光元件，且各个发光元件在像素驱动电路PDC的控制下发光。在本公开中，发光元件可以为有机电致发光二极管(OLED)、高分子有机电致发光二极管(PLED)、微发光二极管(Micro LED)、量子点-有机电致发光二极管(QD-OLED)、量子点发光二极管(QLED)或者其他类型的发光元件。示例性地，发光元件为有机电致发光二极管(OLED)，则该显示面板PNL为OLED显示面板PNL。如下，以发光元件为有机电致发光二极管为例，对像素层FB的一种可行结构进行示例性的介绍。
在该示例中，像素层FB可以设置于驱动层FA远离衬底基板BP的一侧，其可以包括依次层叠设置的像素电极层AND、像素定义层PDL、支撑柱层PS、有机发光功能层EL和公共电极层COML。其中，像素电极层AND在显示面板PNL的显示区具有多个像素电极；像素定义层PDL在显示区具有与多个像素电极一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。支撑柱层PS在显示区包括多个支撑柱，且支撑柱位于像素定义层PDL远离衬底基板BP的表面，以便在蒸镀制程中支撑精细金属掩模版(Fine Metal Mask，FMM)。有机发光功能层EL至少覆盖被像素定义层PDL所暴露的像素电极。其中，有 机发光功能层EL可以包括有机电致发光材料层，以及可以包括有空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一种或者多种。可以通过蒸镀工艺制备有机发光功能层EL的各个膜层，且在蒸镀时可以采用精细金属掩模版或者开放式掩膜板(Open Mask)定义各个膜层的图案。公共电极层COML在显示区可以覆盖有机发光功能层EL。如此，像素电极、公共电极层COML和位于像素电极和公共电极层COML之间的有机发光功能层EL形成有机发电致光二极管，任意一个有机电致发光二极管可以作为显示面板PNL的一个子像素。
可选的，像素层FB还可以包括位于公共电极层COML远离衬底基板BP一侧的光取出层，以增强有机发光二极管的出光效率。
在本公开的一种实施方式中，参见图1和图2，显示面板PNL还可以包括薄膜封装层TFE。薄膜封装层TFE设于像素层FB远离衬底基板BP的表面，可以包括交替层叠设置的无机封装层和有机封装层。触控层TT设置于薄膜封装层TFE远离衬底基板BP的一侧。其中，无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵有机发光功能层EL而导致材料降解。可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间，以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的边缘，可以位于显示区的边缘和无机封装层的边缘之间。
图3示例了一种实施方式中薄膜封装层TFE的结构示意图。薄膜封装层TFE包括交替层叠设置的无机封装层和有机封装层，有机封装层夹设于相邻两层无机封装层之间。其中，最靠近衬底基板和最远离衬底基板的膜层均为无机封装层；无机封装层的边缘超出有机封装层的边缘，以使得有机封装层被无机封装层封闭。这样，所述薄膜封装层包括至少一层有机封装层和至少两层无机封装层。在本公开一种实施方式中，薄膜封装层TFE包括至少两层有机封装层，则至少包括三层无机封装层。在图3的示例中，薄膜封装层TFE包括依次层叠于像素层FB远离衬底基板BP一侧的第一无机封装层CVD1、第一有机封装层IJP1、第二无机封装层CVD2、第二有机封装层IJP2、第三无机封装层CVD3。这样通过增减新的无机封装层和有机封装层，不仅可以提高封装效果，而且可以调整显示面板PNL在 弯折时的应力分布，能够与触控层TT配合以满足显示面板PNL在大角度弯折时的应力需求。
参见图1，所述触控层TT包括触控有机层OC和填埋于所述触控有机层OC中的触控金属层TM，所述触控金属层TM形成有触控通道TS和与所述触控通道TS连接的触控走线TSW。如此，触控通道TS可以响应手指等触控物的触摸而产生触控信号，该触控信号可以通过触控走线TSW传输至控制模组中以定位触控位置。在本公开的实施方式中，参见图1，触控层TT中的触控金属层TM填埋于触控有机层OC中，这使得触控层TT中的有机物含量高，进而使得显示面板PNL具有更大的柔性和可弯折能力，利于实现大角度弯折。
进一步的，通过触控层TT和薄膜封装层TFE的配合，可以调节显示面板PNL在大角度弯折时的应力分布，例如调整显示面板PNL在大角度弯折时的最大应力和中性层等，进而满足显示面板PNL在大角度弯折时的应力需求。
在本公开的一种实施方式中，参见图3，所述触控有机层OC包括在所述像素层FB远离所述衬底基板BP一侧依次层叠的第一触控有机层OC1、第二触控有机层OC2和第三触控有机层OC3；所述触控金属层TM包括夹设于所述第一触控有机层OC1和所述第二触控有机层OC2之间的第一触控金属层TMA，以及包括夹设于所述第二触控有机层OC2和所述第三触控有机层OC3之间的第二触控金属层TMB。如此，触控金属层TM具有两层金属而利于形成方向相交的两种触控通道TS。
在本公开的一种实施方式中，触控金属层TM可以包括层叠设置的一层或者多层金属层，金属层可以金属单质层或者合金层。举例而言，在一种示例中，触控金属层TM(例如第一触控金属层TMA或者第二触控金属层TMB)可以包括层叠设置的钛铝钛等三层金属层。在另一种示例中，触控金属层TM(例如第一触控金属层TMA或者第二触控金属层TMB)可以包括层叠设置的钼铌合金层/铜层/钼铌合金层。
在一种示例中，触控有机层OC中至少一层的材料为光学胶，例如第一触控有机层OC1、第二触控有机层OC2和第三触控有机层OC3中的至少一层为光学胶。进一步的，在制备触控有机层OC时，可以采用低温工 艺进行制备。可选的，第一触控有机层OC1、第二触控有机层OC2和第三触控有机层OC3的材料均为光学胶。
图4示例了本公开一种实施方式中触控金属层TM的结构示意图。参见图3和图4，触控层TT的触控金属层TM形成有多个触控通道TS，这些触控通道TS包括多个沿第二方向DH(参见图5)延伸的第二信号通道Rx和多个沿第一方向DV(参见图5)延伸的第一信号通道Tx；第二方向DH和第一方向DV相交。在一种示例中，第二方向DH和第一方向DV中的一个为显示面板PNL的行方向(扫描走线延伸的方向)，另一个为列方向(数据电压走线延伸的方向)。示例性的，第二方向DH为显示面板PNL的行方向，第一方向DV为显示面板PNL的列方向。
参见图3和图4，在该示例中，第二信号通道Rx在第二触控金属层TMB具有沿第二方向DH依次排列的多个第二信号电极RxP；相邻两个第二信号电极RxP之间通过位于第二触控金属层TMB的连接部RxB电连接；第一信号通道Tx在第二触控金属层TMB具有沿第一方向DV依次排列的多个第一信号电极TxP，且在第一触控金属层TMA设置有多个桥接部TxB，相邻两个第一信号电极TxP之间通过桥接部TxB电连接。其中，在第一信号通道Tx和第二信号通道Rx相交处，桥接部TxB和连接部RxB部分交叠，使得第二信号通道Rx在第二触控金属层TMB保持连续，且使得第一信号通道Tx通过第一触控金属层TMA桥接。各个第一信号通道Tx和各个第二信号通道Rx限定出阵列分布的多个触控定位区。通过触控定位区的第一信号通道Tx和第二信号通道Rx之间互容而形成触控电容。在触控时，触控定位区内的触控电容的电容值会响应触控物(例如手指)而改变，进而使得通过该触控定位区的第一信号通道Tx和第二信号通道Rx产生触控信号。通过检测产生触控信号的第一信号通道Tx和第二信号通道Rx，进而可以确定触控位置。
参见图5，本公开实施方式中，显示面板PNL可以包括显示区AA和位于显示区AA至少一侧的外围区BB，例如外围区BB围绕显示区AA。在显示区AA中，设置有子像素PIX和驱动子像素PIX的像素驱动电路PDC，以使得显示面板PNL在显示区AA显示画面。在外围区BB，驱动层FA设置有用于向显示区AA加载驱动电压的驱动电压总线VDDB和向 显示区AA加载公共电压的公共电压总线VSSB。本公开实施方式中与触控通道TS连接的触控走线TSW也可以至少部分设置于外围区BB，例如完全设置于外围区BB。
参见图5，在外围区BB设置有引脚区PADA，驱动层FA在引脚区PADA中设置有与控制模组绑定连接的引脚。在一种示例中，驱动电压总线VDDB在引脚区PADA和显示区AA之间包括驱动电压接入线VDDBA和驱动电压分布线VDDBB，显示区AA设置有用于向像素驱动电路PDC加载驱动电压的驱动电压走线VDDL。其中，驱动电压接入线VDDBA一端连接位于引脚区PADA中的驱动电压引脚，另一端连接靠近显示区AA设置的驱动电压分布线VDDBB；驱动电压走线VDDL延伸至外围区BB并与驱动电压分布线VDDBB连接。这样，加载至驱动电压引脚上的驱动电压可以通过驱动电压接入线VDDBA和驱动电压分布线VDDBB加载至驱动电压走线VDDL上。在一种示例中，公共电压总线VSSB可以包括与位于引脚区PADA中的公共电压引脚连接的公共电压接入线VSSBA、位于显示区AA两侧(行方向两侧)的公共电压搭接线VSSBC，以及连接公共电压接入线VSSBA和公共电压搭接线VSSBC的公共电压转接线VSSBB。公共电极的两侧可以搭接于公共电压搭接线VSSBC上，进而使得加载至公共电极引脚上的公共电压可以加载至公共电极。
在一种示例中，参见图5，公共电压接入线VSSBA的宽度小于公共电压转接线VSSBB的宽度；触控走线TSW在走线时，可以位于公共电压总线VSSB上以减小来自显示面板PNL的串扰，提高触控信号的准确性。在临近引脚区PADA时，触控走线TSW可以跨出公共电压转接线VSSBB的范围并延伸至引脚区PADA中，以便于位于引脚区PADA中的触控引脚PAD连接。这样，触控通道TS产生的触控信号可以通过触控走线TSW传输至触控引脚PAD；当引脚区PADA中的各个引脚与控制模组连接时，例如通过柔性电路板与控制模组的电路板连接时，触控通道TS上的触控信号可以传输至控制模组。
在本公开的一种实施方式中，参见图8，所述触控走线TSW包括连接于同一触控通道TS的第一触控走线TSWA和第二触控走线TSWB，所述第一触控走线TSWA位于所述第一触控金属层TMA，所述第二触控走 线TSWB位于所述第二触控金属层TMB。所述第二触控走线TSWB远离所述触控通道TS的一端通过过孔与所述第一触控走线TSWA连接。这样，触控走线TSW包括并联设置的两条子走线，可以减小触控走线TSW的阻抗进而保证触控信号的有效传输。进一步的，第一触控走线TSWA和第二触控走线TSWB的延伸轨迹基本一致，以使得两者相互交叠设置。在第一触控走线TSWA和第二触控走线TSWB之间可以根据需要额外设置一个或者多个连接过孔，以使得第一触控走线TSWA和第二触控走线TSWB之间连接更可靠并互为备份，提高触控走线TSW的稳定性。
在相关技术中，参见图6和图7，在触控走线TSW靠近触控引脚PAD的一端，触控走线TSW可以仅设置于第二触控金属层TMB中；该触控走线TSW可以伸出第三触控有机层OC3并连接至触控引脚PAD。然而，由于第二触控金属层TMB下方(靠近衬底基板BP的一侧)设置有第二触控有机层OC2、第一触控有机层OC1等多种有机层，这使得第二触控有机层的边缘OC2L处的坡度较大，第二触控金属层TMB在图案化以形成触控走线TSW时在第二触控有机层的边缘OC2L处(例如图7中区域EA内)容易有导电材料残留，这使得触控走线TSW之间容易发生短路。
在本公开的实施方式中，参见图8和图9，所述触控有机层OC暴露所述触控引脚PAD，且所述触控转接线TRW远离所述触控引脚PAD的端部伸入至所述触控有机层OC与所述衬底基板BP之间；所述触控走线TSW不伸出所述触控有机层OC，且所述触控走线TSW通过过孔与所述触控转接线TRW的端部电连接。这样，本公开实施方式的显示面板PNL中，触控走线TSW不直接连接至触控引脚PAD，而是通过位于驱动层FA的触控转接线TRW转接至触控引脚PAD。这可以避免触控转接线TRW伸出触控有机层OC时因第一触控有机层的边缘OC1L或者第二触控有机层的边缘OC2L处的坡度太大而导致触控转接线TRW短路，进而确保了触控通道TS信号可以有效传输至触控引脚PAD。
在本公开的一种实施方式中，第二触控有机层OC2包覆第一触控有机层OC1的边缘，这可以减少第二触控有机层OC2在临近其边缘的坡度，进而降低第二触控走线TSWB在临近第二触控有机层OC2的边缘处发生短路的风险。
在本公开的一种实施方式中，参见图11，第三触控有机层OC3的边缘OC3L和第一触控有机层OC1的边缘OC1L可以齐平，这使得第三触控有机层OC3和第一触控有机层OC1可以共用掩膜版，进而降低显示面板的制备成本。
在本公开的一种实施方式中，参见图8，所述第一触控走线TSWA远离所述触控通道TS的一端通过过孔与所述触控转接线TRW电连接，所述第二触控走线TSWB远离所述触控通道TS的一端通过过孔与所述第一触控走线TSWA连接。
在本公开的一种实施方式中，参见图8，所述驱动层FA在所述触控引脚PAD与所述显示面板PNL的显示区AA之间设置有公共电压总线VSSB(例如图9中的公共电压转接线VSSBB)，所述公共电压总线VSSB用于向所述像素层FB加载公共电压；所述触控转接线TRW与所述触控走线TSW之间的过孔，位于所述公共电压总线VSSB与所述触控引脚PAD之间。这样，可以使得触控走线TSW尽可能多的获得公共电压总线VSSB的屏蔽保护。
在本公开的一些实施方式中，所述触控转接线TRW位于所述源漏金属层SD；所述触控转接线TRW在所述触控引脚PAD和所述触控有机层OC之间的部分被所述钝化层PVX覆盖；进一步的，所述触控转接线TRW在所述触控引脚PAD和所述触控有机层OC之间的部分，其边缘被钝化层PVX覆盖。
在本公开的一种实施方式中，参见图8，源漏金属层SD包括依次层叠设置的第一源漏金属层SD1和第二源漏金属层SD2，第一源漏金属层SD1和第二源漏金属层SD2之间夹设有钝化层PVX。触控转接线TRW设置于第一源漏金属层SD1；触控转接线TRW在所述触控引脚PAD和所述触控有机层OC之间的部分，被所述钝化层PVX覆盖；尤其是，触控转接线TRW在所述触控引脚PAD和所述触控有机层OC之间的部分，其边缘被钝化层PVX覆盖。这样，触控转接线TRW被钝化层PVX保护；第一触控金属层TMA和第二触控金属层TMB在通过刻蚀进行图案化的过程中，不会导致触控转接线TRW在触控引脚PAD和触控有机层OC之间的部分被腐蚀，尤其是可以避免触控转接线TRW的边缘被腐蚀。
在本公开的一种实施方式中，参见图8，所述第二源漏金属层SD2包括与各个触控转接线TRW一一对应的转接金属部TRM，所述触控转接线TRW远离所述触控引脚PAD的端部与对应的所述转接金属部TRM连接；所述触控走线TSW远离所述触控通道TS的端部，通过所述转接金属部TRM与所述触控转接线TRW连接。如此，转接金属部TRM一方面可以保护触控转接线TRW，另一方面可以减小第一触控金属层TMA与触控转接线TRW之间的段差，避免第一触控走线TSWA在连接至转接金属部TRM的过孔中断路。
在本公开的一种实施方式中，参见图8，所述转接金属部TRM搭接于所述触控转接线TRW远离所述触控引脚PAD的端部；所述触控转接线TRW未搭接有所述转接金属部TRM的部分，被所述钝化层PVX覆盖。如此，可以使得触控转接线TRW受到钝化层PVX和第二源漏金属层SD2的保护，第一触控金属层TMA和第二触控金属层TMB的图案化过程中对触控转接线TRW的腐蚀。进一步的，参见图10，在未被第二源漏金属层SD2覆盖的部分，钝化层PVX覆盖触控转接线TRW的边缘，以避免触控转接线TRW发生侧蚀。
在本公开的一种实施方式中，所述第二源漏金属层SD2包括与各个触控引脚PAD一一对应的叠层金属部PADM，所述叠层金属部PADM与对应的所述触控引脚PAD交叠且电连接。如此，叠层金属部PADM可以保护触控引脚PAD。进一步的，所述触控引脚PAD在所述衬底基板BP上的正投影，位于所述叠层金属部PADM在所述衬底基板BP上的正投影内。
在一种示例中，参见图10，钝化层PVX包覆触控引脚PAD的边缘，且具有暴露触控引脚PAD的局部表面的一个或者多个开口槽。图10中线条PADML表示位于第二源漏金属层SD2的叠层金属部PADM的边缘；根据图10的示例，叠层金属部PADM覆盖各个开口槽，且包覆触控引脚PAD的各个边缘。这样，叠层金属部PADM与触控引脚PAD之间通过开口槽连接，第二源漏金属层SD2在刻蚀过程中不会导致触控引脚PAD的边缘发生侧蚀。
在本公开的一种实施方式中，参见图8，所述触控金属层TM还包括与各个触控引脚PAD一一对应的引脚保护部PADC，所述引脚保护部 PADC与对应的所述触控引脚PAD交叠设置且电连接；所述引脚保护部PADC与所述触控有机层OC的边缘之间具有间隙。如此，在触控金属层TM图案化过程中，引脚保护部PADC可以保护触控引脚PAD，减少对触控引脚PAD的腐蚀。同时，引脚保护部PADC与触控有机层OC的边缘之间具有间隙，这使得触控金属层TM在触控有机层OC的边缘处不连续，因此即便触控有机层OC的边缘之间残留有导电材料也不会导致不同引脚保护部PADC之间电连接，在保证对触控引脚PAD的保护的同时避免了触控引脚PAD间的短路。进一步的，所述触控引脚PAD在所述衬底基板BP上的正投影，位于所述引脚保护部PADC在所述衬底基板BP上的正投影内；即引脚保护部PADC可以完全覆盖触控引脚PAD。
在一种示例中，参见图8和图10，所述引脚保护部PADC包括位于所述第一触控金属层TMA的第一引脚保护部PADCA和位于所述第二触控金属层TMB的第二引脚保护部PADCB。在图10中，线条PADCAL示意出了第一引脚保护部PADCA的边缘，线条PADCBL示意出了第二引脚保护部PADCB的边缘；参见图10，所述触控引脚PAD在所述衬底基板BP上的正投影，在所述第一引脚保护部PADCA在所述衬底基板BP上的正投影内；所述第一引脚保护部PADCA在所述衬底基板BP上的正投影，在所述第二引脚保护部PADCB在所述衬底基板BP上的正投影内。
更进一步地，所述触控引脚PAD在所述衬底基板BP上的正投影，在所述叠层金属部PADM在所述衬底基板BP上的正投影内；所述叠层金属部PADM在所述衬底基板BP上的正投影，在所述第一引脚保护部PADCA在所述衬底基板BP上的正投影内。
如此，叠层金属部PADM包覆触控引脚PAD的边缘；在第二源漏金属层SD2通过刻蚀进行图案化时，可以避免触控引脚PAD的侧壁被侧蚀。第一引脚保护部PADCA包覆叠层金属部PADM的边缘；在第一触控金属层TMA通过刻蚀进行图案化时，可以避免触控引脚PAD和叠层金属部PADM的侧壁被侧蚀。第二引脚保护部PADCB包覆第一引脚保护部PADCA的边缘；在第二触控金属层TMB通过刻蚀进行图案化时，可以避免触控引脚PAD、叠层金属部PADM和第一引脚保护部PADCA的侧壁被侧蚀。
在本公开的一种实施方式中，所述第一引脚保护部PADCA与所述第二引脚保护部PADCB之间不设置第二触控有机层OC2；所述第一引脚保护部PADCA与所述触控引脚PAD之间不设置第一触控有机层OC1。换言之，触控有机层OC可以不延伸至引脚区PADA中。这避免了采用低温工艺的触控有机层OC与绑定时的高温相冲突，避免了引脚区PADA中具有触控有机层OC而在绑定时出现不良。另外，当触控有机层OC与驱动层FA的材料(例如驱动层FA中的有机层)的附着力较弱时，该设置还可以减小出现膜层剥离的风险。不仅如此，在一些情形下，触控有机层OC中的至少一个膜层，例如第一触控有机层OC1、第二触控有机层OC2需要设置的比较厚；如果这些膜层也延伸至引脚区PADA中，这些膜层需要开设通孔以使得上下层的金属电连接；然后较厚的膜层需要开设较大的通孔而影响引脚的排布密度，较深的通孔内的金属层容易出现断路。这些均会降低显示面板PNL的良率和信赖性；该实施方式中通过在引脚区PADA中不设置触控有机层OC而规避了这些风险。当然的，在本公开的其他实施方式中，在有需要时，在引脚区PADA的至少部分区域也可以设置触控有机层OC。
在本公开的一种实施方式中，所述驱动层FA还包括位于所述第二源漏金属层SD2远离所述衬底基板BP一侧的平坦化层PLN；所述平坦化层PLN覆盖所述叠层金属部PADM与所述触控有机层OC的边界之间的间隙。如此，可以在触控有机层OC的边界处抬高触控有机层OC，减小触控有机层OC在临近边界处的段差，进而减小第一触控金属层TMA、第二触控金属层TMB在临近边界处进行图案化时产生导电材料残留的风险；例如，可以减小不同的第一触控走线TSWA之间短路的风险，减小不同的第二触控走线TSWB之间短路的风险，减小相邻第一引脚保护部PADCA之间短路的风险，以及减小第二引脚保护部PADCB之间短路的风险。
进一步的，所述触控有机层OC覆盖所述触控转接线TRW的部分，直接形成于所述平坦化层PLN远离所述衬底基板BP的表面。
进一步的，所述引脚保护部PADC与所述触控有机层OC的边缘之间具有间隙，且所述引脚保护部PADC靠近所述触控有机层OC的部分搭接于所述平坦化层PLN上。
作为一种示例，显示面板PNL在第二源漏金属层SD2与像素层FB之间设置有第二平坦化层PLN2，第二平坦化层PLN2覆盖触控有机层OC的边界与叠层金属部PADM之间的间隙。在临近触控有机层OC的边界处，触控有机层OC直接设置在第二平坦化层PLN2的上表面。引脚保护部PADC靠近触控有机层OC的部分，搭接于第二平坦化层PLN2上。
本公开实施方式还提供一种显示装置，该显示装置包括上述显示面板实施方式所描述的任意一种显示面板PNL。该显示装置可以为智能手机屏幕、智能手表屏幕或者其他类型的显示装置。由于该显示装置具有上述显示面板PNL实施方式所描述的任意一种显示面板PNL，因此具有相同的有益效果，本公开在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (19)

  1. 一种显示面板，包括依次层叠设置的衬底基板、驱动层、像素层和触控层；在所述显示面板的外围区，所述驱动层设置有触控引脚和与所述触控引脚连接的触控转接线；所述触控层包括触控有机层和填埋于所述触控有机层中的触控金属层，所述触控金属层形成有触控通道和与所述触控通道连接的触控走线；
    其中，所述触控有机层暴露所述触控引脚，且所述触控转接线远离所述触控引脚的端部伸入至所述触控有机层与所述衬底基板之间；
    所述触控走线不伸出所述触控有机层，且所述触控走线通过过孔与所述触控转接线远离所述触控引脚的端部电连接。
  2. 根据权利要求1所述的显示面板，其中，所述触控有机层包括在所述像素层远离所述衬底基板一侧依次层叠的第一触控有机层、第二触控有机层和第三触控有机层；所述触控金属层包括夹设于所述第一触控有机层和所述第二触控有机层之间的第一触控金属层，以及包括夹设于所述第二触控有机层和所述第三触控有机层之间的第二触控金属层。
  3. 根据权利要求2所述的显示面板，其中，所述第二触控金属层和所述第一触控金属层形成有所述触控通道；所述触控走线包括连接于同一触控通道的第一触控走线和第二触控走线，所述第一触控走线位于所述第一触控金属层，所述第二触控走线位于所述第二触控金属层；所述第一触控走线远离所述触控通道的一端通过过孔与所述触控转接线电连接，所述第二触控走线远离所述触控通道的一端通过过孔与所述第一触控走线连接。
  4. 根据权利要求1所述的显示面板，其中，所述驱动层在所述触控引脚与所述显示面板的显示区之间设置有公共电压总线，所述公共电压总线用于向所述像素层加载公共电压；
    所述触控转接线与所述触控走线之间的过孔，位于所述公共电压总线与所述触控引脚之间。
  5. 根据权利要求1所述的显示面板，其中，所述驱动层包括源漏金属层和用于保护所述源漏金属层的钝化层；
    所述触控转接线位于所述源漏金属层；所述触控转接线在所述触控引 脚和所述触控有机层之间的部分被所述钝化层覆盖。
  6. 根据权利要求5所述的显示面板，其中，所述源漏金属层包括依次层叠设置于所述衬底基板一侧的第一源漏金属层和第二源漏金属层，所述钝化层位于所述第一源漏金属层和所述第二源漏金属层之间；
    所述触控转接线位于所述第一源漏金属层；所述第二源漏金属层包括与各个触控转接线一一对应的转接金属部，所述触控转接线远离所述触控引脚的端部与对应的所述转接金属部连接；
    所述触控走线远离所述触控通道的端部，通过所述转接金属部与所述触控转接线连接。
  7. 根据权利要求6所述的显示面板，其中，所述转接金属部搭接于所述触控转接线远离所述触控引脚的端部；所述触控转接线未搭接有所述转接金属部的部分，被所述钝化层覆盖。
  8. 根据权利要求1所述的显示面板，其中，所述触控金属层还包括与各个触控引脚一一对应的引脚保护部，所述引脚保护部与对应的所述触控引脚交叠设置且电连接；所述引脚保护部与所述触控有机层的边缘之间具有间隙。
  9. 根据权利要求8所述的显示面板，其中，所述触控引脚在所述衬底基板上的正投影，位于所述引脚保护部在所述衬底基板上的正投影内。
  10. 根据权利要求8所述的显示面板，其中，所述触控有机层包括在所述像素层远离所述衬底基板一侧依次层叠的第一触控有机层、第二触控有机层和第三触控有机层；所述触控金属层包括夹设于所述第一触控有机层和所述第二触控有机层之间的第一触控金属层，以及包括夹设于所述第二触控有机层和所述第三触控有机层之间的第二触控金属层；
    所述引脚保护部包括位于所述第一触控金属层的第一引脚保护部和位于所述第二触控金属层的第二引脚保护部；
    所述触控引脚在所述衬底基板上的正投影，在所述第一引脚保护部在所述衬底基板上的正投影内；所述第一引脚保护部在所述衬底基板上的正投影，在所述第二引脚保护部在所述衬底基板上的正投影内。
  11. 根据权利要求10所述的显示面板，其中，所述第一引脚保护部与所述第二引脚保护部之间不设置第二触控有机层；所述第一引脚保护部 与所述触控引脚之间不设置第一触控有机层。
  12. 根据权利要求5所述的显示面板，其中，所述源漏金属层包括依次层叠设置于所述衬底基板一侧的第一源漏金属层和第二源漏金属层，所述钝化层位于所述第一源漏金属层和所述第二源漏金属层之间；所述触控引脚和所述触控转接线位于所述第一源漏金属层；
    所述第二源漏金属层包括与各个触控引脚一一对应的叠层金属部，所述叠层金属部与对应的所述触控引脚交叠且电连接。
  13. 根据权利要求12所述的显示面板，其中，所述触控引脚在所述衬底基板上的正投影，位于所述叠层金属部在所述衬底基板上的正投影内。
  14. 根据权利要求12所述的显示面板，其中，所述驱动层还包括位于所述第二源漏金属层远离所述衬底基板一侧的平坦化层；
    所述平坦化层覆盖所述叠层金属部与所述触控有机层的边界之间的间隙。
  15. 根据权利要求14所述的显示面板，其中，所述触控有机层覆盖所述触控转接线的部分，直接形成于所述平坦化层远离所述衬底基板的表面。
  16. 根据权利要求14所述的显示面板，其中，所述触控金属层还包括与各个触控引脚一一对应的引脚保护部，所述引脚保护部通过所述叠层金属部与对应的所述触控引脚交叠设置且电连接；
    所述引脚保护部与所述触控有机层的边缘之间具有间隙，且所述引脚保护部靠近所述触控有机层的部分搭接于所述平坦化层上。
  17. 根据权利要求12所述的显示面板，其中，所述触控金属层还包括与各个触控引脚一一对应的引脚保护部，所述引脚保护部通过所述叠层金属部与对应的所述触控引脚交叠设置且电连接；
    其中，所述叠层金属部在所述衬底基板上的正投影，位于所述引脚保护部在所述衬底基板上的正投影内。
  18. 根据权利要求1所述的显示面板，其中，所述显示面板还包括位于所述像素层与所述触控层之间的薄膜封装层，所述薄膜封装层包括交替层叠设置的无机封装层和有机封装层，所述薄膜封装层包括至少一层有机封装层和至少两层无机封装层。
  19. 一种显示装置，包括权利要求1～18任意一项所述的显示面板。
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CN113224084A (zh) * 2021-05-31 2021-08-06 京东方科技集团股份有限公司 显示基板及其制作方法、显示面板、以及柔性显示装置
CN113964109A (zh) * 2021-10-19 2022-01-21 成都京东方光电科技有限公司 显示基板及其制备方法、显示装置

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