WO2023201883A1 - 存储器失效测试方法及装置、存储介质及电子设备 - Google Patents

存储器失效测试方法及装置、存储介质及电子设备 Download PDF

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WO2023201883A1
WO2023201883A1 PCT/CN2022/101614 CN2022101614W WO2023201883A1 WO 2023201883 A1 WO2023201883 A1 WO 2023201883A1 CN 2022101614 W CN2022101614 W CN 2022101614W WO 2023201883 A1 WO2023201883 A1 WO 2023201883A1
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data
memory
storage
word line
array
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French (fr)
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江汉
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and specifically, to a memory failure testing method, a memory failure testing device, a computer-readable storage medium, and an electronic device.
  • DRAM Dynamic Random Access Memory
  • a memory failure testing method includes: performing a data writing action of the memory; the data writing action includes: a memory unit in a storage array of the memory. Write preset storage data in two adjacent word lines, and write data opposite to the data of the memory unit corresponding to the previous word line in the memory unit corresponding to the latter word line of the memory array. ; Repeat the data writing action until the memory cells corresponding to all word lines of the memory array are written; read the data in the memory array and compare it with the written data to obtain the comparison result; according to The comparison result determines the failure status of the memory.
  • the preset storage data includes one first data and a plurality of second data; wherein , the first data and the second data are opposite data.
  • the first data is on any bit of the storage unit of the first burst length.
  • the bits of the first data on the first burst length storage unit are changed to obtain sixteen kinds of preset storage data.
  • the preset storage data includes a plurality of the second data
  • the preset storage data is repeatedly arranged according to the preset storage data of the first burst length and the second burst length.
  • the method further includes: reading the data in the storage array in the same order as writing the data in the storage array.
  • reading data in the memory array includes: turning on a word line, and after sequentially reading the data in the memory cells corresponding to the word line, turning off the word line. line; turn on the next word line, and after sequentially reading the data in the memory unit corresponding to the next word line, turn off the next word line.
  • determining the failure state of the memory based on the comparison result includes: determining the data read in the storage array and the data written in the storage array. Whether they are the same; if they are different, it is determined that there is leakage or open circuit in the input and output lines of the memory.
  • a memory failure testing device includes: a data writing module configured to perform a data writing operation on a storage array of the memory; the data writing operation includes: in the Preset storage data is written into the memory cells in the memory array of the memory; among the two adjacent word lines, the memory cell corresponding to the previous word line is written into the memory cell corresponding to the latter word line of the memory array. the opposite data of the data in the storage unit; repeat the data writing action until the storage units corresponding to all word lines of the storage array are written; a data comparison module is used to read the data in the storage array, And compare it with the written data to obtain the comparison result; a determination module is used to determine the failure state of the memory according to the comparison result.
  • the preset storage data includes one first data and a plurality of second data; wherein, The first data and the second data are opposite data.
  • the first data is on any bit of the storage unit of the first burst length.
  • the device further includes: a preset storage data determination module, configured to change the bits of the first data in the first burst length storage unit to obtain ten Six of these presets store data.
  • the preset storage data includes a plurality of the second data.
  • a data reading module is further included, configured to read data in the storage array in the same order as in writing data in the storage array.
  • the data reading module is used to turn on a word line, and after sequentially reading the data in the memory cells corresponding to the word line, turn off the word line; turn on The next word line, after sequentially reading the data in the memory cells corresponding to the next word line, closes the next word line.
  • the determination module is used to determine whether the data read in the storage array and the data written in the storage array are the same; if they are different, determine whether the memory There is leakage or open circuit in the input and output lines.
  • a computer-readable storage medium is provided, a computer program is stored thereon, and when the computer program is executed by a processor, the above-mentioned memory failure testing method is implemented.
  • an electronic device including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the operation via executing the executable instructions. Perform the memory failure testing method described above.
  • Figure 1 schematically shows a schematic structural diagram of a memory unit according to an exemplary embodiment of the present disclosure
  • FIG. 2 schematically shows a layout diagram of a storage array according to an exemplary embodiment of the present disclosure
  • Figure 3 schematically shows a step flow chart of a memory failure testing method according to an exemplary embodiment of the present disclosure
  • Figure 4 schematically shows a data writing schematic diagram of a storage array according to an exemplary embodiment of the present disclosure
  • Figure 5 schematically shows a schematic diagram of preset storage data writing according to an exemplary embodiment of the present disclosure
  • Figure 6 schematically shows a working timing diagram 1 of a memory according to an exemplary embodiment of the present disclosure
  • Figure 7 schematically shows the second working sequence diagram of a memory according to an exemplary embodiment of the present disclosure
  • FIG. 8 schematically illustrates a block diagram of a memory failure testing device according to an exemplary embodiment of the present disclosure
  • FIG. 9 schematically shows a module diagram of an electronic device according to an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
  • Semiconductor memory is used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices and applications.
  • Semiconductor memory includes a plurality of memory cells in a memory array, each memory cell storing at least one bit of information.
  • DRAM is an example of such a semiconductor memory. This solution is preferably used in DRAM. Accordingly, the following description of embodiments is made with reference to DRAM as a non-limiting example.
  • arrays of memory cells are typically arranged in rows and columns such that a specific memory cell can be addressed by specifying its row and column of the array.
  • the word lines connect the rows to a set of bit line sense amplifiers (SAs) that detect the data in the cells. Then in a read operation, a subset of the data in the sense amplifier is selected or "column selected" for output.
  • SAs bit line sense amplifiers
  • each memory cell 100 in DRAM generally includes a capacitor 110, a transistor 120, a word line (Word Line, WL) 130 and a bit line (Bit Line, BL) 140.
  • the gate of the transistor 120 is connected to the word line 130.
  • the drain of the transistor 120 is connected to the bit line 140, and the source of the transistor 120 is connected to the capacitor 110.
  • the voltage signal on the word line 130 can control the opening or closing of the transistor 120, and then the bit line 140 reads the data stored in the capacitor 110.
  • the data information, or the data information is written into the capacitor 110 through the bit line 140 for storage.
  • the memory array is composed of the above-mentioned multiple memory cells.
  • the memory array generally occupies 50-65% of the entire DRAM device area, and the remaining area of the DRAM device is mainly composed of peripheral circuits.
  • FIG. 2 a schematic layout diagram of a storage array provided by an embodiment of the present disclosure is shown.
  • multiple bit lines can be divided into 128 bit line groups, and each bit line group has 8 bit lines.
  • the bits in each bit line group are The lines are marked as BL0, BL1, BL2...BL7.
  • Multiple word lines can be divided into 8192 word line groups, and each word line group has 8 word lines.
  • the word lines in each word line group are recorded as WL0, WL1, WL2... WL7.
  • a plurality of memory cells P11 to P88 are distributed in a matrix.
  • the memory cells in the first column are all connected to the word line WL0, the memory cells in the second column are all connected to the word line WL1, and so on.
  • the memory cells in the eighth column are all connected to the word line WL0.
  • the word line WL7 is connected; the memory cells in the first row are all connected to the bit line BL0, the memory cells in the second row are all connected to the bit line BL1, and so on, the memory cells in the eighth row are all connected to the bit line BL7, so that each Each memory cell is connected to a word line WL and a bit line BL.
  • embodiments of the present disclosure provide a memory failure testing method.
  • a flip action occurs on the LIO line, so that the memory under test can be read.
  • the environment has become more stringent.
  • it can be accurately determined whether there is an abnormality in the memory under test, which can effectively improve the detection accuracy of the memory and thereby improve the memory yield.
  • the above testing method may include:
  • Step S310 Execute the data writing operation of the storage array of the memory
  • Step S320 Repeat the data writing operation until the memory cells corresponding to all word lines of the memory array are written;
  • Step S330 Read the data in the storage array and compare it with the written data to obtain the comparison result
  • Step S340 Determine the failure state of the memory based on the comparison result.
  • the above-mentioned memory array includes multiple columns of memory cells.
  • preset storage data with a fixed format can be set in advance, and then during the test process, the preset storage data is written into each column of storage cells in the above-mentioned storage array.
  • an initialization operation can be performed first on each memory unit connected to each word line to activate each memory unit, and then a writing operation is performed, so that each memory unit connected to each word line is written with a preset value. Storing data.
  • the above-mentioned data writing action may include: writing preset storage data in a storage unit in a storage array of a memory, in two adjacent word lines, at the rear of the storage array. Data opposite to the data in the memory cell corresponding to the previous word line is written into the memory cell corresponding to one word line.
  • the opposite data of the memory unit corresponding to the previous word line is written into the memory unit corresponding to the next word line of the memory array, for example, the memory unit corresponding to the second word line
  • the data written in the memory unit corresponding to the first word line is opposite to the data written in the memory unit corresponding to the first word line;
  • the data written in the memory unit corresponding to the third word line is the same as the data written in the memory unit corresponding to the second word line.
  • the data is the opposite.
  • the data on adjacent word lines WL can be reversed, that is, the data 01 on the same bit line BL can be arranged alternately, so that the data on the LIO line connected to the bit line BL can be flipped, which is beneficial to failure testing.
  • the preset storage data can be determined according to the actual situation.
  • the storage unit is preset to store data including one first data and a plurality of second data, and the first data and the second data are opposite data. That is to say, when the first data is 1, the second data is 0; when the first data is 0, the second data is 1.
  • Table 1 shows an example of writing data in the storage unit of the first Burst length.
  • the first data is 1, the second data is 0, and the first data 1 is located in the memory cell where the word line WL0 and the bit line BL0 are located.
  • the data written in the storage unit corresponding to the latter word line is different from the data written in the storage unit corresponding to the previous word line.
  • the data is the opposite. That is, the data on the same bit line on adjacent word lines is opposite.
  • the first data may be located in the memory cell of the first burst length in addition to being located in the memory cell where the word line WL0 and the bit line BL0 are located. on any bit of the storage unit.
  • the first data 1 is located in the memory cell where the word line WL0 and the bit line BL1 are located.
  • the corresponding data on the subsequent word lines that is, word lines WL1-WL7, has also changed to meet the requirements of the latter word line.
  • the data written in the memory cell is required to be opposite to the data written in the memory cell corresponding to the previous word line.
  • the first data may be located in any bit position among BL0-BL7.
  • the corresponding bit on the following word line will also change, which is opposite to the same bit on the previous word line.
  • the memory failure testing method writes preset storage data in the storage unit in the storage array, and sets the preset storage data to a data structure containing an opposite second data, so that the storage array
  • the reading environment becomes more stringent. After the reading operation, by comparing the written data and the read data, it can be accurately judged whether there is an abnormality in the memory, which can effectively improve the detection accuracy of the memory and thereby improve the quality of the memory. Rate.
  • the opposite data in the memory unit corresponding to the previous word line in the memory unit corresponding to the latter word line among the two adjacent word lines in the memory array it is possible to write the opposite data in the memory unit corresponding to the previous word line.
  • the opposite data is produced on the same bit, so that the input and output line LIO connected to the bit can have data flipping action, providing a strict reading environment for the storage array, thereby improving the accuracy of the LIO leakage test.
  • FIG. 4 provides a schematic diagram of data writing in a storage array according to an embodiment of the present disclosure.
  • Writing "10000000” in the memory unit of the first burst length of the first word line WL0, and writing "01111111" in the memory unit of the first burst length of the second word line WL1 can cause a gap between LIOs. pressure difference.
  • LIO has a flipping action, which helps to detect whether there is leakage or open circuit problems between LIOs.
  • the preset storage data composed of first data and second data is changed in the first burst by changing the first data.
  • Eight kinds of preset storage data can be obtained from the bits on the length storage unit; and when the first data is respectively 0 or 1, a total of sixteen kinds of preset storage data can be obtained.
  • the exemplary embodiments of the present disclosure will not elaborate on enumerating the sixteen types of preset storage data one by one.
  • the preset storage data may include a plurality of second data, for example, the first word line as shown in Table 3
  • the second data in the bit lines BL8-BL15 corresponding to WL0 is data 0.
  • the second data of the second burst length may also be data 1.
  • the data written in the memory unit corresponding to the later word line is also opposite to the data written in the memory unit corresponding to the previous word line.
  • the preset storage data in its memory unit may be repeatedly arranged according to the first burst length and the second burst length.
  • the preset storage data of the storage unit of the third burst length is the same as the preset storage data of the storage unit of the first burst length
  • the preset storage data of the storage unit of the fourth burst length is the same as the preset storage data of the storage unit of the second burst length.
  • the preset storage data of the storage unit is the same, and so on, until the preset storage data of the storage unit of the 127th burst length is the same as the preset storage data of the storage unit of the first burst length, and the storage unit of the 128th burst length is the same.
  • the preset storage data of the unit is the same as the preset storage data of the storage unit of the second burst length.
  • the preset storage data of the 127th burst length storage unit is the same as the preset storage data of the first burst length storage unit, both are 10000000; the 128th burst length storage unit has the same preset storage data.
  • the preset storage data is the same as the preset storage data of the storage unit of the second burst length, both being 00000000.
  • a simple summary is: among the storage units with remaining burst lengths, the preset storage data of the storage units with odd burst lengths is the same as the preset storage data of the storage units with the first burst length, and the preset storage data of the storage units with even burst lengths is the same.
  • the preset storage data is the same as the preset storage data of the storage unit of the second burst length.
  • FIG. 6 shows the first working sequence diagram of the memory under test in the embodiment of the present disclosure.
  • the column select signal YS is turned on, the bit line BL is connected to LIO, the reference bit line BL/ is connected to LIO/, and the source end of VSS is connected to the bit line BL, at this time LIO and LIO/ are in a floating state (floating means that the Vary Source does not supply power to LIO, because YS is not turned on initially, and the Vary Source has been supplying power to LIO at this time), the VSS of the BL potential will quickly become floating Status LIO(Vary) is pulled low.
  • the potentials of BL and LIO gradually approach VSS, but will not reach VSS.
  • the YS column selection signal is turned off, LIO is disconnected from BL, LIO is not in a floating state, and is reconnected to the Vary Source.
  • the Vary potential quickly pulls LIO up to prepare for the next read or write operation.
  • FIG. 7 a second working sequence diagram of the memory under test in the embodiment of the present disclosure is shown.
  • the column select signal YS is turned on, the bit line BL is connected to LIO, the reference bit line BL/ is connected to LIO/, and the source end of VSS is connected to the bit line BL/ , at this time LIO and LIO/ are in a floating state (floating means that the Vary Source does not supply power to LIO/, because YS is not turned on initially, and the Vary Source always supplies power to LIO/ at this time), the VSS of the BL/ potential will quickly LIO/(Vary) in the floating state is pulled low.
  • the potentials of BL/ and LIO/ gradually approach VSS, but will not reach VSS.
  • the YS column selection signal is turned off, LIO/ is disconnected from BL/, LIO/ is not in a floating state, and is reconnected to the Vary Source.
  • the Vary potential will quickly pull up LIO/ to prepare for the next read or write operation.
  • the memory failure testing method provided by the exemplary embodiments of the present disclosure is to write the opposite of the memory unit corresponding to the previous word line in the memory unit corresponding to the latter word line among the two adjacent word lines of the memory array.
  • the data stored on LIO is flipped, which makes the memory reading environment more stringent. After writing and reading the memory, by comparing the written and read data, you can accurately determine whether the memory is The existence of abnormalities, including whether there is leakage or excessive resistance on the input and output lines of the memory, can effectively improve the detection accuracy of the memory, thereby improving the memory yield.
  • the order of reading data in the storage array is the same as the order of writing data in the storage array. For example, if the way to write data in a storage array is Y-Page writing, then the way to read data is also Y-Page reading.
  • the above-mentioned Y-Page writing method includes: when writing data in the memory cells of the memory array, first open one of the word lines, write all the data to all the memory cells corresponding to this word line, and then close it. This word line; then turn on the next word line, write all the data to all the memory cells corresponding to the next word line, then turn off the word line..., and so on, until the data is written to the memory array in the memory cells connected by each word line.
  • each word line of the memory array can be traversed, and the following operations can be performed on each target word line traversed:
  • Step 1 Turn on the target word line, and write the preset storage data bit by bit into all memory cells connected to the target word line; wherein, each memory unit connected to the target word line writes one bit of the preset storage data.
  • the number of bits of stored data is preset to be the same as the number of memory cells connected to the word line.
  • Step 2 Close the above target word line.
  • the above-mentioned preset storage data can be configured in advance according to the number of memory cells connected to each word line. For example, when there are 16 memory cells connected to each word line, 16 preset storage data can be configured; when there are 32 memory cells connected to each word line, 32 preset storage data can be configured.
  • the above-mentioned Y-Page reading method may include: turning on a word line, and after sequentially reading the data in the memory unit corresponding to the word line, turning off the word line; and then turning on the next word line.
  • Word lines after sequentially reading the data in the memory cells corresponding to the next word line, turn off the next word line..., and so on, until the data in the memory cells connected to each word line of the memory array is read.
  • the read data after reading the data in the storage array, the read data can be compared with the previously written data to obtain a comparison result, and based on the comparison result, the memory failure can be corrected. Status is judged.
  • the specific determination process includes: determining whether the data read from the storage array and the data written into the storage array are the same. If they are the same, it means there is no abnormality in the memory; if they are different, it can be determined that the memory has leakage or open circuit in the input and output lines. risk.
  • the exemplary embodiments of the present disclosure write the opposite data in the memory cell corresponding to the previous word line in the memory cell corresponding to the latter word line among the two adjacent word lines in the memory array, and Write preset storage data in the memory cell corresponding to the first word line, where the preset storage data contains an opposite data.
  • This can provide a condition for the storage data to flip on the LIO, making the memory read
  • the environment has become more stringent. After writing and reading the memory, by comparing the written and read data, you can accurately determine whether there is an abnormality in the memory, including whether there is leakage or resistance on the input and output lines of the memory. If the value is too large, the detection accuracy of the memory can be effectively improved, thereby improving the memory yield.
  • the memory failure testing device 700 may include: a data writing module 710, a data reading module 720, a data comparison module 730, a determination module 740 and a preset storage data determination module 750, wherein:
  • the data writing module 710 is used to perform data writing operations on the storage array of the memory
  • the data writing operation includes: writing preset storage data in the storage unit in the storage array of the memory; among the two adjacent word lines, the storage corresponding to the last word line of the storage array is Write data in the cell that is opposite to the data of the memory cell corresponding to the previous word line; repeat the data writing action until the memory cells corresponding to all word lines of the memory array are written;
  • the data comparison module 730 is used to read the data in the storage array and compare it with the written data to obtain the comparison result;
  • the determination module 740 is configured to determine the failure state of the memory according to the comparison result.
  • the preset storage data includes one first data and a plurality of second data; wherein, the first data and the second data The second data is the opposite data.
  • the first data is on any bit of the storage unit of the first burst length.
  • the preset storage data determination module 750 is configured to change the bits of the first data in the first burst length storage unit to obtain sixteen types of preset storage data.
  • the preset storage data includes a plurality of second data.
  • the data reading module 720 is configured to read data in the storage array in the same order as in writing data in the storage array.
  • the data reading module 720 is used to turn on a word line, and after sequentially reading the data in the memory cells corresponding to the word line, turn off the word line; turn on the next word line, After sequentially reading the data in the memory cell corresponding to the next word line, the next word line is turned off.
  • the determination module 740 is used to determine whether the data in the storage array read and the data written in the storage array are the same; if they are different, determine whether the memory has leakage or open circuit in the input and output lines. .
  • modules or units of the memory failure testing apparatus are mentioned in the above detailed description, this division is not mandatory.
  • the features and functions of two or more modules or units described above may be embodied in one module or unit.
  • the features and functions of one module or unit described above may be further divided into being embodied by multiple modules or units.
  • an electronic device capable of implementing the above method is also provided.
  • FIG. 9 An electronic device 800 according to this embodiment of the invention is described below with reference to FIG. 9 .
  • the electronic device 800 shown in FIG. 9 is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present invention.
  • electronic device 800 is embodied in the form of a general computing device.
  • the components of the electronic device 800 may include, but are not limited to: the above-mentioned at least one processing unit 810, the above-mentioned at least one storage unit 820, a bus 830 connecting different system components (including the storage unit 820 and the processing unit 810), and the display unit 840.
  • the storage unit 820 stores program code, and the program code can be executed by the processing unit 810, so that the processing unit 810 performs various examples according to the present invention described in the "Exemplary Method" section of this specification.
  • sexual implementation steps For example, the processing unit 810 can perform step S310 as shown in FIG. 3 to perform a data writing operation in the storage array of the memory; step S320, repeat the data writing operation until all word lines corresponding to the storage array are written.
  • the storage unit 820 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 8201 and/or a cache storage unit 8202, and may further include a read-only storage unit (ROM) 8203.
  • RAM random access storage unit
  • ROM read-only storage unit
  • Storage unit 820 may also include a program/utility 8204 having a set of (at least one) program modules 8205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, Each of these examples, or some combination, may include the implementation of a network environment.
  • program/utility 8204 having a set of (at least one) program modules 8205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, Each of these examples, or some combination, may include the implementation of a network environment.
  • Bus 830 may be a local area representing one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or using any of a variety of bus structures. bus.
  • Electronic device 800 may also communicate with one or more external devices 870 (e.g., keyboard, pointing device, Bluetooth device, etc.), may also communicate with one or more devices that enable a user to interact with electronic device 800, and/or with Any device that enables the electronic device 800 to communicate with one or more other computing devices (eg, router, modem, etc.). This communication may occur through input/output (I/O) interface 850.
  • the electronic device 800 may also communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN), and/or a public network, such as the Internet) through a network adapter 860. As shown, network adapter 860 communicates with other modules of electronic device 800 via bus 830.
  • network adapter 860 communicates with other modules of electronic device 800 via bus 830.
  • electronic device 800 may be used in conjunction with electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives And data backup storage system, etc.
  • the example embodiments described here can be implemented by software, or can be implemented by software combined with necessary hardware. Therefore, the technical solution according to the embodiment of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to cause a computing device (which may be a personal computer, a server, a terminal device, a network device, etc.) to execute a method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a terminal device, a network device, etc.
  • a computer-readable storage medium is also provided, on which a program product capable of implementing the method described above in this specification is stored.
  • various aspects of the present invention can also be implemented in the form of a program product, which includes program code.
  • the program product is run on a terminal device, the program code is used to cause the The terminal device performs the steps according to various exemplary embodiments of the present invention described in the "Exemplary Method" section above in this specification.
  • the program product for implementing the above method according to an embodiment of the present invention can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer.
  • a terminal device such as a personal computer.
  • the program product of the present invention is not limited thereto.
  • a readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, apparatus or device.
  • the program product may take the form of any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave carrying readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.
  • a readable signal medium may also be any readable medium other than a readable storage medium that can send, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device.
  • Program code embodied on a readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical cable, RF, etc., or any suitable combination of the foregoing.
  • Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., as well as conventional procedural Programming language—such as "C" or a similar programming language.
  • the program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on.
  • the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device, such as provided by an Internet service. (business comes via Internet connection).
  • LAN local area network
  • WAN wide area network

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

一种存储器失效测试方法、存储器失效测试装置、计算机可读存储介质及电子设备，涉及集成电路技术领域。该存储器失效测试方法包括：执行存储器的数据写入动作；数据写入动作包括：在存储器的存储阵列内的存储单元中写入预设存储数据，相邻的两条字线中，在存储阵列的后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元的数据相反的数据；重复数据写入动作，直到写完存储阵列的所有字线所对应的存储单元；读取存储阵列中的数据，并与写入的数据进行比较，获得比较结果；根据比较结果对存储器的失效状态进行判定。提供一种测试LIO漏电引起的DRAM资料读取失效的测试方法。

Description

存储器失效测试方法及装置、存储介质及电子设备
相关申请的交叉引用
本申请要求于2022年04月18日提交的申请号为202210406608.9、名称为“存储器失效测试方法及装置、存储介质及电子设备”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种存储器失效测试方法、存储器失效测试装置、计算机可读存储介质及电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由于具有结构简单，密度高，功耗低，价格低廉等优点，在计算机领域和电子行业中受到了广泛的应用。
对于DRAM而言，当输入输出(Input Output，简称IO)线存在漏电或高阻情况时，就会导致从存储芯片中读取到的数据与原始存储的数据不同，出现存储器失效的情况。
因此，提供一种测试LIO(Local IO，本地输入输出线)漏电引起的DRAM资料读取失效的测试方法，有利于提升存储芯片的良率。
发明内容
根据本公开的第一方面，提供一种存储器失效测试方法，所述方法包括：执行所述存储器的数据写入动作；所述数据写入动作包括：在所述存储器的存储阵列内的存储单元中写入预设存储数据，相邻的两条字线中，在所述存储阵列的后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元的数据相反的数据；重复所述数据写入动作，直到写完所述存储阵列的所有字线所对应的存储单元；读取所述存储阵列中的数据，并与写入的数据进行比较，获得比较结果；根据所述比较结果对所述存储器的失效状态进行判定。
在本公开的一种示例性实施方式中，对于所述存储阵列中任意字线的第一突发长度的存储单元，所述预设存储数据包括一个第一数据和多个第二数据；其中，所述第一数据和所述第二数据是相反的数据。
在本公开的一种示例性实施方式中，所述第一数据在所述第一突发长度的存储单元的任一比特位上。
在本公开的一种示例性实施方式中，改变所述第一数据在所述第一突发长度存储单元上的比特位，获得十六种所述预设存储数据。
在本公开的一种示例性实施方式中，对于所述存储阵列中任意字线的第二突发长度的存储单元，所述预设存储数据包括多个所述第二数据；
对于所述存储阵列中任意所述字线的剩余突发长度的存储单元，所述预设存储数据按照所述第一突发长度和所述第二突发长度的预设存储数据重复排列。
在本公开的一种示例性实施方式中，所述方法还包括：读取所述存储阵列中数据的顺序与写入所述存储阵列中数据的顺序相同。
在本公开的一种示例性实施方式中，读取所述存储阵列中的数据，包括：开启一条字线，顺序读完所述字线所对应的存储单元中的数据之后，关闭所述字线；开启下一条字线，顺序读完所述下一条字线所对应的存储单元中的数据之后，关闭所述下一条字线。
在本公开的一种示例性实施方式中，根据所述比较结果对所述存储器的失效状态进行判定，包括：判断读取的所述存储阵列中的数据与写入所述存储阵列中的数据是否相同；如果不同，则判定所述存储器存在输入输出线漏电或断路。
根据本公开的第二方面，提供一种存储器失效测试装置，所述装置包括：数据写入模块，用于执行存储器的存储阵列的数据写入动作；所述数据写入动作包括：在所述存储器的存储阵列内的存储单元中写入预设存储数据；相邻的两条字线中，在所述存储阵列的后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元的数据相反的数据；重复所述数据写入动作，直到写完所述存储阵列的所有字线所对应的存储单元；数据比较模块，用于读取所述存储阵列中的数据，并与写入的数据进行比较，获得比较结果；判定模块，用于根据所述比较结果对所述存储器的失效状态进行判定。
在本公开的一种示例性实施方式中，对于所述存储阵列中字线的第一突发长度的存储单元，所述预设存储数据包括一个第一数据和多个第二数据；其中，所述第一数据和所述第二数据是相反的数据。
在本公开的一种示例性实施方式中，所述第一数据在所述第一突发长度的存储单元的任一比特位上。
在本公开的一种示例性实施方式中，所述装置还包括：预设存储数据确定模块，用于改变所述第一数据在所述第一突发长度存储单元上的比特位，获得十六种所述预设存储数据。
在本公开的一种示例性实施方式中，对于所述存储阵列中字线的第二突发长度的存储单元，所述预设存储数据包括多个所述第二数据。
在本公开的一种示例性实施方式中，还包括：数据读取模块，用于读取所述存储阵列中数据的顺序与写入所述存储阵列中数据的顺序相同。
在本公开的一种示例性实施方式中，所述数据读取模块，用于开启一条字线，顺序读完所述字线所对应的存储单元中的数据之后，关闭所述字线；开启下一条字线，顺序读完所述下一条字线所对应的存储单元中的数据之后，关闭所述下一条字线。
在本公开的一种示例性实施方式中，所述判定模块，用于判断读取的所述存储阵列中的数据与写入所述存储阵列中数据是否相同；如果不同，则判定所述存储器存在输入输出线漏电或断路。
根据本公开的第三方面，提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述的存储器失效测试方法。
根据本公开的第四方面，提供一种电子设备，包括：处理器；以及存储器，用于存储所述处理器的可执行指令；其中，所述处理器配置为经由执行所述可执行指令来执行上述的存储器失效测试方法。
附图说明
图1示意性示出了根据本公开的示例性实施例的一种存储单元的结构示意图；
图2示意性示出了根据本公开的示例性实施例的一种存储阵列的布局示意图；
图3示意性示出了根据本公开的示例性实施例的一种存储器失效测试方法的步骤流程图；
图4示意性示出了根据本公开的示例性实施例的一种存储阵列的数据写入示意图；
图5示意性示出了根据本公开的示例性实施例的预设存储数据写入示意图；
图6示意性示出了根据本公开的示例性实施例的存储器的工作时序图一；
图7示意性示出了根据本公开的示例性实施例的存储器的工作时序图二；
图8示意性示出了根据本公开的示例性实施例的存储器失效测试装置的方框图；
图9示意性示出了根据本公开的示例性实施例的一种电子设备的模块示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实 施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明，不是必须包括所有的步骤。例如，有的步骤还可以分解，而有的步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。另外，下面所有的术语“第一”、“第二”、“第三”仅是为了区分的目的，不应作为本公开内容的限制。
半导体存储器用于计算机、服务器、诸如移动电话等手持设备、打印机和许多其他电子设备和应用。半导体存储器在存储器阵列中包括多个存储单元，每个存储单元存储信息的至少一位。DRAM为这种半导体存储器的实例。本方案优选地用于DRAM中。因此，接下来的实施例描述是参考作为非限制性示例的DRAM进行的。
在DRAM集成电路设备中，存储单元阵列典型地以行和列布置，使得特定的存储单元可以通过指定其阵列的行和列来寻址。字线将行连接到一组探测单元中数据的位线感应放大器(Sense Amplifier，SA)。然后在读取操作中，选择或者“列选择”感应放大器中的数据子集用于输出。
参照图1，DRAM中的每个存储单元100通常包括电容器110、晶体管120、字线(Word Line，WL)130和位线(Bit Line，BL)140，晶体管120的栅极与字线130相连、晶体管120的漏极与位线140相连、晶体管120的源极与电容器110相连，字线130上的电压信号能够控制晶体管120的打开或关闭，进而通过位线140读取存储在电容器110中的数据信息，或者通过位线140将数据信息写入到电容器110中进行存储。存储阵列就是由上述的多个存储单元所组成，存储阵列一般会占用整个DRAM器件面积的50-65％，DRAM器件的其余面积则主要由外围电路所组成。
参照图2，示出了本公开实施例提供的一种存储阵列的布局示意图。以DRAM存储器中的一个Bank为例，多条位线可以划分为128个位线组，每个位线组中具有8条位线，为了方便下文的描述，将每个位线组中的位线记为BL0、BL1、BL2……BL7。多条字线可以划分为8192个字线组，每个字线组中具有8条字线，为了方便下文的描述，将每个字线组中的字线记为WL0、WL1、WL2……WL7。
多个存储单元P11～P88呈矩阵分布，其中，第一列的存储单元均与字线WL0连接，第二列的存储单元均与字线WL1连接，依次类推，第八列的存储单元均与字线WL7连接；第一行的存储单元均与位线BL0连接，第二行的存储单元均与位线BL1连接，以此类推，第八行的存储单元均与位线BL7连接，使得每个存储单元均与一条字线WL和一条位线BL连接。
在现代集成电路制造工艺中，器件缺陷造成的损失代价极为高昂，例如，当输入输出IO线存在漏电或高阻情况时，就会导致从存储器中读取到的数据与原始存储的数据不同。因此，亟需提供一种测试方法来测试存储器是否存在异常情况，以便于提升存储器的良率。
基于此，本公开实施例提供了一种存储器失效测试方法，通过在存储器的存储阵列内 的存储单元中写入预设存储数据，使LIO线上有翻转的动作，使得待测存储器的读取环境变得更严格，在读取待测存储器中的数据时，通过数据对比，即可准确判断出待测存储器是否存在异常，可以有效提升存储器的检测准确率，进而提升存储器的良率。以下结合具体实施方式进行详细说明。
参照图3，示出了本公开实施例的一种存储器失效测试方法的步骤流程图。在一种可行的实施方式中，上述测试方法可以包括：
步骤S310、执行存储器的存储阵列的数据写入动作；
步骤S320、重复数据写入动作，直到写完存储阵列的所有字线所对应的存储单元；
步骤S330、读取存储阵列中的数据，并与写入的数据进行比较，获得比较结果；
步骤S340、根据比较结果对存储器的失效状态进行判定。
本公开示例性实施方式中，上述存储阵列包括多列存储单元。
在一种可行的实施方式中，可以预先设置具有固定格式的预设存储数据，然后在测试过程中，将该预设存储数据写入到上述存储阵列的每一列存储单元中。
在一些实施例中，可以首先对各个字线连接的各个存储单元进行初始化操作，以激活各个存储单元，然后再进行写入操作，使得与各条字线连接的各个存储单元被写入预设存储数据。
本公开的示例性实施方式中，上述的数据写入动作可以包括：在存储器的存储阵列内的存储单元中写入预设存储数据，在相邻的两条字线中，在存储阵列的后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元中的数据相反的数据。
通过上述的数据写入动作，即存储阵列的后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元相反的数据，例如，第二条字线所对应的存储单元中写入的数据与第一条字线所对应的存储单元写入的数据相反；第三条字线所对应的存储单元中写入的数据与第二条字线所对应的存储单元写入的数据相反等。从而可以使得相邻字线WL上的数据相反，即同一条位线BL上的数据01交替排列，从而可以使与位线BL相连的LIO线上的数据发生翻转，有利于失效测试。
在实际应用中，预设存储数据可以根据实际情况进行确定，本公开示例性实施方式中，预设存储数据可以有多种，对于存储阵列中字线的第一突发长度(第一Burst长度)的存储单元，预设存储数据包括一个第一数据和多个第二数据，并且，第一数据与第二数据是相反的数据。也就是说，第一数据是1的时候，第二数据是0；第一数据是0的时候，第二数据是1。
表1示出了第一Burst长度的存储单元中写入数据的一种示例。对于第一条字线的第一Burst长度的存储单元而言，第一数据是1，第二数据0，第一数据1位于字线WL0和位线BL0所在的存储单元中。
表1
  WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7
BL0 1 0 1 0 1 0 1 0
BL1 0 1 0 1 0 1 0 1
BL2 0 1 0 1 0 1 0 1
BL3 0 1 0 1 0 1 0 1
BL4 0 1 0 1 0 1 0 1
BL5 0 1 0 1 0 1 0 1
BL6 0 1 0 1 0 1 0 1
BL7 0 1 0 1 0 1 0 1
由于对于存储器的同一个BANK存储阵列而言，对于相邻的两条字线中，后一条字线所对应的存储单元中写入的数据，与前一条字线所对应的存储单元中写入的数据相反。也就是说，相邻字线上位于同一条位线上的数据相反。
在实际应用中，对于第一条字线的第一Burst长度的存储单元而言，第一数据除过位于字线WL0和位线BL0所在的存储单元中之外，还可以位于第一Burst长度的存储单元的任一比特位上。例如，如表2所示的，第一数据1位于字线WL0和位线BL1所在的存储单元中。
表2
  WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7
BL0 0 1 0 1 0 1 0 1
BL1 1 0 1 0 1 0 1 0
BL2 0 1 0 1 0 1 0 1
BL3 0 1 0 1 0 1 0 1
BL4 0 1 0 1 0 1 0 1
BL5 0 1 0 1 0 1 0 1
BL6 0 1 0 1 0 1 0 1
BL7 0 1 0 1 0 1 0 1
由于第一数据在第一条字线WL0上的位置发生了变化，相应的，后面的字线，即字线WL1-WL7上相应的数据也发生了变化，以满足后一条字线所对应的存储单元中写入的数据与前一条字线所对应的存储单元中写入的数据相反的要求。
需要说明的是，对于存储阵列中字线的第一突发长度的存储单元而言，第一数据可以位于BL0-BL7中任一比特位上。同时，后面的字线上相应比特位也会发生变化，与前一字线上的同一比特位相反。
本公开实施例提供的存储器失效测试方法，通过在存储阵列内的存储单元中写入预设存储数据，并且将预设存储数据设置为包含一个相反的第二数据的数据结构，使存储阵列的读取环境变得更严格，在读取操作后，通过对比写入的数据与读取的数据，即可准确判断出存储器是否存在异常，可以有效提升存储器的检测准确率，进而提升存储器的良率。
本公开示例性实施方式中，通过在存储阵列相邻的两条字线中，后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元中相反的数据，可以在同一比特位上制造出相反的数据，从而可以使与比特位相连的输入输出线LIO上有数据翻转的动作，以为存储阵列提供严格的读取环境，进而提升LIO漏电测试的准确性。
为了更好地理解本公开实施例，参照图4，提供了本公开实施例的一种存储阵列的数据写入示意图。在第一条字线WL0的第一Burst长度的存储单元中写入“10000000”，在第二条字线WL1的第一Burst长度的存储单元中写入“01111111”，可以造成LIO之间的压差。利用LIO共用的特性，在数据读取的过程中，由于读取的是字线里写入的不同资料，使得LIO有一个翻转的动作，有助于检测LIO之间是否存在漏电或断路问题。
本公开示例性实施方式中，对于具有八个比特位的第一突发长度存储单元而言，由第一数据和第二数据组成的预设存储数据，通过改变第一数据在第一突发长度存储单元上的比特位，可以获得八种预设存储数据；再在第一数据分别为0或1的情况下，总共可以获得十六种预设存储数据。本公开示例性实施方式不再展开对十六种预设存储数据一一进行列举。
本公开示例性实施方式中，对于存储阵列中任意字线的第二突发长度的存储单元，预设存储数据可以包括多个第二数据，例如，如表3所示的第一条字线WL0所对应的位线BL8-BL15，其中的第二数据是数据0。在实际应用中，根据第一突发长度的预设存储数据中第二数据的取值，第二突发长度的第二数据还可以是数据1。
表3
  WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7
BL0 1 0 1 0 1 0 1 0
BL1 0 1 0 1 0 1 0 1
BL2 0 1 0 1 0 1 0 1
BL3 0 1 0 1 0 1 0 1
BL4 0 1 0 1 0 1 0 1
BL5 0 1 0 1 0 1 0 1
BL6 0 1 0 1 0 1 0 1
BL7 0 1 0 1 0 1 0 1
BL8 0 1 0 1 0 1 0 1
BL9 0 1 0 1 0 1 0 1
BL10 0 1 0 1 0 1 0 1
BL11 0 1 0 1 0 1 0 1
BL12 0 1 0 1 0 1 0 1
BL13 0 1 0 1 0 1 0 1
BL14 0 1 0 1 0 1 0 1
BL15 0 1 0 1 0 1 0 1
同样的，对于第二突发长度的存储单元而言，后一条字线所对应的存储单元中写入的数据与前一条字线所对应的存储单元中写入的数据也是相反的。通过在存储阵列中写入如表3所示的数据，可以在数据读取的过程中，使LIO有翻转的动作，以更严格地检测出LIO的漏电问题。
本公开示例性实施方式中，对于存储阵列中任意字线的剩余突发长度而言，其存储单元中的预设存储数据可以按照第一突发长度和第二突发长度重复排列。例如，第三突发长度的存储单元的预设存储数据与第一突发长度的存储单元的预设存储数据相同、第四突发长度的存储单元的预设存储数据与第二突发长度的存储单元的预设存储数据相同，如此重复，直至第127突发长度的存储单元的预设存储数据与第一突发长度的存储单元的预设存储数据相同、第128突发长度的存储单元的预设存储数据与第二突发长度的存储单元的预设存储数据相同。例如，如图5所示，第127突发长度的存储单元的预设存储数据与第一突发长度的存储单元的预设存储数据相同，均为10000000；第128突发长度的存储单元的预设存储数据与第二突发长度的存储单元的预设存储数据相同，均为00000000。
简单总结为：在剩余突发长度的存储单元中，奇数突发长度的存储单元的预设存储数据与第一突发长度的存储单元的预设存储数据相同、偶数突发长度的存储单元的预设存储数据与第二突发长度的存储单元的预设存储数据相同。
为了更好地理解本公开实施例，参照图6，示出了本公开实施例中待测存储器的工作时序图一。如图6所示，当在存储阵列中读取数据0时，列选择信号YS打开，位线BL 与LIO连接，参考位线BL/与LIO/连接，VSS的源(source)端连接位线BL，此时LIO与LIO/处于浮动(floating)状态(浮动即Vary Source不给LIO供电，因为初始时YS不打开，此时Vary Source一直给LIO供电)，BL电位的VSS会迅速将处于浮动状态的LIO(Vary)拉低。经过一段时间后，BL与LIO的电位逐渐靠近VSS，但不会到达VSS。在YS列选择信号关闭后，LIO与BL断开，LIO不处于浮动状态，并重新与Vary Source相连，Vary电位将LIO快速拉升以准备下一次读取或写入操作。
下一步在读1时，若LIO存在短路或高阻情况，LIO电位回拉较慢，存在delta V(如delta v2)不足的情况，存储器会存在由于LIO与LIO/压差不足引起的数据误判：将读1误读成0。
参照图7，示出了本公开实施例中待测存储器的工作时序图二。在图7中，当在存储阵列中读取1时，列选择信号YS打开，位线BL与LIO连接，参考位线BL/与LIO/连接，VSS的源(source)端连接位线BL/，此时LIO与LIO/处于浮动(floating)状态(浮动即Vary Source不给LIO/供电，因为初始时YS不打开，此时Vary Source一直给LIO/供电)，BL/电位的VSS会迅速将处于浮动状态的LIO/(Vary)拉低，经过一段时间后，BL/与LIO/的电位逐渐靠近VSS，但不会到达VSS。在YS列选择信号关闭后，LIO/与BL/断开，LIO/不处于浮动状态，并重新与Vary Source相连，Vary电位将LIO/快速拉升以准备下一次读取或写入操作。
下一步在读0时，若LIO/存在短路或高阻情况，LIO/电位回拉较慢，存在delta V(如delta v2)不足的情况，待测存储器存在由于LIO与LIO/压差不足引起的数据误判：将读0误读成1。
本公开示例性实施方式提供的存储器失效测试方法，通过在存储阵列相邻的两条字线中，后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元中相反的数据，在LIO上存储数据翻转，使存储器的读取环境变得更加严格，在对存储器进行写入与读取操作后，通过对比写入与读取的数据，即可准确判断出存储器是否存在异常，包括存储器的输入输出线上是否存在漏电或阻值过大的情况，可以有效提升存储器的检测准确率，进而提升存储器的良率。
本公开示例性实施方式中，读取存储阵列中数据的顺序与写入存储阵列中数据的顺序相同。例如，如果在存储阵列中写入数据的方式是Y-Page写入方式，那么读取数据的方式也就是Y-Page读取方式。
其中，上述的Y-Page写入方式包括：在存储阵列的存储单元中写入数据的时候，先开启其中一条字线，将数据全部写入这条字线上对应的所有存储单元后，关闭这条字线；然后再开启下一条字线，将数据全部写入该下一条字线上对应的所有存储单元后，关闭该条字线……，以此类推，直至将数据写入存储阵列的各个字线连接的存储单元中。
通过在写完一个BANK上的存储阵列后，再写下一个BANK上的存储阵列，如此重复，直到写完所有BANK的存储阵列的存储单元。
在本公开的一种示例性实施方式中，在存储阵列的存储单元中写入测试数据时，可以遍历存储阵列的各条字线，对遍历到的每一条目标字线分别执行以下操作：
步骤一、开启目标字线，将预设存储数据按照比特依次写入与目标字线连接的所有存储单元；其中，与目标字线连接的每个存储单元写入预设存储数据中的一个比特，预设存储数据的比特数与字线连接的存储单元的个数相同。
步骤二、关闭上述目标字线。
在实际应用中，可以预先根据每条字线上连接的存储单元的个数，配置上述预设存储数据。例如，当每条字线上连接的存储单元为16个时，可以配置16个预设存储数据；当每条字线上连接的存储单元为32个时，可以配置32个预设存储数据。
本公开示例性实施方式中，上述的Y-Page读取方式可以包括：开启一条字线，顺序读 完该字线所对应的存储单元中的数据之后，关闭该条字线；接着开启下一条字线，顺序读完下一条字线所对应的存储单元中的数据之后，关闭下一条字线……，以此类推，直至读取完存储阵列的各个字线连接的存储单元中的数据。
本公开示例性实施方式中，在读取完存储阵列中的数据之后，就可以将读取的数据与之前写入的数据进行比较，以获得比较结果，并且根据比较结果就可以对存储器的失效状态进行判定。
具体的判定过程包括：判断读取的存储阵列中的数据与写入存储阵列中的数据是否相同，如果相同，说明存储器未有异常；如果不同，则可以判定存储器存在输入输出线漏电或断路的风险。
综上，本公开示例性实施方式通过在存储阵列的相邻的两条字线中，后一条字线对应的存储单元中写入与前一条字线所对应的存储单元中相反的数据，并且在第一条字线所对应的存储单元中写入预设存储数据，其中该预设存储数据中含有一个相反的数据，如此可以在LIO上提供一个存储数据翻转的条件，使存储器的读取环境变得更加严格，在对存储器进行写入与读取操作后，通过对比写入与读取的数据，即可准确判断出存储器是否存在异常，包括存储器的输入输出线上是否存在漏电或阻值过大的情况，可以有效提升存储器的检测准确率，进而提升存储器的良率。
需要说明的是，尽管在附图中以特定顺序描述了本发明中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
此外，在本示例实施例中，还提供了一种存储器失效测试装置。参照图8，该存储器失效测试装置700可以包括：数据写入模块710、数据读取模块720、数据比较模块730、判定模块740和预设存储数据确定模块750，其中：
数据写入模块710，用于执行存储器的存储阵列的数据写入动作；
所述数据写入动作包括：在所述存储器的存储阵列内的存储单元中写入预设存储数据；相邻的两条字线中，在所述存储阵列的后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元的数据相反的数据；重复所述数据写入动作，直到写完所述存储阵列的所有字线所对应的存储单元；
数据比较模块730，用于读取所述存储阵列中的数据，并与写入的数据进行比较，获得比较结果；
判定模块740，用于根据所述比较结果对所述存储器的失效状态进行判定。
在本公开的一种示例性实施方式中，对于存储阵列中字线的第一突发长度的存储单元，预设存储数据包括一个第一数据和多个第二数据；其中，第一数据和第二数据是相反的数据。
在本公开的一种示例性实施方式中，第一数据在第一突发长度的存储单元的任一比特位上。
在本公开的一种示例性实施方式中，预设存储数据确定模块750，用于改变第一数据在第一突发长度存储单元上的比特位，获得十六种预设存储数据。
在本公开的一种示例性实施方式中，对于存储阵列中字线的第二突发长度的存储单元，预设存储数据包括多个第二数据。
在本公开的一种示例性实施方式中，数据读取模块720，用于读取存储阵列中数据的顺序与写入存储阵列中数据的顺序相同。
在本公开的一种示例性实施方式中，数据读取模块720，用于开启一条字线，顺序读完字线所对应的存储单元中的数据之后，关闭字线；开启下一条字线，顺序读完下一条字线所对应的存储单元中的数据之后，关闭下一条字线。
在本公开的一种示例性实施方式中，判定模块740，用于判断读取的存储阵列中的数据与写入存储阵列中数据是否相同；如果不同，则判定存储器存在输入输出线漏电或断路。
上述中各存储器失效测试装置的虚拟模块的具体细节已经在对应的存储器失效测试方法中进行了详细的描述，因此，此处不再赘述。
应当注意，尽管在上文详细描述中提及了存储器失效测试装置的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
在本公开的示例性实施例中，还提供了一种能够实现上述方法的电子设备。
所属技术领域的技术人员能够理解，本发明的各个方面可以实现为系统、方法或程序产品。因此，本发明的各个方面可以具体实现为以下形式，即：完全的硬件实施方式、完全的软件实施方式(包括固件、微代码等)，或硬件和软件方面结合的实施方式，这里可以统称为“电路”、“模块”或“系统”。
下面参照图9来描述根据本发明的这种实施方式的电子设备800。图9显示的电子设备800仅仅是一个示例，不应对本发明实施例的功能和使用范围带来任何限制。
如图9所示，电子设备800以通用计算设备的形式表现。电子设备800的组件可以包括但不限于：上述至少一个处理单元810、上述至少一个存储单元820、连接不同系统组件(包括存储单元820和处理单元810)的总线830、显示单元840。
其中，所述存储单元820存储有程序代码，所述程序代码可以被所述处理单元810执行，使得所述处理单元810执行本说明书上述“示例性方法”部分中描述的根据本发明各种示例性实施方式的步骤。例如，所述处理单元810可以执行如图3中所示的步骤S310、执行存储器的存储阵列的数据写入动作；步骤S320、重复数据写入动作，直到写完存储阵列的所有字线所对应的存储单元；步骤S330、读取存储阵列中的数据，并与写入的数据进行比较，获得比较结果；步骤S340、根据比较结果对存储器的失效状态进行判定。
存储单元820可以包括易失性存储单元形式的可读介质，例如随机存取存储单元(RAM)8201和/或高速缓存存储单元8202，还可以进一步包括只读存储单元(ROM)8203。
存储单元820还可以包括具有一组(至少一个)程序模块8205的程序/实用工具8204，这样的程序模块8205包括但不限于：操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或某种组合中可能包括网络环境的实现。
总线830可以为表示几类总线结构中的一种或多种，包括存储单元总线或者存储单元控制器、外围总线、图形加速端口、处理单元或者使用多种总线结构中的任意总线结构的局域总线。
电子设备800也可以与一个或多个外部设备870(例如键盘、指向设备、蓝牙设备等)通信，还可与一个或者多个使得用户能与该电子设备800交互的设备通信，和/或与使得该电子设备800能与一个或多个其它计算设备进行通信的任何设备(例如路由器、调制解调器等等)通信。这种通信可以通过输入/输出(I/O)接口850进行。并且，电子设备800还可以通过网络适配器860与一个或者多个网络(例如局域网(LAN)，广域网(WAN)和/或公共网络，例如因特网)通信。如图所示，网络适配器860通过总线830与电子设备800的其它模块通信。应当明白，尽管图中未示出，可以结合电子设备800使用其它硬件和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、RAID系统、磁带驱动器以及数据备份存储系统等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台 计算设备(可以是个人计算机、服务器、终端装置、或者网络设备等)执行根据本公开实施方式的方法。
在本公开的示例性实施例中，还提供了一种计算机可读存储介质，其上存储有能够实现本说明书上述方法的程序产品。在一些可能的实施方式中，本发明的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当所述程序产品在终端设备上运行时，所述程序代码用于使所述终端设备执行本说明书上述“示例性方法”部分中描述的根据本发明各种示例性实施方式的步骤。
根据本发明的实施方式的用于实现上述方法的程序产品，其可以采用便携式紧凑盘只读存储器(CD-ROM)并包括程序代码，并可以在终端设备，例如个人电脑上运行。然而，本发明的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
所述程序产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以为但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本发明操作的程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。
此外，上述附图仅是根据本发明示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (18)

  1. 一种存储器失效测试方法，所述方法包括：
    执行所述存储器的数据写入动作；
    所述数据写入动作包括：在所述存储器的存储阵列内的存储单元中写入预设存储数据，相邻的两条字线中，在所述存储阵列的后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元的数据相反的数据；
    重复所述数据写入动作，直到写完所述存储阵列的所有字线所对应的存储单元；
    读取所述存储阵列中的数据，并与写入的数据进行比较，获得比较结果；
    根据所述比较结果对所述存储器的失效状态进行判定。
  2. 根据权利要求1所述的方法，其中，对于所述存储阵列中任意所述字线的第一突发长度的存储单元，所述预设存储数据包括一个第一数据和多个第二数据；
    其中，所述第一数据和所述第二数据是相反的数据。
  3. 根据权利要求2所述的方法，其中，所述第一数据在所述第一突发长度的存储单元的任一比特位上。
  4. 根据权利要求2或3所述的方法，其中，改变所述第一数据在所述第一突发长度存储单元上的比特位，获得十六种所述预设存储数据。
  5. 根据权利要求2所述的方法，其中，对于所述存储阵列中任意所述字线的第二突发长度的存储单元，所述预设存储数据包括多个所述第二数据；
    对于所述存储阵列中任意所述字线的剩余突发长度的存储单元，所述预设存储数据按照所述第一突发长度和所述第二突发长度的预设存储数据重复排列。
  6. 根据权利要求1所述的方法，其中，所述方法还包括：
    读取所述存储阵列中数据的顺序与写入所述存储阵列中数据的顺序相同。
  7. 根据权利要求6所述的方法，其中，读取所述存储阵列中的数据，包括：
    开启一条字线，顺序读完所述字线所对应的存储单元中的数据之后，关闭所述字线；
    开启下一条字线，顺序读完所述下一条字线所对应的存储单元中的数据之后，关闭所述下一条字线。
  8. 根据权利要求1所述的方法，其中，根据所述比较结果对所述存储器的失效状态进行判定，包括：判断读取的所述存储阵列中的数据与写入所述存储阵列中的数据是否相同；
    如果不同，则判定所述存储器存在输入输出线漏电或断路。
  9. 一种存储器失效测试装置，所述装置包括：
    数据写入模块，用于执行存储器的存储阵列的数据写入动作；
    所述数据写入动作包括：在所述存储器的存储阵列内的存储单元中写入预设存储数据；相邻的两条字线中，在所述存储阵列的后一条字线所对应的存储单元中写入与前一条字线所对应的存储单元的数据相反的数据；重复所述数据写入动作，直到写完所述存储阵列的所有字线所对应的存储单元；
    数据比较模块，用于读取所述存储阵列中的数据，并与写入的数据进行比较，获得比较结果；
    判定模块，用于根据所述比较结果对所述存储器的失效状态进行判定。
  10. 根据权利要求9所述的装置，其中，对于所述存储阵列中字线的第一突发长度的存储单元，所述预设存储数据包括一个第一数据和多个第二数据；
    其中，所述第一数据和所述第二数据是相反的数据。
  11. 根据权利要求10所述的装置，其中，所述第一数据在所述第一突发长度的存储单元的任一比特位上。
  12. 根据权利要求10或11所述的装置，其中，所述装置还包括：
    预设存储数据确定模块，用于改变所述第一数据在所述第一突发长度存储单元上的比特位，获得十六种所述预设存储数据。
  13. 根据权利要求10所述的装置，其中，对于所述存储阵列中字线的第二突发长度的存储单元，所述预设存储数据包括多个所述第二数据。
  14. 根据权利要求9所述的装置，其中，还包括：
    数据读取模块，用于读取所述存储阵列中数据的顺序与写入所述存储阵列中数据的顺序相同。
  15. 根据权利要求14所述的装置，其中，所述数据读取模块，用于开启一条字线，顺序读完所述字线所对应的存储单元中的数据之后，关闭所述字线；开启下一条字线，顺序读完所述下一条字线所对应的存储单元中的数据之后，关闭所述下一条字线。
  16. 根据权利要求9所述的装置，其中，所述判定模块，用于判断读取的所述存储阵列中的数据与写入所述存储阵列中数据是否相同；如果不同，则判定所述存储器存在输入输出线漏电或断路。
  17. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1-8中任意一项所述的存储器失效测试方法。
  18. 一种电子设备，包括：
    处理器；以及
    存储器，用于存储所述处理器的可执行指令；
    其中，所述处理器配置为经由执行所述可执行指令来执行权利要求1-8中任意一项所述的存储器失效测试方法。
PCT/CN2022/101614 2022-04-18 2022-06-27 存储器失效测试方法及装置、存储介质及电子设备 Ceased WO2023201883A1 (zh)

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