WO2023201813A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2023201813A1
WO2023201813A1 PCT/CN2022/093480 CN2022093480W WO2023201813A1 WO 2023201813 A1 WO2023201813 A1 WO 2023201813A1 CN 2022093480 W CN2022093480 W CN 2022093480W WO 2023201813 A1 WO2023201813 A1 WO 2023201813A1
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Prior art keywords
electrode
array substrate
display panel
layer
cathode
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PCT/CN2022/093480
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English (en)
French (fr)
Inventor
章仟益
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/779,147 priority Critical patent/US20240172524A1/en
Publication of WO2023201813A1 publication Critical patent/WO2023201813A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel and a display panel preparation method.
  • the cathodes of existing display panels are usually made of materials with high resistivity such as thin layers of metallic silver, which results in a large voltage drop and a large difference between the actual driving voltage of the array substrate and the power supply voltage. In large-size display panels, It manifests as uneven brightness over a large area, thus affecting the display effect.
  • Embodiments of the present application provide a display panel and a display panel preparation method, which can alleviate the technical problem of large cathode voltage drop in existing display panels.
  • An embodiment of the present application provides a display panel, including a surface cathode overlapping area, where the surface cathode overlapping area includes:
  • An auxiliary electrode, the auxiliary electrode is arranged above the array substrate;
  • a luminescent material layer, the luminescent material layer is disposed above the array substrate;
  • a cathode the cathode is disposed above the luminescent material layer and the auxiliary electrode, and the cathode overlaps the auxiliary electrode;
  • a passivation layer, a flat layer, and a pixel definition layer are arranged in sequence above the array substrate, and a layer penetrating the passivation layer, the flat layer, and the pixel definition layer is arranged in the surface cathode overlapping area.
  • a via hole, the auxiliary electrode is disposed in the via hole, an undercut groove is formed between the auxiliary electrode and the array substrate, and the undercut groove is filled with the luminescent material layer.
  • the auxiliary electrode is arranged in a convex shape on a surface away from the array substrate, and the convexity faces a side away from the array substrate.
  • the auxiliary electrode includes a first electrode and a second electrode disposed on a side of the first electrode away from the array substrate, and the first electrode is connected to the array substrate.
  • the substrate forms the undercut groove, and the surface of the second electrode away from the array substrate is arranged in a protrusion shape, and the protrusion faces a side away from the array substrate.
  • the array substrate includes a substrate and a source electrode and a drain electrode located on one side of the substrate, and the first electrode is the same as the source electrode and drain electrode. Layer settings.
  • the display panel further includes an anode connected to the source electrode, and the second electrode is arranged in the same layer as the anode.
  • no luminescent material layer is provided on the upper surface of the second electrode, and the cathode is provided covering the second electrode.
  • the first electrode includes a first part and a second part disposed on a side of the first part away from the array substrate, and the first part is on the array substrate.
  • the orthographic projection of is smaller than the orthographic projection of the second part on the array substrate.
  • the first part and the second part of the first electrode are provided integrally.
  • the contact area between the cathode and the second electrode and the first electrode is larger than the upper surface area of the second electrode.
  • the protrusion is an independent component
  • the protrusion structure is made of a conductive material
  • the protrusion structure may be made of a different material than the second electrode
  • the protrusion is in a triangular pyramid shape, and the lower surface of the second electrode is in flush contact with the upper surface of the first electrode.
  • the vertex angle range of the protrusion on the side away from the array substrate is greater than or equal to 60 degrees, and the thickness range of the protrusion is greater than or equal to 110 nanometers.
  • a pixel definition layer and a flat layer are also provided above the array substrate, and the orthographic projections of the pixel definition layer and the flat layer on the substrate are different from the The orthographic projection of the undercut groove on the substrate is offset.
  • the pixel definition layer and the flat layer are made of a positive photoresist material.
  • the cathode covers the second electrode.
  • the cathode is also partially disposed in the undercut groove, and the part of the cathode located in the undercut groove can be in contact with the side of the first part.
  • the lateral depth of the undercut groove is greater than 2 microns.
  • the second electrode and the cathode are made of any one of indium tin oxide, indium zinc oxide, molybdenum titanium, and titanium.
  • Embodiments of the present application provide a display panel preparation method, including:
  • An auxiliary electrode is prepared above the array substrate, and an undercut groove is formed between the auxiliary electrode and the array substrate;
  • a passivation layer, a flat layer, and a pixel definition layer are sequentially prepared above the array substrate;
  • a luminescent material layer is prepared on the side of the pixel definition layer away from the array substrate, and the luminescent material layer is filled in the undercut groove in the cathode overlap area.
  • the steps of preparing the first part and the second part disposed on the first part further include: etching the first electrode layer through a photolithography process to prepare an undercut recess. groove, the second part is disposed covering the first part, and the depth of the undercut groove is greater than 2 microns.
  • An undercut groove is formed between the auxiliary electrode and the array substrate, and at the same time, the upper surface of the auxiliary electrode is arranged in a convex shape, so that the luminescent material layer is filled in the undercut groove, exposing part of the auxiliary electrode, and the cathode and the
  • the auxiliary electrode surface contact reduces the contact resistance of the cathode by increasing the contact area between the cathode and the auxiliary electrode, thereby alleviating the technical problem of large cathode voltage drop in existing display panels.
  • Figure 1 is a schematic cross-sectional view of a display panel provided by this application.
  • Figure 2A is a first cross-sectional schematic diagram of the display panel preparation method provided by this application.
  • Figure 2B is a second cross-sectional schematic diagram of the display panel preparation method provided by this application.
  • Figure 2C is a third schematic cross-sectional view of the display panel preparation method provided by this application.
  • Figure 2D is a fourth schematic cross-sectional view of the display panel preparation method provided by this application.
  • Figure 2E is a fifth cross-sectional schematic diagram of the display panel preparation method provided by this application.
  • Figure 2F is a sixth cross-sectional schematic diagram of the display panel preparation method provided by this application.
  • FIG. 2G is a seventh cross-sectional schematic diagram of the display panel preparation method provided by this application.
  • Figure 3 is a schematic flow chart of a display panel preparation method provided by this application.
  • the material used to prepare the cathode usually has high resistivity and thin thickness, which results in a large voltage drop in the display panel and uneven brightness in a large area of the display panel, thus affecting the display effect; in order to reduce the cathode voltage In the surface cathode overlapping area 1, the cathode is usually placed in contact with the auxiliary electrode through a via hole that at least penetrates the luminescent material layer, thereby reducing the resistance of the cathode.
  • the cathode is only in contact with the upper surface portion of the auxiliary electrode. Due to the small contact area, the contact resistance is large, and the effect of reducing the cathode resistance is not obvious, resulting in the technical problem of large voltage drop at the cathode.
  • the existing technology urgently needs to provide a display panel that can reduce the cathode contact impedance of the surface cathode lapping area 1 .
  • the present application provides a display panel.
  • the display panel includes an array substrate 10, an auxiliary electrode, a luminescent material layer 60, and a cathode 70.
  • the auxiliary electrode is disposed on the array.
  • the luminescent material layer 60 is disposed above the array substrate 70
  • the cathode 70 is disposed above the luminescent material layer 60 and the auxiliary electrode
  • the cathode 70 overlaps with the auxiliary electrode
  • a passivation layer 102, a flat layer 40, and a pixel definition layer 50 are arranged in sequence above the array substrate 10, and a layer penetrating the passivation layer 102, the flat layer 40 is provided in the surface cathode overlapping area 1 , the via hole of the pixel definition layer 50, the auxiliary electrode is arranged in the via hole, an undercut groove 2 is formed between the auxiliary electrode and the array substrate 10, the undercut groove 2
  • the luminescent material layer 60 is filled inside.
  • the exposed part of the auxiliary electrode is in contact with the cathode, thereby increasing the contact area between the cathode and the auxiliary electrode, reducing the contact resistance of the cathode, and easing the problem of existing display
  • the panel has a technical problem with a large cathode voltage drop.
  • the auxiliary electrode includes a first electrode 20 and a second electrode 30 disposed on a side of the first electrode 20 away from the array substrate 10 .
  • the luminescent material layer 60 is in the same layer as the luminescent layer and is prepared through a one-step process.
  • the display panel includes a luminescent area and a surface cathode lapping area 1, and the luminescent layer is disposed in the luminescent area.
  • the array substrate 10 further includes a passivation layer 102, the passivation layer 102 is provided above the substrate 101, a via hole is provided in the passivation layer 102, and the first electrode 20 is located on the inside the via hole.
  • the luminescent material layer 60 is filled in the undercut groove 2, and the exposed first electrode 20 can be in surface contact with the cathode 70, thereby increasing the distance between the cathode 70 and the third cathode 70.
  • the contact area between the two electrodes 30 and the first electrode 20 further reduces the contact resistance of the cathode 70 , thereby further reducing the resistance of the cathode 70 .
  • the surface of the auxiliary electrode away from the array substrate 10 is arranged in a protrusion shape, and the protrusion faces a side away from the array substrate 10 .
  • the first electrode 20 and the array substrate 10 form the undercut groove 2
  • the second electrode 30 is disposed in a convex shape on a surface away from the array substrate 10 .
  • the protrusion faces toward the side away from the array substrate 10 .
  • the array substrate 10 includes a substrate 101 and a source electrode and a drain electrode located on one side of the substrate.
  • the display panel also includes an anode connected to the source electrode.
  • the third An electrode 20 is arranged in the same layer as the source electrode and the drain electrode, and the second electrode 30 is arranged in the same layer as the anode.
  • the luminescent material layer 60 is not provided on the upper surface of the second electrode 30 , and the cathode 70 is provided covering the second electrode 30 .
  • the luminescent material layer is filled in the undercut groove, and part or all of the upper surface of the second electrode 30 can be exposed for contact with the cathode, so as to increase the contact area between the cathode and the auxiliary electrode. , thereby reducing the contact resistance and thereby reducing the cathode voltage drop.
  • no luminescent material layer is provided on the upper surface of the second electrode 30 , that is, the upper surface is completely exposed to increase the contact area with the cathode 70 , and the design in which the upper surface of the second electrode 30 is fully exposed reduces the risk of The effect of cathode 70 contact resistance is better.
  • the first part 201 and the second part 202 of the first electrode 20 are integrated.
  • the array substrate 10 further includes a source-drain layer, the source-drain layer includes a source electrode and a drain electrode, and the first electrode 20 is in the same layer as the source electrode/drain electrode.
  • the preparation process is simplified and the cost is reduced.
  • the upper surface of the second electrode 30 is arranged in a protrusion shape, and the protrusion faces a side away from the substrate 101 .
  • the convex shape may be any one of a trapezoidal shape, a cone shape, and a triangular shape.
  • the organic material is guided into the undercut groove 2 through the protrusions, and the protruded upper surface is conducive to filling the luminescent material layer 60 into the undercut groove 2, preventing the luminescent material from being filled in the undercut groove 2. It is disposed on the surface of the first electrode 20 and the second electrode 30 to increase the contact area between the cathode 70 and the second electrode 30 and the first electrode 20, thereby reducing the contact area between the cathode 70 and the second electrode 30 and the first electrode. Contact resistance of 20.
  • the upper surface of the second electrode 30 needs at least an inclined surface, and the inclined surface is used to guide the organic material into the undercut groove 2 .
  • the upper surface of the second electrode 30 is convex, which can also increase the contact area between the upper surface of the second electrode 30 and the cathode 70 .
  • the luminescent material of the luminescent material layer 60 to enter the undercut groove 2 and partially expose the first electrode 20 to reduce the cathode. Contact resistance of 70.
  • the contact area between the cathode 70 and the second electrode 30 and the first electrode 20 is larger than the upper surface area of the second electrode 30 .
  • the surface of the cathode 70 away from the array substrate 10 may not be provided with a luminescent material layer, that is, the side of the cathode away from the array substrate is completely exposed, and at the same time, the cathode is also partially in contact with the side surface of the auxiliary electrode.
  • the contact area between the cathode 70 and the auxiliary electrode is further limited, the cathode impedance is reduced, and the voltage drop of the cathode 70 is reduced.
  • the cathode 70 is only in contact with the second electrode 30 , and a protruding structure is provided on the upper surface of the second electrode 30 , and the protruding structure is an independent component.
  • the cathode 70 is in contact with the side surface of the second electrode 30 .
  • the protruding structure is made of a conductive material, and the protruding structure may be made of a different material than the second electrode 30 .
  • the protruding structure may be the same as the second electrode 30 .
  • the independent components are protrusions, thereby reducing the contact resistance of the cathode 70.
  • the protrusion is in the shape of a triangular pyramid, and the lower surface of the second electrode 30 is flush with the upper surface of the second part 202 .
  • the apex angle range of the protrusion is greater than or equal to 60 degrees, and the thickness range of the protrusion is greater than or equal to 110 nanometers.
  • the vertex angle is an angle of a side of the protrusion away from the array substrate.
  • a pixel definition layer 50 and a flat layer 40 are also provided above the array substrate 10.
  • the orthographic projections of the pixel definition layer 50 and the flat layer 40 on the substrate 101 are different from each other.
  • the orthographic projection of the undercut groove 2 on the substrate 101 is offset.
  • the thickness of the pixel definition layer 50 may be 2000 Angstroms.
  • the pixel definition layer 50 and the flat layer 40 are made of a positive photoresist material.
  • the pixel definition layer 50 and the flat layer 40 are made of the same material.
  • the flat layer 40 is made of a material with strong leveling properties.
  • the flat layer 40 has strong leveling properties, which is beneficial for the flat layer 40 to fill the undercut groove 2 .
  • the cathode 70 is also partially disposed in the undercut groove 2 , and the portion of the cathode 70 located in the undercut groove 2 can be in contact with the side surface of the first part 201 .
  • the cathode located in the undercut groove is also in contact with the side surface of the first electrode, which further increases the contact area and reduces the contact resistance.
  • the second electrode 30 and the cathode 70 are made of any one of indium tin oxide, indium zinc oxide, molybdenum titanium, and titanium.
  • the second electrode 30 and the cathode 70 may be made of the same material.
  • the lateral depth of the undercut groove 2 is greater than 2 microns.
  • the width of the second part 202 is greater than that of the first part 201 by at least 4 microns.
  • the luminescent material layer 60 when preparing the luminescent layer of the existing display panel, it is easy to simultaneously prepare the luminescent material layer 60 in the surface cathode connecting area 1, and the luminescent material layer 60 will cover the first electrode 20 and the second electrode 30. side surface, resulting in a smaller contact area between the cathode 70 and the second electrode 30 and a larger contact resistance.
  • embodiments of the present application provide a display panel preparation method, including:
  • a luminescent material layer 60 is prepared on the side of the pixel definition layer 50 away from the array substrate 10 , and the luminescent material layer 60 is filled in the undercut groove 2 in the cathode lapping area 1 .
  • the contact area between the cathode 70 and the auxiliary electrode is larger than the upper surface area of the auxiliary electrode.
  • the contact area between the cathode 70 and the second electrode 30 and the first electrode 20 is larger than the upper surface area of the second electrode 30 .
  • an array substrate 10 is provided, and the array substrate 10 includes a first electrode 20;
  • the second electrode 30 is prepared, and the upper surface of the second electrode 30 may be in a tapered shape;
  • a layer of second organic material is coated, and the first organic material and the second organic material above the undercut groove 2 are removed by exposure to prepare a flat layer 40 and a pixel definition layer. 50;
  • the luminescent material layer 60 is prepared, and the undercut groove 2 is filled with the luminescent material layer 60;
  • the cathode 70 is prepared, and the cathode 70 is in surface contact with the second electrode 30 and the first electrode 20.
  • the pixel definition layer 50 can be formed by exposure using a semi-transparent mask.
  • the steps of preparing the first part 201 and the second part 202 disposed on the first part 201 further include: etching the first electrode 20 layer through a photolithography process to prepare the undercut groove 2 , the second part 202 is provided covering the first part 201, and the depth of the undercut groove 2 is greater than 2 microns.
  • the step of preparing the flat layer 40 and the pixel definition layer 50 further includes: the first organic material is the same as the second organic material, and the first organic material is processed in a one-step process.
  • the flat layer 40 and the pixel definition layer 50 are prepared by exposing the material and the second organic material.
  • the flat layer 40 and the pixel definition layer 50 are prepared in a one-step process, which simplifies the process and reduces the cost.
  • the step of preparing the second electrode 30 further includes: evaporating a layer of conductive material, patterning the conductive material to form a triangular pyramid-shaped upper surface of the second electrode 30, and The lower surface is flush with the upper surface of the second part 202 .
  • This application also proposes a display module and a display device, wherein both the display module and the display device include the above-mentioned display panel, which will not be described again here.
  • the display panel provided in this embodiment includes a surface-cathode overlap area.
  • the surface-cathode overlap area includes an array substrate, an auxiliary electrode, a luminescent material layer, and a cathode.
  • An undercut groove is formed between the auxiliary electrode and the array substrate. , the undercut groove is filled with the luminescent material layer; by forming an undercut groove between the auxiliary electrode and the array substrate, the luminescent material layer is filled in the undercut groove, and the exposed auxiliary electrode and Cathode contact increases the contact area between the cathode and the auxiliary electrode, reduces the contact resistance of the cathode, thereby reducing the cathode voltage drop.

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Abstract

一种显示面板、一种显示面板制备方法，在面阴极搭接区（1），该显示面板包括阵列基板（10）、辅助电极、发光材料层（60）、阴极（70），辅助电极与阵列基板（10）之间设置有底切凹槽（2），发光材料层（60）填充于底切凹槽（2）内；通过使发光材料层（60）填充于底切凹槽（2）内，露出的部分辅助电极与阴极（70）接触，增大了阴极（70）与辅助电极的接触面积。

Description

显示面板及其制备方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板、一种显示面板制备方法。
背景技术
现有显示面板的阴极通常采用薄层金属银等电阻率较大的材料制备，造成电压降较大，导致阵列基板的实际驱动电压与电源电压有较大的差异，在大尺寸显示面板中，表现为大面积的亮度不均匀，从而影响显示效果。
技术问题
因此，现有显示面板存在阴极电压降较大的技术问题。
技术解决方案
本申请实施例提供一种显示面板、一种显示面板制备方法，可以缓解现有显示面板存在阴极电压降较大的技术问题。
本申请实施例提供一种显示面板，包括面阴极搭接区，所述面阴极搭接区包括：
阵列基板；
辅助电极，所述辅助电极设置于所述阵列基板上方；
发光材料层，所述发光材料层设置于所述阵列基板上方；
阴极，所述阴极设置于所述发光材料层、所述辅助电极上方，所述阴极与所述辅助电极搭接；
其中，所述阵列基板上方还依次设置有钝化层、平坦层、像素定义层，在所述面阴极搭接区设置有一贯穿所述钝化层、所述平坦层、所述像素定义层的过孔，所述辅助电极设置于所述过孔内，所述辅助电极与所述阵列基板之间形成有底切凹槽，所述底切凹槽内填充有所述发光材料层。
可选的，在本申请的一些实施例中，所述辅助电极远离所述阵列基板的表面呈凸起状设置，所述凸起朝向远离所述阵列基板的一侧。
可选的，在本申请的一些实施例中，所述辅助电极包括第一电极以及设置 于所述第一电极远离所述阵列基板一侧的第二电极，所述第一电极与所述阵列基板形成所述底切凹槽，所述第二电极远离所述阵列基板的表面呈凸起状设置，所述凸起朝向远离所述阵列基板的一侧。
可选的，在本申请的一些实施例中，所述阵列基板包括一衬底以及位于所述衬底一侧的源极、漏极，所述第一电极与所述源极、漏极同层设置。
可选的，在本申请的一些实施例中，所述显示面板还包括与所述源极连接的阳极，所述第二电极与所述阳极同层设置。
可选的，在本申请的一些实施例中，所述第二电极上表面未设置发光材料层，所述阴极覆盖所述第二电极设置。
可选的，在本申请的一些实施例中，所述第一电极包括第一部分、设置于所述第一部分远离所述阵列基板一侧的第二部分，所述第一部分在所述阵列基板上的正投影小于所述第二部分在所述阵列基板上的正投影。
可选的，在本申请的一些实施例中，所述第一电极的第一部分及第二部分一体化设置。
可选的，在本申请的一些实施例中，所述阴极与所述第二电极、所述第一电极的接触面积，大于所述第二电极的上表面面积。
可选的，在本申请的一些实施例中，所述凸起为独立构件，所述凸起结构的制备材料为导电材料，所述凸起结构的制备材料可以与所述第二电极不同。
可选的，在本申请的一些实施例中，所述凸起状为三角锥状，所述第二电极的下表面与所述第一电极的上表面平齐接触。
可选的，在本申请的一些实施例中，所述凸起远离所述阵列基板一侧的顶角角度范围大于或等于60度，所述凸起的厚度范围大于或等于110纳米。
可选的，在本申请的一些实施例中，所述阵列基板上方还设置有像素定义层、平坦层，所述像素定义层和所述平坦层在所述衬底上的正投影，与所述底切凹槽在所述衬底上的正投影错位设置。
可选的，在本申请的一些实施例中，所述像素定义层、所述平坦层的制备材料为正性光阻材料。
可选的，在本申请的一些实施例中，所述阴极覆盖所述第二电极设置。
可选的，在本申请的一些实施例中，所述阴极还部分设置于所述底切凹槽 内，所述阴极位于所述底切凹槽的部分可以与所述第一部分的侧面接触。
可选的，在本申请的一些实施例中，所述底切凹槽的横向深度大于2微米。
可选的，在本申请的一些实施例中，所述第二电极、所述阴极的制备材料为氧化铟锡、氧化铟锌、钼钛、钛中的任一。
本申请实施例提供一种显示面板制备方法，包括：
提供一阵列基板；
在所述阵列基板上方制备得到辅助电极，所述辅助电极与所述阵列基板之间形成底切凹槽；
在所述阵列基板上方依次制备得到钝化层、平坦层、像素定义层；
形成一贯穿所述钝化层、所述平坦层、所述像素定义层的过孔，使所述辅助电极位于所述过孔内；
在所述像素定义层远离所述阵列基板一侧制备得到发光材料层，在面阴极搭接区，所述发光材料层填充于所述底切凹槽内。
可选的，在本申请的一些实施例中，制备得到第一部分、设置于所述第一部分上的第二部分的步骤还包括：通过光刻工艺，刻蚀第一电极层制备得到底切凹槽，所述第二部分覆盖所述第一部分设置，且所述底切凹槽的深度大于2微米。
有益效果
在辅助电极与阵列基板之间形成底切凹槽，同时辅助电极上表面呈凸起状设置，使发光材料层填充于所述底切凹槽内，露出部分所述辅助电极，阴极与所述辅助电极面接触，通过增大所述阴极与所述辅助电极的接触面积，降低所述阴极的接触阻抗，缓解了现有显示面板存在阴极电压降较大的技术问题。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的显示面板的截面示意图；
图2A是本申请提供的显示面板制备方法的第一种截面示意图；
图2B是本申请提供的显示面板制备方法的第二种截面示意图；
图2C是本申请提供的显示面板制备方法的第三种截面示意图；
图2D是本申请提供的显示面板制备方法的第四种截面示意图；
图2E是本申请提供的显示面板制备方法的第五种截面示意图；
图2F是本申请提供的显示面板制备方法的第六种截面示意图；
图2G是本申请提供的显示面板制备方法的第七种截面示意图；
图3是本申请提供的显示面板制备方法的流程示意图。
附图标记说明：
Figure PCTCN2022093480-appb-000001
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而 “内”和“外”则是针对装置的轮廓而言的。
在现有显示面板中，阴极的制备材料通常电阻率大、且厚度薄，导致显示面板的电压降较大，使得显示面板呈现大面积的亮度不均匀，从而影响显示效果；为了减小阴极压降，在面阴极搭接区1，通常使所述阴极通过一至少贯穿发光材料层的过孔与辅助电极接触设置，从而降低所述阴极的电阻，然而，阴极仅与辅助电极的上表面部分接触，由于接触面积较小，导致接触阻抗较大，降低所述阴极电阻的效果不明显，导致阴极仍然存在电压降较大的技术问题。
因此，现有技术亟需提供一种能降低面阴极搭接区1阴极接触阻抗的显示面板。
请参阅图1，本申请提供一种显示面板，在面阴极搭接区1，所述显示面板包括阵列基板10、辅助电极、发光材料层60、阴极70，所述辅助电极设置于所述阵列基板10上方，所述发光材料层60设置于所述阵列基板70上方，所述阴极70设置于所述发光材料层60、所述辅助电极上方，所述阴极70与所述辅助电极搭接，其中，所述阵列基板10上方还依次设置有钝化层102、平坦层40、像素定义层50，在所述面阴极搭接区1设置有一贯穿所述钝化层102、所述平坦层40、所述像素定义层50的过孔，所述辅助电极设置于所述过孔内，所述辅助电极与所述阵列基板10之间形成有底切凹槽2，所述底切凹槽2内填充有所述发光材料层60。
在本实施例中，通过使发光材料层填充于底切凹槽内，露出的部分辅助电极与阴极接触，增大阴极与辅助电极的接触面积，降低了阴极的接触阻抗，缓解了现有显示面板存在阴极电压降较大的技术问题。
其中，所述辅助电极包括第一电极20、设置于所述第一电极20远离阵列基板10一侧的第二电极30。
其中，所述发光材料层60与所述发光层同层，且通过一步工序制备得到，所述显示面板包括发光区、面阴极搭接区1，所述发光层设置于所述发光区。
其中，所述阵列基板10还包括钝化层102，所述钝化层102设置于所述衬底101上方，所述钝化层102内设置有过孔，所述第一电极20位于所述过孔内。
可以理解的是，所述发光材料层60填充于所述底切凹槽2内，露出的所 述第一电极20可以与所述阴极70面接触，从而增大所述阴极70与所述第二电极30、所述第一电极20的接触面积，进而降低阴极70的接触阻抗，从而进一步降低了所述阴极70的电阻。
现结合具体实施例对本申请的技术方案进行描述。
在一种实施例中，所述辅助电极远离所述阵列基板10的表面呈凸起状设置，所述凸起朝向远离所述阵列基板10的一侧。
在一种实施例中，所述第一电极20与所述阵列基板10形成所述底切凹槽2，所述第二电极30远离所述阵列基板10的表面呈凸起状设置，所述凸起朝向远离所述阵列基板10的一侧。
在一种实施例中，所述阵列基板10包括一衬底101以及位于所述衬底一侧的源极、漏极，所述显示面板还包括与所述源极连接的阳极，所述第一电极20与所述源极、漏极同层设置，所述第二电极30与所述阳极同层设置。
在一种实施例中，所述第二电极30上表面未设置发光材料层60，所述阴极70覆盖所述第二电极30设置。
可以理解的是，所述发光材料层填充在底切凹槽内，可以使部分或全部第二电极30上表面暴露出，用于与阴极接触，以增大阴极与辅助电极之间的接触面积，从而降低接触阻抗，进而降低阴极压降。
在本实施例中，所述第二电极30上表面未设置发光材料层，即上表面完全露出用于增大与阴极70的接触面积，使第二电极30上表面完全露出的设计，对于降低阴极70接触阻抗的效果更好。
在一种实施例中，所述第一电极20的第一部分201及第二部分202一体化设置。
其中，所述阵列基板10还包括源漏极层，所述源漏极层包括源极、漏极，所述第一电极20与所述源极/漏极同层。
可以理解的是，无需额外的工艺制备得到第一电极20，再制备所述源极/漏极时，同时形成所述第一电极20。
在本实施例中，通过将第一电极20与现有膜层同层设置，简化制备工艺，降低成本。
在一种实施例中，所述第二电极30的上表面呈凸起状设置，所述凸起朝向远离所述衬底101的一侧。
其中，所述凸起状可以为梯形状、锥形状、三角状中的任一种。
可以理解的是，通过凸起引导有机材料进入到底切凹槽2内，所述凸起状的上表面有利于使发光材料层60填充于所述底切凹槽2内，避免所述发光材料设置于所述第一电极20、所述第二电极30表面，增大阴极70与第二电极30、第一电极20之间的接触面积，从而降低阴极70与第二电极30、第一电极20的接触阻抗。
可以理解的是，所述第二电极30的上表面至少需要一斜面，所述斜面用于引导所述有机材料进入底切凹槽2内。
需要注意的是，所述第二电极30上表面呈凸起，也能增大所述第二电极30上表面与所述阴极70之间的接触面积。
在本实施例中，通过将第二电极30的上表面设置为凸起状，有利于发光材料层60的发光材料进入底切凹槽2内，使第一电极20部分露出以降低所述阴极70的接触阻抗。
在一种实施例中，所述阴极70与所述第二电极30、所述第一电极20的接触面积，大于所述第二电极30的上表面面积。
其中，所述阴极70远离所述阵列基板10的一侧表面可以未设置发光材料层，即阴极远离阵列基板一侧完全暴露，同时，阴极还与辅助电极的侧面部分接触。
在本实施例中，进一步限定阴极70与辅助电极的接触面积，降低阴极阻抗，减小阴极70压降。
在一种实施例中，所述阴极70仅与所述第二电极30接触，所述第二电极30的上表面设置有凸起结构，所述凸起结构为独立构件。
其中，所述阴极70与所述第二电极30的侧面接触。
其中，所述凸起结构的制备材料为导电材料，所述凸起结构的制备材料可以与所述第二电极30不同。
其中，所述凸起结构可以与所述第二电极30相同。
在本实施例中，通过在第二电极30表面进一步设置独立构件，所述独立 构件为凸起，进而降低所述阴极70的接触阻抗。
在一种实施例中，所述凸起状为三角锥状，所述第二电极30的下表面与所述第二部分202的上表面平齐。
在一种实施例中，所述凸起的顶角角度范围大于或等于60度，所述凸起的厚度范围大于或等于110纳米。
其中，所述顶角角度为凸起远离所述阵列基板一侧的角度。
在一种实施例中，所述阵列基板10上方还设置有像素定义层50、平坦层40，所述像素定义层50和所述平坦层40在所述衬底101上的正投影，与所述底切凹槽2在所述衬底101上的正投影错位设置。
其中，所述像素定义层50的厚度可以为2000埃。
可以理解的是，将所述底切凹槽2内的平坦层40、像素定义层50去除，使底切凹槽2内仅用于容纳发光材料层60。
在一种实施例中，所述像素定义层50、所述平坦层40的制备材料为正性光阻材料。
在一种实施例中，所述像素定义层50、所述平坦层40的制备材料相同。
其中，所述平坦层40为流平性较强的制备材料。
在本实施例中，所述平坦层40的流平性较强，有利于所述平坦层40填充所述底切凹槽2。
在一种实施例中，所述阴极70还部分设置于所述底切凹槽2内，所述阴极70位于所述底切凹槽2的部分可以与所述第一部分201的侧面接触。
在本实施例中，位于底切凹槽内的所述阴极还与第一电极的侧面接触，进一步增大了接触面积，降低了接触阻抗。
在一种实施例中，所述第二电极30、所述阴极70的制备材料为氧化铟锡、氧化铟锌、钼钛、钛中的任一种。
其中，所述第二电极30与所述阴极70的制备材料可以相同。
在一种实施例中，所述底切凹槽2的横向深度大于2微米。
其中，所述第二部分202与所述第一部分201的宽度大至少4微米。
可以理解的是，现有显示面板在制备发光层时，容易在面阴极搭接区1同步制备得到发光材料层60，所述发光材料层60会覆盖所述第一电极20及第 二电极30的侧面，导致所述阴极70与所述第二电极30的接触面积较小，接触阻抗较大。
在本实施例中，通过限定所述底切凹槽2的横向深度，确保所述底切凹槽2存在足够的容纳空间以填充发光材料层60。
请参阅图2A至图2G、图3，本申请实施例提供一种显示面板制备方法，包括：
S1：提供一阵列基板10；
S2：在所述阵列基板10上方制备得到辅助电极，所述辅助电极与所述阵列基板10之间形成底切凹槽2；
S3：在所述阵列基板10上方依次制备得到钝化层102、平坦层40、像素定义层50；
S4：形成一贯穿所述钝化层102、所述平坦层40、所述像素定义层50的过孔，使所述辅助电极位于所述过孔内；
S5：在所述像素定义层50远离所述阵列基板10一侧制备得到发光材料层60，在面阴极搭接区1，所述发光材料层60填充于所述底切凹槽2内。
其中，所述阴极70与所述辅助电极的接触面积，大于所述辅助电极的上表面面积。
进一步的，所述阴极70与所述第二电极30、所述第一电极20的接触面积，大于所述第二电极30的上表面面积。
其中，请参阅图2A，提供一阵列基板10，所述阵列基板10包括第一电极20；
其中，请参阅图2B，制备得到第一电极20的第一部分201、第二部分202、底切凹槽2；
其中，请参阅图2C，涂布一层流动性较强的第一有机材料，填充所述底切凹槽2；
其中，请参阅图2D，制备得到所述第二电极30，所述第二电极30的上表面可以为锥形状；
其中，请参阅图2E，涂布一层第二有机材料，曝光去除所述底切凹槽2上方的所述第一有机材料、所述第二有机材料，制备得到平坦层40、像素定 义层50；
其中，请参阅图2F，制备所述发光材料层60，所述底切凹槽2内填充有所述发光材料层60；
其中，请参阅图2G，制备得到所述阴极70，所述阴极70与所述第二电极30、所述第一电极20均面接触。
在一种实施例中，像素定义层50可采用半透掩膜板曝光制作完成。
在一种实施例中，制备得到第一部分201、设置于所述第一部分201上的第二部分202的步骤还包括：通过光刻工艺，刻蚀第一电极20层制备得到底切凹槽2，所述第二部分202覆盖所述第一部分201设置，且所述底切凹槽2的深度大于2微米。
在一种实施例中，制备得到所述平坦层40、所述像素定义层50的步骤还包括：所述第一有机材料与所述第二有机材料相同，在一步工艺中通过对第一有机材料和第二有机材料曝光制备得到所述平坦层40和所述像素定义层50。
在本实施例中，通过将平坦层40和像素定义层50在一步工艺中制备得到，简化了工艺，降低了成本。
在一种实施例中，制备得到第二电极30的步骤还包括：蒸镀一层导电材料，图案化所述导电材料形成第二电极30呈三角锥状的上表面，且第二电极30的下表面与所述第二部分202的上表面平齐设置。
本申请还提出了一种显示模组、一种显示装置，其中，所述显示模组和所述显示装置均包括上述显示面板，此处不再赘述。
本实施例提供的显示面板包括面阴极搭接区，所述面阴极搭接区包括阵列基板、辅助电极、发光材料层、阴极，所述辅助电极与所述阵列基板之间形成底切凹槽，所述底切凹槽内填充有所述发光材料层；通过在辅助电极与阵列基板之间形成底切凹槽，使发光材料层填充于所述底切凹槽内，露出的辅助电极与阴极接触，增大了阴极与辅助电极之间的接触面积，降低了阴极的接触阻抗，从而减少了阴极压降。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板、一种显示面板制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，包括面阴极搭接区，所述面阴极搭接区包括：
    阵列基板；
    辅助电极，所述辅助电极设置于所述阵列基板上方；
    发光材料层，所述发光材料层设置于所述阵列基板上方；
    阴极，所述阴极设置于所述发光材料层、所述辅助电极上方，所述阴极与所述辅助电极搭接；
    其中，所述阵列基板上方还依次设置有钝化层、平坦层、像素定义层，在所述面阴极搭接区设置有一贯穿所述钝化层、所述平坦层、所述像素定义层的过孔，所述辅助电极设置于所述过孔内，所述辅助电极与所述阵列基板之间形成有底切凹槽，所述底切凹槽内填充有所述发光材料层。
  2. 如权利要求1所述的显示面板，其中，所述辅助电极远离所述阵列基板的表面呈凸起状设置，所述凸起朝向远离所述阵列基板的一侧。
  3. 如权利要求2所述的显示面板，其中，所述辅助电极包括第一电极以及设置于所述第一电极远离所述阵列基板一侧的第二电极，所述第一电极与所述阵列基板形成所述底切凹槽，所述第二电极远离所述阵列基板的表面呈凸起状设置，所述凸起朝向远离所述阵列基板的一侧。
  4. 如权利要求3所述的显示面板，其中，所述阵列基板包括一衬底以及位于所述衬底一侧的源极、漏极，所述第一电极与所述源极、漏极同层设置。
  5. 如权利要求4所述的显示面板，其中，所述显示面板还包括与所述源极连接的阳极，所述第二电极与所述阳极同层设置。
  6. 如权利要求3所述的显示面板，其中，所述第二电极上表面未设置发光材料层，所述阴极覆盖所述第二电极设置。
  7. 如权利要求3所述的显示面板，其中，所述第一电极包括第一部分、设置于所述第一部分远离所述阵列基板一侧的第二部分，所述第一部分在所述阵列基板上的正投影小于所述第二部分在所述阵列基板上的正投影。
  8. 如权利要求7所述的显示面板，其中，所述第一电极的第一部分及第二部分一体化设置。
  9. 如权利要求3所述的显示面板，其中，所述阴极与所述第二电极、所 述第一电极的接触面积，大于所述第二电极的上表面面积。
  10. 如权利要求3所述的显示面板，其中，所述凸起为独立构件，所述凸起结构的制备材料为导电材料，所述凸起结构的制备材料可以与所述第二电极不同。
  11. 如权利要求3所述的显示面板，其中，所述凸起状为三角锥状，所述第二电极的下表面与所述第一电极的上表面平齐接触。
  12. 如权利要求11所述的显示面板，其中，所述凸起远离所述阵列基板一侧的顶角角度范围大于或等于60度，所述凸起的厚度范围大于或等于110纳米。
  13. 如权利要求2所述的显示面板，其中，所述阵列基板上方还设置有像素定义层、平坦层，所述像素定义层和所述平坦层在所述衬底上的正投影，与所述底切凹槽在所述衬底上的正投影错位设置。
  14. 如权利要求13所述的显示面板，其中，所述像素定义层、所述平坦层的制备材料为正性光阻材料。
  15. 如权利要求3所述的显示面板，其中，所述阴极覆盖所述第二电极设置。
  16. 如权利要求15所述的显示面板，其中，所述阴极还部分设置于所述底切凹槽内，所述阴极位于所述底切凹槽的部分可以与所述第一部分的侧面接触。
  17. 如权利要求1所述的显示面板，其中，所述底切凹槽的横向深度大于2微米。
  18. 如权利要求3所述的显示面板，其中，所述第二电极、所述阴极的制备材料为氧化铟锡、氧化铟锌、钼钛、钛中的任一。
  19. 一种显示面板制备方法，其包括：
    提供一阵列基板；
    在所述阵列基板上方制备得到辅助电极，所述辅助电极与所述阵列基板之间形成底切凹槽；
    在所述阵列基板上方依次制备得到钝化层、平坦层、像素定义层；
    形成一贯穿所述钝化层、所述平坦层、所述像素定义层的过孔，使所述辅 助电极位于所述过孔内；
    在所述像素定义层远离所述阵列基板一侧制备得到发光材料层，在面阴极搭接区，所述发光材料层填充于所述底切凹槽内。
  20. 如权利要求19所述的显示面板制备方法，其中，制备得到第一部分、设置于所述第一部分上的第二部分的步骤还包括：通过光刻工艺，刻蚀第一电极层制备得到底切凹槽，所述第二部分覆盖所述第一部分设置，且所述底切凹槽的深度大于2微米。
PCT/CN2022/093480 2022-04-20 2022-05-18 显示面板及其制备方法 Ceased WO2023201813A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282723A (zh) * 2013-07-04 2015-01-14 三星显示有限公司 有机发光显示装置及制造该有机发光显示装置的方法
CN106057844A (zh) * 2015-04-02 2016-10-26 乐金显示有限公司 降低有机发光显示装置的阴极中的电阻的辅助线
CN106206645A (zh) * 2014-11-25 2016-12-07 乐金显示有限公司 有机发光显示设备和制造该有机发光显示设备的方法
US20180261783A1 (en) * 2017-03-09 2018-09-13 Samsung Display Co., Ltd. Light emitting display device
CN109103215A (zh) * 2017-06-21 2018-12-28 京东方科技集团股份有限公司 一种有机发光二极管显示面板及其制作方法、显示装置
CN114284331A (zh) * 2021-12-24 2022-04-05 深圳市华星光电半导体显示技术有限公司 一种有机发光显示面板及其制作方法
CN114335116A (zh) * 2021-12-30 2022-04-12 深圳市华星光电半导体显示技术有限公司 一种有机发光显示面板及其制作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9478591B2 (en) * 2013-12-23 2016-10-25 Lg Display Co., Ltd. Organic light emitting display device and repair method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282723A (zh) * 2013-07-04 2015-01-14 三星显示有限公司 有机发光显示装置及制造该有机发光显示装置的方法
CN106206645A (zh) * 2014-11-25 2016-12-07 乐金显示有限公司 有机发光显示设备和制造该有机发光显示设备的方法
CN106057844A (zh) * 2015-04-02 2016-10-26 乐金显示有限公司 降低有机发光显示装置的阴极中的电阻的辅助线
US20180261783A1 (en) * 2017-03-09 2018-09-13 Samsung Display Co., Ltd. Light emitting display device
CN109103215A (zh) * 2017-06-21 2018-12-28 京东方科技集团股份有限公司 一种有机发光二极管显示面板及其制作方法、显示装置
CN114284331A (zh) * 2021-12-24 2022-04-05 深圳市华星光电半导体显示技术有限公司 一种有机发光显示面板及其制作方法
CN114335116A (zh) * 2021-12-30 2022-04-12 深圳市华星光电半导体显示技术有限公司 一种有机发光显示面板及其制作方法

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