WO2023201804A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023201804A1
WO2023201804A1 PCT/CN2022/093080 CN2022093080W WO2023201804A1 WO 2023201804 A1 WO2023201804 A1 WO 2023201804A1 CN 2022093080 W CN2022093080 W CN 2022093080W WO 2023201804 A1 WO2023201804 A1 WO 2023201804A1
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Prior art keywords
binding
binding detection
state
detection signal
pin
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PCT/CN2022/093080
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English (en)
French (fr)
Inventor
李纪辉
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/780,993 priority Critical patent/US12033561B2/en
Publication of WO2023201804A1 publication Critical patent/WO2023201804A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
    • G01M11/00—Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
    • G01M11/02—Testing optical properties
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel and a display device.
  • This application provides a display panel and a display device to alleviate the technical problems of poor accuracy and low efficiency in detecting the binding status of each pin.
  • this application provides a display panel.
  • the display panel includes a driving chipset, a pad group and a false voltage test circuit.
  • the driving chipset includes N pins for transmitting corresponding driving signals, where N is a positive integer;
  • the pad group includes N pads, one pad is bound to one pin correspondingly; each input end of the false voltage test circuit is connected to one pad respectively, and the first control end of the false voltage test circuit is connected to the first control line connection, the second control end of the false voltage test circuit is connected to the second control line, the first output end of the false voltage test circuit is connected to the first binding detection line, and the second output end of the false voltage test circuit is connected to the second binding
  • the detection line connection is used to determine the binding status of each pin and the corresponding pad according to the timing and status of the binding detection signal output by the first binding detection line and the second binding detection line.
  • N pins are arranged sequentially along the first direction and transmit corresponding driving signals sequentially and time-sharing along the first direction;
  • N pads are arranged sequentially along the first direction, wherein the first The pads to the Nth pad and the 1st pin to the Nth pin are bound in sequence;
  • the false voltage test circuit includes N switching devices arranged sequentially along the first direction, and the N switching devices are divided into odd numbers A group of switching devices and an even-numbered group of switching devices, in which the input terminal of the first switching device to the input terminal of the N-th switching device are connected correspondingly to the first to N-th pads in sequence, and the odd-numbered group of switching devices
  • Each control terminal is connected to one of the first control line or the second control line, each control terminal of the even-numbered group of switching devices is connected to the other of the first control line or the second control line, and each output terminal of the odd-numbered group of switching devices is is connected to one of the first binding detection line or the second binding detection line, each output terminal of the even-numbered group of switching devices is connected
  • the location of the corresponding pin is determined based on the timing comparison results of each driving signal and each binding detection signal; based on the status comparison results and/or timing comparison results of each driving signal and each binding detection signal , determine the binding status of the corresponding pin and the corresponding pad.
  • the pin corresponding to the Nth binding detection signal is determined to be the Nth pin.
  • the binding state includes a normal binding state.
  • the corresponding pin is the same as the corresponding welding pin.
  • the binding status between disks is the normal binding status.
  • the binding state further includes a poor binding state.
  • the pulse amplitude of the binding detection signal being less than the pulse amplitude of the corresponding driving signal, it is determined that the pin corresponding to the binding detection signal is in a binding state. Determine bad status.
  • the binding state further includes a binding short circuit state
  • the binding detection signal includes a first binding detection signal transmitted by the first binding detection line and a second binding signal transmitted by the second binding detection line. detection signal, in response to the pulse duration of the first binding detection signal and the pulse duration of the second binding detection signal overlapping in timing, it is determined that at least two adjacent corresponding pins are in a binding short-circuit state.
  • the bonded state also includes an unbound state. In response to the number of pulses of the bonding detection signal being less than the number of pulses of each driving signal, it is determined that the corresponding pin is in the unbound state.
  • the switching device in the false voltage test circuit in response to the display panel being in the display state, the switching device in the false voltage test circuit is in the off state.
  • the present application provides a display device, which includes the display panel in at least one of the above embodiments, wherein the driving chipset, the pad set, and the false voltage test circuit are sequentially arranged along the second direction.
  • the display panel and display device provided by this application are bound to a pin through a bonding pad.
  • Each input end of the false voltage test circuit is connected to a bonding pad.
  • the first control end of the false voltage test circuit is connected to the first pin.
  • the control line is connected, the second control end of the false voltage test circuit is connected to the second control line, the first output end of the false voltage test circuit is connected to the first binding detection line, and the second output end of the false voltage test circuit is connected to the second
  • the binding detection line connection can determine the binding status of each pin and the corresponding pad according to the timing and status of the binding detection signal output by the first binding detection line and the second binding detection line.
  • the binding status of each pin improves the accuracy of binding status detection; and the binding status of each pin and the corresponding pad can be judged through the timing and status of the binding detection signal, which is different from relying on a microscope to detect each pin. Compared with viewing the binding status of pins one by one, the efficiency of binding status detection is improved.
  • display panels in the related art usually use a false voltage test circuit for lighting tests.
  • This application can give the false voltage test circuit a new purpose or function, which not only saves the number of circuits used in the display panel, but also achieves more advanced Binding status detection.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of different binding states provided by an embodiment of the present application.
  • Figure 3 is a timing diagram of an enable signal provided by an embodiment of the present application.
  • Figure 4 is a timing diagram of signals to be tested in a normal binding state provided by an embodiment of the present application.
  • Figure 5 is a timing diagram of signals to be tested in a poor binding state provided by an embodiment of the present application.
  • FIG. 6 is a timing diagram of signals to be tested in a bonded short-circuit state provided by an embodiment of the present application.
  • FIG. 7 is a timing diagram of signals to be tested in the unbound state provided by an embodiment of the present application.
  • the display panel includes a driving chipset 300, a pad group 200 and a false voltage test circuit 100.
  • the driving chipset 300 includes N pins for transmitting corresponding driving signals, N is a positive integer;
  • the pad group 200 includes N pad, a pad is bound to a pin correspondingly;
  • each input terminal of the false voltage test circuit 100 is connected to a pad respectively, and the first control terminal of the false voltage test circuit 100 is connected to the first control line 10.
  • the second control terminal of the voltage test circuit 100 is connected to the second control line 20
  • the first output terminal of the false voltage test circuit 100 is connected to the first binding detection line 30
  • the second output terminal of the false voltage test circuit 100 is connected to the second
  • the binding detection line 40 is connected and used to determine the binding status of each pin and the corresponding pad according to the timing and status of the binding detection signal correspondingly output by the first binding detection line 30 and the second binding detection line 40 .
  • the display panel provided in this embodiment is bound to a pin through a bonding pad, and each input terminal of the false voltage test circuit 100 is connected to a bonding pad.
  • the first terminal of the false voltage test circuit 100 The control end is connected to the first control line 10, the second control end of the false voltage test circuit 100 is connected to the second control line 20, the first output end of the false voltage test circuit 100 is connected to the first binding detection line 30, and the false pressure
  • the second output end of the test circuit 100 is connected to the second binding detection line 40, and can determine each pin according to the timing and status of the binding detection signals correspondingly output by the first binding detection line 30 and the second binding detection line 40.
  • the binding status of the pin and the corresponding pad not only can detect the binding status of each pin, but also improves the accuracy of binding status detection; each pin can also be judged through the timing and status of the binding detection signal. Compared with relying on a microscope to check the binding status of each pin one by one, the efficiency of binding status detection is improved.
  • display devices in the related art usually use a false voltage test circuit 100 to perform a lighting test.
  • This embodiment can give the false voltage test circuit 100 a new purpose or function, which not only saves the number of circuits used in the display panel, but also realizes More advanced binding status detection.
  • the driver chipset 300 may include at least one driver chip, and the N pins of the driver chipset 300 may be all output pins of the at least one driver chip, and each output pin is used to output a corresponding drive signal.
  • N pins are arranged in sequence along the first direction DR1 and the corresponding driving signals are sequentially time-divided along the first direction DR1; N pads are arranged in sequence along the first direction DR1, where, The first pads PAD1 to the Nth pads are bound to the first pins S1 to the Nth pins in sequence; the false voltage test circuit 100 includes N switching devices arranged in sequence along the first direction DR1, The N switching devices are divided into an odd number group of switching devices 110 and an even number group of switching devices 120. Among them, the input terminal of the first switching device to the input terminal of the Nth switching device and the first pad to the Nth pad are in sequence.
  • each control end of the odd-numbered group of switching devices 110 is connected to one of the first control line 10 or the second control line 20
  • each control end of the even-numbered group of switching devices 120 is connected to the first control line 10 or the second control line.
  • each output terminal of the odd-numbered group switching device 110 is connected to one of the first binding detection line 30 or the second binding detection line 40
  • each output terminal of the even-numbered group switching device 120 is connected to the first binding detection line 30 or the second binding detection line 40.
  • the other one of the fixed detection line 30 or the second binding detection line 40 is connected, and the odd number group of switching devices 110 and the even number group of switching devices 120 are alternately turned on in a time-sharing manner.
  • the corresponding driving signals are sequentially time-divided along the first direction DR1.
  • the 1st output pin to the Nth output pin from left to right along the first direction DR1 sequentially output the 1 drive signal to Nth drive signal.
  • the 1st drive signal to the Nth drive signal have the same frequency, but the phase of the 1st drive signal to the Nth drive signal changes sequentially.
  • the pulse duration of the 1st drive signal ends.
  • the pulse duration of the second drive signal will not start until or after the end, and the phases of other drive signals can be deduced by analogy. It can be understood that this helps to determine the binding state of the corresponding output pin based on the binding detection signal output by the false voltage test circuit 100 at the corresponding time.
  • N pins are arranged sequentially along the first direction DR1, such as the first output pin S1, the second output pin S2, the third output pin S3, and the fourth output pin.
  • S4 the fifth output pin S5, the sixth output pin S6, the seventh output pin S7, the eighth output pin S8..., the 2N-3 output pin S2N-3, the 2N-2 output pins S2N-2, 2N-1 output pin S2N-1, 2N output pin S2N...etc.
  • N pads are arranged in sequence along the first direction DR1, for example 1 pad PAD1, 2nd pad PAD2, 3rd pad PAD3, 4th pad PAD4...
  • N pins and N pads are calibrated accordingly, which helps to update the timing through timing. To accurately identify the corresponding output pin.
  • the odd-numbered group of switching devices 110 may be the first switching device T1, the third switching device T1 from left to right along the first direction DR1.
  • a collection of switching devices T3...the 2N-3rd switching device T2N-3, the 2N-1st switching device T2N-1, etc.; the even-numbered group of switching devices 120 may be the 2N-th switching device T2N-3 from left to right along the first direction DR1.
  • the above-mentioned binding state includes a normal binding state, a poor binding state, a binding short-circuit state, and an unbound state.
  • the normal binding state is QK1 as shown in Figure 2
  • the pins shown in the white pattern and the pads shown in the black pattern completely overlap in the thickness direction of the display panel.
  • the poor binding state of QK2 as shown in Figure 2 the pins shown in the white pattern and the pads shown in the black pattern partially overlap in the thickness direction of the display panel.
  • the QK3 in the short-circuit state shown in Figure 2 is bound.
  • the pins shown in the white pattern and the corresponding pads shown in the black pattern completely overlap in the thickness direction of the display panel, due to the two adjacent The pins shown in the white pattern are electrically connected, causing two adjacent pins to be short-circuited.
  • the pins shown in the white pattern and the pads shown in the black pattern do not overlap at all in the thickness direction of the display panel.
  • the first control line 10 is used to transmit the first enable signal EN1
  • the second control line 20 is used to transmit the second enable signal EN2.
  • the first enable signal EN1 and the second enable signal EN2 are both at high potential.
  • each switching device in the false voltage test circuit 100 is in an off state. It can be understood that in this display stage P11, the display panel is in the display state.
  • the first enable signal EN1 is at a low level and the second enable signal EN2 is at a high level.
  • each of the odd-numbered group switching devices 110 The switching devices are all in the on state, and each switching device in the even number group of switching devices 120 is in the off state; in the second binding state detection sub-phase P122 in the binding state detection phase P12, the first enable signal EN1 is in The high potential and the second enable signal EN2 are at low potential.
  • each switching device in the odd-numbered group of switching devices 110 is in the off state, and each of the switching devices in the even-numbered group of switching devices 120 is in the on state.
  • each switching device in the false voltage test circuit 100 is a P-channel thin film transistor. It can be understood that other embodiments are not limited to this. , N-channel thin film transistors can also be used, P-channel thin film transistors and/or N-channel thin film transistors can also be used.
  • the required timing of the first enable signal EN1 and the second enable signal EN2 is based on It can be adjusted according to the inventive concept of the embodiment, and will not be described again here.
  • the binding detection signal includes a first binding detection signal DETECT1 transmitted by the first binding detection line 30 and a second binding detection signal transmitted by the second binding detection line 40 .
  • the position of the corresponding pin is determined based on the timing comparison results of each driving signal and each binding detection signal. For example, as shown in Figure 4, the first output pin S1 to the eighth output pin S8 sequentially output a driving signal including a pulse in a time-sharing manner. Correspondingly, the first binding detection signal DETECT1 and the second binding detection signal DETECT1 can be simultaneously monitored. The corresponding waveforms of the two detection signals DETECT2 are obtained as shown in Figure 4, and then it can be determined according to the above corresponding hardware connection relationships: the first pulse in the first binding detection signal DETECT1 originates from the first output pin S1. The first pulse in the second binding detection signal DETECT2 is derived from the second output pin S2.
  • the second pulse in the first binding detection signal DETECT1 is derived from the third output pin S3.
  • the second pulse in the second binding detection signal DETECT2 is derived from the fourth output pin S4, and the third pulse in the first binding detection signal DETECT1 is derived from the fifth output pin S5.
  • the third pulse in the binding detection signal DETECT2 is derived from the sixth output pin S6, and the fourth pulse in the first binding detection signal DETECT1 is derived from the seventh output pin S7.
  • the fourth pulse in the detection signal DETECT2 is derived from the 8th output pin S8...and so on.
  • the pulse of the Nth driving signal and the pulse of the Nth binding detection signal are in the same period, then it is determined that the pin corresponding to the Nth binding detection signal is the N pins.
  • the pulse of the first driving signal output by the first output pin S1 and the pulse of the first binding detection signal, that is, the first pulse of the first binding detection signal DETECT1 are located in the same time period, then it is determined that the pulse of the first driving signal outputted by the first output pin S1 is in the same period.
  • the pin corresponding to the first pulse in the binding detection signal DETECT1 is the first pin or the first output pin S1.
  • the binding status of the corresponding pin and the corresponding pad is determined based on the status comparison result and/or the timing comparison result of each driving signal and each binding detection signal.
  • the pulse of the first driving signal output by the first output pin S1 and the pulse of the first binding detection signal are located in the same period, that is, the timing of the two. are consistent, and at the same time, the amplitude of the first pulse in the first binding detection signal DETECT1 and the amplitude of the pulse of the first driving signal output by the first output pin S1 are also approximately equal or equal, then it is determined that the first The binding state of the output pin S1 and the first pad PAD1 is the normal binding state, and the others can be deduced by analogy.
  • the amplitude of the second pulse in the second binding detection signal DETECT2 is significantly smaller than the amplitude of the pulse of the fourth driving signal output by the fourth output pin S4. Based on this, it can be determined that the amplitude of the second binding detection signal is the same as that of the second binding detection signal DETECT2.
  • the fourth output pin S4 corresponding to the second pulse in the signal DETECT2 is in a bad binding state.
  • the fifth output pin S5 outputs the fifth driving signal
  • the first binding detection signal DETECT1 should receive the third pulse
  • the second binding detection signal DETECT2 should not receive to the third pulse
  • the sixth output pin S6 outputs the sixth driving signal
  • the second binding detection signal DETECT2 should receive the third pulse
  • the first binding detection signal DETECT2 should receive the third pulse.
  • the detection signal DETECT1 should not receive the fourth pulse.
  • both the first binding detection signal DETECT1 and the second binding detection signal DETECT2 receive pulses at the same time, it can be concluded that the fifth output pin S5 and the sixth output pin S6 have a binding short circuit. connection status.
  • the third output pin S3 when the third output pin S3 outputs the third driving signal, the first binding detection signal DETECT1 should receive the second pulse, but because the third output pin S3 is connected to The third pad PAD3 is not bound, resulting in the first binding detection signal DETECT1 not receiving the second pulse. From this, it can be determined that the third output pin S3 is in an unbound state.
  • this embodiment provides a display device, which includes the display panel in at least one of the above embodiments, wherein the driving chipset 300, the pad group 200 and the false voltage test circuit 100 are sequentially configured along the first Two-way DR2 arrangement.
  • the display device provided in this embodiment is bound to a pin through a bonding pad, and each input terminal of the false voltage test circuit 100 is connected to a bonding pad respectively.
  • the first terminal of the false voltage test circuit 100 The control end is connected to the first control line 10
  • the second control end of the false voltage test circuit 100 is connected to the second control line 20
  • the first output end of the false voltage test circuit 100 is connected to the first binding detection line 30, and the false pressure
  • the second output end of the test circuit 100 is connected to the second binding detection line 40, and can determine each pin according to the timing and status of the binding detection signals correspondingly output by the first binding detection line 30 and the second binding detection line 40.
  • the binding status of the pin and the corresponding pad not only can detect the binding status of each pin, but also improves the accuracy of binding status detection; each pin can also be judged through the timing and status of the binding detection signal. Compared with relying on a microscope to check the binding status of each pin one by one, the efficiency of binding status detection is improved.
  • display devices in the related art usually use a false voltage test circuit 100 to perform a lighting test.
  • This embodiment can give the false voltage test circuit 100 a new purpose or function, which not only saves the number of circuits used in the display panel, but also realizes More advanced binding status detection.
  • the above display panel may be, but is not limited to, an organic light emitting diode display panel, a liquid crystal display panel, a micro light emitting diode display panel, a mini light emitting diode display panel or a quantum dot light emitting diode display panel. Any kind.

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Abstract

一种显示面板及显示装置，显示面板包括驱动芯片组(300)、焊盘组(200)以及假压测试电路(100)，能够根据第一绑定检测线(30)、第二绑定检测线(40)对应输出的绑定检测信号的时序、状态判断每个引脚(S1, S2... S2N)与对应焊盘(PAD1, PAD2... PAD2N)的绑定状态，提高了绑定状态检测的准确性；且与依靠显微镜对各引脚(S1, S2... S2N)的绑定状态逐个查看相比，提高了绑定状态检测的效率。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
 背景技术
在显示面板的制作过程中，通常需要绑定驱动芯片的引脚至对应的焊盘上，但是，驱动芯片的引脚与对应焊盘的绑定结果容易存在瑕疵，这会影响显示面板的正常工作。
于是，检测绑定（Bonding）不良的方式应运而生，其中一种是仅在驱动芯片两侧的两个引脚上预留绑定测试点位，这种方式实际上并不能够检测或者识别其他引脚的绑定结果，绑定检测的准确性较差；其中另一种是依靠显微镜对这些引脚的绑定结果逐个查看，这种方式的检测效率非常低。
 技术问题
本申请提供一种显示面板及显示装置，以缓解各引脚的绑定状态检测存在准确性较差及效率较低的技术问题。
 技术解决方案
第一方面，本申请提供一种显示面板，该显示面板包括驱动芯片组、焊盘组以及假压测试电路，驱动芯片组包括用于传输对应驱动信号的N个引脚，N为正整数；焊盘组包括N个焊盘，一焊盘与一引脚对应绑定；假压测试电路的各输入端分别与一焊盘对应连接，假压测试电路的第一控制端与第一控制线连接，假压测试电路的第二控制端与第二控制线连接，假压测试电路的第一输出端与第一绑定检测线连接，假压测试电路的第二输出端与第二绑定检测线连接，用于根据第一绑定检测线、第二绑定检测线对应输出的绑定检测信号的时序、状态判断每个引脚与对应焊盘的绑定状态。
在其中一些实施方式中，N个引脚依次沿第一方向排布且沿第一方向依次分时传输对应的各驱动信号；N个焊盘依次沿第一方向排布，其中，第1个焊盘至第N个焊盘与第1个引脚至第N个引脚依次对应绑定；假压测试电路包括沿第一方向依次排布的N个开关器件，N个开关器件分为奇数组开关器件和偶数组开关器件，其中，第1个开关器件的输入端至第N个开关器件的输入端与第1个焊盘至第N个焊盘依次分别对应连接，奇数组开关器件的各控制端与第一控制线或者第二控制线中的一个连接，偶数组开关器件的各控制端与第一控制线或者第二控制线中的另一个连接，奇数组开关器件的各输出端与第一绑定检测线或者第二绑定检测线中的一个连接，偶数组开关器件的各输出端与第一绑定检测线或者第二绑定检测线中的另一个连接，且奇数组开关器件、偶数组开关器件分时交替导通。
在其中一些实施方式中，根据各驱动信号与各绑定检测信号的时序比较结果，确定对应引脚所在的位置；根据各驱动信号与各绑定检测信号的状态比较结果和/或时序比较结果，确定对应引脚与对应焊盘的绑定状态。
在其中一些实施方式中，第N个驱动信号的脉冲与第N个绑定检测信号的脉冲位于同一时段，则确定与第N个绑定检测信号对应的引脚为第N个引脚。
在其中一些实施方式中，绑定状态包括绑定正常状态，响应于各驱动信号的时序、脉冲幅值与各绑定检测信号的时序、脉冲幅值均一致，则确定对应引脚与对应焊盘之间的绑定状态为绑定正常状态。
在其中一些实施方式中，绑定状态还包括绑定不良状态，响应于绑定检测信号的脉冲幅值小于对应的驱动信号的脉冲幅值，则确定与绑定检测信号对应的引脚处于绑定不良状态。
在其中一些实施方式中，绑定状态还包括绑定短接状态，绑定检测信号包括第一绑定检测线传输的第一绑定检测信号和第二绑定检测线传输的第二绑定检测信号，响应于第一绑定检测信号的脉冲持续时间与第二绑定检测信号的脉冲持续时间在时序上重叠，则确定至少两个相邻的对应引脚处于绑定短接状态。
在其中一些实施方式中，绑定状态还包括未绑定上状态，响应于绑定检测信号的脉冲数量少于各驱动信号的脉冲数量，则确定对应引脚处于未绑定上状态。
在其中一些实施方式中，响应于显示面板处于显示状态，假压测试电路中的开关器件处于断开状态。
第二方面，本申请提供一种显示装置，该显示装置包括上述至少一实施方式中的显示面板，其中，驱动芯片组、焊盘组以及假压测试电路依次沿第二方向排布。
 有益效果
本申请提供的显示面板及显示装置，通过一焊盘与一引脚对应绑定，假压测试电路的各输入端分别与一焊盘对应连接，假压测试电路的第一控制端与第一控制线连接，假压测试电路的第二控制端与第二控制线连接，假压测试电路的第一输出端与第一绑定检测线连接，假压测试电路的第二输出端与第二绑定检测线连接，能够根据第一绑定检测线、第二绑定检测线对应输出的绑定检测信号的时序、状态判断每个引脚与对应焊盘的绑定状态，不仅能够检测到每个引脚的绑定状态，提高了绑定状态检测的准确性；且通过绑定检测信号的时序、状态即可判断每个引脚与对应焊盘的绑定状态，与依靠显微镜对各引脚的绑定状态逐个查看相比，提高了绑定状态检测的效率。
又，相关技术中的显示面板通常采用假压测试电路进行点灯测试，本申请可以赋予该假压测试电路以新的用途或者功能，不仅节省了显示面板的电路使用数量，还实现了更为先进的绑定状态检测。
 附图说明
图1为本申请实施例提供的显示面板的结构示意图。
图2为本申请实施例提供的不同绑定状态的示意图。
图3为本申请实施例提供的使能信号的时序示意图。
图4为本申请实施例提供的绑定正常状态下待测试信号的时序示意图。
图5为本申请实施例提供的绑定不良状态下待测试信号的时序示意图。
图6为本申请实施例提供的绑定短接状态下待测试信号的时序示意图。
图7为本申请实施例提供的未绑定上状态下待测试信号的时序示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
有鉴于上述提及的各引脚的绑定状态检测存在准确性较差及效率较低的技术问题，本实施例提供了一种显示面板，请参阅图1至图7，如图1所示，该显示面板包括驱动芯片组300、焊盘组200以及假压测试电路100，驱动芯片组300包括用于传输对应驱动信号的N个引脚，N为正整数；焊盘组200包括N个焊盘，一焊盘与一引脚对应绑定；假压测试电路100的各输入端分别与一焊盘对应连接，假压测试电路100的第一控制端与第一控制线10连接，假压测试电路100的第二控制端与第二控制线20连接，假压测试电路100的第一输出端与第一绑定检测线30连接，假压测试电路100的第二输出端与第二绑定检测线40连接，用于根据第一绑定检测线30、第二绑定检测线40对应输出的绑定检测信号的时序、状态判断每个引脚与对应焊盘的绑定状态。
可以理解的是，本实施例提供的显示面板，通过一焊盘与一引脚对应绑定，假压测试电路100的各输入端分别与一焊盘对应连接，假压测试电路100的第一控制端与第一控制线10连接，假压测试电路100的第二控制端与第二控制线20连接，假压测试电路100的第一输出端与第一绑定检测线30连接，假压测试电路100的第二输出端与第二绑定检测线40连接，能够根据第一绑定检测线30、第二绑定检测线40对应输出的绑定检测信号的时序、状态判断每个引脚与对应焊盘的绑定状态，不仅能够检测到每个引脚的绑定状态，提高了绑定状态检测的准确性；且通过绑定检测信号的时序、状态即可判断每个引脚与对应焊盘的绑定状态，与依靠显微镜对各引脚的绑定状态逐个查看相比，提高了绑定状态检测的效率。
又，相关技术中的显示装置通常采用假压测试电路100进行点灯测试，本实施例可以赋予该假压测试电路100以新的用途或者功能，不仅节省了显示面板的电路使用数量，还实现了更为先进的绑定状态检测。
需要进行说明的是，驱动芯片组300可以包括至少一个驱动芯片，而驱动芯片组300的N个引脚可以为该至少一个驱动芯片的所有输出引脚，每一输出引脚用于输出一对应的驱动信号。
在其中一个实施例中，N个引脚依次沿第一方向DR1排布且沿第一方向DR1依次分时传输对应的各驱动信号；N个焊盘依次沿第一方向DR1排布，其中，第1个焊盘PAD1至第N个焊盘与第1个引脚S1至第N个引脚依次对应绑定；假压测试电路100包括沿第一方向DR1依次排布的N个开关器件，N个开关器件分为奇数组开关器件110和偶数组开关器件120，其中，第1个开关器件的输入端至第N个开关器件的输入端与第1个焊盘至第N个焊盘依次分别对应连接，奇数组开关器件110的各控制端与第一控制线10或者第二控制线20中的一个连接，偶数组开关器件120的各控制端与第一控制线10或者第二控制线20中的另一个连接，奇数组开关器件110的各输出端与第一绑定检测线30或者第二绑定检测线40中的一个连接，偶数组开关器件120的各输出端与第一绑定检测线30或者第二绑定检测线40中的另一个连接，且奇数组开关器件110、偶数组开关器件120分时交替导通。
需要进行说明的是，沿第一方向DR1依次分时传输对应的各驱动信号，例如，沿第一方向DR1自左至右的第1个输出引脚至第N个输出引脚依次分别输出第1个驱动信号至第N个驱动信号。其中，第1个驱动信号至第N个驱动信号具有相同的频率，但是，第1个驱动信号的相位至第N个驱动信号的相位依次变化，例如，第1个驱动信号的脉冲持续时间结束时或者结束后才开始第2个驱动信号的脉冲持续时间，其他驱动信号的相位可以依次类推。可以理解的是，如此有助于根据假压测试电路100在对应时间输出的绑定检测信号确定对应输出引脚的绑定状态。
在本实施例中，通过N个引脚依次沿第一方向DR1排布例如第1个输出引脚S1、第2个输出引脚S2、第3个输出引脚S3、第4个输出引脚S4、第5个输出引脚S5、第6个输出引脚S6、第7个输出引脚S7、第8个输出引脚S8...、第2N-3个输出引脚S2N-3、第2N-2个输出引脚S2N-2、第2N-1个输出引脚S2N-1、第2N个输出引脚S2N...等等，N个焊盘依次沿第一方向DR1排布例如第1个焊盘PAD1、第2个焊盘PAD2、第3个焊盘PAD3、第4个焊盘PAD4...第2N-3个焊盘PAD2N-3、第2N-2个焊盘PAD2N-2、第2N-1个焊盘PAD2N-1、第2N个焊盘PAD2N...等等，这样实现了对N个引脚、N个焊盘分别进行了对应标定，有助于通过时序来更为准确地识别对应的输出引脚。
其中，假设假压测试电路100包括沿第一方向DR1依次排布的2N个开关器件，则奇数组开关器件110可以为沿第一方向DR1自左至右的第1个开关器件T1、第3个开关器件T3...第2N-3个开关器件T2N-3、第2N-1个开关器件T2N-1等的集合；偶数组开关器件120可以为沿第一方向DR1自左至右的第2个开关器件T2、第4个开关器件T4...第2N-2个开关器件T2N-2、第2N个开关器件T2N等的集合。
在其中一个实施例中，如图2所示，上述绑定状态包括绑定正常状态、绑定不良状态、绑定短接状态以及未绑定上状态。其中，绑定正常状态如图2所示的QK1，白色图案所示的引脚与黑色图案所示的焊盘在显示面板的厚度方向上完全重叠。绑定不良状态如图2所示的QK2，白色图案所示的引脚与黑色图案所示的焊盘在显示面板的厚度方向上部分重叠。绑定短接状态如图2所示的QK3，虽然白色图案所示的引脚与对应的黑色图案所示的焊盘在显示面板的厚度方向上各自完全重叠，但是，由于两个相邻的白色图案所示的引脚发生电性连接，造成了两个相邻的引脚短路。未绑定上状态如图2所示的QK4，白色图案所示的引脚与黑色图案所示的焊盘在显示面板的厚度方向上完全不重叠。
在其中一个实施例中，如图3所示，第一控制线10用于传输第一使能信号EN1，第二控制线20用于传输第二使能信号EN2，在显示面板的显示阶段P11中，第一使能信号EN1、第二使能信号EN2均处于高电位，此时，假压测试电路100中各开关器件均处于断开状态。可以理解的是，在该显示阶段P11中，显示面板处于显示状态。
在绑定状态检测阶段P12中的第一绑定状态检测子阶段P121中，第一使能信号EN1处于低电位、第二使能信号EN2处于高电位，此时，奇数组开关器件110中各开关器件均处于导通状态，偶数组开关器件120中各开关器件均处于断开状态；在绑定状态检测阶段P12中的第二绑定状态检测子阶段P122中，第一使能信号EN1处于高电位、第二使能信号EN2处于低电位，此时，奇数组开关器件110中各开关器件均处于断开状态，偶数组开关器件120中各开关器件均处于导通状态。
需要进行说明的是，图3所示的时序示意图是以假压测试电路100中各开关器件均为P沟道型薄膜晶体管为例进行的说明，可以理解的是，其他实施例并不限于此，也可以均采用N沟道型薄膜晶体管，还可以采用P沟道型薄膜晶体管和/或N沟道型薄膜晶体管，所需的第一使能信号EN1、第二使能信号EN2的时序根据对应实施例的发明构思去调整即可，在此不作赘述。
在其中一个实施例中，如图4至图7所示，绑定检测信号包括第一绑定检测线30传输的第一绑定检测信号DETECT1和第二绑定检测线40传输的第二绑定检测信号DETECT2。
在其中一个实施例中，根据各驱动信号与各绑定检测信号的时序比较结果，确定对应引脚所在的位置。例如图4所示，第1个输出引脚S1至第8个输出引脚S8依次分时输出包括一个脉冲的驱动信号，对应地，可以通过同时监测第一绑定检测信号DETECT1、第二绑定检测信号DETECT2获得两者如图4所示的对应波形，然后根据上述对应的硬件连接关系即可确定：第一绑定检测信号DETECT1中的第一个脉冲是源自第1个输出引脚S1、第二绑定检测信号DETECT2中的第一个脉冲是源自第2个输出引脚S2、第一绑定检测信号DETECT1中的第二个脉冲是源自第3个输出引脚S3、第二绑定检测信号DETECT2中的第二个脉冲是源自第4个输出引脚S4、第一绑定检测信号DETECT1中的第三个脉冲是源自第5个输出引脚S5、第二绑定检测信号DETECT2中的第三个脉冲是源自第6个输出引脚S6、第一绑定检测信号DETECT1中的第四个脉冲是源自第7个输出引脚S7、第二绑定检测信号DETECT2中的第四个脉冲是源自第8个输出引脚S8...等等依次类推。
在其中一个实施例中，如图4所示，第N个驱动信号的脉冲与第N个绑定检测信号的脉冲位于同一时段，则确定与第N个绑定检测信号对应的引脚为第N个引脚。
例如，第1个输出引脚S1输出的第1个驱动信号的脉冲与第1个绑定检测信号的脉冲即第一绑定检测信号DETECT1中的第一个脉冲位于同一时段，则确定与第一绑定检测信号DETECT1中的第一个脉冲对应的引脚为第1个引脚或者第1个输出引脚S1。
在其中一个实施例中，根据各驱动信号与各绑定检测信号的状态比较结果和/或时序比较结果，确定对应引脚与对应焊盘的绑定状态。
在其中一个实施例中，如图4所示，响应于各驱动信号的时序、脉冲幅值与各绑定检测信号的时序、脉冲幅值均一致，则确定对应引脚与对应焊盘之间的绑定状态为绑定正常状态。
例如，第1个输出引脚S1输出的第1个驱动信号的脉冲与第1个绑定检测信号的脉冲即第一绑定检测信号DETECT1中的第一个脉冲位于同一时段即两者的时序一致，同时第一绑定检测信号DETECT1中的第一个脉冲的幅值与第1个输出引脚S1输出的第1个驱动信号的脉冲的幅值也近似相等或者相等，则确定第1个输出引脚S1与第一个焊盘PAD1的绑定状态为绑定正常状态，其他可以依次类推。
在其中一个实施例中，如图5所示，响应于绑定检测信号的脉冲幅值小于对应的驱动信号的脉冲幅值，则确定与绑定检测信号对应的引脚处于绑定不良状态。
例如，第二绑定检测信号DETECT2中的第二个脉冲的幅值明显小于第4个输出引脚S4输出的第4个驱动信号的脉冲的幅值，基于此可以确定与第二绑定检测信号DETECT2中的第二个脉冲对应的第4个输出引脚S4处于绑定不良状态。
在其中一个实施例中，如图6所示，响应于第一绑定检测信号的脉冲持续时间与第二绑定检测信号的脉冲持续时间在时序上重叠，则确定至少两个相邻的对应引脚处于绑定短接状态。
例如，第5个输出引脚S5输出的第5个驱动信号时，对应地，第一绑定检测信号DETECT1应该接收到第三个脉冲，而此时第二绑定检测信号DETECT2是不应该接收到第三个脉冲的；同理，第6个输出引脚S6输出的第6个驱动信号时，对应地，第二绑定检测信号DETECT2应该接收到第三个脉冲，而此时第一绑定检测信号DETECT1是不应该接收到第四个脉冲的。但是，由于第一绑定检测信号DETECT1、第二绑定检测信号DETECT2均存在同时接收到脉冲的情况，由此可以断定第5个输出引脚S5与第6个输出引脚S6存在绑定短接状态。
在其中一个实施例中，如图7所示，响应于绑定检测信号的脉冲数量少于各驱动信号的脉冲数量，则确定对应引脚处于未绑定上状态。
例如，在绑定正常状态下，第3个输出引脚S3输出的第3个驱动信号时，第一绑定检测信号DETECT1应该接收到第二个脉冲，但是由于第3个输出引脚S3与第3个焊盘PAD3未绑定上，导致第一绑定检测信号DETECT1没有接收到第二个脉冲，由此可以确定第3个输出引脚S3处于未绑定上状态。
在其中一个实施例中，本实施例提供一种显示装置，该显示装置包括上述至少一实施例中的显示面板，其中，驱动芯片组300、焊盘组200以及假压测试电路100依次沿第二方向DR2排布。
可以理解的是，本实施例提供的显示装置，通过一焊盘与一引脚对应绑定，假压测试电路100的各输入端分别与一焊盘对应连接，假压测试电路100的第一控制端与第一控制线10连接，假压测试电路100的第二控制端与第二控制线20连接，假压测试电路100的第一输出端与第一绑定检测线30连接，假压测试电路100的第二输出端与第二绑定检测线40连接，能够根据第一绑定检测线30、第二绑定检测线40对应输出的绑定检测信号的时序、状态判断每个引脚与对应焊盘的绑定状态，不仅能够检测到每个引脚的绑定状态，提高了绑定状态检测的准确性；且通过绑定检测信号的时序、状态即可判断每个引脚与对应焊盘的绑定状态，与依靠显微镜对各引脚的绑定状态逐个查看相比，提高了绑定状态检测的效率。
又，相关技术中的显示装置通常采用假压测试电路100进行点灯测试，本实施例可以赋予该假压测试电路100以新的用途或者功能，不仅节省了显示面板的电路使用数量，还实现了更为先进的绑定状态检测。
需要进行说明的是，上述显示面板可以但不限于为有机发光二极管显示面板，也可以为液晶显示面板，还可以为微发光二极管显示面板、迷你发光二极管显示面板或者量子点发光二极管显示面板中的任一种。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    驱动芯片组，所述驱动芯片组包括用于传输对应驱动信号的N个引脚，N为正整数；
    焊盘组，所述焊盘组包括N个焊盘，一所述焊盘与一所述引脚对应绑定；以及
    假压测试电路，所述假压测试电路的各输入端分别与一所述焊盘对应连接，所述假压测试电路的第一控制端与第一控制线连接，所述假压测试电路的第二控制端与第二控制线连接，所述假压测试电路的第一输出端与第一绑定检测线连接，所述假压测试电路的第二输出端与第二绑定检测线连接，用于根据所述第一绑定检测线、所述第二绑定检测线对应输出的绑定检测信号的时序、状态判断每个所述引脚与对应焊盘的绑定状态。
  2. 根据权利要求1所述的显示面板，其中，所述N个引脚依次沿第一方向排布且沿所述第一方向依次分时传输对应的各所述驱动信号；
    所述N个焊盘依次沿所述第一方向排布，其中，第1个焊盘至第N个焊盘与第1个引脚至第N个引脚依次对应绑定；
    所述假压测试电路包括沿所述第一方向依次排布的N个开关器件，所述N个开关器件分为奇数组开关器件和偶数组开关器件，其中，第1个开关器件的输入端至第N个开关器件的输入端与所述第1个焊盘至第N个焊盘依次分别对应连接，所述奇数组开关器件的各控制端与所述第一控制线或者所述第二控制线中的一个连接，所述偶数组开关器件的各控制端与所述第一控制线或者所述第二控制线中的另一个连接，所述奇数组开关器件的各输出端与所述第一绑定检测线或者所述第二绑定检测线中的一个连接，所述偶数组开关器件的各输出端与所述第一绑定检测线或者所述第二绑定检测线中的另一个连接，且所述奇数组开关器件、所述偶数组开关器件分时交替导通。
  3. 根据权利要求2所述的显示面板，其中，根据各所述驱动信号与各所述绑定检测信号的时序比较结果，确定对应引脚所在的位置；
    根据各所述驱动信号与各所述绑定检测信号的状态比较结果和/或所述时序比较结果，确定对应引脚与对应焊盘的绑定状态。
  4. 根据权利要求3所述的显示面板，其中，第N个驱动信号的脉冲与第N个绑定检测信号的脉冲位于同一时段，则确定与所述第N个绑定检测信号对应的引脚为第N个引脚。
  5. 根据权利要求3所述的显示面板，其中，所述绑定状态包括绑定正常状态，响应于各所述驱动信号的时序、脉冲幅值与各所述绑定检测信号的时序、脉冲幅值均一致，则确定对应引脚与对应焊盘之间的绑定状态为所述绑定正常状态。
  6. 根据权利要求3所述的显示面板，其中，所述绑定状态还包括绑定不良状态，响应于所述绑定检测信号的脉冲幅值小于对应的所述驱动信号的脉冲幅值，则确定与所述绑定检测信号对应的引脚处于所述绑定不良状态。
  7. 根据权利要求3所述的显示面板，其中，所述绑定状态还包括绑定短接状态，所述绑定检测信号包括所述第一绑定检测线传输的第一绑定检测信号和所述第二绑定检测线传输的第二绑定检测信号，响应于所述第一绑定检测信号的脉冲持续时间与所述第二绑定检测信号的脉冲持续时间在时序上重叠，则确定至少两个相邻的对应引脚处于所述绑定短接状态。
  8. 根据权利要求3所述的显示面板，其中，所述绑定状态还包括未绑定上状态，响应于所述绑定检测信号的脉冲数量少于各所述驱动信号的脉冲数量，则确定对应引脚处于所述未绑定上状态。
  9. 根据权利要求1所述的显示面板，其中，响应于所述显示面板处于显示状态，所述假压测试电路中的开关器件处于断开状态。
  10. 一种显示装置，包括如权利要求1所述的显示面板，其中，所述驱动芯片组、所述焊盘组以及所述假压测试电路依次沿第二方向排布。
  11. 根据权利要求10所述的显示装置，其中，所述N个引脚依次沿第一方向排布且沿所述第一方向依次分时传输对应的各所述驱动信号；
    所述N个焊盘依次沿所述第一方向排布，其中，第1个焊盘至第N个焊盘与第1个引脚至第N个引脚依次对应绑定；
    所述假压测试电路包括沿所述第一方向依次排布的N个开关器件，所述N个开关器件分为奇数组开关器件和偶数组开关器件，其中，第1个开关器件的输入端至第N个开关器件的输入端与所述第1个焊盘至第N个焊盘依次分别对应连接，所述奇数组开关器件的各控制端与所述第一控制线或者所述第二控制线中的一个连接，所述偶数组开关器件的各控制端与所述第一控制线或者所述第二控制线中的另一个连接，所述奇数组开关器件的各输出端与所述第一绑定检测线或者所述第二绑定检测线中的一个连接，所述偶数组开关器件的各输出端与所述第一绑定检测线或者所述第二绑定检测线中的另一个连接，且所述奇数组开关器件、所述偶数组开关器件分时交替导通。
  12. 根据权利要求11所述的显示装置，其中，根据各所述驱动信号与各所述绑定检测信号的时序比较结果，确定对应引脚所在的位置；
    根据各所述驱动信号与各所述绑定检测信号的状态比较结果和/或所述时序比较结果，确定对应引脚与对应焊盘的绑定状态。
  13. 根据权利要求12所述的显示装置，其中，第N个驱动信号的脉冲与第N个绑定检测信号的脉冲位于同一时段，则确定与所述第N个绑定检测信号对应的引脚为第N个引脚。
  14. 根据权利要求12所述的显示装置，其中，所述绑定状态包括绑定正常状态，响应于各所述驱动信号的时序、脉冲幅值与各所述绑定检测信号的时序、脉冲幅值均一致，则确定对应引脚与对应焊盘之间的绑定状态为所述绑定正常状态。
  15. 根据权利要求12所述的显示装置，其中，所述绑定状态还包括绑定不良状态，响应于所述绑定检测信号的脉冲幅值小于对应的所述驱动信号的脉冲幅值，则确定与所述绑定检测信号对应的引脚处于所述绑定不良状态。
  16. 根据权利要求12所述的显示装置，其中，所述绑定状态还包括绑定短接状态，所述绑定检测信号包括所述第一绑定检测线传输的第一绑定检测信号和所述第二绑定检测线传输的第二绑定检测信号，响应于所述第一绑定检测信号的脉冲持续时间与所述第二绑定检测信号的脉冲持续时间在时序上重叠，则确定至少两个相邻的对应引脚处于所述绑定短接状态。
  17. 根据权利要求12所述的显示装置，其中，所述绑定状态还包括未绑定上状态，响应于所述绑定检测信号的脉冲数量少于各所述驱动信号的脉冲数量，则确定对应引脚处于所述未绑定上状态。
  18. 根据权利要求10所述的显示装置，其中，响应于所述显示面板处于显示状态，所述假压测试电路中的开关器件处于断开状态。
  19. 根据权利要求11所述的显示装置，其中，所述第一方向异于所述第二方向。
  20. 根据权利要求11所述的显示装置，其中，所述开关器件为薄膜晶体管。
PCT/CN2022/093080 2022-04-19 2022-05-16 显示面板及显示装置 Ceased WO2023201804A1 (zh)

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