WO2023199160A1 - 半導体装置、及び、半導体装置の作製方法 - Google Patents

半導体装置、及び、半導体装置の作製方法 Download PDF

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Publication number
WO2023199160A1
WO2023199160A1 PCT/IB2023/053329 IB2023053329W WO2023199160A1 WO 2023199160 A1 WO2023199160 A1 WO 2023199160A1 IB 2023053329 W IB2023053329 W IB 2023053329W WO 2023199160 A1 WO2023199160 A1 WO 2023199160A1
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Prior art keywords
layer
transistor
semiconductor
conductive layer
insulating layer
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English (en)
French (fr)
Japanese (ja)
Inventor
保坂泰靖
井口貴弘
三澤千恵子
佐藤亜美
土橋正佳
神長正美
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to CN202380033837.3A priority Critical patent/CN119013783A/zh
Priority to JP2024515177A priority patent/JPWO2023199160A1/ja
Priority to US18/851,736 priority patent/US20250221037A1/en
Priority to KR1020247037521A priority patent/KR20250003781A/ko
Publication of WO2023199160A1 publication Critical patent/WO2023199160A1/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the technical field of one embodiment of the present invention includes semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), and devices equipped with them. Examples include electronic devices, their driving methods, and their manufacturing methods.
  • Semiconductor devices having transistors are widely applied to display devices and electronic devices, and there is a demand for higher integration and higher speed of semiconductor devices. For example, when applying a semiconductor device to a high-definition display device, a highly integrated semiconductor device is required. 2. Description of the Related Art As one means of increasing the degree of integration of transistors, the development of microsized transistors is progressing.
  • VR virtual reality
  • AR augmented reality
  • SR substitute reality
  • MR mixed reality
  • XR Extended Reality
  • Display devices for XR are desired to have high definition and high color reproducibility in order to enhance the sense of reality and immersion.
  • Examples of devices that can be applied to the display device include a light emitting device including a light emitting device (also referred to as a light emitting element) such as a liquid crystal display device, an organic EL (Electro Luminescence) element, and a light emitting diode (LED).
  • a light emitting device also referred to as a light emitting element
  • a light emitting element such as a liquid crystal display device, an organic EL (Electro Luminescence) element, and a light emitting diode (LED).
  • Patent Document 1 discloses a display device for VR using an organic EL device (also referred to as an organic EL element).
  • An object of one embodiment of the present invention is to provide a semiconductor device having a microsized transistor and a method for manufacturing the same.
  • an object of one embodiment of the present invention is to provide a semiconductor device in which transistors are arranged at high density, and a method for manufacturing the same.
  • an object of one embodiment of the present invention is to provide a semiconductor device including a transistor with a large on-state current, and a method for manufacturing the same.
  • Another object of one embodiment of the present invention is to provide a highly integrated semiconductor device and a method for manufacturing the same.
  • Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics and a method for manufacturing the same.
  • Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same.
  • an object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.
  • an object of one embodiment of the present invention is to provide a novel semiconductor device and a method for manufacturing the same.
  • One embodiment of the present invention includes a first transistor, a second transistor, and a first insulating layer
  • the first transistor includes a first semiconductor layer, a second insulating layer
  • the second transistor has a first conductive layer to a third conductive layer
  • the second transistor includes a second semiconductor layer, a third insulating layer, a fourth conductive layer to a sixth conductive layer
  • the first insulating layer is provided on the first conductive layer and has an opening reaching the first conductive layer
  • the second conductive layer is provided on the first insulating layer.
  • the first semiconductor layer is in contact with the upper surface of the first conductive layer, the inner wall of the opening, and the second conductive layer
  • the third conductive layer is in contact with the second conductive layer through the second insulating layer.
  • the third insulating layer is provided on the first semiconductor layer so as to have a region overlapping with the inner wall of the opening, the third insulating layer is provided on the fourth conductive layer, and the second semiconductor layer overlaps with the fourth conductive layer.
  • the fifth conductive layer is provided on the third insulating layer so as to have a region, the fifth conductive layer is in contact with the side surface and the top surface of the second semiconductor layer at the first side end, and the sixth conductive layer is The second semiconductor layer is in contact with the side surface and top surface of the second side end opposite to the first side end, and is in contact with one of the source electrode, drain electrode, or gate electrode of the first transistor.
  • a semiconductor device is electrically connected to any one of the source electrode, drain electrode, or gate electrode of the transistor No. 2.
  • the second conductive layer and the fourth conductive layer are formed of the same conductive layer.
  • the third conductive layer and the fifth conductive layer are formed of the same conductive layer.
  • the second conductive layer and the fifth conductive layer are formed of the same conductive layer.
  • one embodiment of the present invention includes a first transistor, a second transistor, and a first insulating layer
  • the first transistor includes a first semiconductor layer and a second insulating layer. and a first conductive layer to a third conductive layer
  • the second transistor has a second semiconductor layer, a third insulating layer, and a fourth conductive layer to a sixth conductive layer.
  • the first insulating layer is provided on the second semiconductor layer and has an opening reaching the first conductive layer
  • the second conductive layer is provided on the first insulating layer.
  • the fifth conductive layer is provided on the third insulating layer so as to have a region overlapping with the second semiconductor layer, and the fifth conductive layer is in contact with the side surface and the top surface of the second semiconductor layer at the first side end, is in contact with the side surface and top surface of the second semiconductor layer at the second side end opposite to the first side end, and is in contact with one of the source electrode, drain electrode, or gate electrode of the first transistor.
  • the first semiconductor layer and the second semiconductor layer each include an oxide semiconductor.
  • the first conductive layer and the fifth conductive layer are formed of the same conductive layer.
  • a first conductive film is formed, the first conductive film is processed to form a first conductive layer, and a first insulating layer is formed over the first conductive layer.
  • a second conductive film is formed on the first insulating layer, and the second conductive film and the first insulating layer are processed to form the second conductive film and the first insulating layer.
  • An opening is formed in the insulating layer, and a first metal oxide film is formed to cover the top surface of the first conductive layer, the inner wall of the opening, and the top surface of the second conductive film.
  • a second semiconductor layer is formed by processing the film so as to have a region overlapping with the inner wall of the opening to form a first semiconductor layer, a second conductive film is processed to form a second conductive layer, the first semiconductor layer, a second insulating layer is formed on the second conductive layer and the first insulating layer; a second metal oxide film is formed on the second insulating layer; A second semiconductor layer is formed by processing the film so as to have a region overlapping with the second conductive layer, and a third conductive film is formed on the second semiconductor layer and the second insulating layer.
  • a semiconductor device having a microsized transistor and a method for manufacturing the same can be provided.
  • a semiconductor device in which transistors are arranged at high density and a method for manufacturing the same can be provided.
  • a semiconductor device including a transistor with a large on-current and a method for manufacturing the same can be provided.
  • a highly integrated semiconductor device and a method for manufacturing the same can be provided.
  • a semiconductor device with good electrical characteristics and a method for manufacturing the same can be provided.
  • a highly reliable semiconductor device and a method for manufacturing the same can be provided.
  • a method for manufacturing a semiconductor device with high productivity can be provided.
  • a novel semiconductor device and a method for manufacturing the same can be provided.
  • FIG. 1A is a plan view showing an example of a semiconductor device.
  • FIG. 1B is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 2A is a plan view showing an example of a semiconductor device.
  • FIG. 2B is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 3A is a plan view showing an example of a semiconductor device.
  • FIG. 3B is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 4A is a plan view showing an example of a semiconductor device.
  • FIG. 4B is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 5A is a plan view showing an example of a semiconductor device.
  • FIGS. 12A to 12C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 13A to 13D are circuit diagrams of pixel circuits.
  • 14A to 14D are circuit diagrams of pixel circuits.
  • FIG. 15 is a perspective view showing an example of a display device.
  • FIG. 16 is a cross-sectional view showing an example of a display device.
  • FIG. 17 is a cross-sectional view showing an example of a display device.
  • FIG. 18 is a cross-sectional view showing an example of a display device.
  • FIG. 19 is a cross-sectional view showing an example of a display device.
  • FIG. 20 is a cross-sectional view showing an example of a display device.
  • 21A to 21H are diagrams showing examples of pixels.
  • 22A to 22K are diagrams showing examples of pixels.
  • 23A to 23F are diagrams illustrating configuration examples of light emitting devices.
  • 24A to 24C are diagrams showing configuration examples of light emitting devices.
  • 25A and 25B are diagrams illustrating a configuration example of a light receiving device.
  • 25C to 25E are diagrams illustrating configuration examples of a display device.
  • 26A to 26D are diagrams illustrating an example of an electronic device.
  • 27A to 27F are diagrams illustrating an example of an electronic device.
  • 28A to 28G are diagrams illustrating an example of an electronic device.
  • film and “layer” can be interchanged depending on the situation or circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • a device manufactured using a metal mask or FMM fine metal mask, high-definition metal mask
  • a device with a MM (metal mask) structure is sometimes referred to as a device with an MML (metal maskless) structure.
  • SBS Side By Side
  • materials and configurations can be optimized for each light emitting device, which increases the degree of freedom in selecting materials and configurations, making it easier to improve brightness and reliability.
  • holes or electrons may be referred to as “carriers”.
  • a hole injection layer or an electron injection layer is called a “carrier injection layer”
  • a hole transport layer or an electron transport layer is called a “carrier transport layer”
  • a hole blocking layer or an electron blocking layer is called a “carrier injection layer.”
  • the carrier injection layer, carrier transport layer, and carrier block layer described above may not be clearly distinguishable depending on their respective cross-sectional shapes or characteristics.
  • one layer may serve as two or three functions among a carrier injection layer, a carrier transport layer, and a carrier block layer.
  • a light emitting device has an EL layer between a pair of electrodes.
  • the EL layer has at least a light emitting layer.
  • the layers (also referred to as functional layers) included in the EL layer include a light emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and Examples include carrier block layers (hole block layers and electron block layers).
  • a light-receiving device (also referred to as a light-receiving element) has an active layer that functions as at least a photoelectric conversion layer between a pair of electrodes.
  • island-like refers to a state in which two or more layers formed in the same process and using the same material are physically separated.
  • an island-shaped light emitting layer indicates that the light emitting layer and an adjacent light emitting layer are physically separated.
  • a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • it refers to a shape having a region in which the angle between the inclined side surface and the substrate surface or the surface to be formed (also referred to as a taper angle) is less than 90 degrees.
  • the side surface of the structure, the substrate surface, or the surface to be formed does not necessarily have to be completely flat, and may be substantially planar with a minute curvature or may be substantially planar with minute irregularities.
  • a mask layer (also referred to as a sacrificial layer) is a layer located above at least a light emitting layer (more specifically, a layer that is processed into an island shape among the layers constituting the EL layer). , has a function of protecting the light emitting layer during the manufacturing process.
  • step breakage refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step difference).
  • the planar shapes roughly match means that at least a portion of the outlines of the laminated layers overlap. For example, this includes a case where the upper layer and the lower layer are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case, it is also said that the planar shapes roughly match.
  • One embodiment of the present invention includes one horizontal channel transistor (described later) and one vertical channel transistor (described later), and includes a source electrode, a drain electrode, or a gate of the horizontal channel transistor.
  • This is a semiconductor device in which one of the electrodes is electrically connected to one of the source electrode, drain electrode, or gate electrode of a vertical channel transistor.
  • the semiconductor device can occupy a smaller area within the substrate plane than a semiconductor device having two lateral channel transistors.
  • a semiconductor device of one embodiment of the present invention, a method for manufacturing the same, and the like will be described with reference to FIGS. 1A to 14D.
  • FIG. 1A shows a plan view (also referred to as a top view) of the semiconductor device 10.
  • FIG. 1B shows a cross-sectional view taken along the dashed line A1-A2 shown in FIG. 1A. Note that some components of the semiconductor device 10 are omitted in FIG. 1A. Regarding the plan view of the semiconductor device, some of the constituent elements are omitted in the subsequent drawings as well, similar to FIG. 1A.
  • the semiconductor device 10 includes a transistor M1 and a transistor M2 on a substrate 102.
  • the transistor M1 covers a conductive layer 112b provided on the conductive layer 112a and the insulating layer 110 stacked on the substrate 102, the side and top surfaces of the conductive layer 112b, and a part of the top surface of the insulating layer 110.
  • the conductive layer 112b functions as a gate electrode.
  • the insulating layer 106 functions as a gate insulating layer.
  • the semiconductor layer 109 functions as a semiconductor layer in which a channel is formed.
  • the conductive layer 116a functions as either a source electrode or a drain electrode, and the conductive layer 116b functions as the other source electrode or drain electrode.
  • the gate electrode (conductive layer 112b) is located below the semiconductor layer (semiconductor layer 109) in which the channel is formed, and the upper surface of the semiconductor layer (semiconductor layer 109) in which the channel is formed is located.
  • a source electrode and a drain electrode (the conductive layer 116a and the conductive layer 116b) are in contact with each other, which is a "bottom gate top contact type" transistor.
  • the transistor M2 includes a conductive layer 112a on the substrate 102, a conductive layer 112b on the insulating layer 110 provided on the conductive layer 112a, and an inner wall of an opening 141 provided in the insulating layer 110 etc. (a top surface of the conductive layer 112a).
  • the semiconductor layer 108 is in contact with a portion of the side surface of the insulating layer 110 and the side surface of the conductive layer 112b) and a portion of the top surface of the conductive layer 112b;
  • the conductive layer 104 includes an insulating layer 106 having a region, and a conductive layer 104 provided on the insulating layer 106 so as to have a region overlapping with the inner wall of the opening 141.
  • the conductive layer 112a functions as either a source electrode or a drain electrode, and the conductive layer 112b functions as the other source electrode or drain electrode.
  • the semiconductor layer 108 functions as a semiconductor layer in which a channel is formed.
  • the insulating layer 106 functions as a gate insulating layer.
  • the conductive layer 104 functions as a gate electrode.
  • the transistor M2 is located at a height between the upper surface of the conductive layer 112a and the lower surface of the conductive layer 112b in a cross-sectional view (see FIG. 1B), and overlaps with the conductive layer 104 via the insulating layer 106.
  • a region of the semiconductor layer 108 functions as a channel formation region. That is, the length of this region becomes the channel length of transistor M2. Therefore, in the transistor M2, the channel length can be determined by adjusting the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor with a short channel length can be manufactured with high precision. Furthermore, when a plurality of transistors M2 are manufactured, variations in characteristics among the transistors M2 can also be reduced.
  • the transistor M2 is provided in a region where the semiconductor layer 108 overlaps with the opening 141 in a plan view (see FIG. 1A), the outer circumference of the opening 141, more precisely, the semiconductor layer 108 in the opening 141 ( The outer peripheral length of the channel forming region of the transistor M2 becomes the channel width of the transistor M2. Note that in FIG. 1B, the width of the opening 141 in the X direction is narrower toward the conductive layer 112a and wider toward the conductive layer 112b.
  • the outer circumference of the channel forming region in the region where the width of the opening 141 in the X direction is the narrowest may be defined as the channel width of the transistor M2, or conversely, the width of the opening 141 in the X direction may be the narrowest.
  • the outer circumferential length of the channel formation region in a wide area may be defined as the channel width of the transistor M2.
  • an intermediate value between the two may be defined as the channel width of the transistor M2.
  • the conductive layer 112b functions as the gate electrode in the transistor M1, and functions as the other of the source electrode and the drain electrode in the transistor M2. That is, the gate electrode of the transistor M1 and the other of the source electrode or the drain electrode of the transistor M2 are electrically connected. Therefore, it can be said that the semiconductor device 10 of one embodiment of the present invention includes two transistors (transistor M1 and transistor M2) that are electrically connected.
  • the drain current flows through the region between the conductive layer 116a and the conductive layer 116b of the semiconductor layer 109, whereas in the transistor M2, the drain current flows between the conductive layer 112a and the conductive layer 112b of the semiconductor layer 108. Drain current flows through the region between the two. That is, in the transistor M1, the direction in which the drain current flows is approximately parallel to the substrate surface, whereas in the transistor M2, the direction in which the drain current flows is approximately perpendicular to the substrate surface (more More precisely, the direction along the side surface of the opening 141).
  • a transistor like the transistor M1, in which the source electrode and the drain electrode are arranged in the lateral direction (the X direction or the Y direction shown in FIGS. 1A and 1B), and the drain current flows in the lateral direction, is referred to as a "lateral channel”. Also called a type transistor.
  • a transistor in which the source electrode and the drain electrode are arranged in the vertical direction (Z direction shown in FIGS. 1A and 1B) and the drain current flows in the vertical direction is referred to as a "vertical channel type" transistor. Also called "transistor”.
  • Vertical channel transistors have a source electrode and a drain electrode arranged in a direction perpendicular to the substrate surface (Z direction shown in FIGS. 1A and 1B), so compared to horizontal channel transistors, the substrate The in-plane area occupied by the transistor can be significantly reduced.
  • one of the two transistors included in the semiconductor device is a vertical channel transistor. Therefore, in the semiconductor device 10 of one embodiment of the present invention, the area occupied by the semiconductor device in the substrate plane can be reduced compared to a semiconductor device in which two lateral channel transistors are arranged laterally.
  • one of the two transistors included in the semiconductor device is a lateral channel transistor. Therefore, some transistor components such as a source electrode and a drain electrode can be manufactured all at once on the same plane. Therefore, the number of manufacturing steps can be reduced compared to vertical channel transistors.
  • the transistor M1 is a bottom gate top contact type transistor. In a bottom-gate top-contact transistor, a region of the semiconductor layer that is sandwiched between a source electrode and a drain electrode and faces a gate electrode functions as a channel formation region. Therefore, in the bottom-gate top-contact transistor, the channel formation region in the semiconductor layer is not exposed during the transistor manufacturing process.
  • a semiconductor device in which transistors having good characteristics are arranged at high density can be realized. Further, a highly integrated semiconductor device can be realized. For example, when the semiconductor device 10 of one embodiment of the present invention is used in a pixel circuit (described later) of a display device, the display device can have higher definition.
  • Substrate 102 There are no major restrictions on the material used for the substrate 102. Depending on the purpose, it may be determined by taking into consideration the presence or absence of translucency and heat resistance to withstand heat treatment. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. Further, a semiconductor substrate having an insulating surface, a flexible substrate, a bonding film, a base film, etc. may be used.
  • a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc.
  • a semiconductor substrate having an insulating surface, a flexible substrate, a bonding film, a base film, etc. may be used.
  • the semiconductor substrate examples include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • the semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.
  • the substrate 102 can be, for example, 6th generation (1500 mm x 1850 mm), 7th generation (1870 mm x 2200 mm), 8th generation (2200 mm x 2400 mm), A glass substrate with a large area, such as 9th generation (2400 mm x 2800 mm) or 10th generation (2950 mm x 3400 mm), can be used. Thereby, a large-sized display device can be manufactured. Furthermore, by increasing the size of the substrate, more display devices can be produced from one substrate, and production costs can be reduced.
  • a flexible substrate, a bonded film, a base film, or the like may be used as the substrate 102.
  • polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, and polymethyl methacrylate.
  • a lightweight semiconductor device can be provided. Furthermore, by using the above material for the substrate 102, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above material for the substrate 102, a semiconductor device that is less likely to be damaged can be provided.
  • the flexible substrate used for the substrate 102 may be made of a material having a coefficient of linear expansion of 1 ⁇ 10 ⁇ 3 /K or less, 5 ⁇ 10 ⁇ 5 /K or less, or 1 ⁇ 10 ⁇ 5 /K or less, for example.
  • aramid is suitable as a flexible substrate used for the substrate 102 because it has a low coefficient of linear expansion.
  • a conductive layer (conductive layer 116a, conductive layer 116b) functions as a source electrode and a drain electrode of transistor M1
  • a conductive layer (conductive layer 112b) functions as a gate electrode of transistor M1
  • a source electrode and drain electrode of transistor M2 In addition to the conductive layers (conductive layer 112a, conductive layer 112b) and the conductive layer (conductive layer 104) that functions as the gate electrode of transistor M2, various wirings, electrodes, etc.
  • Conductive materials that can be used for the conductive layer include aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), and nickel ( Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium ( A metal element selected from Be), an alloy containing the above-mentioned metal elements, an alloy combining the above-mentioned metal elements, etc. can be used.
  • a semiconductor such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the method for forming the conductive material is not particularly limited, and various methods such as vapor deposition, chemical vapor deposition (CVD), sputtering, and spin coating can be used.
  • a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied as the conductive material. Since the layer formed of the Cu-X alloy can be processed by a wet etching process, it is possible to suppress manufacturing costs. Further, as the conductive material, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
  • conductive materials that can be used for the conductive layer indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin containing titanium oxide, etc.
  • Conductive materials with oxygen can also be used, such as oxides, indium zinc oxide, indium tin oxide doped with silicon oxide.
  • conductive materials containing nitrogen such as titanium nitride, tantalum nitride, and tungsten nitride can also be used.
  • the conductive layer can also have a laminated structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the metal element described above are appropriately combined.
  • the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, or a tungsten layer on a titanium nitride layer.
  • a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, and a three-layer structure in which a titanium layer is laminated, an aluminum layer is laminated on the titanium layer, and a titanium layer is laminated on top of that. good.
  • the conductive layer may have a laminated structure in which a material containing the aforementioned metal element and a conductive material containing oxygen are combined.
  • a layered structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be used in which a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • a conductive layer is formed by laminating a conductive layer containing copper on a conductive layer containing at least one of indium or zinc and oxygen, and further containing at least one of indium or zinc and oxygen on top of the conductive layer containing at least one of indium or zinc and oxygen. It may also have a three-layer structure in which conductive layers are laminated. In this case, it is preferable that the side surfaces of the conductive layer containing copper are also covered with a conductive layer containing at least one of indium or zinc and oxygen. Further, for example, a plurality of conductive layers containing at least one of indium or zinc and oxygen may be stacked and used as the conductive layer.
  • the conductive layer 112a and the conductive layer 112b in contact with the semiconductor layer 108, and the conductive layer 116a and the conductive layer 116b in contact with the semiconductor layer 109 are oxidized.
  • a conductive material that converts the semiconductor into an n-type semiconductor For example, a conductive material containing nitrogen may be used.
  • a conductive material containing titanium or tantalum and nitrogen may be used.
  • another conductive material may be provided over the conductive material containing nitrogen.
  • various insulating layers that constitute the semiconductor device 10 of one embodiment of the present invention include aluminum nitride, aluminum nitride, Aluminum oxide, aluminum nitride oxide, aluminum oxide nitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, oxide
  • a material selected from tantalum, aluminum silicate, etc. is used in a single layer or in a stacked manner.
  • a mixture of a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitrided oxide materials may be used in a single layer or in a stacked manner.
  • a mixture of a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitrided oxide materials may be
  • oxynitride refers to a material containing more oxygen than nitrogen.
  • nitrided oxide refers to a material containing more nitrogen than oxygen. Note that the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS) method.
  • RBS Rutherford Backscattering Spectrometry
  • an oxide semiconductor for the semiconductor layer 108 and the semiconductor layer 109 it is preferable to use an insulating material containing reduced hydrogen and oxygen for the insulating layer 106 and the insulating layer 110.
  • an insulating material containing reduced hydrogen and oxygen for the insulating layer 106 and the insulating layer 110 For example, it is preferable to use silicon oxide for each of the insulating layer 106 and the insulating layer 110.
  • silicon oxide for the insulating layer 106 and the insulating layer 110 respectively, the semiconductor layer 108 and the semiconductor layer 109 having regions in contact with these insulating layers are unlikely to become n-type.
  • oxygen can be efficiently supplied to the semiconductor layer 108 and the semiconductor layer 109 from these insulating layers.
  • oxygen vacancies (V O ) in the semiconductor layer 108 and the semiconductor layer 109 are reduced, and the electrical characteristics and reliability of the transistors M1 and M2 can be improved at the same time.
  • an insulating material that is difficult for impurities to pass through for an insulating layer located above or below the transistors M1 and M2 (none of which are shown).
  • a single layer of an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum Alternatively, it may be used in a laminated manner.
  • Examples of insulating materials that are difficult for impurities to pass through include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, Examples include silicon nitride.
  • impurities can be prevented from entering the transistor M1 and M2 side from above and below the transistors M1 and M2. Since diffusion can be suppressed, the reliability of the semiconductor device 10 can be improved.
  • an insulating layer that can function as a planarization layer may be used as the insulating layer located above or below the transistors M1 and M2.
  • an insulating layer that can function as a planarization layer heat-resistant organic materials such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin can be used.
  • heat-resistant organic materials such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin can be used.
  • low dielectric constant materials low-k materials
  • siloxane resins low-k materials
  • PSG phosphorus glass
  • BPSG phosphorus boron glass
  • the siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material.
  • an organic group for example, an alkyl group or an aryl group
  • a fluoro group may be used as a substituent. Further, the organic group may have a fluoro group.
  • a chemical mechanical polishing (CMP) process may be performed on the surface of the insulating layer that can function as a planarization layer.
  • CMP chemical mechanical polishing
  • the semiconductor layer 109 that functions as a semiconductor layer in which the channel of the transistor M1 is formed, and the semiconductor layer 108 that functions as a semiconductor layer in which the channel of the transistor M2 is formed include a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, Alternatively, an amorphous semiconductor or the like can be used alone or in combination.
  • the semiconductor material silicon, germanium, etc. can be used, for example. Further, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor may be used.
  • an organic substance having semiconductor properties or a metal oxide having semiconductor properties also referred to as an oxide semiconductor
  • these semiconductor materials may contain impurities as dopants.
  • oxide semiconductors have a band gap of 2 eV or more
  • transistors also referred to as "OS transistors”
  • the off-state current is significantly smaller than when using this material. Therefore, the power consumption of the semiconductor device 10 can be reduced.
  • OS transistors operate stably even in high-temperature environments, with little variation in characteristics. For example, even in a high-temperature environment, the off-state current hardly increases. Specifically, the off-state current hardly increases even under an environmental temperature of room temperature or higher and 200° C. or lower. Furthermore, the on-state current is less likely to decrease even in a high-temperature environment. Therefore, a semiconductor device using an OS transistor operates stably even in a high-temperature environment and has high reliability.
  • examples of silicon that can be used for the semiconductor layer in which the channel is formed include single crystal silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon, and the like.
  • examples of polycrystalline silicon include low temperature polysilicon (LTPS).
  • a transistor using amorphous silicon for the semiconductor layer in which a channel is formed can be formed on a large glass substrate and can be manufactured at low cost.
  • a transistor using polycrystalline silicon for a semiconductor layer in which a channel is formed has high field effect mobility and can operate at high speed.
  • a transistor using microcrystalline silicon for a semiconductor layer in which a channel is formed has higher field effect mobility than a transistor using amorphous silicon, and can operate at high speed.
  • OS transistors are used for both transistor M1 and transistor M2. That is, an oxide semiconductor is used for both the semiconductor layer 108 and the semiconductor layer 109. Since the OS transistor has a high dielectric strength voltage between the source and the drain, the channel length can be shortened. Therefore, the on-state current of the transistor can be increased.
  • metal oxides that can be used in the semiconductor layer in which the channel of the OS transistor is formed include indium oxide, gallium oxide, and zinc oxide. It is preferable that the metal oxide contains at least indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide has two or three selected from indium, element M, and zinc.
  • element M is gallium, aluminum, silicon, boron, yttrium, tin, antimony, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, One or more selected from cobalt and magnesium.
  • the element M is preferably one or more selected from aluminum, gallium, yttrium, and tin.
  • indium tin oxide containing silicon or the like can be used.
  • the element M is one or more selected from gallium, aluminum, yttrium, and tin.
  • element M is preferably gallium.
  • composition of the metal oxide used in the semiconductor layer in which the channel is formed greatly affects the electrical characteristics and reliability of the OS transistor.
  • the atomic ratio of indium is greater than or equal to the atomic ratio of zinc.
  • the atomic ratio of indium is greater than or equal to the atomic ratio of tin.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin can be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of aluminum can be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum.
  • In-Ga-Zn oxide for the semiconductor layer in which the channel of the OS transistor is formed, use a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium. I can do it. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium.
  • a metal oxide is used in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of element M. be able to. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • the sum of the atomic ratios of the metal elements can be the atomic ratio of the element M.
  • the atomic ratio of the element M can be the sum of the atomic ratio of gallium and the atomic ratio of aluminum.
  • the atomic ratio of indium, element M, and zinc is within the above-mentioned range.
  • the ratio of the number of indium atoms to the number of atoms of the metal element contained in the metal oxide is 30 atom % or more and 100 atom % or less, preferably 30 atom % or more and 95 atom % or less, more preferably 35 atom % or more and 95 atom %. % or less, more preferably 35 atom % or more and 90 atom % or less, more preferably 40 atom % or more and 90 atom % or less, more preferably 45 atom % or more and 90 atom % or less, more preferably 50 atom % or more and 80 atom % or less.
  • a metal oxide whose content is more preferably 60 atom % or more and 80 atom % or less, more preferably 70 atom % or more and 80 atom % or less.
  • the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is within the above range.
  • the ratio of the number of atoms of indium to the number of atoms of the metal element contained is sometimes referred to as the content rate of indium.
  • a transistor with a large on-current can be obtained.
  • a circuit that can operate at high speed can be manufactured. Furthermore, it becomes possible to reduce the area occupied by the circuit. For example, when applying the transistor to a large display device or a high-definition display device, even if the number of wires increases, signal delay in each wire can be reduced, and display unevenness can be suppressed. . Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be made narrower.
  • the composition of metal oxides can be analyzed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), or inductively coupled plasma mass spectroscopy.
  • Analysis method ICP-MS: Inductively Coupled Plasma-Mass Spectrometry
  • ICP-AES Inductively Coupled Plasma-Atomic Em Spectrometry
  • analysis may be performed by combining two or more of these methods. Note that for elements with low content rates, the actual content rate and the content rate obtained by analysis may differ due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the atomic ratio of indium when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1. 2 or less, including cases where the atomic ratio of zinc is greater than 0.1 and 2 or less.
  • a sputtering method or an atomic layer deposition (ALD) method can be preferably used to form the metal oxide.
  • the atomic ratio of the target and the atomic ratio of the metal oxide may be different.
  • the atomic ratio of the metal oxide may be smaller than the atomic ratio of the target.
  • the atomic ratio of zinc contained in the target may be about 40% or more and 90% or less.
  • GBT Gate Bias Temperature
  • PBTS Positive Bias Temperature Stress
  • NBTS Negative Bias Temperature Stress
  • the PBTS test and NBTS test performed under light irradiation are respectively PBTIS (Positive Bias Temperature Illumination Stress) test and NBTIS (Negative Bias Temperature Illumination Stress) test. It is called the Illumination Stress test.
  • n-type transistor In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (state where current flows), so the amount of variation in threshold voltage in the PBTS test is an indicator of the reliability of the transistor. This is one of the important items to pay attention to.
  • the transistor By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer in which the channel of the transistor is formed, the transistor can have high reliability against application of a positive bias. In other words, a transistor with a small threshold voltage variation in the PBTS test can be obtained. Further, when using a metal oxide containing gallium, it is preferable that the gallium content is lower than the indium content. Thereby, a highly reliable transistor can be realized.
  • One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer where the channel of the transistor is formed and the gate insulating layer.
  • the greater the defect level density the more significant the deterioration in the PBTS test.
  • threshold voltage fluctuations in PBTS tests can be suppressed by using metal oxides that do not contain gallium or have a low gallium content in the semiconductor layer where the transistor channel is formed.
  • gallium contained in metal oxides has a property of attracting oxygen more easily than other metal elements (for example, indium or zinc). Therefore, it is presumed that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, gallium combines with excess oxygen in the gate insulating layer, making it easier to generate carrier (electron in this case) trap sites. . Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer where the channel of the transistor is formed and the gate insulating layer, causing the threshold voltage to fluctuate. .
  • In-Ga-Zn oxide for the semiconductor layer in which the channel of the transistor is formed, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium. Further, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to apply a metal oxide in which the atomic ratio of metal elements satisfies In>Ga and Zn>Ga to the semiconductor layer in which the channel of the transistor is formed.
  • the ratio of the number of gallium atoms to the number of atoms of the metal elements contained is greater than 0 atom % and less than 50 atom %, preferably 0.1 atom % or more and 40 atom %.
  • the following is more preferably 0.1 atomic % or more and 35 atomic % or less, more preferably 0.1 atomic % or more and 30 atomic % or less, more preferably 0.1 atomic % or more and 25 atomic % or less, and more preferably 0.1 It is preferable to use a metal oxide whose content is 0.1 atomic % or more and 15 atomic % or less, more preferably 0.1 atomic % or more and 10 atomic % or less, more preferably 0.1 atomic % or more and 15 atomic % or less.
  • a metal oxide that does not contain gallium may be applied to the semiconductor layer in which the channel of the OS transistor is formed.
  • In--Zn oxide can be applied to the semiconductor layer.
  • the field effect mobility of the transistor can be increased by increasing the ratio of the number of atoms of indium to the number of atoms of the metal element contained in the metal oxide.
  • the metal oxide becomes highly crystalline, which suppresses fluctuations in the electrical characteristics of the transistor and increases reliability. be able to.
  • a metal oxide that does not contain gallium and zinc, such as indium oxide may be applied to the semiconductor layer. By using a metal oxide that does not contain gallium, it is possible to make threshold voltage fluctuations extremely small, especially in PBTS tests.
  • an oxide containing indium and zinc can be used for the semiconductor layer in which the channel of the OS transistor is formed.
  • the present invention can also be applied to the case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M to the semiconductor layer in which the channel of the OS transistor is formed. Further, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • the electrical characteristics of the transistor may change.
  • a transistor applied to a region where light can enter has small fluctuations in electrical characteristics under light irradiation and high reliability against light. Reliability with respect to light can be evaluated, for example, by the amount of variation in threshold voltage in an NBTIS test.
  • a transistor with high reliability against light can be realized.
  • a metal oxide in which the atomic ratio of element M is greater than or equal to that of indium has a larger band gap, making it possible to reduce the amount of variation in threshold voltage in transistor NBTIS tests.
  • the band gap of the metal oxide of the semiconductor layer in which the channel of the transistor is formed is preferably 2.0 eV or more, more preferably 2.5 eV or more, further preferably 3.0 eV or more, and even more preferably 3.2 eV or more. is preferable, more preferably 3.3 eV or more, further preferably 3.4 eV or more, even more preferably 3.5 eV or more.
  • the ratio of the number of atoms of element M to the number of atoms of metal elements contained is 20 atom % or more and 70 atom % or less, preferably 30 atom % or more and 70 atom % or less. , more preferably 30 atom % or more and 60 atom % or less, more preferably 40 atom % or more and 60 atom % or less, and even more preferably 50 atom % or more and 60 atom % or less.
  • In-Ga-Zn oxide is used for the semiconductor layer in which the channel of the transistor is formed, it is possible to use a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is equal to or lower than the atomic ratio of gallium.
  • the ratio of the number of gallium atoms to the number of atoms of the metal element contained is 20 atom % or more and 60 atom % or less, preferably 30 atom % or more and 60 atom % or less, A metal oxide having a content of more preferably 40 atom % or more and 60 atom % or less, more preferably 50 atom % or more and 60 atom % or less can be suitably used.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer in which the channel of the transistor is formed. Therefore, by changing the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a display device that has both excellent electrical characteristics and high reliability can be realized.
  • the semiconductor layer in which the channel of the transistor is formed may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition.
  • the two or more metal oxide layers included in the semiconductor layer in which the channel of the transistor is formed may have different compositions.
  • a first metal oxide layer having a composition of In:M:Zn 1:3:4 [atomic ratio] or a composition close to that, and In:M:Zn provided on the first metal oxide layer.
  • a stacked structure including a second metal oxide layer having an atomic ratio of 1:1:1 or a composition close to this can be suitably used.
  • the element M it is particularly preferable to use gallium or aluminum. For example, using a laminated structure of one selected from indium oxide, indium gallium oxide, and IGZO and one selected from IAZO, IAGZO, and ITZO (registered trademark), etc. Good too.
  • a metal oxide layer with crystallinity As the semiconductor layer in which the channel of the transistor is formed.
  • a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline structure, a nano-crystalline (NC) structure, or the like can be used.
  • CAAC C-Axis Aligned Crystal
  • NC nano-crystalline
  • the semiconductor layer in which the channel of the OS transistor is formed may have a stacked structure of two or more metal oxide layers with different crystallinities.
  • the layered structure includes a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer
  • the structure can include a region having higher crystallinity than the oxide layer.
  • the second metal oxide layer can have a region having lower crystallinity than the first metal oxide layer.
  • the two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition.
  • a stacked structure of two or more metal oxide layers having different crystallinity can be formed.
  • the two or more metal oxide layers included in the semiconductor layer may have different compositions.
  • the semiconductor device 10A shown in FIGS. 2A and 2B differs from the semiconductor device 10 shown in FIGS. 1A and 1B in that the transistor M1 is provided below the insulating layer 110.
  • an insulating layer 107 that functions as the gate insulating layer of the transistor M1 is provided on the conductive layer 112a that functions as either the source electrode or the drain electrode of the transistor M2.
  • a semiconductor layer 109 functioning as a semiconductor layer in which a channel of transistor M1 is formed is provided thereover.
  • the semiconductor layer 109 is provided so as to have a region covering the side surface of the conductive layer 112a with the insulating layer 107 interposed therebetween.
  • the conductive layer 116a functioning as one of the source electrode and the drain electrode of the transistor M1 is located on the side surface and top surface of one of the side ends of the semiconductor layer 109, and on the insulating layer 107.
  • a conductive layer 116b, which is provided in contact with the upper surface and functions as the other of the source electrode or the drain electrode of the transistor M1, is connected to the side surface and the upper surface of the other side end portion facing one of the side end portions of the semiconductor layer 109, and to the insulating layer 116b. It is provided in contact with the upper surface of layer 107.
  • the conductive layer 112a functions as the gate electrode of the transistor M1, and also functions as either the source electrode or the drain electrode of the transistor M2. That is, the semiconductor device 10A has a configuration in which the gate electrode of the transistor M1 and one of the source electrode or the drain electrode of the transistor M2 are electrically connected. With this configuration, effects similar to those obtained with the semiconductor device 10 can be obtained.
  • an insulating layer 110 is provided to cover the transistor M1. That is, a semiconductor layer 109 functioning as a semiconductor layer in which a channel of the transistor M1 is formed is covered with an insulating layer 110 and an insulating layer 107 functioning as a gate insulating layer of the transistor M1.
  • the same material as the insulating layer 106 that functions as the gate insulating layer of the transistor M2 can be used for the insulating layer 107.
  • an insulating material containing reduced hydrogen and oxygen can be used, respectively.
  • the semiconductor layer 109 is covered with the insulating layer 110 and the insulating layer 107, oxygen can be efficiently supplied from the insulating layer 110 and the insulating layer 107 to the semiconductor layer 109. can. Thereby, oxygen vacancies (V O ) in the semiconductor layer 109 and V OH generated by hydrogen entering the oxygen vacancies can be reduced, and the electrical characteristics and reliability of the transistor M1 can be improved.
  • the conductive layer 112b functioning as the other of the source electrode and the drain electrode of the transistor M2 is located above the transistor M1 with the insulating layer 110 interposed therebetween.
  • the conductive layer 112b can also be used as the second gate electrode of the transistor M1, for example.
  • the threshold voltage of the transistor M1 can be controlled more reliably than when the transistor M1 has one gate electrode (conductive layer 112a).
  • the conductive layer 112b serves both as the other of the source electrode and the drain electrode of the transistor M2, and as the second gate electrode of the transistor M1.
  • one end of the conductive layer 104 that functions as the gate electrode of the transistor M2 extends toward the transistor M1, and functions as a semiconductor layer in which the channel of the transistor M1 is formed.
  • the semiconductor layer 109 has a structure in which it is in contact with the side surface and top surface of one side end portion of the semiconductor layer 109 .
  • the conductive layer functioning as the other of the source electrode or the drain electrode of the transistor M2 and the conductive layer functioning as the gate electrode of the transistor M1 have an independent configuration. are doing.
  • the conductive layer 112c functions as a gate electrode of the transistor M1.
  • the conductive layer 104 functions as one of a source electrode or a drain electrode of the transistor M1, and also functions as a gate electrode of the transistor M2. That is, the semiconductor device 10B has a configuration in which one of the source electrode or the drain electrode of the transistor M1 and the gate electrode of the transistor M2 are electrically connected. It can also be said that the transistor M1 in the semiconductor device 10B corresponds to the transistor M2 of the semiconductor device 10A, and the transistor M2 in the semiconductor device 10B corresponds to the transistor M1 of the semiconductor device 10A. With this configuration, effects similar to those obtained with the semiconductor device 10 can be obtained.
  • the semiconductor device 10C shown in FIGS. 4A and 4B has a configuration of the gate electrode of the transistor M1, a configuration of one of the source electrode or the drain electrode of the transistor M1, a configuration of the other source electrode or the drain electrode of the transistor M2, and a configuration of the gate electrode of the transistor M1, a configuration of the other source electrode or the drain electrode of the transistor M2, and The configuration of the gate insulating layer of M1 is different from that of the semiconductor device 10 shown in FIGS. 1A and 1B.
  • the conductive layer 112b that functions as either the source electrode or the drain electrode of the transistor M1 extends to the transistor M2 side, and functions as a semiconductor layer in which the channel of the transistor M2 is formed.
  • the lower surface of the semiconductor layer 108 is in contact with the lower surface of the semiconductor layer 108.
  • an insulating layer 107 that functions as a gate insulating layer of the transistor M1 is provided separately from an insulating layer 106 that functions as a gate insulating layer of the transistor M2.
  • the insulating layer 106 that functions as a gate insulating layer of the transistor M2 extends toward the transistor M1 side, and includes a conductive layer 112b, a semiconductor layer 109 that functions as a semiconductor layer in which a channel of the transistor M1 is formed, and a source of the transistor M1. 112d of conductive layers which function as the other electrode or drain electrode.
  • the conductive layer 103 functions as a gate electrode of the transistor M1. Further, the conductive layer 112b functions as one of the source electrode and the drain electrode of the transistor M1, and also functions as the other source electrode and the drain electrode of the transistor M2. That is, in the semiconductor device 10C, one of the source electrode or the drain electrode of the transistor M1 and the other of the source electrode or the drain electrode of the transistor M2 are electrically connected. With this configuration, effects similar to those obtained with the semiconductor device 10 can be obtained.
  • the semiconductor layer 109 that functions as a semiconductor layer in which the channel of the transistor M1 is formed has an insulating layer 106 that functions as a gate insulating layer of the transistor M2, and an insulating layer that functions as a gate insulating layer of the transistor M1. 107. Therefore, by using an insulating material containing reduced hydrogen and oxygen for the insulating layer 106 and the insulating layer 107, oxygen is efficiently supplied from the insulating layer 106 and the insulating layer 107 to the semiconductor layer 109. be able to. Thereby, oxygen vacancies (V O ) in the semiconductor layer 109 and V OH generated by hydrogen entering the oxygen vacancies can be reduced, and the electrical characteristics and reliability of the transistor M1 can be improved.
  • V O oxygen vacancies
  • the semiconductor device 10D shown in FIGS. 5A and 5B differs from the semiconductor device 10 shown in FIG. 1 in that the transistor M1 is provided below the insulating layer 110. Further, the structure of the gate electrode of the transistor M1, the structure of one of the source electrodes or the drain electrode of the transistor M1, and the structure of the other source electrode or the drain electrode of the transistor M2 are the semiconductor devices shown in FIGS. 1A and 1B. It is different from 10.
  • a conductive layer 103 functioning as a gate electrode of the transistor M1 is provided on the substrate 102, and serves as a gate insulating layer of the transistor M1 so as to cover the conductive layer 103 and the substrate 102.
  • a functional insulating layer 107 is provided.
  • a semiconductor layer 109 that functions as a semiconductor layer in which a channel of the transistor M1 is formed is provided on the insulating layer 107 so as to cover the conductive layer 103.
  • the conductive layer 112a functioning as one of the source electrode and the drain electrode of the transistor M1 has a side surface and a top surface at one of the side ends of the semiconductor layer 109, a top surface of the insulating layer 107,
  • a conductive layer 112e which is provided in contact with the lower surface of the semiconductor layer 108 which functions as a semiconductor layer in which a channel of the transistor M2 is formed, and which functions as the other of the source electrode or the drain electrode of the transistor M1, It is provided in contact with the side surface and top surface of the other side end portion opposite to one of the side end portions, and the top surface of the insulating layer 107 .
  • the conductive layer 112a functions as one of the source electrode and the drain electrode of the transistor M1, and also functions as one of the source electrode and the drain electrode of the transistor M2. That is, the semiconductor device 10D has a configuration in which one of the source electrode or the drain electrode of the transistor M1 and one of the source electrode or the drain electrode of the transistor M2 are electrically connected. With this configuration, effects similar to those obtained with the semiconductor device 10 can be obtained.
  • an insulating layer 110 is provided to cover the transistor M1. That is, a semiconductor layer 109 functioning as a semiconductor layer in which a channel of the transistor M1 is formed is covered with an insulating layer 110 and an insulating layer 107 functioning as a gate insulating layer of the transistor M1.
  • the same material as the insulating layer 106 that functions as the gate insulating layer of the transistor M2 can be used for the insulating layer 107.
  • an insulating material containing reduced hydrogen and oxygen can be used, respectively.
  • the semiconductor layer 109 is covered with the insulating layer 110 and the insulating layer 107, oxygen can be efficiently supplied from the insulating layer 110 and the insulating layer 107 to the semiconductor layer 109. can. Thereby, oxygen vacancies (V O ) in the semiconductor layer 109 and V OH generated by hydrogen entering the oxygen vacancies can be reduced, and the electrical characteristics and reliability of the transistor M1 can be improved.
  • the conductive layer 112b functioning as the other of the source electrode and the drain electrode of the transistor M2 is located above the transistor M1 with the insulating layer 110 interposed therebetween.
  • the conductive layer 112b can also be used as the second gate electrode of the transistor M1, for example.
  • the threshold voltage of the transistor M1 can be controlled more reliably than when the transistor M1 has one gate electrode (conductive layer 103).
  • the conductive layer 112b serves both as the other of the source electrode and the drain electrode of the transistor M2, and as the second gate electrode of the transistor M1.
  • the semiconductor device 10E shown in FIGS. 6A and 6B has a configuration of the gate electrode of the transistor M1, a configuration of the gate insulating layer of the transistor M1, a configuration of one of the source electrode or the drain electrode of the transistor M1, and a source electrode of the transistor M2.
  • the configuration of one of the drain electrodes and the configuration of the other source or drain electrode of the transistor M2 are different from the semiconductor device 10 shown in FIGS. 1A and 1B.
  • a conductive layer 112a that functions as one of the source electrode or the drain electrode of the transistor M2 and a conductive layer 112g that functions as the gate electrode of the transistor M1 are provided on the substrate 102, respectively. It is set up independently.
  • An insulating layer 110 functioning as a gate insulating layer of the transistor M1 is provided on the conductive layer 112a and the conductive layer 112g, and a channel of the transistor M1 is formed on the insulating layer 110 so as to have a region overlapping with the conductive layer 112g.
  • a semiconductor layer 109 is provided which functions as a semiconductor layer to be formed.
  • the conductive layer 112b functioning as one of the source electrode and the drain electrode of the transistor M1 has a side surface and a top surface at one of the side ends of the semiconductor layer 109, a top surface of the insulating layer 110,
  • a conductive layer 112d which is provided in contact with the lower surface of the semiconductor layer 108 which functions as a semiconductor layer in which a channel of the transistor M2 is formed, and which functions as the other of the source electrode or the drain electrode of the transistor M1, is provided on the lower surface of the semiconductor layer 109. It is provided in contact with the side surface and top surface of the other side end portion opposite to one of the side end portions, and the top surface of the insulating layer 110 .
  • an insulating layer 106 functioning as a gate insulating layer of the transistor M2 extends toward the transistor M1 and covers the conductive layer 112b, the semiconductor layer 109, and the conductive layer 112d, respectively.
  • the conductive layer 112b functions as one of the source electrode or the drain electrode of the transistor M1, and also functions as the other source electrode or the drain electrode of the transistor M2. That is, in the semiconductor device 10E, one of the source electrode or the drain electrode of the transistor M1 and the other of the source electrode or the drain electrode of the transistor M2 are electrically connected. With this configuration, effects similar to those obtained with the semiconductor device 10 can be obtained. Furthermore, in the semiconductor device 10E, the insulating layer 110 has both the function of an interlayer film and the function of a gate insulating layer of the transistor M1. As described above, the insulating layer 110 that functions as an interlayer film is also a layer that determines the channel length of the transistor M2 depending on its thickness.
  • the thickness of the insulating layer 110 in the manufacturing process of the semiconductor device 10E it is possible to simultaneously control both the thickness of the gate insulating layer of the transistor M1 and the channel length of the transistor M2. , the total number of steps can be reduced.
  • the insulating layer 106 is provided to cover the transistor M1. Furthermore, the lower surface of the semiconductor layer 109 is in contact with the upper surface of the insulating layer 110. That is, the semiconductor layer 109 functioning as a semiconductor layer in which the channel of the transistor M1 is formed is covered with the insulating layer 106 and the insulating layer 110. As described above, an insulating material containing reduced hydrogen and oxygen can be used for the insulating layer 106 and the insulating layer 110, respectively. Therefore, since the semiconductor layer 109 is covered with the insulating layer 106 and the insulating layer 110, oxygen can be efficiently supplied from the insulating layer 106 and the insulating layer 110 to the semiconductor layer 109. can. Thereby, oxygen vacancies (V O ) in the semiconductor layer 109 and V OH generated by hydrogen entering the oxygen vacancies can be reduced, and the electrical characteristics and reliability of the transistor M1 can be improved.
  • V O oxygen vacancies
  • the semiconductor device 10F shown in FIG. 7A has the following points: the other of the source electrode or the drain electrode (conductive layer 112b) of the transistor M2 is in contact with the upper surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed; , differs from the semiconductor device 10 shown in FIGS. 1A and 1B in that the lower surface of the semiconductor layer and the upper surface of the insulating layer 110 are in contact with each other.
  • the other configurations are the same as those of the semiconductor device 10. With this configuration, effects similar to those obtained with the semiconductor device 10 can be obtained.
  • the semiconductor device 10G shown in FIG. 7B has the following points: the other of the source electrode or the drain electrode (conductive layer 112b) of the transistor M2 is in contact with the upper surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed; , differs from the semiconductor device 10A shown in FIGS. 2A and 2B in that the lower surface of the semiconductor layer and the upper surface of the insulating layer 110 are in contact with each other.
  • the other configurations are the same as those of the semiconductor device 10A. With this configuration, effects similar to those obtained with the semiconductor device 10A can be obtained.
  • the semiconductor device 10H shown in FIG. 7C has the following points: the other of the source electrode or the drain electrode (conductive layer 112b) of the transistor M2 is in contact with the upper surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed; This differs from the semiconductor device 10B shown in FIGS. 3A and 3B in that the lower surface of the semiconductor layer and the upper surface of the insulating layer 110 are in contact with each other.
  • the other configurations are the same as those of the semiconductor device 10B. With this configuration, effects similar to those obtained with the semiconductor device 10B can be obtained.
  • the semiconductor device 10I shown in FIG. 8A has the following points: the other of the source electrode or the drain electrode (conductive layer 112b) of the transistor M2 is in contact with the upper surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed; , differs from the semiconductor device 10C shown in FIGS. 4A and 4B in that the lower surface of the semiconductor layer is in contact with the upper surface of the gate insulating layer (insulating layer 107) of the transistor M1.
  • the other configurations are the same as those of the semiconductor device 10C. With this configuration, effects similar to those obtained with the semiconductor device 10C can be obtained.
  • the semiconductor device 10J shown in FIG. 8B has the following points: the other of the source electrode or the drain electrode (conductive layer 112b) of the transistor M2 is in contact with the upper surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed; , differs from the semiconductor device 10D shown in FIGS. 5A and 5B in that the lower surface of the semiconductor layer and the upper surface of the insulating layer 110 are in contact with each other.
  • the other configurations are the same as those of the semiconductor device 10D. With this configuration, effects similar to those obtained with the semiconductor device 10D can be obtained.
  • the semiconductor device 10K shown in FIG. 8C has the following points: the other of the source electrode or the drain electrode (conductive layer 112b) of the transistor M2 is in contact with the upper surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed; This differs from the semiconductor device 10E shown in FIGS. 6A and 6B in that the lower surface of the semiconductor layer and the upper surface of the insulating layer 110 are in contact with each other.
  • the other configurations are the same as those of the semiconductor device 10E. With this configuration, effects similar to those obtained with the semiconductor device 10E can be obtained.
  • Insulating layers, semiconductor layers, conductive layers for forming electrodes or wiring, etc. may be formed using a sputtering method, a CVD method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. I can do it.
  • the CVD method may be a plasma enhanced CVD (PECVD) method or a thermal CVD method.
  • PECVD plasma enhanced CVD
  • thermal CVD method a metal organic chemical vapor deposition (MOCVD) method may be used.
  • Insulating layers, semiconductor layers, conductive layers, etc. that make up semiconductor devices can be coated using spin coating, dip coating, spray coating, inkjet coating, dispensing, screen printing, offset printing, slit coating, roll coating, curtain coating, knife coating, etc. It may be formed by a method.
  • the PECVD method can obtain high-quality films at relatively low temperatures.
  • a film formation method that does not use plasma during film formation such as MOCVD, ALD, or thermal CVD
  • damage is less likely to occur on the surface on which the film is formed.
  • wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the semiconductor device.
  • a film forming method that does not use plasma such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Furthermore, since no plasma damage occurs during film formation, a film with fewer defects can be obtained.
  • the CVD method and the ALD method are film-forming methods in which a film is formed by a reaction on the surface of an object, unlike film-forming methods in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of source gases.
  • a film having an arbitrary composition can be formed by changing the flow rate ratio of source gases.
  • by changing the flow rate ratio of the raw material gas while forming the film it is possible to form a film in which the composition changes continuously.
  • a photolithography method or the like can be used when processing the layers (thin films) that constitute the semiconductor device.
  • an island-shaped layer may be formed by a film formation method using a shielding mask.
  • the layer may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • a resist mask is formed on the layer (thin film) to be processed, a part of the layer (thin film) is selectively removed using the resist mask as a mask, and then the resist mask is removed.
  • One method is to form a photosensitive layer and then perform exposure and development to process the layer into a desired shape.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • exposure may be performed using immersion exposure technology.
  • extreme ultraviolet (EUV) light or X-rays may be used.
  • an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or electron beams because extremely fine processing becomes possible. Note that when exposure is performed by scanning a beam such as an electron beam, a photomask is not necessary.
  • Dry etching, wet etching, sandblasting, etc. can be used to remove (etch) the layer (thin film). Further, a combination of these etching methods may be used.
  • a conductive layer 112a is formed on the substrate 102, and an insulating layer 110 is formed on the conductive layer 112a (see FIG. 9A).
  • an insulating substrate having an insulating surface is used as the substrate 102.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate.
  • a semiconductor substrate or a conductive substrate may be used as the substrate 102, if necessary.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • a semiconductor substrate having an insulator region inside the semiconductor substrate described above such as an SOI (Silicon On Insulator) substrate.
  • conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates.
  • substrates in which a conductor or a semiconductor is provided on an insulator substrate a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like.
  • these substrates provided with elements may be used.
  • Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, memory elements, and the like.
  • the conductive film that becomes the conductive layer 112a can be formed, for example, by a sputtering method using the above-mentioned material. Furthermore, after forming a resist mask (not shown) on the conductive film by a photolithography process, the conductive film is processed to form the conductive layer 112a, which will later become either the source electrode or the drain electrode of the transistor M2. Form. One or both of a wet etching method and a dry etching method may be used to process the conductive film.
  • the wiring is preferably formed of a material with low electrical resistance. Therefore, it is preferable that the conductive layer 112a be formed of a material with low electrical resistance. Alternatively, it is preferable that a conductive layer formed of a material having lower electrical resistance than the conductive layer 112a be stacked above or below the conductive layer 112a.
  • a conductive oxide material for the conductive layer 112a, and to use a metal, an alloy, or a nitride thereof that can be used for the above-mentioned conductive layer 104 etc. for the conductive layer laminated with the conductive layer 112a.
  • a conductive layer having lower electrical resistance than the conductive layer 112a in contact with the conductive layer 112a when the conductive layer 112a is used as a wiring, the wiring resistance can be reduced.
  • the insulating layer 110 can be formed by PECVD using the above-mentioned materials, for example.
  • the insulating layer 110 may have a laminated structure of two or more layers. In this case, it is preferable that the surfaces of each layer be formed successively in a vacuum without exposing them to the atmosphere. This makes it possible to suppress atmospheric impurities from adhering to the surface of each layer. Examples of the impurities include water and organic substances.
  • the substrate temperature during formation of the insulating layer 110 is preferably 180°C or more and 450°C or less, more preferably 200°C or more and 450°C or less, further preferably 250°C or more and 450°C or less, and even more preferably 300°C or more and 450°C or less. is preferable, more preferably 300°C or more and 400°C or less, and even more preferably 350°C or more and 400°C or less.
  • impurities for example, water and hydrogen
  • the insulating layer 110 is formed before the semiconductor layer 108 and the semiconductor layer 109, there is a need to be concerned that oxygen may be desorbed from the semiconductor layer 108 and the semiconductor layer 109 due to the heat applied during the formation of the insulating layer 110. There isn't.
  • Heat treatment may be performed after forming the insulating layer 110. By performing the heat treatment, water and hydrogen can be released from the surface and inside of the insulating layer 110.
  • the temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, further preferably 250°C or higher and 450°C or lower, and even more preferably 300°C or higher and 450°C or lower. Further, the temperature is preferably 300°C or more and 400°C or less, and even more preferably 350°C or more and 400°C or less.
  • the heat treatment can be performed in an atmosphere containing one or more of a rare gas, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) may be used as the atmosphere containing nitrogen or the atmosphere containing oxygen. Note that it is preferable that the content of hydrogen, water, etc. in the atmosphere is as low as possible.
  • the atmosphere it is preferable to use a high-purity gas having a dew point of -60°C or lower, preferably -100°C or lower.
  • a high-purity gas having a dew point of -60°C or lower, preferably -100°C or lower.
  • a process of supplying oxygen 160 to the insulating layer 110 is performed (see FIG. 9B).
  • the oxygen 160 include oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, and the like.
  • a method for supplying the oxygen 160 for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used.
  • a device also referred to as a plasma etching device or a plasma ashing device
  • plasma treatment may be performed in an atmosphere containing oxygen.
  • oxygen may be supplied to the insulating layer 110 by plasma treatment in an atmosphere containing an oxidizing gas such as dinitrogen monoxide (N 2 O).
  • an oxidizing gas such as dinitrogen monoxide (N 2 O).
  • a conductive film 112f that will later become a conductive layer 112b is formed on the insulating layer 110 (see FIG. 9C).
  • the conductive film 112f can be formed, for example, by a sputtering method using the above-mentioned material.
  • a resist mask is formed by a photolithography process (not shown) on the conductive film 112f that does not overlap with the position where the transistor M2 will be formed later, and then the conductive film 112f and the insulating layer 110 are processed respectively.
  • An opening 141 is formed that reaches layer 112a (see FIG. 10A).
  • a wet etching method and a dry etching method can be used.
  • a dry etching method can be suitably used to form the opening 141.
  • the semiconductor layer 108 which will later become the semiconductor layer 108, is placed so as to cover the inner wall of the opening 141 (part of the upper surface of the conductive layer 112a, the side surface of the insulating layer 110, and the side surface of the conductive film 112f) and the upper surface of the conductive film 112f.
  • a metal oxide film 108f is formed (see FIG. 10B).
  • the metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.
  • the metal oxide film 108f is preferably a dense film with as few defects as possible. Further, it is preferable that the metal oxide film 108f is a highly pure film in which impurities containing hydrogen elements are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.
  • oxygen gas when forming the metal oxide film 108f.
  • oxygen gas when forming the metal oxide film 108f oxygen can be suitably supplied into the insulating layer 110 from the inner wall of the opening 141.
  • oxygen vacancies (V O ) in the semiconductor layer 108 and V generated by hydrogen entering the oxygen vacancies are removed. OH can be reduced.
  • oxygen gas and an inert gas for example, helium gas, argon gas, xenon gas, etc.
  • an inert gas for example, helium gas, argon gas, xenon gas, etc.
  • oxygen gas and an inert gas for example, helium gas, argon gas, xenon gas, etc.
  • oxygen flow rate ratio oxygen flow rate ratio
  • the lower the oxygen flow rate ratio the lower the crystallinity of the metal oxide film 108f may become. Thereby, it may be possible to realize a transistor M2 with a high on-state current.
  • the substrate temperature during formation of the metal oxide film 108f may be at least room temperature and at most 250°C, preferably at least room temperature and at most 200°C, more preferably at least room temperature and at most 140°C. For example, it is preferable to set the substrate temperature at room temperature or higher and 140° C. or lower because productivity increases.
  • the semiconductor layer 108 has a laminated structure, after the first metal oxide film is formed, the next metal oxide film is formed continuously without exposing the surface to the atmosphere. is preferred.
  • Heat treatment may be performed after forming the metal oxide film 108f.
  • water and hydrogen can be desorbed from the surface and inside of the metal oxide film 108f.
  • oxygen can be supplied from the insulating layer 110 to the metal oxide film 108f.
  • the heat treatment may improve the film quality of the metal oxide film 108f (for example, reduce defects, improve crystallinity, etc.). Note that the heat treatment conditions that can be used after forming the insulating layer 110 described above can be applied as the conditions for the heat treatment.
  • the heat treatment does not need to be performed if unnecessary. Further, the heat treatment may not be performed here, but may also serve as the heat treatment performed in a later step. Further, in some cases, the heat treatment can also be used as a treatment at a high temperature in a later process (for example, a film forming process).
  • the metal oxide film 108f is processed into an island shape so as to have a region overlapping with the inner wall of the opening 141, and the semiconductor layer 108 is formed (see FIG. 10C).
  • a wet etching method and a dry etching method can be used.
  • a wet etching method can be suitably used to form the semiconductor layer 108.
  • a resist mask is formed by a photolithography process (not shown) on the conductive film 112f that will overlap with the position that will later become the gate electrode of the transistor M1, and then the conductive layer 112b is formed by processing the conductive film.
  • a wet etching method and a dry etching method can be used to form the conductive layer 112b.
  • a wet etching method can be suitably used to form the conductive layer 112b.
  • the insulating layer 106 which will later become the gate insulating layer of the transistor M1 and the transistor M2, is formed on the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110 (see FIG. 11B).
  • the insulating layer 106 can be formed, for example, using the above-mentioned materials by PECVD.
  • the insulating layer 106 is preferably made of an insulating material containing reduced hydrogen and oxygen. This makes it difficult for the semiconductor layer 108 and the semiconductor layer 109, each of which has a region in contact with the insulating layer 106, to become n-type. Further, since oxygen can be efficiently supplied from the insulating layer 106 to the semiconductor layer 108 and the semiconductor layer 109, oxygen vacancies (V O ) in the semiconductor layer 108 and the semiconductor layer 109 can be reduced.
  • the semiconductor layer 108 is a layer that functions as a semiconductor layer in which a channel of the transistor M2 will be formed later
  • the semiconductor layer 109 is a layer that functions as a semiconductor layer in which a channel of the transistor M1 will be formed later. Therefore, by using the above-described material for the insulating layer 106, it is possible to realize the transistor M2 and the transistor M1, which exhibit good electrical characteristics and are highly reliable.
  • the insulating layer 106 By increasing the temperature during formation of the insulating layer 106 that functions as the gate insulating layer of the transistor M1 and the transistor M2, the insulating layer can have fewer defects. However, if the temperature during formation of the insulating layer 106 is high, oxygen is desorbed from the semiconductor layer 108, and oxygen vacancies (V O ) in the semiconductor layer 108 and V O generated by hydrogen entering the oxygen vacancies are generated. H may increase.
  • the substrate temperature during formation of the insulating layer 106 is preferably 180°C or more and 450°C or less, more preferably 200°C or more and 450°C or less, further preferably 250°C or more and 450°C or less, and even more preferably 300°C or more and 450°C or less.
  • the substrate temperature during the formation of the insulating layer 106 is preferable, and more preferably 300°C or more and 400°C or less.
  • the surface of the semiconductor layer 108 may be subjected to plasma treatment.
  • plasma treatment Through the plasma treatment, impurities such as water adsorbed on the surface of the semiconductor layer 108 can be reduced. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor M2 can be realized. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the formation of the insulating layer 106.
  • Plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, dinitrogen monoxide, argon, or the like. Further, it is preferable that the plasma treatment and the formation of the insulating layer 106 are performed continuously without exposure to the atmosphere.
  • a metal oxide film 109f that will later become the semiconductor layer 109 is formed on the insulating layer 106 (see FIG. 11C).
  • the metal oxide film 109f is preferably formed by a sputtering method using a metal oxide target.
  • the conditions for forming the metal oxide film 109f and the conditions for the heat treatment performed after forming the metal oxide film 109f are as described above.
  • the conditions of the heat treatment to be performed can be referred to.
  • the metal oxide film 109f is processed into an island shape, and the semiconductor layer 109 is formed so as to have a region overlapping with the conductive layer 112b (see FIG. 12A).
  • a wet etching method and a dry etching method can be used for forming the semiconductor layer 109.
  • a wet etching method can be suitably used to form the semiconductor layer 109.
  • a portion of the insulating layer 106 in a region that does not overlap with the semiconductor layer 109 may be etched and the film thickness may become thinner. Note that in etching the metal oxide film 109f, by using a material with a high selectivity for the insulating layer 106, it is possible to prevent the thickness of the insulating layer 106 from becoming thin.
  • a conductive film 116f which will later become the conductive layer 104, the conductive layer 116a, and the conductive layer 116b, is formed on the semiconductor layer 109 and the insulating layer 106 (see FIG. 12B).
  • the conductive film 116f can be formed, for example, by a sputtering method using the above-mentioned material.
  • a resist mask is formed on the conductive film 116f by a photolithography process (not shown).
  • the resist mask has at least a region that overlaps with the opening 141, a region that covers one of the side edges of the semiconductor layer 109 in a cross-sectional view, and a region that faces one of the side edges of the semiconductor layer 109 in a cross-sectional view. Provided in each area covering the other side end.
  • a conductive layer 104 having a region overlapping with the opening 141, a conductive layer 116a covering one of the side edges of the semiconductor layer 109 in a cross-sectional view, and a conductive layer 116a that covers one side end of the semiconductor layer 109 in a cross-sectional view
  • a conductive layer 116b covering one side end portion and the other opposing side end portion of the semiconductor layer 109 is formed in the step (see FIG. 12C).
  • the conductive layer 104 is a conductive layer that becomes the gate electrode of the transistor M2.
  • the conductive layer 116a is a conductive layer that serves as either a source electrode or a drain electrode of the transistor M1.
  • the conductive layer 116b is a conductive layer that serves as the other of the source electrode and the drain electrode of the transistor M1.
  • One or both of a wet etching method and a dry etching method can be used to form the conductive layer 104, the conductive layer 116a, and the conductive layer 116b.
  • a wet etching method can be suitably used to form the conductive layer 104, the conductive layer 116a, and the conductive layer 116b.
  • the thickness of the insulating layer 106 in a region that does not overlap with the conductive layer 116a, the conductive layer 116b, and the semiconductor layer 109 may become thinner. Further, the thickness of the semiconductor layer 109 in a region that does not overlap with the conductive layer 116a and the conductive layer 116b may be thinner than the thickness of the semiconductor layer 109 in a region that overlaps with the conductive layer 116a and the conductive layer 116b.
  • a cleaning process may be performed after forming the conductive layer 104, the conductive layer 116a, and the conductive layer 116b.
  • As the cleaning process wet cleaning using a cleaning liquid or the like, or cleaning by plasma processing using plasma can be used. The above-mentioned cleaning may be performed in combination as appropriate.
  • impurities for example, metals and organic substances attached to the surfaces of the insulating layer 106 and the semiconductor layer 109 during the formation of the conductive layer 104, the conductive layer 116a, and the conductive layer 116b can be removed. I can do it.
  • a cleaning liquid containing one or more of phosphoric acid, oxalic acid, and hydrochloric acid can be used.
  • a cleaning solution containing phosphoric acid can be suitably used for wet cleaning.
  • the concentration of the cleaning solution is preferably determined in consideration of the etching rate for the insulating layer 106 and the semiconductor layer 109.
  • a gas containing one or more of oxygen, ozone, nitrogen, dinitrogen monoxide (N 2 O), and argon can be used for the plasma treatment. It is preferable to use a gas containing oxygen for the plasma treatment.
  • a gas containing dinitrogen monoxide (N 2 O) organic substances on the surfaces of the insulating layer 106 and the semiconductor layer 109 can be suitably removed.
  • a PECVD device or an etching device can be used for the plasma treatment.
  • the transistor M1 and the transistor M2 are respectively formed.
  • the semiconductor device 10 (FIGS. 1A and 1B) which is one embodiment of the present invention and includes the transistor M1 and the transistor M2 can be manufactured.
  • the semiconductor device of one embodiment of the present invention can be applied to, for example, a pixel circuit of a display device.
  • a pixel circuit of a display device A configuration example of a pixel circuit to which a semiconductor device of one embodiment of the present invention can be applied will be described below.
  • FIGS. 14A to 14D illustrate configuration examples of a pixel 230 of a display device to which the semiconductor device of one embodiment of the present invention can be applied.
  • the pixel 230 includes a pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, or pixel circuit 51D) and a light emitting device 61.
  • a "light-emitting device” described in this embodiment mode and the like refers to a self-emitting display device (also referred to as a display element) such as an organic EL element (also referred to as an OLED (Organic LED)).
  • the light emitting element electrically connected to the pixel circuit can be a self-emitting type light emitting element such as an LED, a micro LED, a QLED (Quantum-dot LED), or a semiconductor laser.
  • the pixel circuit 51A shown in FIG. 13A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitor 53.
  • One of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL.
  • the other of the source and drain of transistor 52A is electrically connected to the gate of transistor 52B.
  • One of the source and drain of the transistor 52B and one terminal of the capacitor 53 are electrically connected to the wiring ANO.
  • the other terminal of capacitor 53 is electrically connected to the gate of transistor 52B.
  • the other of the source and drain of transistor 52B is electrically connected to the anode of light emitting device 61.
  • the cathode of the light emitting device 61 is electrically connected to the wiring VCOM.
  • the wiring GL corresponds to the conductive layer 104 of the semiconductor device 10
  • the wiring SL corresponds to the conductive layer 112a of the semiconductor device 10.
  • the wiring VCOM is a wiring that provides a potential for supplying current to the light emitting device 61.
  • the transistor 52A has a function of controlling the conducting state or non-conducting state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.
  • the transistor 52B has a function of controlling the amount of current flowing to the light emitting device 61.
  • Capacitor 53 has a function of holding the gate potential of transistor 52B. The intensity of the light emitted by the light emitting device 61 is controlled according to the image signal supplied to the gate of the transistor 52B.
  • an n-channel transistor is used as the transistor 52A, and a p-channel transistor is used as the transistor 52B.
  • an n-channel transistor may be used as the transistor 52B.
  • one terminal of the capacitor 53 may be electrically connected to the other of the source or drain of the transistor 52B.
  • the semiconductor device of one embodiment of the present invention can be used for the pixel circuit 51A shown in FIG. 13B.
  • the transistor M2 included in each semiconductor device shown in FIGS. 1A to 2B and FIGS. 7A and 7B can be used as the transistor 52A included in the pixel circuit 51A, and the transistor M2 included in each semiconductor device shown in FIGS.
  • the transistor M1 included in each semiconductor device shown in FIGS. 1A to 2B and FIGS. 7A and 7B can be used.
  • the transistor M1 included in each of the semiconductor devices shown in FIGS. 3A, 3B, and 7C can be used as the transistor 52A included in the pixel circuit 51A, and the transistor M1 included in each of the semiconductor devices shown in FIGS.
  • the transistor M2 included in each semiconductor device shown in FIG. 3B and FIG. 7C can be used.
  • the pixel circuit 51B shown in FIG. 13C is a 3Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53.
  • a pixel circuit 51B shown in FIG. 13C has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in FIG. 13A.
  • a pixel circuit 51B shown in FIG. 13D has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in FIG. 13B.
  • one of the source or drain of the transistor 52C is electrically connected to the other of the source or drain of the transistor 52B.
  • the other of the source and drain of the transistor 52C is electrically connected to the wiring V0.
  • a reference potential is supplied to the wiring V0.
  • the transistor 52C has a function of controlling the conducting state or non-conducting state between the other of the source or drain of the transistor 52B and the wiring V0 based on the potential of the wiring GL.
  • the wiring V0 is a wiring for applying a reference potential.
  • variations in the gate-source voltage of the transistor 52B can be suppressed by the reference potential of the wiring V0 applied via the transistor 52C.
  • the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light emitting device 61 to the outside.
  • the current output to the wiring V0 is converted into a voltage by a source follower circuit or the like, and can be output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.
  • the semiconductor device of one embodiment of the present invention can be used for the pixel circuit 51B shown in FIG. 13D.
  • the transistor M2 included in each of the semiconductor devices shown in FIGS. 1A to 2B and FIGS. 7A and 7B can be used as the transistor 52A included in the pixel circuit 51B, and The transistor M1 included in each semiconductor device shown in FIGS. 1A to 2B and FIGS. 7A and 7B can be used.
  • the transistor M1 included in each of the semiconductor devices shown in FIGS. 3A, 3B, and 7C can be used as the transistor 52A included in the pixel circuit 51B, and the transistor M1 included in each semiconductor device shown in FIGS.
  • the transistor M2 included in each semiconductor device shown in FIG. 3B and FIG. 7C can be used.
  • the transistor M1 (transistor M2) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52B included in the pixel circuit 51B, and the pixel circuit 51B
  • the transistor M2 (transistor M1) included in each of the semiconductor devices shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52C.
  • a pixel circuit 51C shown in FIG. 14A has a configuration in which a transistor 52D is added to the pixel circuit 51B shown in FIG. 13C.
  • the pixel circuit 51C shown in FIG. 14A is a 4Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, and a capacitor 53.
  • One of the source and the drain of the transistor 52D is electrically connected to the wiring ANO, and the other is electrically connected to the other of the source and the drain of the transistor 52A, the other terminal of the capacitor 53, and the gate of the transistor 52B. .
  • a wiring GL1, a wiring GL2, and a wiring GL3 are electrically connected to the pixel circuit 51C.
  • the wiring GL1, the wiring GL2, and the wiring GL3 may be collectively referred to as the wiring GL. Therefore, the number of wiring GL is not limited to one, but may be multiple.
  • the wiring GL1 is electrically connected to the gate of the transistor 52A
  • the wiring GL2 is electrically connected to the gate of the transistor 52C
  • the wiring GL3 is electrically connected to the gate of the transistor 52D.
  • the source and gate of the transistor 52B are at the same potential, and the transistor 52B can be turned off. Thereby, the current flowing through the light emitting device 61 can be forcibly interrupted.
  • Such a pixel circuit is suitable when using a display method in which display periods and light-off periods are provided alternately.
  • the transistor 52C may be turned on at the same time as the transistor 52D is turned on.
  • the semiconductor device of one embodiment of the present invention can be used for the pixel circuit 51C shown in FIG. 14A.
  • the transistor M1 (transistor M2) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52A included in the pixel circuit 51C.
  • the transistor M2 (transistor M1) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used.
  • n-channel transistors are used for the transistor 52A, transistor 52C, and transistor 52D, and a p-channel transistor is used for the transistor 52B.
  • an n-channel transistor may be used as the transistor 52B.
  • one terminal of the capacitor 53 may be electrically connected to the other of the source or drain of the transistor 52B.
  • either the source or the drain of the transistor 52D may be electrically connected to the wiring V0.
  • the semiconductor device of one embodiment of the present invention can be used for the pixel circuit 51C shown in FIG. 14B.
  • the transistor M1 (transistor M2) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52A included in the pixel circuit 51C.
  • 52D the transistor M2 (transistor M1) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used.
  • the transistor M1 (transistor M2) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52B included in the pixel circuit 51C, and the pixel circuit 51C
  • the transistor M2 (transistor M1) included in each of the semiconductor devices shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52C.
  • the transistor M2 included in each of the semiconductor devices shown in FIGS. 1A to 2B and FIGS. 7A and 7B can be used as the transistor 52A included in the pixel circuit 51C, and the transistor M2 included in each semiconductor device shown in FIGS. , FIGS. 1A to 2B, and the transistor M1 included in each semiconductor device shown in FIGS. 7A and 7B.
  • the transistor M1 included in each of the semiconductor devices shown in FIGS. 3A, 3B, and 7C can be used as the transistor 52A included in the pixel circuit 51C, and the transistor M1 included in each semiconductor device shown in FIGS.
  • the transistor M2 included in each semiconductor device shown in FIG. 3B and FIG. 7C can be used.
  • the transistor M2 included in each semiconductor device shown in FIGS. 1A to 2B and FIGS. 7A and 7B can be used as the transistor 52D included in the pixel circuit 51C, and the transistor M2 included in each semiconductor device shown in FIGS. , FIGS. 1A to 2B, and the transistor M1 included in each semiconductor device shown in FIGS. 7A and 7B.
  • the transistor M1 included in each of the semiconductor devices shown in FIGS. 3A, 3B, and 7C can be used as the transistor 52D included in the pixel circuit 51C, and the transistor M1 included in each semiconductor device shown in FIGS.
  • the transistor M2 included in each semiconductor device shown in FIG. 3B and FIG. 7C can be used.
  • a pixel circuit 51D shown in FIG. 14C has a configuration in which a capacitor 53A is added to the pixel circuit 51C shown in FIG. 14A.
  • one terminal of the capacitor 53A is electrically connected to the other of the source or drain of the transistor 52B, and the other terminal is electrically connected to the gate of the transistor 52B.
  • the semiconductor device of one embodiment of the present invention can be used for the pixel circuit 51D shown in FIG. 14C.
  • the transistor M1 (transistor M2) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52A included in the pixel circuit 51D.
  • the transistor M2 (transistor M1) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used.
  • a pixel circuit 51D shown in FIG. 14D has a configuration in which a capacitor 53A is added to the pixel circuit 51C shown in FIG. 14B.
  • one terminal of the capacitor 53A is electrically connected to the wiring ANO, and the other terminal is electrically connected to the gate of the transistor 52B.
  • the capacitor 53 and the capacitor 53A each function as a holding capacitor.
  • the pixel circuit 51D shown in FIGS. 14C and 14D is a 4Tr2C type pixel circuit.
  • the semiconductor device of one embodiment of the present invention can be used for the pixel circuit 51D shown in FIG. 14D.
  • the transistor M1 (transistor M2) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52A included in the pixel circuit 51D.
  • the transistor M2 (transistor M1) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used.
  • the transistor M1 (transistor M2) included in each semiconductor device shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52B included in the pixel circuit 51D, and the pixel circuit 51D
  • the transistor M2 (transistor M1) included in each of the semiconductor devices shown in FIGS. 4A to 6B and FIGS. 8A to 8C can be used as the transistor 52C.
  • the transistor M2 included in each semiconductor device shown in FIGS. 1A to 2B and FIGS. 7A and 7B can be used as the transistor 52A included in the pixel circuit 51D, and the transistor M2 included in each semiconductor device shown in FIGS. , FIGS. 1A to 2B, and the transistor M1 included in each semiconductor device shown in FIGS. 7A and 7B.
  • the transistor M1 included in each of the semiconductor devices shown in FIGS. 3A, 3B, and 7C can be used as the transistor 52A included in the pixel circuit 51D, and the transistor M1 included in each semiconductor device shown in FIGS.
  • the transistor M2 included in each semiconductor device shown in FIG. 3B and FIG. 7C can be used.
  • the transistor M2 included in each semiconductor device shown in FIGS. 1A to 2B and FIGS. 7A and 7B can be used as the transistor 52D included in the pixel circuit 51D, and the transistor M2 included in each semiconductor device shown in FIGS. , FIGS. 1A to 2B, and the transistor M1 included in each semiconductor device shown in FIGS. 7A and 7B.
  • the transistor M1 included in each of the semiconductor devices shown in FIGS. 3A, 3B, and 7C can be used as the transistor 52D included in the pixel circuit 51D, and the transistor M1 included in each semiconductor device shown in FIGS.
  • the transistor M2 included in each semiconductor device shown in FIG. 3B and FIG. 7C can be used.
  • Each of the transistors 52A, 52B, 52C, and 52D preferably includes a back gate electrode (second gate electrode), and in this case, the back gate electrode has a configuration in which the same signal as the gate electrode is given; A configuration can be adopted in which a signal different from that of the gate electrode is given to the back gate electrode.
  • P-channel transistors may be used not only as the transistor 52B but also as the transistor 52A, the transistor 52C, and the transistor 52D.
  • the semiconductor device of one embodiment of the present invention can be applied to a pixel circuit of a display device.
  • transistors are arranged at high density and can be highly integrated; therefore, a display device in which the semiconductor device is applied to a pixel circuit can achieve high definition.
  • the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in display units of information terminals (wearable devices) such as wristwatch-type and bracelet-type devices, VR devices such as head-mounted displays (HMD), and glasses-type display devices. It can be used in the display section of wearable devices that can be worn on the head, such as AR devices.
  • wearable devices such as wristwatch-type and bracelet-type devices
  • VR devices such as head-mounted displays (HMD)
  • HMD head-mounted displays
  • AR devices such as AR devices.
  • the display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used, for example, on relatively large screens such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines.
  • the present invention can be used in display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.
  • FIG. 15 shows a perspective view of the display device 200A.
  • the display device 200A has a configuration in which a substrate 152 and a substrate 151 are bonded together.
  • the substrate 152 is clearly indicated by a broken line.
  • the display device 200A includes a display section 162, a connection section 140, a circuit 164, wiring 165, and the like.
  • FIG. 15 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 200A. Therefore, the configuration shown in FIG. 15 can also be called a display module that includes the display device 200A, an IC (integrated circuit), and an FPC.
  • a plurality of pixels are arranged in a matrix. Each pixel has multiple subpixels.
  • Each subpixel has a display device.
  • display devices include liquid crystal devices (also referred to as liquid crystal elements) and light emitting devices.
  • OLED or QLED as the light emitting device.
  • light-emitting substances included in a light-emitting device include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF)). materials), and inorganic compounds (quantum dot materials, etc.).
  • an LED such as a micro LED can also be used as the light emitting device.
  • the emitted light color of the light emitting device can be infrared, red, green, blue, cyan, magenta, yellow, white, or the like. Further, color purity can be increased by providing a light emitting device with a microcavity structure.
  • a display device has light-emitting devices made separately for each emission color, and is capable of full-color display.
  • the display device of one embodiment of the present invention is a top emission type display device that emits light in the opposite direction to the substrate on which the light-emitting device is formed, and a display device that emits light in the opposite direction to the substrate on which the light-emitting device is formed. It may be either a bottom emission type (bottom emission type) or a double emission type (dual emission type) that emits light on both sides.
  • the connecting section 140 is provided outside the display section 162.
  • the connecting portion 140 can be provided along one side or a plurality of sides of the display portion 162, for example.
  • the planar shape of the connecting portion 140 is not particularly limited, and may be a band shape, an L shape, a U shape, a frame shape, or the like.
  • the connecting portion 140 may be singular or plural.
  • FIG. 15 shows an example in which the connection portions 140 are provided so as to surround the four sides of the display portion 162.
  • the connection part 140 the common electrode of the light emitting device and the conductive layer are electrically connected, and a potential can be supplied to the common electrode.
  • the connecting portion 140 can also be called a cathode contact portion.
  • a scanning line drive circuit can be used.
  • the wiring 165 has a function of supplying signals and power to the display section 162 and the circuit 164.
  • the signal and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.
  • FIG. 15 shows an example in which the IC 173 is provided on the substrate 151 using a COG (Chip On Glass) method, a COF (Chip On Film) method, or the like.
  • a COG Chip On Glass
  • COF Chip On Film
  • an IC having a scanning line drive circuit or a signal line drive circuit can be applied to the IC 173.
  • the display device 200A and the display module may have a configuration in which no IC is provided.
  • the IC may be mounted on the FPC using a COF method or the like.
  • An example is shown in FIG.
  • a display device 200A shown in FIG. 16 includes a transistor 201, a transistor 205R (not shown), a transistor 205G, a transistor 205B, a transistor 206R (not shown), a transistor 206G, and a transistor 206B (not shown) between a substrate 151 and a substrate 152. ), a light emitting device 130R (not shown), a light emitting device 130G, a light emitting device 130B, etc.
  • a transistor 201, a transistor 205R, a transistor 205G, a transistor 205B, a transistor 206R, a transistor 206G, and a transistor 206B are provided on the substrate 151.
  • An insulating layer 218 and an insulating layer 235 over the insulating layer 218 are provided so as to cover the transistor 201, the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B.
  • a light emitting device 130R, a light emitting device 130G, and a light emitting device 130B are provided on the insulating layer 235.
  • the alphabet that distinguishes them may be omitted and the light-emitting device 130 may be written.
  • constituent elements such as the transistor 205R, the transistor 205G, and the transistor 205B, which are distinguished by alphabets, when describing common items, the symbols omitting the alphabet may be used in the description.
  • the transistor 201, the transistor 205R, the transistor 205G, and the transistor 205B can be manufactured using the same material and the same process. Further, the transistor 206R, the transistor 206G, and the transistor 206B can be manufactured using the same material and using the same process. Note that although FIG. 16 shows an example in which the transistor 201 has the same structure as the transistor 205 (the transistor 205R, the transistor 205G, and the transistor 205B), the present invention is not limited to this.
  • the transistor 201 may have the same structure as the transistor 206 (transistor 206R, transistor 206G, and transistor 206B).
  • FIG. 16 shows a structure in which the transistor M2 in the semiconductor device 10 shown in FIGS. 1A and 1B is applied to the transistor 201, the transistor 205R, the transistor 205G, and the transistor 205B. Further, a structure is shown in which the transistor M1 in the semiconductor device 10 shown in FIGS. 1A and 1B is applied to the transistor 206R, the transistor 206G, and the transistor 206B.
  • the transistor 205R and the transistor 206R constitute a semiconductor device in a subpixel that emits red (R) light
  • the transistor 205G and the transistor 206G constitute a semiconductor device in a subpixel that emits green (G) light
  • the transistor 205B and the transistor 206B form a semiconductor device in a subpixel that emits blue (B) light.
  • FIG. 16 shows an example in which the insulating layer 110 has a three-layer stacked structure of an insulating layer 110c, an insulating layer 110a, and an insulating layer 110b.
  • All of the transistors included in the display section 162 may be OS transistors, all of the transistors included in the display section 162 may be Si transistors, or some of the transistors included in the display section 162 may be OS transistors and the rest may be Si transistors. good.
  • a transistor using LTPS hereinafter referred to as an LTPS transistor may be used as the Si transistor.
  • an LTPS transistor for example, by using both an LTPS transistor and an OS transistor in the display section 162, a display device with low power consumption and high driving ability can be realized. Furthermore, a configuration in which an LTPS transistor and an OS transistor are combined is sometimes referred to as an LTPO.
  • an OS transistor as a transistor that functions as a switch for controlling conduction and non-conduction between wirings, and to use an LTPS transistor as a transistor that controls current.
  • one of the transistors (transistor 206) included in the display portion 162 functions as a transistor for controlling the current flowing to the light emitting device, and can also be called a drive transistor.
  • One of the source and drain of the drive transistor is electrically connected to a pixel electrode of the light emitting device. It is preferable to use an LTPS transistor as the drive transistor. Thereby, it is possible to increase the current flowing to the light emitting device in the pixel circuit.
  • the other transistor (transistor 205) included in the display portion 162 functions as a switch for controlling selection and non-selection of pixels, and can also be called a selection transistor.
  • the gate of the selection transistor is electrically connected to the gate line, and one of the source and drain is electrically connected to the source line (signal line). It is preferable to use an OS transistor as the selection transistor. This allows the pixel gradation to be maintained even if the frame frequency is significantly reduced (for example, 1 fps or less), so power consumption can be reduced by stopping the driver when displaying still images. can.
  • the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B each have a pair of electrodes and a layer sandwiched between the pair of electrodes.
  • the layer has at least a light emitting layer.
  • one electrode functions as an anode and the other electrode functions as a cathode.
  • the pixel electrode functions as an anode and the common electrode functions as a cathode may be described as an example.
  • the light emitting device 130R includes a pixel electrode 111R on the insulating layer 235, an island-shaped layer 113R (not shown) on the pixel electrode 111R, and a common electrode 115 on the island-shaped layer 113R.
  • the light emitting device 130G includes a pixel electrode 111G on the insulating layer 235, an island-shaped layer 113G on the pixel electrode 111G, and a common electrode 115 on the island-shaped layer 113G.
  • the light emitting device 130B includes a pixel electrode 111B on the insulating layer 235, an island-shaped layer 113B on the pixel electrode 111B, and a common electrode 115 on the island-shaped layer 113B.
  • the layer 113R, the layer 113G, or the layer 113B each has at least a light emitting layer.
  • the light emitting device 130R may be configured to emit red (R) light
  • the light emitting device 130G may be configured to emit green (G) light
  • the light emitting device 130B may be configured to emit blue (B) light.
  • the layer 113R has a light emitting layer that emits red light
  • the layer 113G has a light emitting layer that emits green light
  • the layer 113B has a light emitting layer that emits blue light.
  • layer 113R has a luminescent material that emits red light
  • layer 113G has a luminescent material that emits green light
  • layer 113B has a luminescent material that emits blue light.
  • Layer 113R, layer 113G, or layer 113B may each have one or more functional layers.
  • the functional layer include a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).
  • the layers 113R, 113G, and 113B are all shown to have the same thickness in FIG. 16, the present invention is not limited to this.
  • the layer 113R, layer 113G, and layer 113B may have different thicknesses.
  • the layer 113R, the layer 113G, and the layer 113B can each be formed, for example, by a vacuum evaporation method using a fine metal mask.
  • the layers 113R, 113G, and 113B can be formed in a wider area than the opening of the fine metal mask.
  • the end portions of the layer 113R, the layer 113G, and the layer 113B each have a tapered shape.
  • a sputtering method using a fine metal mask or an inkjet method may be used to form the layers 113R, 113G, and 113B.
  • the light emitting device of this embodiment may have a single structure (a structure having only one light emitting unit) or a tandem structure (a structure having a plurality of light emitting units).
  • the light emitting unit has at least one light emitting layer.
  • the layer 113R has a structure that has a plurality of light emitting units that emit red light
  • the layer 113G has a structure that has a plurality of light emitting units that emit green light
  • the layer 113B has a structure that has a plurality of light emitting units that emit green light. It is preferable that the structure has a plurality of light emitting units that emit light of . It is preferable to provide a charge generation layer (also referred to as an intermediate layer) between each light emitting unit.
  • the common electrode 115 is shared by the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B.
  • the common electrode 115 is electrically connected to the conductive layer 123 provided in the connection part 140. It is preferable to use a conductive layer formed of the same material and in the same process as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B for the conductive layer 123. It is preferable that the layer 113R, the layer 113G, and the layer 113B not be formed over the conductive layer 123.
  • a common electrode 115 is provided on the conductive layer 123.
  • a sputtering method or a vacuum evaporation method can be used.
  • a film formed by vapor deposition and a film formed by sputtering may be stacked.
  • a mask also referred to as an area mask or a rough metal mask, to be distinguished from a fine metal mask for defining a region where the common electrode 115 is to be formed may be used.
  • the insulating layer 218 provided over the transistor 205R, transistor 205G, transistor 205B, transistor 206R, transistor 206G, and transistor 206B functions as a protective layer for the transistor 205R, transistor 205G, transistor 205B, transistor 206R, transistor 206G, and transistor 206B. do.
  • the insulating layer 218 it is preferable to use a material in which impurities are difficult to diffuse.
  • the insulating layer 218 functions as a blocking film that suppresses impurities from diffusing into the transistor from the outside. Examples of impurities include water and hydrogen.
  • the insulating layer 218 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material.
  • An inorganic material can be suitably used for the insulating layer 218.
  • the inorganic material one or more of oxides, oxynitrides, nitrided oxides, and nitrides can be used. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used.
  • silicon nitride oxide releases little impurity (e.g., water and hydrogen) from itself, and can function as a blocking film that suppresses impurities from diffusing into the transistor from above the transistor. It can be suitably used as the layer 218.
  • the organic material for example, one or more of acrylic resin and polyimide resin can be used.
  • a photosensitive material may be used as the organic material.
  • two or more of the above-mentioned insulating films may be stacked and used.
  • the insulating layer 218 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.
  • the substrate temperature during formation of the insulating film is preferably 180°C or more and 450°C or less, more preferably 200°C or more and 450°C or less, further preferably 250°C or more and 450°C or less, and even more preferably 300°C or more and 450°C or less. is preferable, and more preferably 300°C or more and 400°C or less.
  • the insulating layer 235 has a function of reducing unevenness caused by the transistors 205R, 205G, 205B, 206R, 206G, and 206B, and making the surface on which the light-emitting device 130 is formed more flat. Note that in this specification and the like, the insulating layer 235 is sometimes referred to as a planarization layer.
  • An organic material can be suitably used for the insulating layer 235. It is preferable to use a photosensitive organic resin as the organic material, and for example, it is preferable to use a photosensitive resin composition containing an acrylic resin. Note that in this specification and the like, acrylic resin does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to the entire acrylic polymer in a broad sense.
  • the insulating layer 235 acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, precursors of these resins, etc. are used. It's okay. Further, the insulating layer 235 may be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Furthermore, a photoresist may be used as the photosensitive resin. As the photosensitive organic resin, either a positive type material or a negative type material may be used.
  • PVA polyvinyl alcohol
  • a photoresist may be used as the photosensitive resin.
  • the photosensitive organic resin either a positive type material or a negative type material may be used.
  • the insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer.
  • the insulating layer 235 can have a stacked structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer.
  • an inorganic insulating layer on the outermost surface of the insulating layer 235, it can function as an etching protection layer. This can prevent a portion of the insulating layer 235 from being etched when forming the pixel electrode 111 and reducing the flatness of the insulating layer 235.
  • the flatness of the upper surface of the insulating layer 235 which is the surface on which the light emitting device 130 is formed, is low, for example, there may be a connection failure due to a break in the common electrode 115, or the film thickness of the common electrode 115 may become locally thin, resulting in an increase in electrical resistance. Problems such as rising may occur. Further, if the flatness of the upper surface of the insulating layer 235 is low, the processing accuracy of a layer formed on the insulating layer 235 may be reduced. By making the upper surface of the insulating layer 235 flat, the processing accuracy of the light emitting device 130 and the like provided on the insulating layer 235 is increased, and a display device with high definition can be obtained. In addition, it is possible to prevent problems such as poor connection due to disconnection of the common electrode 115 and an increase in electrical resistance due to local thinning of the common electrode 115, resulting in high display quality. It can be a display device.
  • part of the insulating layer 235 may be removed when forming the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B.
  • the insulating layer 235 may have a recess in a region that does not overlap with any of the pixel electrodes 111R, 111G, and 111B.
  • the structure of the pixel electrode that can be applied to the display device that is one embodiment of the present invention is not limited to the structure of the pixel electrode 111 shown in FIG. 16 and the like.
  • the insulating layer 237 covers the upper end portions of the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B.
  • the insulating layer 237 functions as a partition wall (also referred to as a bank, bank, or spacer).
  • the insulating layer 237 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material.
  • a material that can be used for the insulating layer 218 or a material that can be used for the insulating layer 235 can be used.
  • the insulating layer 237 may have a stacked structure of an inorganic insulating layer and an organic insulating layer.
  • the end portion of the insulating layer 237 has a tapered shape.
  • the coverage of the film formed later can be improved.
  • the insulating layer 237 may be an inorganic insulating layer. By using an inorganic insulating layer for the insulating layer 237, a high-definition display device can be obtained.
  • the insulating layer 237 can be formed by applying a composition containing the organic material by spin coating, and then selectively exposing and developing the composition. I can do it.
  • a photosensitive organic material is used for the film serving as the insulating layer 237
  • a positive type photosensitive resin or a negative type photosensitive resin may be used.
  • the light used for exposure includes i-line.
  • the light used for exposure may include at least one of the g-line and the h-line. By adjusting the exposure amount, the width of the aperture can be controlled.
  • sputtering method, vapor deposition method, droplet discharge method (inkjet method), screen printing, and offset printing may be used.
  • the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B are formed to cover the openings of the insulating layer 218 and the insulating layer 235.
  • An insulating layer 237 is embedded in the recesses of the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B.
  • the island-shaped layer 113R, layer 113G, and layer 113B can be formed using a fine metal mask.
  • a layer 113R, a layer 113G, and a layer 113B may be provided on the insulating layer 237.
  • FIG. 16 shows a structure in which adjacent layers 113 are not in contact with each other, one embodiment of the present invention is not limited to this.
  • Adjacent layers 113 may be in contact with each other on the insulating layer 237. Further, adjacent layers 113 may overlap on the insulating layer 237.
  • the layer 113R and the layer 113G may be in contact with each other, or the layer 113R and the layer 113G may be overlapped.
  • insulating layer 237 can also be applied to other configuration examples.
  • a protective layer 131 is provided on the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B.
  • the protective layer 131 and the substrate 152 are bonded to each other via an adhesive layer 142.
  • a light shielding layer 117 is provided on the substrate 152.
  • a solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light emitting device.
  • a space between a substrate 152 and a substrate 151 is filled with an adhesive layer 142, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (such as nitrogen or argon) and a hollow sealing structure may be applied.
  • the adhesive layer 142 may be provided so as not to overlap the light emitting device.
  • the space may be filled with a resin different from that of the adhesive layer 142 provided in a frame shape.
  • a protective layer 131 on the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B.
  • the protective layer 131 may have a single layer structure or a laminated structure of two or more layers. The conductivity of the protective layer 131 does not matter.
  • the protective layer 131 at least one of an insulating layer, a semiconductor layer, and a conductive layer can be used.
  • An inorganic material can be used for the protective layer 131.
  • one or more of an oxide, an oxynitride, a nitride oxide, or a nitride can be used, for example. Specific examples include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, and hafnium oxide.
  • the protective layer 131 preferably contains nitride or nitride oxide, and more preferably contains nitride.
  • a layer containing In-Sn oxide (ITO), In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or In-Ga-Zn oxide (IGZO) may be used. You can also do it.
  • the layer preferably has a high resistance, and specifically, preferably has a higher resistance than the common electrode 115.
  • the layer may further contain nitrogen.
  • the protective layer 131 When emitting light from a light emitting device is extracted through the protective layer 131, the protective layer 131 preferably has high transparency to visible light.
  • the protective layer 131 preferably has high transparency to visible light.
  • In-Sn oxide, In-Ga-Zn oxide, and aluminum oxide are preferable because they each have high transparency to visible light.
  • the protective layer 131 may include an organic film.
  • the protective layer 131 may include both an organic film and an inorganic film.
  • Examples of the method for forming the protective layer 131 include a vacuum evaporation method, a sputtering method, a CVD method, and an ALD method.
  • the protective layer 131 may have a laminated structure formed using different film formation methods.
  • the protective layer 131 is provided at least on the display section 162, and is preferably provided so as to cover the entire display section 162. It is preferable that the protective layer 131 is provided so as to cover not only the display section 162 but also the connection section 140 and the circuit 164. Moreover, it is preferable that the protective layer 131 is provided up to the end of the display device 200A.
  • a connecting portion 204 is provided in a region of the substrate 151 where the substrate 152 does not overlap.
  • the wiring 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242.
  • the conductive layer 166 can be formed in the same process as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B.
  • the conductive layer 166 is exposed on the upper surface of the connection portion 204. Thereby, the connecting portion 204 and the FPC 172 can be electrically connected via the connecting layer 242.
  • connection layer 242 for example, an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP) can be used.
  • ACF anisotropic conductive film
  • ACP anisotropic conductive paste
  • the connecting portion 204 there is a portion where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166.
  • the conductive layer 166 can be exposed by removing a region of the protective layer 131 that overlaps with the conductive layer 166 using a mask.
  • a stacked structure of at least one organic layer and a conductive layer may be provided on the conductive layer 166, and the protective layer 131 may be provided on the stacked structure. Then, a laser or a sharp blade (for example, a needle or a cutter) is used to form a starting point for peeling (a part that triggers peeling) on the laminated structure, and the laminated structure and its top
  • the protective layer 131 may be selectively removed to expose the conductive layer 166.
  • the protective layer 131 can be selectively removed by pressing an adhesive roller against the substrate 151 and moving the roller relatively while rotating.
  • an adhesive tape may be attached to the substrate 151 and then peeled off.
  • the adhesion between the organic layer and the conductive layer or the adhesion between the organic layers is low, separation occurs at the interface between the organic layer and the conductive layer or within the organic layer. Thereby, the region of the protective layer 131 that overlaps with the conductive layer 166 can be selectively removed. Note that if an organic layer or the like remains on the conductive layer 166, it can be removed using an organic solvent or the like.
  • the organic layer for example, at least one organic layer (a layer functioning as a light emitting layer, a carrier block layer, a carrier transport layer, or a carrier injection layer) used in any of the layers 113B, 113G, and 113R is used. be able to.
  • the organic layer may be formed when forming any of the layers 113B, 113G, and 113R, or may be provided separately.
  • the conductive layer can be formed using the same process and the same material as the common electrode 115. For example, it is preferable to form an ITO film as the common electrode 115 and the conductive layer. Note that when a stacked structure is used for the common electrode 115, at least one layer among the layers constituting the common electrode 115 is provided as a conductive layer.
  • the upper surface of the conductive layer 166 may be covered with a mask so that the protective layer 131 is not formed on the conductive layer 166.
  • a mask for example, a metal mask (area metal mask) may be used, or a tape or film having adhesiveness or adsorption properties may be used.
  • connection portion 204 a region where the protective layer 131 is not provided is formed in the connection portion 204, and the conductive layer 166 and the FPC 172 are electrically connected in this region via the connection layer 242. be able to.
  • connection portion 140 a conductive layer 123 is provided on the insulating layer 235. The ends of the conductive layer 123 are covered with an insulating layer 237. Further, a common electrode 115 is provided on the conductive layer 123.
  • the display device 200A shown in FIG. 16 is a top emission type. Light emitted by the light emitting device is emitted to the substrate 152 side.
  • the substrate 152 is preferably made of a material that is highly transparent to visible light.
  • the pixel electrode 111 includes a material that reflects visible light, and the common electrode 115 includes a material that transmits visible light.
  • light G and light B emitted from the light emitting device 130G and the light emitting device 130B toward the substrate 152 are indicated by broken arrows, respectively.
  • the light shielding layer 117 can be provided between adjacent light emitting devices, at the connection portion 140, and at the circuit 164.
  • the light blocking layer 117 By providing the light blocking layer 117, light emitted from adjacent subpixels is blocked, and color mixing can be prevented. Further, external light can be suppressed from reaching the transistor 201, the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B. Deterioration of the transistor 206R, the transistor 206G, and the transistor 206B due to the external light can be suppressed. Note that a configuration may be adopted in which the light shielding layer 117 is not provided.
  • optical members can be arranged on the outside of the substrate 152.
  • optical members include polarizing plates, retardation plates, light diffusion layers (for example, diffusion films), antireflection layers, and light-condensing films.
  • surface protection is provided such as an antistatic film that suppresses the adhesion of dust, a water-repellent film that prevents dirt from adhering, a hard coat film that suppresses the occurrence of scratches due to use, and a shock absorption layer.
  • Layers may be arranged. For example, it is preferable to provide a glass layer or a silica layer (SiO x layer) as the surface protective layer, since surface contamination and scratches can be suppressed.
  • DLC diamond-like carbon
  • AlO x aluminum oxide
  • polyester material a polycarbonate material, or the like
  • polycarbonate material a material with high transmittance to visible light.
  • Materials that can be used for the substrate 102 shown in FIG. 1B etc. can be used for the substrate 151 and the substrate 152, respectively.
  • a material that transmits the light is used for the substrate on the side from which the light from the light emitting device is extracted.
  • a polarizing plate may be used as the substrate from which light from the light emitting device is extracted.
  • the substrate 151 and the substrate 152 are each made of, for example, polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, Polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetra Fluoroethylene (PTFE) resin, ABS resin, or cellulose nanofibers can be used.
  • the substrate 151 and the substrate 152 may each be made of glass having a thickness sufficient to have flexibility.
  • a substrate with high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small).
  • the absolute value of the retardation (phase difference) value of the substrate with high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.
  • films with high optical isotropy examples include triacetyl cellulose (TAC, also referred to as cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.
  • TAC triacetyl cellulose
  • COP cycloolefin polymer
  • COC cycloolefin copolymer
  • a film with low water absorption for the substrate.
  • a film with a water absorption rate of 1% or less more preferably a film with a water absorption rate of 0.1% or less, and even more preferably a film with a water absorption rate of 0.01% or less.
  • various curable adhesives can be used, such as a photo-curable adhesive such as an ultraviolet curable adhesive, a reaction-curable adhesive, a thermosetting adhesive, and an anaerobic adhesive.
  • these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, EVA (ethylene vinyl acetate) resins, and the like.
  • materials with low moisture permeability such as epoxy resin are preferred.
  • a two-liquid mixed type resin may be used.
  • an adhesive sheet or the like may be used.
  • the display device 200B shown in FIG. 17 mainly differs from the display device 200A shown in FIG. 16 in that the configurations of a light-emitting device 130R (not shown), a light-emitting device 130G, and a light-emitting device 130B are different.
  • the light emitting device 130R has a layer 113W instead of the layer 113R.
  • Light emitting device 130G has layer 113W instead of layer 113G.
  • Light emitting device 130B has layer 113W instead of layer 113B.
  • the layer 113W can be configured to emit white light.
  • a vacuum evaporation method or a sputtering method can be used to form the layer 113W.
  • the layer 113W can be configured to be shared by the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B. By sharing the layer 113W among a plurality of light emitting devices 130, the layer 113W can be formed without using a fine metal mask.
  • the layer 113W is provided in the display section 162. For example, an area mask can be used to form the layer 113W.
  • An optical adjustment layer (not shown) may be provided between the pixel electrode 111 and the layer 113.
  • a conductive layer that is transparent to visible light can be used.
  • the thickness of the optical adjustment layer may be made different between the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B.
  • a colored layer 132R (not shown) that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light are provided on the surface of the substrate 152 on the adhesive layer 142 side. It's okay.
  • the colored layer 132R is provided in a region overlapping with the light emitting device 130R.
  • the colored layer 132G is provided in a region overlapping with the light emitting device 130G.
  • the colored layer 132B is provided in a region overlapping with the light emitting device 130B.
  • the colored layer 132R can block unnecessary wavelength light emitted from the red light emitting device 130R. With such a configuration, the color purity of light emitted from each light emitting device can be increased. Note that the same effects can be achieved also in the combination of the light emitting device 130G and the colored layer 132G, and in the combination of the light emitting device 130B and the colored layer 132B.
  • the colored layer 132R, the colored layer 132G, and the colored layer 132B can also be applied to other configuration examples.
  • the display device 200C shown in FIG. 18 differs in the configurations of a pixel electrode 111R (not shown), a pixel electrode 111G, a pixel electrode 111B, a conductive layer 123, and a conductive layer 166, and does not have an insulating layer 237.
  • the main difference from the display device 200A shown in FIG. 16 is that the display device 113 covers the top and side surfaces of the pixel electrode 111, and that it includes a common layer 114, an insulating layer 125, and an insulating layer 127.
  • the light emitting device 130R (not shown) includes a pixel electrode 111R on the insulating layer 235, an island-like layer 113R (not shown) on the pixel electrode 111R, a common layer 114 on the island-like layer 113R, and a common layer 114 on the island-like layer 113R. a common electrode 115 on layer 114;
  • layer 113R and common layer 114 can be collectively referred to as an EL layer.
  • the light emitting device 130G includes a pixel electrode 111G on the insulating layer 235, an island-like layer 113G on the pixel electrode 111G, a common layer 114 on the island-like layer 113G, and a common electrode 115 on the common layer 114.
  • layer 113G and common layer 114 can be collectively referred to as an EL layer.
  • the light emitting device 130B includes a pixel electrode 111B on an insulating layer 235, an island-like layer 113B on the pixel electrode 111B, a common layer 114 on the island-like layer 113B, and a common electrode 115 on the common layer 114.
  • layer 113B and common layer 114 may be collectively referred to as an EL layer.
  • a layer provided in an island shape for each light-emitting device is referred to as a layer 113R, a layer 113G, or a layer 113B
  • a layer shared by multiple light-emitting devices is referred to as a layer 113R, a layer 113G, or a layer 113B.
  • the layers 113R, 113G, and 113B may be referred to as an island-shaped EL layer, an island-shaped EL layer, or the like, without including the common layer 114.
  • the layer 113R, the layer 113G, and the layer 113B may each include a hole injection layer, a hole transport layer, a light emitting layer, and an electron transport layer in this order.
  • an electron blocking layer may be provided between the hole transport layer and the light emitting layer.
  • a hole blocking layer may be provided between the electron transport layer and the light emitting layer.
  • an electron injection layer may be provided on the electron transport layer.
  • the layer 113R, the layer 113G, and the layer 113B may each have an electron injection layer, an electron transport layer, a light emitting layer, and a hole transport layer in this order.
  • a hole blocking layer may be provided between the electron transport layer and the light emitting layer.
  • an electron blocking layer may be provided between the hole transport layer and the light emitting layer.
  • a hole injection layer may be provided on the hole transport layer.
  • the layer 113R, the layer 113G, and the layer 113B each have a light emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light emitting layer.
  • each of the layers 113R, 113G, and 113B preferably includes a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer.
  • each of the layers 113R, 113G, and 113B preferably includes a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer.
  • a tandem structure may be applied to the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B.
  • the layer 113R has a structure that has a plurality of light emitting units that emit red light
  • the layer 113G has a structure that has a plurality of light emitting units that emit green light
  • the layer 113B has a structure that has a plurality of light emitting units that emit blue light. It is preferable that the structure has a plurality of light emitting units that emit light. It is preferable to provide a charge generation layer between each light emitting unit.
  • the layer 113R, the layer 113G, and the layer 113B may include, for example, a first light-emitting unit, a charge generation layer on the first light-emission unit, and a second light-emission unit on the charge generation layer. .
  • the second light emitting unit preferably has a light emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light emitting layer.
  • the second light-emitting unit preferably includes a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer.
  • the second light-emitting unit preferably includes a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer.
  • the surface of the second light-emitting unit is exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer, it is possible to prevent the light-emitting layer from being exposed on the outermost surface. damage to the light emitting layer can be reduced. Thereby, the reliability of the light emitting device can be improved.
  • the light-emitting unit provided in the uppermost layer includes a light-emitting layer and one or both of a carrier transport layer and a carrier block layer on the light-emitting layer.
  • the common layer 114 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or may have a hole transport layer and a hole injection layer stacked together. .
  • the common layer 114 is shared by the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B.
  • a vapor deposition method including a vacuum vapor deposition method
  • a transfer method a printing method, an inkjet method, or a coating method can be used.
  • FIG. 18 shows a configuration in which the common electrode 115 is provided directly on the conductive layer 123. Note that a common layer 114 may be provided on the conductive layer 123, and the conductive layer 123 and the common electrode 115 may be electrically connected via the common layer 114. For example, by using an area mask, the regions where the common layer 114 and the common electrode 115 are formed can be changed.
  • the pixel electrode 111G included in the light emitting device 130G has a stacked structure of a conductive layer 124G, a conductive layer 126G on the conductive layer 124G, and a conductive layer 129G on the conductive layer 126G.
  • the conductive layer 124G is electrically connected to the conductive layer 116b of the transistor 206G through openings provided in the insulating layer 218 and the insulating layer 235.
  • the end of the conductive layer 124G is located outside the end of the conductive layer 126G.
  • the end of the conductive layer 126G is located inside the end of the conductive layer 129G.
  • the end of the conductive layer 124G is located outside the end of the conductive layer 129G.
  • the end of the conductive layer 126G is located on the conductive layer 124G.
  • an end portion of the conductive layer 129G is located on the conductive layer 124G.
  • the upper surface and side surfaces of the conductive layer 126G are covered with a conductive layer 129G.
  • the transmittance and reflectivity of the conductive layer 124G to visible light are not particularly limited.
  • a conductive layer that is transparent to visible light or a conductive layer that is reflective to visible light can be used.
  • a conductive layer that is transparent to visible light for example, a conductive layer containing an oxide conductor (also referred to as an oxide conductive layer) can be used.
  • In-Si-Sn oxide also referred to as ITSO
  • ITSO can be suitably used as the conductive layer 124G.
  • a conductive layer that is reflective to visible light metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, tin, zinc, silver, platinum, gold, molybdenum, tantalum, or tungsten, or An alloy containing this as a main component (for example, an alloy of silver, palladium, and copper (APC: Ag-Pd-Cu)) can be used.
  • the conductive layer 124G may have a laminated structure of a conductive layer that is transparent to visible light and a conductive layer that is reflective over the conductive layer.
  • a material that has high adhesion to the surface on which the conductive layer 124G is formed here, the insulating layer 235
  • peeling of the conductive layer 124G can be suppressed.
  • a conductive layer that is reflective to visible light can be used for the conductive layer 126G.
  • the conductive layer 126G may have a laminated structure of a conductive layer that is transparent to visible light and a conductive layer that is reflective over the conductive layer.
  • the same material as the conductive layer 124G can be applied to the conductive layer 126G.
  • a laminated structure of In-Si-Sn oxide (ITSO) and an alloy of silver, palladium, and copper (APC) on the In-Si-Sn oxide (ITSO) is preferably used. Can be used.
  • the same material as the conductive layer 124G can be applied to the conductive layer 129G.
  • a conductive layer that is transparent to visible light can be used.
  • In-Si-Sn oxide (ITSO) can be used as the conductive layer 129G.
  • oxidation of the conductive layer 126G can be suppressed by applying a material that is not easily oxidized to the conductive layer 129G and covering the conductive layer 126G with the conductive layer 129G. can. Further, it is possible to suppress the metal components contained in the conductive layer 126G from being deposited. For example, when a material containing silver is used for the conductive layer 126G, In-Si-Sn oxide (ITSO) can be suitably used for the conductive layer 129G. Thereby, oxidation of the conductive layer 126G can be suppressed, and silver precipitation can be suppressed.
  • ITSO In-Si-Sn oxide
  • Conductive layer 124R (not shown), conductive layer 126R (not shown), and conductive layer 129R (not shown) in light emitting device 130R, and conductive layer 124B, conductive layer 126B, and conductive layer 129B in light emitting device 130B. are the same as the conductive layer 124G, the conductive layer 126G, and the conductive layer 129G in the light emitting device 130G, respectively, so detailed description thereof will be omitted.
  • pixel electrode 111R pixel electrode 111G
  • pixel electrode 111B conductive layer 123
  • conductive layer 166 shown in FIG. 18 etc. can also be applied to other configuration examples.
  • the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B are formed to cover the openings provided in the insulating layer 218 and the insulating layer 235.
  • a layer 128 is embedded in the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B.
  • the layer 128 has a function of flattening the concave portions of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B.
  • a conductive layer 126R, a conductive layer 126G, and a conductive layer are electrically connected to the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B, respectively. 126B is provided.
  • the regions of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B that overlap with the recesses also function as light emitting regions, and the aperture ratio of the pixel can be increased.
  • the layer 128 may be an insulating layer or a conductive layer.
  • various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate.
  • layer 128 is formed using an organic material. It is particularly preferable to use a photosensitive organic resin as the organic material.
  • a photosensitive resin composition containing an acrylic resin can be suitably used for the layer 128.
  • the layer 128 when the layer 128 is a conductive layer, the layer 128 can function as a part of the pixel electrode.
  • an organic resin in which metal particles are dispersed can be used for the layer 128.
  • FIG. 18 shows an example in which the end of the layer 113G is located outside the end of the pixel electrode 111G.
  • the layer 113G is formed to cover the end of the pixel electrode 111G.
  • the aperture ratio can be increased.
  • by covering the side surfaces of the pixel electrode 111 with the EL layer it is possible to prevent the pixel electrode 111 and the common electrode 115 from coming into contact with each other, thereby suppressing short circuits in the light emitting device 130.
  • the pixel electrode 111G and the layer 113G are described here as an example, the same can be said for the pixel electrode 111R and the layer 113R, and the pixel electrode 111B and the layer 113B.
  • An insulating layer (see insulating layer 237 in FIG. 16) that covers the upper end of the pixel electrode 111G is not provided between the pixel electrode 111G and the layer 113G. Further, an insulating layer covering the upper end of the pixel electrode 111B is not provided between the pixel electrode 111B and the layer 113B. Therefore, the interval between adjacent light emitting devices can be reduced. Therefore, a high definition or high resolution display device can be realized. Further, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.
  • the EL layer can be formed using, for example, a photolithography method. Specifically, after a pixel electrode is formed for each subpixel, a film that will become a light emitting layer is formed over a plurality of pixel electrodes. Thereafter, the film is processed using a photolithography method to form one island-shaped light emitting layer for one pixel electrode. Thereby, the light-emitting layer is divided into sub-pixels, and an island-shaped light-emitting layer can be formed for each sub-pixel. By using a photolithography method, an EL layer with a fine size can be formed. By providing the EL layer in an island shape for each light emitting device, leakage current between adjacent light emitting devices can be suppressed. Thereby, crosstalk caused by unintended light emission can be prevented, and a display device with extremely high contrast can be realized. In particular, a display device with high current efficiency at low brightness can be realized.
  • the heat resistance temperature of the compounds contained in the layer 113R, the layer 113G, and the layer 113B is preferably 100°C or more and 180°C or less, preferably 120°C or more and 180°C or less, and more preferably 140°C or more and 180°C or less.
  • the glass transition point (Tg) of each of these compounds is preferably 100°C or more and 180°C or less, preferably 120°C or more and 180°C or less, and more preferably 140°C or more and 180°C or less.
  • an insulating layer 125 and an insulating layer 127 on the insulating layer 125 are provided.
  • a plurality of cross sections of the insulating layer 125 and the insulating layer 127 are shown in FIG. 18, when the display device 200C is viewed from the top, the insulating layer 125 and the insulating layer 127 are each connected to one.
  • the display device 200C can have, for example, one insulating layer 125 and one insulating layer 127.
  • the display device 200C may have a plurality of insulating layers 125 separated from each other, or may have a plurality of insulating layers 127 separated from each other.
  • the insulating layer 125 is in contact with each side surface of the layer 113R, the layer 113G, and the layer 113B.
  • peeling of the layer 113R, the layer 113G, and the layer 113B can be prevented.
  • the insulating layer 125 and the layer 113R, the layer 113G, or the layer 113B are in close contact with each other, the adjacent layers 113 and the like are fixed or bonded together by the insulating layer 125. Thereby, the reliability of the light emitting device can be improved. Furthermore, the manufacturing yield of light emitting devices can be increased.
  • An inorganic material can be used for the insulating layer 125.
  • the insulating layer 125 one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used, for example.
  • the insulating layer 125 may have a single layer structure or a laminated structure.
  • the oxide include silicon oxide, aluminum oxide, magnesium oxide, indium gallium zinc oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
  • nitrides include silicon nitride and aluminum nitride.
  • Examples of oxynitrides include silicon oxynitride and aluminum oxynitride.
  • Examples of nitrided oxides include silicon nitrided oxide and aluminum nitrided oxide.
  • aluminum oxide is preferable because it has a high etching selectivity with respect to the EL layer and has a function of protecting the EL layer.
  • the insulating layer 125 preferably has a function as a barrier insulating layer against at least one of water and oxygen. Further, the insulating layer 125 preferably has a function of suppressing diffusion of at least one of water and oxygen. Further, the insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) at least one of water and oxygen.
  • a barrier insulating layer refers to an insulating layer having barrier properties. Further, in this specification and the like, barrier property refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability).
  • the insulating layer 125 has a function as a barrier insulating layer or a gettering function, thereby suppressing the intrusion of impurities (typically, at least one of water and oxygen) that can diffuse into each light emitting device from the outside.
  • impurities typically, at least one of water and oxygen
  • the insulating layer 127 is provided on the insulating layer 125 so as to fill the recessed portion of the insulating layer 125.
  • the insulating layer 127 can be configured to overlap with a part of the upper surface and side surfaces of each of the layer 113R, the layer 113G, and the layer 113B with the insulating layer 125 interposed therebetween.
  • the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.
  • the space between adjacent island-like layers can be filled, so that the surface on which layers (for example, carrier injection layer, common electrode, etc.) to be provided on the island-like layer are formed can be It is possible to reduce the unevenness of the layer and improve the coverage of the layer.
  • the upper surface of the insulating layer 127 preferably has a shape with higher flatness, but may have a convex portion, a convex curved surface, a concave curved surface, or a concave portion.
  • an insulating layer containing an organic material can be suitably used. It is preferable to use a photosensitive organic resin as the organic material, and for example, it is preferable to use a photosensitive resin composition containing an acrylic resin.
  • acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, precursors of these resins, etc. may be used. good.
  • an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin may be used.
  • a photoresist may be used as the photosensitive resin.
  • the photosensitive organic resin either a positive type material or a negative type material may be used.
  • the insulating layer 127 may be made of a material that absorbs visible light. Since the insulating layer 127 absorbs light emitted from the light emitting device, light leakage (stray light) from the light emitting device to an adjacent light emitting device via the insulating layer 127 can be suppressed. Thereby, the display quality of the display device can be improved. Furthermore, since display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.
  • Materials that absorb visible light include materials that contain pigments such as black, materials that contain dyes, resin materials that have light-absorbing properties (for example, polyimide, etc.), and resin materials that can be used for color filters (color filter materials).
  • pigments such as black
  • resin materials that contain dyes for example, polyimide, etc.
  • resin materials that can be used for color filters color filter materials.
  • by mixing color filter materials of three or more colors it is possible to form a black or nearly black resin layer.
  • a mask layer 118R and a mask layer 119R are located on the layer 113R of the light emitting device 130R, a mask layer 118G and a mask layer 119G are located on the layer 113G of the light emitting device 130G, and a layer 113B of the light emitting device 130B is located.
  • Mask layer 118B and mask layer 119B are located at.
  • Mask layer 118 and mask layer 119 are provided so as to surround the light emitting region. In other words, mask layer 118 and mask layer 119 have openings in portions that overlap with the light emitting regions. In the mask layer 118R and the mask layer 119R, a portion of the mask layer provided on the layer 113R remains when forming the layer 113R.
  • the common layer 114 and the common electrode 115 are provided on the layer 113R, the layer 113G, the layer 113B, the mask layer 118, the mask layer 119, the insulating layer 125, and the insulating layer 127.
  • the insulating layer 125 and the insulating layer 127 there are a region where the pixel electrode and the island-shaped EL layer are provided, a region where the pixel electrode and the island-like EL layer are not provided (a region between the light emitting devices), There is a step caused by this.
  • the step difference can be reduced and the coverage of the common layer 114 and the common electrode 115 can be improved. Therefore, connection failures due to disconnection between the common layer 114 and the common electrode 115 can be suppressed. Further, due to the step difference, the film thickness of the common electrode 115 is locally reduced, and it is possible to suppress an increase in the electrical resistance of the common electrode 115.
  • the insulating layer 127 covers the side surfaces of the insulating layer 125, the mask layer 118R, the mask layer 119R, the mask layer 118G, the mask layer 119G, the mask layer 118B, and the mask layer 119B. It may be at least partially covered. Further, the insulating layer 127 may have a region in contact with the layer 113R, the layer 113G, and the layer 113B.
  • the display device 200D shown in FIG. 19 differs from the display device 200C shown in FIG. 18 mainly in that it includes an insulating layer 239.
  • the insulating layer 239 is provided on the insulating layer 235 and has an opening in a region that overlaps with the opening that the insulating layer 235 has.
  • the pixel electrode 111 is provided so as to cover the openings provided in the insulating layer 239, the insulating layer 235, and the insulating layer 218.
  • the insulating layer 239 can function as an etching protection film when forming the layer 113, the mask layer 118, and the mask layer 119.
  • the insulating layer 239 when forming the layer 113, the mask layer 118, and the mask layer 119, part of the insulating layer 235 can be prevented from being etched and unevenness can be prevented from occurring in the insulating layer 235.
  • the level difference on the surface on which the insulating layer 125 is formed becomes smaller, and the coverage of the insulating layer 125 can be improved. Therefore, the side surfaces of the layer 113 are covered with the insulating layer 125, and peeling of the layer 113 can be prevented.
  • the insulating layer 239 can be an insulating layer containing an inorganic material.
  • an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, a nitride oxide insulating film, etc. can be used, for example.
  • the insulating layer 239 may have a single layer structure or a laminated structure.
  • oxide insulating films include silicon oxide film, aluminum oxide film, magnesium oxide film, indium gallium zinc oxide film, gallium oxide film, germanium oxide film, yttrium oxide film, zirconium oxide film, lanthanum oxide film, neodymium oxide film, and oxide film.
  • Examples include a hafnium film and a tantalum oxide film.
  • Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film.
  • Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, and the like.
  • Examples of the nitride oxide insulating film include a silicon nitride oxide film, an aluminum nitride oxide film, and the like.
  • a silicon oxide film or a silicon oxynitride film can be suitably used for the insulating layer 239.
  • the insulating layer 239 when etching the layer 113, the mask layer 118, and the film that will become the mask layer 119, it is possible to select a material that has a high etching rate ratio (also referred to as a high selectivity) with respect to the film. preferable.
  • the flatness of the surface on which the light emitting device 130 is formed is low, for example, there may be a connection failure due to a break in the common electrode 115, or the film thickness of the common electrode 115 may locally become thinner, resulting in an increase in electrical resistance. Failure may occur. Furthermore, there is a possibility that the processing accuracy of the layer formed on the surface to be formed may be reduced.
  • the surface on which the light-emitting device 130 is formed can be made flatter. Therefore, the processing accuracy of the light emitting device 130 and the like provided on the insulating layer 239 is increased, and a display device with high definition can be obtained. In addition, it is possible to prevent problems such as poor connection due to disconnection of the common electrode 115 and an increase in electrical resistance due to local thinning of the film thickness of the common electrode 115, resulting in high display quality. It can be a display device.
  • the insulating layer 239 is shown to have a single-layer structure in FIG. 19, one embodiment of the present invention is not limited to this.
  • the insulating layer 239 may have a laminated structure.
  • a portion of the insulating layer 239 may be removed in a region that does not overlap with any of the layers 113R, 113G, and 113B.
  • the thickness of the insulating layer 239 in a region that does not overlap with any of the layer 113R, the layer 113G, and the layer 113B may be thinner than the thickness of the insulating layer 239 in a region that overlaps with the layer 113R, the layer 113G, or the layer 113B.
  • insulating layer 239 can also be applied to other configuration examples.
  • the display device 200E shown in FIG. 20 is mainly different from the display device 200D shown in FIG. 19 in that it includes a light receiving device 150.
  • the light receiving device 150 for example, a pn type or pin type photodiode can be used.
  • the light receiving device 150 functions as a photoelectric conversion device (also referred to as a photoelectric conversion element) that detects light incident on the light receiving device and generates an electric charge. Based on the amount of light incident on the light receiving device 150, the amount of charge generated from the light receiving device 150 is determined.
  • the light receiving device 150 can detect one or both of visible light and infrared light.
  • visible light one or more of light such as blue, violet, blue-violet, green, yellow-green, yellow, orange, and red can be detected.
  • infrared light it is possible to detect an object even in a dark place, which is preferable.
  • organic photodiode having a layer containing an organic compound as the light receiving device 150.
  • Organic photodiodes can be easily made thinner, lighter, and larger in area, and have a high degree of freedom in shape and design, so they can be applied to various display devices.
  • an organic EL device is used as the light emitting device 130, and an organic photodiode is used as the light receiving device 150.
  • the organic EL device and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL device.
  • FIG. 20 the light G emitted from the light emitting device 130G to the substrate 152 side and the light Lin entering the light receiving device 150 from the substrate 152 side are shown by broken line arrows, respectively.
  • a manufacturing method similar to that for the light emitting device 130 can be applied to the light receiving device 150.
  • the island-shaped active layer (also referred to as a photoelectric conversion layer) included in the light receiving device can be formed using, for example, a fine metal mask.
  • the active layer can be formed using photolithography instead of using a fine metal mask.
  • the photolithography method the active layer is formed by forming a film over one surface and then processing it, so that the island-shaped active layer can be formed with a uniform thickness. Further, by providing a mask layer over the active layer, damage to the active layer during the manufacturing process of the display device can be reduced, and the reliability of the light receiving device can be improved.
  • a configuration in which the active layer is formed using a photolithography method will be described as an example.
  • the light receiving device 150 includes a pixel electrode 111S, a layer 113S, a common layer 114, and a common electrode 115.
  • Layer 113S includes at least an active layer.
  • the pixel electrode 111S has a laminated structure of a conductive layer 124S, a conductive layer 126S on the conductive layer 124S, and a conductive layer 129S on the conductive layer 126S.
  • the pixel electrode 111S can be formed in the same process as the pixel electrode 111R (not shown), the pixel electrode 111G, and the pixel electrode 111B (not shown).
  • the pixel electrode 111S is electrically connected to the conductive layer 116b of the transistor 206S.
  • the transistor 205S can be formed in the same process as the transistor 205R, the transistor 205G, and the transistor 205B. Further, the transistor 206S can be formed in the same process as the transistor 206R, the transistor 206G, and the transistor 206B.
  • the insulating layer 235 and the insulating layer 218 each have an opening in a region overlapping with the conductive layer 116b of the transistor 206S.
  • a pixel electrode 111S included in the light receiving device 150 is provided so as to cover the opening.
  • the conductive layer 116b of the transistor 206S is electrically connected to the pixel electrode 111S through the opening.
  • the layer 113S is provided on the pixel electrode 111S.
  • a common layer 114 is provided on the layer 113S, and a common electrode 115 is provided on the common layer 114.
  • the common layer 114 is a continuous layer provided in common to the light receiving device 150 and the light emitting device 130.
  • the layer 113S includes at least an active layer, and preferably has a plurality of functional layers.
  • the functional layer include a carrier transport layer (a hole transport layer and an electron transport layer), a carrier block layer (a hole block layer and an electron block layer), and the like.
  • the layer 113S is a layer provided in the light receiving device 150 and not provided in the light emitting device 130.
  • the functional layers other than the active layer included in the layer 113S may have the same material as the functional layers other than the light emitting layer included in the layer 113R, the layer 113G, and the layer 113B.
  • the common layer 114 is a continuous layer shared by the light emitting device 130 and the light receiving device 150.
  • a layer that the light-receiving device and the light-emitting device have in common may have different functions in the light-emitting device and in the light-receiving device.
  • components may be referred to based on their functions in a light emitting device.
  • the hole injection layer functions as a hole injection layer in a light emitting device and as a hole transport layer in a light receiving device.
  • the electron injection layer functions as an electron injection layer in a light emitting device and as an electron transport layer in a light receiving device.
  • a layer that the light-receiving device and the light-emitting device have in common may have the same function in the light-emitting device and in the light-receiving device.
  • a hole transport layer functions as a hole transport layer in both a light emitting device and a light receiving device
  • an electron transport layer functions as an electron transport layer in both a light emitting device and a light receiving device.
  • An insulating layer 125 and an insulating layer 127 on the insulating layer 125 are provided in a region between the adjacent light emitting device 130 and the light receiving device 150. Although not shown, an insulating layer 125 and an insulating layer 127 on the insulating layer 125 are also provided in a region between adjacent light emitting devices.
  • a mask layer 118R and a mask layer 119R are located between the layer 113R and the insulating layer 125, and a mask layer 118S and a mask layer 119S are located between the layer 113S and the insulating layer 125.
  • a portion of the mask layer provided on the layer 113R remains when the layer 113R is processed.
  • a portion of the mask layer provided in contact with the upper surface of the layer 113S remains when the layer 113S, which is a layer including an active layer, is processed.
  • the mask layer 118R and the mask layer 118S may have the same material or different materials.
  • the mask layer 119R and the mask layer 119S may have the same material or different materials.
  • the pixel layout will be explained. There are no particular limitations on the arrangement of subpixels, and various methods can be applied. Examples of the sub-pixel arrangement include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.
  • planar shape of the subpixel examples include polygons such as triangles, quadrilaterals (including rectangles and squares), and pentagons, shapes with rounded corners of these polygons, ellipses, and circles.
  • the planar shape of the subpixel corresponds to the planar shape of a light emitting region of a light emitting device or a light receiving region of a light receiving device.
  • the pixel 210 is composed of three types of subpixels: a subpixel 11a, a subpixel 11b, and a subpixel 11c.
  • the subpixel 11a, the subpixel 11b, and the subpixel 11c each exhibit different colors of light.
  • the subpixels 11a, 11b, and 11c are subpixels of three colors: red (R), green (G), and blue (B), yellow (Y), cyan (C), and magenta (M). ) and three-color subpixels.
  • the number of subpixel colors is not limited to three, but may be four or more.
  • subpixels of four colors subpixels of four colors of R, G, B, and white (W), subpixels of four colors of R, G, B, and Y, and subpixels of four colors of R, G, B, and red.
  • Examples include subpixels for four colors of external light (IR).
  • Each subpixel has a pixel circuit that controls a light emitting device.
  • the pixel circuit is not limited to the subpixel range shown in FIG. 21A, and may be placed outside the subpixel range.
  • the transistor included in the pixel circuit of the subpixel 11a may be located within the range of the subpixel 11a shown in FIG. 21A, or some or all of the transistors may be located outside the range of the subpixel 11a.
  • the subpixel 11a, the subpixel 11b, and the subpixel 11c have the same or approximately the same aperture ratio (size, which can also be called the size of the light emitting region), but one embodiment of the present invention is not limited to this.
  • the aperture ratios of the sub-pixel 11a, the sub-pixel 11b, and the sub-pixel 11c can be determined as appropriate.
  • the aperture ratios of the subpixel 11a, the subpixel 11b, and the subpixel 11c may be different from each other, or two or more may be equal or approximately equal.
  • the S stripe arrangement is applied to the pixel 210 shown in FIG. 21B.
  • the pixel 210 shown in FIG. 21B is composed of three types of subpixels: a subpixel 11a, a subpixel 11b, and a subpixel 11c, and two subpixels (subpixel 11a, One sub-pixel (sub-pixel 11c) is provided in the right column (second column).
  • the pixel 210 shown in FIG. 21C includes a subpixel 11a having a substantially trapezoidal planar shape with rounded corners, a subpixel 11b having a substantially triangular planar shape with rounded corners, and a substantially quadrangular or substantially hexagonal planar shape with rounded corners. and a sub-pixel 11c. Further, the subpixel 11a has a smaller light emitting area than the subpixel 11b. In this way, the shape and size of each subpixel can be determined independently. For example, a subpixel having a more reliable light emitting device can be made smaller in size.
  • FIG. 21D shows an example in which a pixel 210a having a subpixel 11a and a subpixel 11b and a pixel 210b having a subpixel 11b and a subpixel 11c are arranged alternately.
  • a delta arrangement is applied to the pixels 210a and 210b shown in FIGS. 21E to 21G.
  • the pixel 210a has two subpixels (subpixel 11a and subpixel 11b) in the top row (first row), and one subpixel (subpixel 11c) in the bottom row (second row). has.
  • the pixel 210b has one subpixel (subpixel 11c) in the top row (first row), and two subpixels (subpixel 11a and subpixel 11b) in the bottom row (second row). has.
  • FIG. 21E shows an example in which each subpixel has a substantially rectangular planar shape with rounded corners
  • FIG. 21F shows an example in which each subpixel has a circular planar shape
  • FIG. 21G shows an example in which each subpixel has a substantially rectangular planar shape with rounded corners.
  • each subpixel is arranged inside a hexagonal area that is most densely arranged.
  • Each subpixel is arranged so as to be surrounded by six subpixels when focusing on that one subpixel.
  • sub-pixels exhibiting the same color of light are provided so as not to be adjacent to each other. For example, when focusing on the sub-pixel 11a, three sub-pixels 11b and three sub-pixels 11c are provided so as to be alternately arranged so as to surround it.
  • FIG. 21H is an example in which sub-pixels of each color are arranged in a zigzag pattern. Specifically, in plan view, the positions of the upper sides of two subpixels (for example, subpixel 11a and subpixel 11b, or subpixel 11b and subpixel 11c) aligned in the column direction are shifted.
  • the subpixel 11a is a subpixel R that emits red light
  • the subpixel 11b is a subpixel G that emits green light
  • the subpixel 11c is a subpixel that emits blue light. It is preferable to use subpixel B.
  • the configuration of the subpixels is not limited to this, and the colors exhibited by the subpixels and the order in which they are arranged can be determined as appropriate.
  • the subpixel 11b may be a subpixel R that emits red light
  • the subpixel 11a may be a subpixel G that emits green light.
  • the planar shape of the subpixel may be a polygon with rounded corners, an ellipse, or a circle.
  • a technique (Optical Proximity Correction) technique is used to correct the mask pattern in advance so that the design pattern and the transferred pattern match. ) may be used. Specifically, in the OPC technique, a correction pattern is added to a corner of a figure on a mask pattern.
  • a pixel can be configured to have four types of subpixels.
  • a stripe arrangement is applied to the pixels 210 shown in FIGS. 22A to 22C.
  • FIG. 22A is an example in which each subpixel has a rectangular planar shape
  • FIG. 22B is an example in which each subpixel has a planar shape in which two semicircles and a rectangle are connected
  • FIG. 22C is an example in which each subpixel has a planar shape in which two semicircles and a rectangle are connected. This is an example in which the subpixel has an elliptical planar shape.
  • a matrix arrangement is applied to the pixels 210 shown in FIGS. 22D to 22F.
  • FIG. 22D shows an example in which each subpixel has a square planar shape
  • FIG. 22E shows an example in which each subpixel has a substantially square planar shape with rounded corners
  • FIG. 22F shows an example in which each subpixel has a substantially square planar shape with rounded corners.
  • FIGS. 22G and 22H show an example in which one pixel 210 is arranged in two rows and three columns.
  • the pixel 210 shown in FIG. 22G has three subpixels (subpixel 11a, subpixel 11b, and subpixel 11c) in the top row (first row), and has three subpixels (subpixel 11a, subpixel 11b, and subpixel 11c) in the bottom row (second row). It has one subpixel (subpixel 11d).
  • the pixel 210 has the subpixel 11a in the left column (first column), the subpixel 11b in the center column (second column), and the subpixel 11b in the right column (third column). It has a pixel 11c, and further has sub-pixels 11d across these three columns.
  • the pixel 210 shown in FIG. 22H has three subpixels (subpixel 11a, subpixel 11b, and subpixel 11c) in the top row (first row), and three subpixels (subpixel 11a, subpixel 11b, and subpixel 11c) in the bottom row (second row). It has three sub-pixels 11d.
  • the pixel 210 has a subpixel 11a and a subpixel 11d in the left column (first column), a subpixel 11b and a subpixel 11d in the center column (second column), and a subpixel 11b and a subpixel 11d in the center column (second column).
  • the column (third column) has a subpixel 11c and a subpixel 11d.
  • FIG. 22H by aligning the arrangement of the subpixels in the upper row and the lower row, it is possible to efficiently remove dust and the like that may occur during the manufacturing process. Therefore, a display device with high display quality can be provided.
  • FIG. 22I shows an example in which one pixel 210 is arranged in three rows and two columns.
  • the pixel 210 shown in FIG. 22I has a subpixel 11a in the upper row (first row), a subpixel 11b in the middle row (second row), and extends from the first row to the second row. It has a subpixel 11c, and one subpixel (subpixel 11d) in the lower row (third row). In other words, the pixel 210 has the sub-pixel 11a and the sub-pixel 11b in the left column (first column), the sub-pixel 11c in the right column (second column), and the sub-pixel 11c in the right column (second column). A sub-pixel 11d is provided throughout the area.
  • the pixel 210 shown in FIGS. 22A to 22I is composed of four sub-pixels: a sub-pixel 11a, a sub-pixel 11b, a sub-pixel 11c, and a sub-pixel 11d.
  • the sub-pixel 11a, the sub-pixel 11b, the sub-pixel 11c, and the sub-pixel 11d can each have a configuration including a light-emitting device that emits light of a different color.
  • the subpixel 11a, the subpixel 11b, the subpixel 11c, and the subpixel 11d are subpixels of four colors R, G, B, and white (W), and subpixels of four colors R, G, B, and Y. , or four-color subpixels of R, G, B, and infrared light (IR).
  • the subpixel 11a is a subpixel R that emits red light
  • the subpixel 11b is a subpixel G that emits green light
  • the subpixel 11c is a subpixel G that emits a blue light.
  • the subpixel B be the subpixel B that emits light
  • the subpixel 11d be one of the subpixel W that emits white light, the subpixel Y that emits yellow light, or the subpixel IR that emits near infrared light.
  • the layout of R, G, and B becomes a stripe arrangement, so that display quality can be improved.
  • the layout of R, G, and B is a so-called S stripe arrangement, so that display quality can be improved.
  • the pixel 210 may have a subpixel having a light receiving device.
  • any one of the subpixels 11a to 11d may be a subpixel having a light receiving device.
  • the subpixel 11a is a subpixel R that emits red light
  • the subpixel 11b is a subpixel G that emits green light
  • the subpixel 11c is a subpixel that emits blue light.
  • the sub-pixel B has a light-receiving device
  • the sub-pixel 11d is a sub-pixel S that has a light-receiving device.
  • the layout of R, G, and B becomes a stripe arrangement, so that display quality can be improved.
  • the layout of R, G, and B is a so-called S stripe arrangement, so that display quality can be improved.
  • a pixel can be configured to have five types of subpixels.
  • FIG. 22J shows an example in which one pixel 210 is arranged in two rows and three columns.
  • the pixel 210 shown in FIG. 22J has three subpixels (subpixel 11a, subpixel 11b, and subpixel 11c) in the top row (first row), and three subpixels (subpixel 11a, subpixel 11b, and subpixel 11c) in the bottom row (second row). It has two subpixels (subpixel 11d and subpixel 11e).
  • the pixel 210 has a sub-pixel 11a and a sub-pixel 11d in the left column (first column), a sub-pixel 11b in the center column (second column), and a sub-pixel 11b in the center column (second column). It has a sub-pixel 11c in the second column), and further has a sub-pixel 11e from the second column to the third column.
  • the pixel 210 shown in FIG. 22K has a subpixel 11a in the upper row (first row), a subpixel 11b in the middle row (second row), and extends from the first row to the second row. It has a subpixel 11c, and two subpixels (subpixel 11d and subpixel 11e) in the lower row (third row). In other words, the pixel 210 has subpixel 11a, subpixel 11b, and subpixel 11d in the left column (first column), and subpixel 11c and subpixel 11e in the right column (second column). has.
  • the subpixel 11a is a subpixel R that emits red light
  • the subpixel 11b is a subpixel G that emits green light
  • the subpixel 11c is a subpixel that emits blue light.
  • the sub-pixel B be the sub-pixel B.
  • the layout of R, G, and B becomes a stripe arrangement, so that display quality can be improved.
  • the layout of R, G, and B is a so-called S stripe arrangement, so that display quality can be improved.
  • each pixel 210 shown in FIGS. 22J and 22K it is preferable to apply a subpixel S having a light receiving device to at least one of the subpixel 11d and the subpixel 11e.
  • the structures of the light receiving devices may be different from each other.
  • at least some of the wavelength ranges of the lights detected may be different from each other.
  • one of the sub-pixels 11d and 11e may have a light-receiving device that mainly detects visible light, and the other may have a light-receiving device that mainly detects infrared light. .
  • a subpixel S having a light receiving device is applied to one of the subpixel 11d and the subpixel 11e, and the other is a light emitting device that can be used as a light source. It is preferable to apply a subpixel having .
  • one of the subpixels 11d and 11e be a subpixel IR that emits infrared light, and the other be a subpixel S that has a light receiving device that detects infrared light.
  • subpixel S In a pixel having subpixel R, subpixel G, subpixel B, subpixel IR, and subpixel S, while displaying an image using subpixel R, subpixel G, and subpixel B, subpixel IR is By using it as a light source, the subpixel S can detect reflected infrared light emitted by the subpixel IR.
  • each pixel includes both a light-emitting device and a light-receiving device. Even in this case, various layouts can be applied.
  • the light-emitting layer 771 has at least a light-emitting substance (also referred to as a light-emitting material).
  • a structure having layer 780, light emitting layer 771, and layer 790 provided between a pair of electrodes can function as a single light emitting unit, and in this specification, the structure of FIG. 23A is referred to as a single structure.
  • FIG. 23B shows a modification of the EL layer 763 included in the light emitting device shown in FIG. 23A.
  • the light emitting device shown in FIG. 23B includes a layer 781 on the lower electrode 761, a layer 782 on the layer 781, a light emitting layer 771 on the layer 782, a layer 791 on the light emitting layer 771, and a layer 791 on the layer 781. an upper layer 792 and an upper electrode 762 on layer 792.
  • the layer 781 is a hole injection layer
  • the layer 782 is a hole transport layer
  • the layer 791 is an electron transport layer
  • the layer 792 is an electron injection layer.
  • the layer 781 is an electron injection layer
  • the layer 782 is an electron transport layer
  • the layer 791 is a hole transport layer
  • the layer 792 is a hole injection layer.
  • a structure in which a plurality of light emitting layers (a light emitting layer 771, a light emitting layer 772, and a light emitting layer 773) are provided between a layer 780 and a layer 790 is also a variation of the single structure. It is. Note that although FIGS. 23C and 23D show an example having three light emitting layers, the light emitting layer in a single structure light emitting device may have two layers, or four or more layers. Furthermore, a single structure light emitting device may have a buffer layer between two light emitting layers. As the buffer layer, for example, a carrier transport layer (hole transport layer or electron transport layer) can be used.
  • a carrier transport layer hole transport layer or electron transport layer
  • FIGS. 23D and 23F are examples in which the display device includes a layer 764 that overlaps with the light-emitting device.
  • FIG. 23D is an example in which layer 764 overlaps the light emitting device shown in FIG. 23C
  • FIG. 23F is an example in which layer 764 overlaps the light emitting device shown in FIG. 23E.
  • a conductive film that transmits visible light is used for the upper electrode 762 in order to extract light to the upper electrode 762 side.
  • the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 may use a light-emitting substance that emits light of the same color, or even the same light-emitting substance.
  • a light-emitting substance that emits blue light may be used for the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773.
  • a subpixel that emits blue light can extract blue light emitted by a light emitting device.
  • a color conversion layer is provided as a layer 764 shown in FIG.
  • the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 may each use light-emitting substances that emit light of different colors.
  • the lights emitted by the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 are of complementary colors, the respective lights are mixed and white light emission is obtained as a whole.
  • a single structure light emitting device preferably has a light emitting layer containing a light emitting substance that emits blue light and a light emitting layer containing a light emitting substance that emits visible light with a longer wavelength than blue light.
  • a light-emitting layer containing a light-emitting substance that emits red (R) light a light-emitting layer containing a light-emitting substance that emits green (G) light, and a light-emitting layer containing a light-emitting substance that emits green (G) light
  • R red
  • G green
  • G light-emitting layer
  • B light-emitting layer containing a light-emitting substance that emits light
  • the stacking order of the light emitting layers can be R, G, B from the anode side, or R, B, G from the anode side.
  • a buffer layer may be provided between R and G or B.
  • a single-structure light-emitting device when it has two light-emitting layers, it has a light-emitting layer containing a light-emitting substance that emits blue (B) light, and a light-emitting layer containing a light-emitting substance that emits yellow (Y) light.
  • B blue
  • Y yellow
  • configuration is preferred. This configuration may be referred to as a BY single structure.
  • a light emitting device that emits white light preferably contains two or more types of light emitting substances.
  • two or more light-emitting substances may be selected such that each of the light-emitting substances has a complementary color relationship.
  • a luminescent device that emits white light can be obtained as a whole. The same applies to a light emitting device having three or more light emitting layers.
  • the layer 780 and the layer 790 may each independently have a laminated structure consisting of two or more layers, as shown in FIG. 23B.
  • the light-emitting layer 771 and the light-emitting layer 772 may use a light-emitting substance that emits light of the same color, or even the same light-emitting substance.
  • a light-emitting substance that emits blue light may be used for the light-emitting layer 771 and the light-emitting layer 772, respectively.
  • a subpixel that emits blue light can extract blue light emitted by a light emitting device.
  • a color conversion layer is provided as a layer 764 shown in FIG. 23F to convert the blue light emitted by the light emitting device into light with a longer wavelength. It can extract red or green light. Further, as the layer 764, it is preferable to use both a color conversion layer and a colored layer.
  • a light emitting device having the configuration shown in FIG. 23E or 23F for subpixels that emit light of each color
  • different light emitting substances may be used depending on the subpixel.
  • a light emitting substance that emits red light may be used for the light emitting layer 771 and the light emitting layer 772, respectively.
  • a light emitting substance that emits green light may be used for the light emitting layer 771 and the light emitting layer 772, respectively.
  • a light-emitting substance that emits blue light may be used for the light-emitting layer 771 and the light-emitting layer 772, respectively.
  • a display device having such a configuration uses a tandem structure light emitting device and can be said to have an SBS structure. Therefore, it is possible to have both the advantages of the tandem structure and the advantages of the SBS structure. Thereby, it is possible to realize a highly reliable light emitting device that can emit light with high brightness.
  • the light-emitting layer 771 and the light-emitting layer 772 may use light-emitting substances that emit light of different colors.
  • the respective lights are mixed and white light emission is obtained as a whole.
  • a color filter may be provided as the layer 764 shown in FIG. 23F. By transmitting white light through a color filter, light of a desired color can be obtained.
  • FIGS. 23E and 23F show an example in which the light emitting unit 763a has one layer of light emitting layer 771 and the light emitting unit 763b has one layer of light emitting layer 772, the present invention is not limited to this.
  • the light emitting unit 763a and the light emitting unit 763b may each have two or more light emitting layers.
  • the light emitting device may have three or more light emitting units. Note that a configuration having two light emitting units may be referred to as a two-stage tandem structure, and a configuration having three light emitting units may be referred to as a three-stage tandem structure.
  • the light emitting unit 763a has a layer 780a, a light emitting layer 771, and a layer 790a
  • the light emitting unit 763b has a layer 780b, a light emitting layer 772, and a layer 790b.
  • the layer 780a and the layer 780b each have one or more of a hole injection layer, a hole transport layer, and an electron blocking layer. Furthermore, each of the layers 790a and 790b includes one or more of an electron injection layer, an electron transport layer, and a hole blocking layer.
  • the layers 780a and 790a have the opposite configurations, and the layers 780b and 790b also have the opposite configurations.
  • the layer 780a has a hole injection layer and a hole transport layer on the hole injection layer, and further has a hole transport layer. It may have an electronic blocking layer on top of the layer.
  • the layer 790a includes an electron transport layer, and may further include a hole blocking layer between the light emitting layer 771 and the electron transport layer.
  • the layer 780b includes a hole transport layer and may further include an electron blocking layer on the hole transport layer.
  • the layer 790b includes an electron transport layer, an electron injection layer on the electron transport layer, and may further include a hole blocking layer between the light emitting layer 772 and the electron transport layer.
  • the layer 780a has an electron injection layer, an electron transport layer on the electron injection layer, and a positive electrode on the electron transport layer. It may also have a pore blocking layer.
  • the layer 790a includes a hole transport layer, and may further include an electron blocking layer between the light emitting layer 771 and the hole transport layer.
  • the layer 780b includes an electron transport layer and may further include a hole blocking layer on the electron transport layer.
  • the layer 790b may include a hole transport layer, a hole injection layer on the hole transport layer, and may further include an electron blocking layer between the light emitting layer 772 and the hole transport layer. good.
  • charge generation layer 785 When producing a light emitting device with a tandem structure, two light emitting units are stacked with the charge generation layer 785 interposed in between.
  • Charge generation layer 785 has at least a charge generation region.
  • the charge generation layer 785 has a function of injecting electrons into one of the two light emitting units and injecting holes into the other when a voltage is applied between the pair of electrodes.
  • An example of a light emitting device with a tandem structure includes the configurations shown in FIGS. 24A to 24C.
  • FIG. 24A shows a configuration having three light emitting units.
  • a plurality of light emitting units (light emitting unit 763a, light emitting unit 763b, and light emitting unit 763c) are connected in series through charge generation layers 785, respectively.
  • the light emitting unit 763a includes a layer 780a, a light emitting layer 771, and a layer 790a
  • the light emitting unit 763b includes a layer 780b, a light emitting layer 772, and a layer 790b
  • the light emitting unit 763c includes a layer 780b, a light emitting layer 772, and a layer 790b.
  • a layer 780c a structure applicable to the layers 780a and 780b can be used
  • a structure applicable to the layers 790a and 790b can be used.
  • the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 preferably contain light-emitting substances that emit light of the same color.
  • the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 each have a red (R) light-emitting substance (so-called R ⁇ R ⁇ R three-stage tandem structure)
  • the light-emitting layer 771, the light-emitting layer 772 and the light-emitting layer 773 each have a green (G) light-emitting substance (so-called G ⁇ G ⁇ G three-stage tandem structure)
  • the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 each have a green (G) light-emitting substance.
  • a structure having the light emitting substance (B) (so-called B ⁇ B ⁇ B three-stage tandem structure) can be used.
  • a ⁇ b means that a light-emitting unit having a light-emitting substance that emits light b is provided on a light-emitting unit having a light-emitting substance emitting light b, with a charge generation layer interposed therebetween.
  • a, b mean color.
  • a light-emitting substance that emits light of different colors may be used for some or all of the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773.
  • the combinations of the emitted light colors of the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 include, for example, two of them are blue (B) and the other one is yellow (Y), and one of them is red (R). ), the other one is green (G), and the remaining one is blue (B).
  • FIG. 24B shows a configuration in which two light emitting units (a light emitting unit 763a and a light emitting unit 763b) are connected in series via a charge generation layer 785.
  • the light emitting unit 763a includes a layer 780a, a light emitting layer 771a, a light emitting layer 771b, a light emitting layer 771c, and a layer 790a
  • the light emitting unit 763b includes a layer 780b, a light emitting layer 772a, a light emitting layer 772b, and a light emitting layer 772c and a layer 790b.
  • light-emitting substances having complementary colors are selected for the light-emitting layer 771a, the light-emitting layer 771b, and the light-emitting layer 771c, and the light-emitting unit 763a is configured to be capable of emitting white light (W).
  • the light-emitting layer 772a, the light-emitting layer 772b, and the light-emitting layer 772c light-emitting substances having complementary colors are selected, and the light-emitting unit 763b is configured to be capable of emitting white light (W). That is, the configuration shown in FIG. 24B is a two-stage tandem structure of W ⁇ W.
  • the stacking order of the luminescent substances that have a complementary color relationship.
  • the operator can select the optimal stacking order as appropriate.
  • a three-stage tandem structure of W ⁇ W ⁇ W or a tandem structure of four or more stages may also be used.
  • a two-stage tandem structure of B ⁇ Y or Y ⁇ B having a light emitting unit that emits yellow (Y) light and a light emitting unit that emits blue (B) light, a red ( R/G ⁇ B or B ⁇ R/G two-stage tandem structure having a light emitting unit that emits R) and green (G) light, and a light emitting unit that emits blue (B) light, blue (B)
  • B ⁇ Y ⁇ B which has a light-emitting unit that emits yellow (Y) light, and a light-emitting unit that emits blue (B) light, in this order.
  • a three-stage tandem structure of B ⁇ YG ⁇ B which has a light-emitting unit that emits light of B), a light-emitting unit that emits yellow-green (YG) light, and a light-emitting unit that emits blue (B) light in this order.
  • a three-stage B ⁇ G ⁇ B having a light emitting unit that emits blue (B) light, a light emitting unit that emits green (G) light, and a light emitting unit that emits blue (B) light in this order.
  • Examples include a tandem structure.
  • a/b means that one light emitting unit has a light emitting substance that emits light of a and a light emitting substance that emits light of b.
  • a light emitting unit having one light emitting layer and a light emitting unit having multiple light emitting layers may be combined.
  • a plurality of light emitting units (light emitting unit 763a, light emitting unit 763b, and light emitting unit 763c) are connected in series through charge generation layers 785.
  • the light emitting unit 763a includes a layer 780a, a light emitting layer 771, and a layer 790a
  • the light emitting unit 763b includes a layer 780b, a light emitting layer 772a, a light emitting layer 772b, a light emitting layer 772c, and a layer 790b
  • the light emitting unit 763c has a layer 780c, a light emitting layer 773, and a layer 790c.
  • the light emitting unit 763a is a light emitting unit that emits blue (B) light
  • the light emitting unit 763b is a light emitting unit that emits red (R), green (G), and yellow-green (YG) light
  • the light emitting unit 763c is a light emitting unit that emits blue (B) light, and a three-stage tandem structure of B ⁇ R, G, YG ⁇ B, etc. can be applied.
  • the order of the number of stacked layers and colors of the light emitting units is, from the anode side, a two-tier structure of B and Y, a two-tier structure of B and light-emitting unit X, a three-tier structure of B, Y, and B, B, X,
  • the three-layer structure of B is mentioned, and the order of the number of laminated layers and the color of the light-emitting layers in the light-emitting unit
  • the structure can be a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Further, another layer may be provided between the two light emitting layers.
  • a conductive film that transmits visible light is used for the electrode on the side from which light is taken out. Further, it is preferable to use a conductive film that reflects visible light for the electrode on the side from which light is not extracted.
  • the display device has a light emitting device that emits infrared light
  • a conductive film that transmits visible light and infrared light is used for the electrode on the side from which light is extracted
  • a conductive film that transmits visible light and infrared light is used for the electrode on the side from which light is not extracted. It is preferable to use a conductive film that reflects visible light and infrared light.
  • a conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted.
  • the electrode is preferably disposed between the reflective layer and the EL layer 763. That is, the light emitted from the EL layer 763 may be reflected by the reflective layer and extracted from the display device.
  • Metals, alloys, electrically conductive compounds, mixtures thereof, and the like can be used as appropriate as materials for forming the pair of electrodes of the light emitting device.
  • the materials include aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, and yttrium. , metals such as neodymium, and alloys containing these in appropriate combinations.
  • such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and Examples include In-W-Zn oxide.
  • such materials include alloys containing aluminum (aluminum alloys) such as alloys of aluminum, nickel, and lanthanum (Al-Ni-La), alloys of silver and magnesium, and alloys of silver, palladium, and copper ( Examples include alloys containing silver such as APC).
  • such materials include elements belonging to Group 1 or Group 2 of the Periodic Table of Elements (for example, lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, and appropriate combinations of these.
  • Examples include alloys containing carbon dioxide, graphene, etc.
  • a micro optical resonator (microcavity) structure is applied to the light emitting device. Therefore, it is preferable that one of the pair of electrodes included in the light emitting device has an electrode that is transparent and reflective to visible light (semi-transparent/semi-reflective electrode), and the other is an electrode that is reflective to visible light ( It is preferable to have a reflective electrode). Since the light emitting device has a microcavity structure, the light emitted from the light emitting layer can resonate between both electrodes, and the light emitted from the light emitting device can be intensified.
  • the light transmittance of the transparent electrode is 40% or more.
  • an electrode that has a transmittance of visible light (light with a wavelength of 400 nm or more and less than 750 nm) of 40% or more as a transparent electrode of a light-emitting device.
  • the visible light reflectance of the semi-transparent/semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less.
  • the visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less.
  • the resistivity of these electrodes is preferably 1 ⁇ 10 ⁇ 2 ⁇ cm or less.
  • the light emitting device has at least a light emitting layer.
  • the light-emitting device may include a material with high hole injection property, a material with high hole transport property, a hole blocking material, a material with high electron transport property, an electron block material, a material with high electron injection property, as a layer other than the light emitting layer. It may further include a layer containing a material or a bipolar material (a material with high electron transporting properties and hole transporting properties).
  • a light-emitting device may include one or more of the following: a hole injection layer, a hole transport layer, a hole block layer, a charge generation layer, an electron block layer, an electron transport layer, and an electron injection layer. It is possible to have a configuration having the following.
  • the light-emitting device can use either a low-molecular compound or a high-molecular compound, and may also contain an inorganic compound.
  • the layers constituting the light emitting device can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • the light-emitting layer contains one or more types of light-emitting substances.
  • a substance exhibiting a luminescent color such as blue, violet, blue-violet, green, yellow-green, yellow, orange, or red is appropriately used.
  • a substance that emits near-infrared light can also be used as the light-emitting substance.
  • Examples of light-emitting substances include fluorescent materials, phosphorescent materials, TADF materials, quantum dot materials, and the like.
  • fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives. It will be done.
  • an organometallic complex (especially an iridium complex) having a 4H-triazole skeleton, 1H-triazole skeleton, imidazole skeleton, pyrimidine skeleton, pyrazine skeleton, or pyridine skeleton, or a phenylpyridine derivative having an electron-withdrawing group
  • organometallic complexes especially iridium complexes
  • platinum complexes platinum complexes
  • rare earth metal complexes rare earth metal complexes.
  • the light emitting layer may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light emitting substance (guest material).
  • organic compounds host material, assist material, etc.
  • one or both of a material with high hole transport properties (hole transport material) and a material with high electron transport property (electron transport material) can be used.
  • hole transport material a material with high hole-transporting properties that can be used for a hole-transporting layer, which will be described later
  • the electron-transporting material a material with high electron-transporting properties that can be used for an electron-transporting layer, which will be described later, can be used.
  • a bipolar material or a TADF material may be used as one or more kinds of organic compounds.
  • the light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that tends to form an exciplex.
  • ExTET Exciplex-Triplet Energy Transfer
  • a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest energy absorption band of the light-emitting substance energy transfer becomes smoother and luminescence can be efficiently obtained.
  • high efficiency, low voltage drive, and long life of the light emitting device can be achieved at the same time.
  • the hole injection layer is a layer that injects holes from the anode to the hole transport layer, and is a layer containing a material with high hole injection properties.
  • materials with high hole-injecting properties include aromatic amine compounds and composite materials containing a hole-transporting material and an acceptor material (electron-accepting material).
  • hole-transporting material a material with high hole-transporting properties that can be used for a hole-transporting layer, which will be described later, can be used.
  • oxides of metals belonging to Groups 4 to 8 in the periodic table of elements can be used.
  • specific examples include molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide.
  • molybdenum oxide is particularly preferred because it is stable in the atmosphere, has low hygroscopicity, and is easy to handle.
  • an organic acceptor material containing fluorine can also be used.
  • organic acceptor materials such as quinodimethane derivatives, chloranil derivatives, and hexaazatriphenylene derivatives can also be used.
  • a material with high hole injection properties a material containing a hole transporting material and an oxide of a metal belonging to Group 4 to Group 8 in the periodic table of elements (typically, molybdenum oxide) is used. may also be used.
  • the hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light emitting layer.
  • the hole transport layer is a layer containing a hole transporting material.
  • a hole transporting material a substance having a hole mobility of 1 ⁇ 10 ⁇ 6 cm 2 /Vs or more is preferable. Note that materials other than these can also be used as long as they have a higher transportability for holes than for electrons.
  • hole-transporting materials materials with high hole-transporting properties such as ⁇ -electron-rich heteroaromatic compounds (e.g., carbazole derivatives, thiophene derivatives, furan derivatives, etc.), aromatic amines (compounds having an aromatic amine skeleton), etc. is preferred.
  • the electron block layer is provided in contact with the light emitting layer.
  • the electron blocking layer is a layer containing a material that has hole transport properties and is capable of blocking electrons.
  • a material having electron blocking properties among the above-mentioned hole transporting materials can be used.
  • the electron block layer has hole transport properties, it can also be called a hole transport layer. Further, among the hole transport layers, a layer having electron blocking properties can also be referred to as an electron blocking layer.
  • the electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light emitting layer.
  • the electron transport layer is a layer containing an electron transport material.
  • As the electron transporting material a substance having an electron mobility of 1 ⁇ 10 ⁇ 6 cm 2 /Vs or more is preferable. Note that materials other than these can also be used as long as they have a higher ability to transport electrons than holes.
  • metal complexes having a quinoline skeleton metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, etc., as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives with quinoline ligands, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other ⁇ -electron deficient compounds, including nitrogen-containing heteroaromatic compounds Materials with high electron transport properties such as heteroaromatic compounds can be used.
  • the hole blocking layer is provided in contact with the light emitting layer.
  • the hole blocking layer is a layer containing a material that has electron transport properties and is capable of blocking holes.
  • a material having hole blocking properties among the above electron transporting materials can be used.
  • the hole blocking layer has electron transporting properties, it can also be called an electron transporting layer. Further, among the electron transport layers, a layer having hole blocking properties can also be referred to as a hole blocking layer.
  • the electron injection layer is a layer that injects electrons from the cathode to the electron transport layer, and is a layer containing a material with high electron injection properties.
  • Alkali metals, alkaline earth metals, or compounds thereof can be used as materials with high electron injection properties.
  • a composite material containing an electron transport material and a donor material (electron donating material) can also be used as a material with high electron injection properties.
  • the lowest unoccupied molecular orbital (LUMO) level of a material with high electron injection properties should have a small difference from the work function value of the material used for the cathode (specifically, 0.5 eV or less). preferable.
  • the electron injection layer examples include lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF x , where X is an arbitrary number), and 8-(quinolinolato) lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatlithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolatlithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)pheno Alkali metals, alkaline earth metals, or compounds thereof, such as latium (abbreviation: LiPPP), lithium oxide (LiO x ), cesium carbonate, etc., can be used.
  • the electron injection layer may have a laminated structure of two or more layers.
  • the laminated structure includes, for example, a structure in which lithium fluoride is used in the first layer and ytterbium is provided
  • the electron injection layer may include an electron transporting material.
  • an electron transporting material for example, a compound having a lone pair of electrons and an electron-deficient heteroaromatic ring can be used as the electron-transporting material.
  • a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring can be used.
  • the LUMO level of the organic compound having a lone pair of electrons is preferably ⁇ 3.6 eV or more and ⁇ 2.3 eV or less.
  • the highest occupied molecular orbital (HOMO) level and LUMO level of organic compounds can be determined by CV (cyclic voltammetry), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, etc. can be estimated.
  • BPhen 4,7-diphenyl-1,10-phenanthroline
  • NBPhen 2,9-di(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline
  • mPPhen2P 2,9-di(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline
  • mPPhen2P 2,9-di(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline
  • mPPhen2P 2,9-di(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline
  • mPPhen2P 2,4-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine
  • TmPPPyTz 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]
  • the charge generation layer has at least a charge generation region.
  • the charge generation region preferably contains an acceptor material, for example, preferably contains a hole transport material and an acceptor material that can be applied to the hole injection layer described above.
  • the charge generation layer preferably has a layer containing a material with high electron injection properties. This layer can also be called an electron injection buffer layer.
  • the electron injection buffer layer is preferably provided between the charge generation region and the electron transport layer. By providing the electron injection buffer layer, the injection barrier between the charge generation region and the electron transport layer can be relaxed, so that electrons generated in the charge generation region can be easily injected into the electron transport layer.
  • the electron injection buffer layer preferably contains an alkali metal or an alkaline earth metal, and can be configured to contain an alkali metal compound or an alkaline earth metal compound, for example.
  • the electron injection buffer layer preferably has an inorganic compound containing an alkali metal and oxygen, or an inorganic compound containing an alkaline earth metal and oxygen, and an inorganic compound containing lithium and oxygen (oxidized It is more preferable to include lithium (such as lithium (Li 2 O)).
  • materials applicable to the above-mentioned electron injection layer can be suitably used for the electron injection buffer layer.
  • the charge generation layer preferably has a layer containing a material with high electron transport properties. This layer can also be called an electronic relay layer.
  • the electron relay layer is provided between the charge generation region and the electron injection buffer layer.
  • an electron relay layer is preferably provided between the charge generation region and the electron transport layer.
  • the electron relay layer has the function of preventing interaction between the charge generation region and the electron injection buffer layer (or electron transport layer) and smoothly transferring electrons.
  • the electron relay layer preferably uses a phthalocyanine-based material such as copper (II) phthalocyanine (abbreviation: CuPc), or a metal complex having a metal-oxygen bond and an aromatic ligand.
  • a phthalocyanine-based material such as copper (II) phthalocyanine (abbreviation: CuPc)
  • CuPc copper phthalocyanine
  • metal complex having a metal-oxygen bond and an aromatic ligand.
  • charge generation region electron injection buffer layer, and electron relay layer described above may not be clearly distinguishable depending on their cross-sectional shape or characteristics.
  • the charge generation layer may have a donor material instead of an acceptor material.
  • the charge generation layer may include a layer containing an electron transporting material and a donor material, which is applicable to the above-described electron injection layer.
  • the light receiving device has a layer 765 between a pair of electrodes (a lower electrode 761 and an upper electrode 762).
  • Layer 765 has at least one active layer and may have additional layers.
  • FIG. 25B shows a modification of the layer 765 included in the light receiving device shown in FIG. 25A.
  • the light receiving device shown in FIG. 25B includes a layer 766 on the lower electrode 761, an active layer 767 on the layer 766, a layer 768 on the active layer 767, and an upper electrode 762 on the layer 768.
  • the active layer 767 functions as a photoelectric conversion layer.
  • the layer 766 has one or both of a hole transport layer and an electron blocking layer.
  • layer 768 includes one or both of an electron transport layer and a hole blocking layer.
  • the light-receiving device can use either a low-molecular compound or a high-molecular compound, and may also contain an inorganic compound.
  • the layers constituting the light-receiving device can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • the active layer of the light receiving device includes a semiconductor.
  • the semiconductor include inorganic semiconductors such as silicon, and organic semiconductors containing organic compounds.
  • an organic semiconductor is used as the semiconductor included in the active layer.
  • the light-emitting layer and the active layer can be formed by the same method (eg, vacuum evaporation method), and manufacturing equipment can be shared, which is preferable.
  • n-type semiconductor material included in the active layer examples include electron-accepting organic semiconductor materials such as fullerene (eg, C 60 , C 70 , etc.) and fullerene derivatives.
  • fullerene derivatives include [6,6]-Phenyl-C71-butyric acid methyl ester (abbreviation: PC70BM), [6,6]-Phenyl-C61-butyric acid methyl ester (abbreviation: PC60BM), 1',1 '',4',4''-Tetrahydro-di[1,4]methanonaphthaleno[1,2:2',3',56,60:2'',3''][5,6]fullerene-C60 (abbreviation: ICBA), etc.
  • PC70BM [6,6]-Phenyl-C71-butyric acid methyl ester
  • PC60BM [6,6]-Phenyl-C61-butyric acid methyl ester
  • n-type semiconductor materials include perylenetetracarboxylic acid derivatives such as N,N'-dimethyl-3,4,9,10-perylenetetracarboxylic acid diimide (abbreviation: Me-PTCDI), and 2,2' -(5,5'-(thieno[3,2-b]thiophene-2,5-diyl)bis(thiophene-5,2-diyl))bis(methane-1-yl-1-ylidene)dimalononitrile (abbreviation) :FT2TDMN).
  • Me-PTCDI N,N'-dimethyl-3,4,9,10-perylenetetracarboxylic acid diimide
  • T2TDMN 2,2' -(5,5'-(thieno[3,2-b]thiophene-2,5-diyl)bis(thiophene-5,2-diyl))bis(methane-1-yl-1-ylidene)
  • metal complexes having a quinoline skeleton As materials for the n-type semiconductor, metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, Thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, quinone derivatives, etc. Can be mentioned.
  • CuPc copper
  • DBP tetraphenyldibenzoperiflanthene
  • Zinc Phthalocyanine zinc phthalocyanine
  • Examples of materials for the p-type semiconductor include carbazole derivatives, thiophene derivatives, furan derivatives, and compounds having an aromatic amine skeleton.
  • p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, and porphyrins.
  • phthalocyanine derivatives phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, rubrene derivatives, tetracene derivatives, polyphenylene vinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, polythiophene derivatives, and the like.
  • the HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material.
  • the LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.
  • a spherical fullerene as the electron-accepting organic semiconductor material, and to use a nearly flat organic semiconductor material as the electron-donating organic semiconductor material.
  • Molecules with similar shapes tend to aggregate together, and when molecules of the same type aggregate, their molecular orbital energy levels are close, which can improve carrier transport performance.
  • PBDB-T polymer
  • a polymer compound such as a PBDB-T derivative
  • a method of dispersing an acceptor material in PBDB-T or a PBDB-T derivative can be used.
  • the active layer is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor.
  • the active layer may be formed by stacking an n-type semiconductor and a p-type semiconductor.
  • the active layer may include three or more types of materials.
  • a third material may be mixed for the purpose of expanding the absorption wavelength range.
  • the third material may be a low molecular compound or a high molecular compound.
  • the light receiving device further includes a layer containing a material with high hole transport properties, a material with high electron transport properties, a bipolar material (a material with high electron transport properties and high hole transport properties), etc. as a layer other than the active layer. May have.
  • the material is not limited to the above, and may further include a layer containing a material with high hole injection property, a hole blocking material, a material with high electron injection property, an electron blocking material, or the like.
  • materials that can be used in the above-mentioned light-emitting device can be used, for example.
  • hole transport materials or electronic block materials polymer compounds such as poly(3,4-ethylenedioxythiophene)/poly(styrene sulfonic acid) (PEDOT/PSS), molybdenum oxide, iodide Inorganic compounds such as copper (CuI) can be used.
  • PEDOT/PSS poly(3,4-ethylenedioxythiophene)/poly(styrene sulfonic acid)
  • CuI iodide Inorganic compounds
  • an inorganic compound such as zinc oxide (ZnO) or an organic compound such as polyethyleneimine ethoxylate (PEIE) can be used.
  • the light receiving device may have a mixed film of PEIE and ZnO, for example.
  • Display device with light detection function In a display device according to one embodiment of the present invention, light-emitting devices are arranged in a matrix in a display portion, and images can be displayed on the display portion. Moreover, the light receiving devices are arranged in a matrix in the display section, and the display section has one or both of an imaging function and a sensing function in addition to an image display function.
  • the display unit can be used as an image sensor or a touch sensor. That is, by detecting light on the display unit, it is possible to capture an image or detect the proximity or contact of an object (such as a finger, hand, or pen).
  • a light-emitting device can be used as a light source of a sensor.
  • the light-receiving device can detect the reflected light (or scattered light). Therefore, imaging or touch detection is possible even in a dark place.
  • a display device of one embodiment of the present invention includes a light-emitting device and a light-receiving device in a pixel.
  • an organic EL device is used as a light-emitting device
  • an organic photodiode is used as a light-receiving device.
  • the organic EL device and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL device.
  • a display device that includes a light-emitting device and a light-receiving device in a pixel
  • contact or proximity of an object can be detected while displaying an image.
  • some subpixels provide light as a light source, some other subpixels perform light detection, and the remaining subpixels You can also display images.
  • the display device can capture an image using the light-receiving device.
  • the display device of this embodiment can be used as a scanner.
  • an image sensor can be used to capture images for personal authentication using fingerprints, palm prints, iris, pulse shapes (including vein shapes and artery shapes), or faces.
  • an image sensor can be used to image the periphery of the eye, the surface of the eye, or the inside of the eye (fundus, etc.) of the wearable device user. Therefore, the wearable device can be equipped with a function of detecting one or more of the user's blinks, movements of the iris, and movements of the eyelids.
  • the light receiving device can be used as a touch sensor (also referred to as a direct touch sensor), a near touch sensor (also referred to as a hover sensor, a hover touch sensor, a non-contact sensor, a touchless sensor), or the like.
  • a touch sensor also referred to as a direct touch sensor
  • a near touch sensor also referred to as a hover sensor, a hover touch sensor, a non-contact sensor, a touchless sensor
  • the touch sensor or near touch sensor can detect the proximity or contact of an object (such as a finger, hand, or pen).
  • a touch sensor can detect an object when the display device and the object come into direct contact. Furthermore, the near touch sensor can detect an object even if the object does not come into contact with the display device.
  • the display device be configured to be able to detect the target object when the distance between the display device and the target object is in a range of 0.1 mm or more and 300 mm or less, preferably 3 mm or more and 50 mm or less.
  • a display device can have a variable refresh rate. For example, power consumption can be reduced by adjusting the refresh rate (for example, within a range of 1 Hz or more and 240 Hz or less) depending on the content displayed on the display device. Further, the drive frequency of the touch sensor or the near touch sensor may be changed depending on the refresh rate. For example, when the refresh rate of the display device is 120 Hz, the drive frequency of the touch sensor or near touch sensor can be configured to be higher than 120 Hz (typically, 240 Hz). With this configuration, low power consumption can be achieved and the response speed of the touch sensor or near touch sensor can be increased.
  • the display device 200 shown in FIGS. 25C to 25E has a layer 353 having a light receiving device, a functional layer 355, and a layer 357 having a light emitting device between a substrate 351 and a substrate 359.
  • the functional layer 355 has a circuit that drives the light receiving device and a circuit that drives the light emitting device.
  • the functional layer 355 can be provided with one or more of a switch, a transistor, a capacitor, a resistor, a wiring, a terminal, and the like. Note that when the light-emitting device and the light-receiving device are driven by a passive matrix method, a configuration may be adopted in which the switch and the transistor are not provided.
  • the transistor provided in the functional layer 355 the transistor described in Embodiment 1 can be suitably used.
  • the finger 352 in contact with the display device 200 reflects the light emitted by the light emitting device in the layer 357 having the light emitting device
  • the light receiving device in the layer 353 having the light receiving device reflects the light emitted by the light emitting device. Detect reflected light. Thereby, it is possible to detect that the finger 352 has touched the display device 200.
  • FIGS. 25D and 25E it may have a function of detecting or imaging an object that is close to (not in contact with) the display device.
  • FIG. 25D shows an example of detecting a person's finger
  • FIG. 25E shows an example of detecting information around, on the surface, or inside a person's eyes (number of blinks, eyeball movement, eyelid movement, etc.) .
  • the electronic device of this embodiment includes the display device of one embodiment of the present invention in the display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in display units of various electronic devices.
  • Examples of electronic devices include electronic devices with relatively large screens such as television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and digital cameras. , digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like.
  • the display device of one embodiment of the present invention can improve definition, so it can be suitably used for electronic devices having a relatively small display portion.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), VR devices such as head-mounted displays, glasses-type AR devices, MR devices, and other head-mounted devices. Examples include wearable devices that can be attached to the device.
  • the display device of one embodiment of the present invention includes HD (number of pixels 1280 x 720), FHD (number of pixels 1920 x 1080), WQHD (number of pixels 2560 x 1440), WQXGA (number of pixels 2560 x 1600), and 4K (number of pixels It is preferable to have an extremely high resolution such as 3840 ⁇ 2160) or 8K (pixel count 7680 ⁇ 4320). In particular, it is preferable to set the resolution to 4K, 8K, or higher.
  • the pixel density (definition) in the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, and 3000 ppi or more. More preferably, it is 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment includes sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage). , power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared rays).
  • the electronic device of this embodiment can have various functions. For example, functions that display various information (still images, videos, text images, etc.) on the display, touch panel functions, calendars, functions that display date or time, etc., functions that execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, etc.
  • FIGS. 26A to 26D An example of a wearable device that can be worn on the head will be described with reference to FIGS. 26A to 26D.
  • These wearable devices have at least one of a function of displaying AR content, a function of displaying VR content, a function of displaying SR content, and a function of displaying MR content.
  • an electronic device has a function of displaying at least one content such as AR, VR, SR, and MR, it becomes possible to enhance the user's immersive feeling.
  • An electronic device 700A shown in FIG. 26A and an electronic device 700B shown in FIG. 26B each include a pair of display panels 751, a pair of casings 721, a communication section (not shown), and a pair of mounting sections 723. , a control section (not shown), an imaging section (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of extremely high definition display can be achieved.
  • the electronic device 700A and the electronic device 700B can each project the image displayed on the display panel 751 onto the display area 756 of the optical member 753. Since the optical member 753 has translucency, the user can see the image displayed in the display area superimposed on the transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.
  • the electronic device 700A and the electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Further, the electronic device 700A and the electronic device 700B are each equipped with an acceleration sensor such as a gyro sensor to detect the direction of the user's head and display an image corresponding to the direction in the display area 756. You can also.
  • an acceleration sensor such as a gyro sensor to detect the direction of the user's head and display an image corresponding to the direction in the display area 756. You can also.
  • the communication unit has a wireless communication device, and the wireless communication device can supply video signals and the like. Note that instead of or in addition to the wireless communication device, a connector to which a cable to which a video signal and a power supply potential are supplied may be connected may be provided.
  • the electronic device 700A and the electronic device 700B are provided with batteries, and can be charged wirelessly and/or by wire.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a user's tap operation, slide operation, etc., and execute various processes. For example, a tap operation can be used to pause or restart a video, and a slide operation can be used to fast forward or rewind. Further, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.
  • Various touch sensors can be applied to the touch sensor module.
  • various methods such as a capacitance method, a resistive film method, an infrared method, an electromagnetic induction method, a surface acoustic wave method, an optical method, etc. can be adopted.
  • a photoelectric conversion device (also referred to as a photoelectric conversion element) can be used as the light receiving device.
  • a photoelectric conversion device also referred to as a photoelectric conversion element
  • One or both of an inorganic semiconductor and an organic semiconductor can be used in the active layer of a photoelectric conversion device.
  • the electronic device 800A shown in FIG. 26C and the electronic device 800B shown in FIG. 26D each include a pair of display sections 820, a housing 821, a communication section 822, a pair of mounting sections 823, and a control section 824. It has a pair of imaging units 825 and a pair of lenses 832.
  • a display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of extremely high definition display can be achieved. This allows the user to feel highly immersive.
  • the display section 820 is provided inside the housing 821 at a position where it can be visually recognized through the lens 832. Furthermore, by displaying different images on the pair of display units 820, three-dimensional display using parallax can be performed.
  • the electronic device 800A and the electronic device 800B can each be said to be an electronic device for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • the electronic device 800A and the electronic device 800B each have a mechanism that can adjust the left and right positions of the lens 832 and the display unit 820 so that they are in optimal positions according to the position of the user's eyes. It is preferable that you do so. Further, it is preferable to have a mechanism for adjusting the focus by changing the distance between the lens 832 and the display section 820.
  • the mounting portion 823 allows the user to wear the electronic device 800A or the electronic device 800B on the head.
  • the shape is illustrated as a temple (also referred to as a joint or temple) of glasses, but the shape is not limited to this.
  • the mounting portion 823 only needs to be worn by the user, and may have a helmet-shaped or band-shaped shape, for example.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • a plurality of cameras may be provided so as to be able to support a plurality of angles of view such as telephoto and wide-angle.
  • a distance measuring sensor (hereinafter also referred to as a detection unit) that can measure the distance to an object may be provided. That is, the imaging unit 825 is one aspect of a detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism in order to function as a bone conduction earphone.
  • a configuration having the vibration mechanism can be applied to one or more of the display section 820, the housing 821, and the mounting section 823.
  • the electronic device 800A and the electronic device 800B may each have an input terminal.
  • a cable for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device can be connected to the input terminal.
  • An electronic device may have a function of wirelessly communicating with the earphone 750.
  • Earphone 750 includes a communication section (not shown) and has a wireless communication function.
  • Earphone 750 can receive information (eg, audio data) from an electronic device using a wireless communication function.
  • electronic device 700A shown in FIG. 26A has a function of transmitting information to earphone 750 using a wireless communication function.
  • electronic device 800A shown in FIG. 26C has a function of transmitting information to earphone 750 using a wireless communication function.
  • the electronic device may have an earphone section.
  • Electronic device 700B shown in FIG. 26B includes earphone section 727.
  • the earphone section 727 and the control section can be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone section 727 and the control section may be arranged inside the housing 721 or the mounting section 723.
  • the electronic device 800B shown in FIG. 26D has an earphone section 827.
  • the earphone section 827 and the control section 824 can be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone section 827 and the control section 824 may be arranged inside the housing 821 or the mounting section 823.
  • the earphone section 827 and the mounting section 823 may include magnets. Thereby, the earphone section 827 can be fixed to the mounting section 823 by magnetic force, which is preferable because it can be easily stored.
  • the electronic device may have an audio output terminal to which earphones, headphones, or the like can be connected. Further, the electronic device may have one or both of an audio input terminal and an audio input mechanism.
  • the audio input mechanism for example, a sound collection device such as a microphone can be used.
  • the electronic device may be provided with a function as a so-called headset.
  • the electronic device can be either a glasses type (electronic device 700A, electronic device 700B, etc.) or a goggle type (electronic device 800A, electronic device 800B, etc.). It is also suitable for application.
  • An electronic device can transmit information to earphones by wire or wirelessly.
  • An electronic device 6500 shown in FIG. 27A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like.
  • the display section 6502 has a touch panel function.
  • a display device of one embodiment of the present invention can be applied to the display portion 6502.
  • FIG. 27B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a light-transmitting protection member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, A printed circuit board 6517, a battery 6518, etc. are arranged.
  • a display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 with an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded part.
  • An IC6516 is mounted on the FPC6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • a flexible display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while suppressing the thickness of the electronic device. Further, by folding back a part of the display panel 6511 and arranging the connection portion with the FPC 6515 on the back side of the display portion 6502, an electronic device with a narrow frame can be realized.
  • FIG. 27C shows an example of a television device.
  • a television device 7100 has a display section 7000 built into a housing 7101. Here, a configuration in which a casing 7101 is supported by a stand 7103 is shown.
  • a display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the television device 7100 shown in FIG. 27C can be operated using an operation switch included in the housing 7101 and a separate remote controller 7111.
  • the display section 7000 may include a touch sensor, and the television device 7100 may be operated by touching the display section 7000 with a finger or the like.
  • the remote control device 7111 may have a display unit that displays information output from the remote control device 7111. Using operation keys or a touch panel included in the remote controller 7111, the channel and volume can be controlled, and the video displayed on the display section 7000 can be controlled.
  • the television device 7100 is configured to include a receiver, a modem, and the like.
  • the receiver can receive general television broadcasts. Also, by connecting to a wired or wireless communication network via a modem, information can be communicated in one direction (from a sender to a receiver) or in two directions (between a sender and a receiver, or between receivers, etc.). is also possible.
  • FIG. 27D shows an example of a notebook personal computer.
  • the notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like.
  • a display section 7000 is incorporated into the housing 7211.
  • a display device of one embodiment of the present invention can be applied to the display portion 7000.
  • FIGS. 27E and 27F An example of digital signage is shown in FIGS. 27E and 27F.
  • the digital signage 7300 shown in FIG. 27E includes a housing 7301, a display section 7000, a speaker 7303, and the like. Furthermore, it can have an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.
  • FIG. 27F shows a digital signage 7400 attached to a cylindrical pillar 7401.
  • Digital signage 7400 has a display section 7000 provided along the curved surface of pillar 7401.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the wider the display section 7000 is, the more information that can be provided at once can be increased. Furthermore, the wider the display section 7000 is, the easier it is to attract people's attention, and for example, the effectiveness of advertising can be increased.
  • a touch panel By applying a touch panel to the display section 7000, not only images or videos can be displayed on the display section 7000, but also the user can operate it intuitively, which is preferable. Further, when used for providing information such as route information or traffic information, usability can be improved by intuitive operation.
  • the digital signage 7300 or the digital signage 7400 can cooperate with an information terminal 7311 or an information terminal 7411 such as a smartphone owned by the user through wireless communication.
  • advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched.
  • the digital signage 7300 or the digital signage 7400 can execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the electronic device shown in FIGS. 28A to 28G includes a housing 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, Speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared rays. (including a function of detecting, detecting, or measuring), a microphone 9008, and the like.
  • the display device of one embodiment of the present invention can be applied to the display portion 9001.
  • the electronic devices shown in FIGS. 28A to 28G have various functions. For example, functions to display various information (still images, videos, text images, etc.) on a display unit, touch panel functions, functions to display a calendar, date or time, etc., functions to control processing using various software (programs), It can have a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, and the like. Note that the functions of the electronic device are not limited to these, and can have various functions.
  • the electronic device may have multiple display units. Furthermore, the electronic device may be equipped with a camera, etc., and have the function of taking still images or videos and saving them on a recording medium (external or built into the camera), the function of displaying the taken images on a display unit, etc. .
  • FIGS. 28A to 28G The details of the electronic device shown in FIGS. 28A to 28G will be described below.
  • FIG. 28A is a perspective view showing the mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as a smartphone, for example.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces thereof.
  • FIG. 28A shows an example in which three icons 9050 are displayed.
  • information 9051 indicated by a dashed rectangle can also be displayed on another surface of the display section 9001. Examples of the information 9051 include notification of incoming e-mail, SNS, telephone, etc., title of e-mail or SNS, sender's name, date and time, remaining battery level, radio field strength, and the like.
  • an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
  • FIG. 28B is a perspective view showing the mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are displayed on different surfaces.
  • the user can check the information 9053 displayed at a position visible from above the mobile information terminal 9102 while storing the mobile information terminal 9102 in the chest pocket of clothes.
  • the user can check the display without taking out the mobile information terminal 9102 from his pocket, and can, for example, determine whether or not to accept a call.
  • FIG. 28C is a perspective view showing the tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text viewing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display section 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000, operation keys 9005 as operation buttons on the side of the housing 9000, and connection buttons on the bottom. It has a terminal 9006.
  • FIG. 28D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used, for example, as a smart watch (registered trademark).
  • the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface.
  • the mobile information terminal 9200 can also make a hands-free call by mutually communicating with a headset capable of wireless communication, for example.
  • the mobile information terminal 9200 can also perform data transmission and charging with other information terminals through the connection terminal 9006. Note that the charging operation may be performed by wireless power supply.
  • FIGS. 28E to 28G are perspective views showing a foldable portable information terminal 9201. Further, FIG. 28E is a perspective view of the portable information terminal 9201 in an expanded state, FIG. 28G is a folded state, and FIG. 28F is a perspective view of a state in the middle of changing from one of FIGS. 28E and 28G to the other.
  • the portable information terminal 9201 has excellent portability in a folded state, and has excellent visibility in display due to its wide seamless display area in an unfolded state.
  • a display portion 9001 included in a mobile information terminal 9201 is supported by three casings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.

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PCT/IB2023/053329 2022-04-14 2023-04-03 半導体装置、及び、半導体装置の作製方法 Ceased WO2023199160A1 (ja)

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CN202380033837.3A CN119013783A (zh) 2022-04-14 2023-04-03 半导体装置及半导体装置的制造方法
JP2024515177A JPWO2023199160A1 (https=) 2022-04-14 2023-04-03
US18/851,736 US20250221037A1 (en) 2022-04-14 2023-04-03 Semiconductor device and method of manufacturing semiconductor device
KR1020247037521A KR20250003781A (ko) 2022-04-14 2023-04-03 반도체 장치 및 반도체 장치의 제작 방법

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KR20250003781A (ko) 2025-01-07
CN119013783A (zh) 2024-11-22

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