WO2023197340A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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Publication number
WO2023197340A1
WO2023197340A1 PCT/CN2022/087494 CN2022087494W WO2023197340A1 WO 2023197340 A1 WO2023197340 A1 WO 2023197340A1 CN 2022087494 W CN2022087494 W CN 2022087494W WO 2023197340 A1 WO2023197340 A1 WO 2023197340A1
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WIPO (PCT)
Prior art keywords
groove
etching
conductive layer
layer
mask layer
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Ceased
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PCT/CN2022/087494
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English (en)
French (fr)
Inventor
徐陈明
林红波
武贺
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/842,788 priority Critical patent/US12300502B2/en
Publication of WO2023197340A1 publication Critical patent/WO2023197340A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor manufacturing technology, and in particular, to a method of manufacturing a semiconductor structure and a semiconductor structure.
  • the packaging structure includes a rewiring layer.
  • the rewiring layer is disposed on the side of the chip with contact pads.
  • the rewiring layer has a plurality of metal lines. One end of each metal line is connected to the contact pad, and the other end of the metal line is provided with a welding Structure, reasonable setting of the shape of metal wires can change the arrangement of the welding structure.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including:
  • Dry etching removes part of the conductive layer to form a first groove, the depth of the first groove is less than the thickness of the conductive layer, and there is polymer residue on the groove wall of the first groove;
  • a passivation layer is formed filling the second groove.
  • dry etching removes part of the conductive layer to form the first groove, including:
  • the conductive layer is etched to form the first groove.
  • the conductive layer corresponding to the groove wall and groove bottom of the first groove is removed to form a conductive line and a second groove formed between adjacent conductive lines;
  • a second mask layer is formed on the conductive layer, the second mask layer has a second etching opening, the second etching opening is disposed facing the first groove, and the second etching opening
  • the orthographic projected area on the substrate is greater than the orthographic projected area of the first etching opening on the substrate;
  • the conductive layer is etched using the second mask layer as a mask to form the conductive line and the second groove.
  • forming the second mask layer on the conductive layer includes:
  • the first mask layer is shrunk to increase the orthographic projection area of the first etching opening on the substrate to form the second mask layer and
  • the second etching opening is located on the second mask layer.
  • shrinking the first mask layer includes:
  • the first mask layer is etched to remove sidewalls of the first etching opening.
  • etching the first mask layer includes dry etching, and the etching gas of the dry etching includes at least one of oxygen, hydrogen, and nitrogen.
  • the conductive layer is etched using the first mask layer as a mask to form a first groove, and the depth of the first groove is the thickness of the conductive layer. 1/3-1/2.
  • the distance between the second etching opening and the groove wall of the first groove includes 50 nm-100 nm.
  • etching the conductive layer using the second mask layer as a mask to form the second groove includes:
  • the conductive layer and part of the substrate are etched to form the second groove.
  • the conductive layer is etched by dry etching using the first mask layer as a mask; and dry etching is performed by using the second mask layer as a mask.
  • the conductive layer is etched.
  • removing the conductive layer corresponding to the groove wall and groove bottom of the first groove to form the conductive line and the second groove includes: intermediate etching;
  • the intermediate etching includes:
  • An intermediate mask layer is formed on the conductive layer.
  • the intermediate mask layer has an intermediate etching opening.
  • the intermediate etching opening is disposed facing the first groove.
  • the intermediate etching opening is located on the substrate.
  • the orthographic projection area of the first etching opening on the substrate is larger than the orthographic projection area of the middle etching opening on the substrate, and the orthographic projection area of the middle etching opening on the substrate is smaller than the orthographic projection of the second etching opening on the substrate. area;
  • the conductive layer is etched to form a middle groove.
  • the depth of the middle groove is greater than the depth of the first groove and less than the depth of the second groove. depth.
  • the conductive layer corresponding to the groove wall and groove bottom of the first groove is removed to form the conductive line and the second groove, and include:
  • the conductive layer corresponding to the groove wall and groove bottom of the middle groove is removed to form the conductive line and the second groove.
  • forming an intermediate mask layer on the conductive layer includes:
  • the first mask layer is shrunk to increase the orthographic projection area of the first etching opening on the substrate, and the intermediate mask layer is formed and located The second etching opening on the intermediate mask layer.
  • shrinking the intermediate mask layer includes:
  • the first mask layer is etched to remove sidewalls of the first etching opening.
  • etching the intermediate mask layer includes dry etching, and the etching gas of the dry etching includes at least one of oxygen, hydrogen, and nitrogen.
  • the intermediate etching is performed multiple times, and in each intermediate etching, the orthogonal projected area of the intermediate etching opening on the substrate is larger than that in the previous intermediate etching.
  • the orthogonal projected area of the middle etching opening on the substrate is larger than that in the previous intermediate etching.
  • forming a passivation layer, before filling the second groove further includes:
  • forming a passivation layer before filling the second groove further includes: after removing the second mask layer,
  • An insulating layer is formed covering the conductive line and the groove wall and groove bottom of the second groove.
  • the conductive layer includes a plurality of sub-conductive layers arranged sequentially on the substrate.
  • embodiments of the present disclosure provide a semiconductor structure, including a semiconductor structure formed by the above-mentioned manufacturing method of a semiconductor structure.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure.
  • the method for manufacturing a semiconductor structure includes: providing a substrate covered with a conductive layer; dry etching to remove part of the conductive layer to form a first groove, and a first groove.
  • the depth of the groove is less than the thickness of the conductive layer, and there is polymer residue on the groove wall of the first groove; remove the corresponding part of the conductive layer on the groove wall and bottom of the first groove to form conductive lines and adjacent conductive lines the second groove between; forming a passivation layer, which is filled in the second groove.
  • the polymer deposited on the groove wall of the first groove can be removed at the same time, thereby avoiding premature sealing when the passivation layer is subsequently filled in the second groove, further preventing The presence of gaps inside the passivation layer is beneficial to improving the performance of the semiconductor structure.
  • Figure 1 is a schematic structural diagram of a conductive line formed by dry etching
  • Figure 2 is a schematic structural diagram of a passivation layer formed on a conductive line
  • Figure 3 is a step flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of forming a first mask layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of forming a first groove in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of forming a second mask layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 7 is a structural schematic diagram 1 of forming a second groove in the manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 8 is a schematic structural diagram of forming a passivation layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of forming an intermediate mask layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of forming an intermediate groove in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram 2 of the structure of forming a second mask layer in the manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 12 is a schematic diagram 2 of the structure of forming a second groove in the manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 13 is a second structural schematic diagram of forming a passivation layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • a passivation layer covering the metal lines and filling the grooves between adjacent metal lines needs to be formed to perform the formed metal lines. protection while ensuring that adjacent metal wires are insulated from each other.
  • the passivation layer formed through the above process flow is of relatively low quality and has relatively poor performance.
  • Figure 1 is a schematic structural diagram of a conductive line formed by dry etching
  • Figure 2 is a schematic structural diagram of a passivation layer formed on a conductive line.
  • the inventor of the present disclosure found that, as shown in FIG. 1 , after performing a dry etching on the metal layer in the redistribution layer to obtain the metal lines 20 , the side walls of the grooves between adjacent metal lines 20 are easily Polymer residue 40 is formed; as shown in Figure 2, due to the existence of polymer residue 40, when the passivation layer 60 is subsequently formed, the passivation layer 60 in the groove is easily sealed in advance, resulting in gaps in the passivation layer 60. , making the performance of the passivation layer 60 relatively poor.
  • inventions of the present disclosure provide a method of manufacturing a semiconductor structure and a semiconductor structure.
  • the method of manufacturing a semiconductor structure includes: providing a substrate covered with a conductive layer; dry etching to remove part of the conductive layer to form a first recess. groove, the depth of the first groove is less than the thickness of the conductive layer, and there is polymer residue on the groove wall of the first groove; remove the corresponding part of the conductive layer on the groove wall of the first groove and the bottom of the groove to form a conductive line and a
  • the second groove between adjacent conductive lines forms a passivation layer, which is filled in the second groove.
  • the polymer deposited on the groove wall of the first groove can be removed at the same time, thereby avoiding premature sealing when the passivation layer is subsequently filled in the second groove, further preventing The presence of gaps inside the passivation layer is beneficial to improving the performance of the semiconductor structure.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps S101 to S104.
  • Step S101 Provide a substrate covered with a conductive layer.
  • the substrate 10 can be a semiconductor substrate, such as single crystal silicon, polycrystalline silicon, amorphous silicon or silicon germanium (SiGe), or a mixed semiconductor structure, such as silicon carbide, antimony Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof. This embodiment does not limit it here.
  • the conductive layer 30 may be formed by electroplating or deposition.
  • the conductive layer 30 may be connected to contact pads provided inside the substrate 10 , so that the semiconductor structure can subsequently be electrically connected to the outside through the conductive layer 30 .
  • the material of the conductive layer 30 may include, for example, conductive metals and/or compounds such as aluminum, titanium, tungsten, and titanium nitride.
  • the conductive layer 30 may include a plurality of sub-conductive layers sequentially disposed on the substrate 10 .
  • the conductive layer 30 may include three sub-conductive layers arranged sequentially on the substrate 10 , namely a first sub-conductive layer 301 , a second sub-conductive layer 302 , and a third sub-conductive layer 303 .
  • the material of the first sub-conductive layer 301 may include titanium
  • the material of the second sub-conductive layer 302 may include aluminum
  • the material of the third sub-conductive layer 303 may include titanium nitride. It should be noted that this embodiment includes but is not limited to this.
  • Step S102 Dry etching removes part of the conductive layer to form a first groove, the depth of the first groove is less than the thickness of the conductive layer, and a polymer is formed on the groove wall of the first groove.
  • dry etching removes part of the conductive layer 30 , including forming a first mask layer 50 on the conductive layer 30 , and having a first etching opening 51 on the first mask layer 50 .
  • the material of the first mask layer 50 may include photoresist, and part of the photoresist is removed through an exposure and development process to form the first etching opening 51 .
  • dry etching removes part of the conductive layer 30 , which also includes: after forming the first mask layer 50 on the conductive layer 30 , using the first mask layer 50 as a mask, etching the conductive layer 30 Etching is performed to form the first groove 31 .
  • the conductive layer 30 is dry etched using the first mask layer 50 as a mask. Dry etching is a technology that uses plasma to etch thin films. During the etching process, the plasma is bombarded and etched. The surface of the object, thereby removing the etched object and achieving the purpose of etching. In this embodiment, the conductive layer 30 is removed by dry etching. During the process of plasma bombardment of the conductive layer 30, a bond will be generated, and the bond will remain on the groove wall of the first groove 31. The remaining bond is 40 is the polymer residue.
  • the depth of the formed first groove 31 can be controlled by controlling the time of dry etching, so that the depth of the first groove 31 is smaller than the thickness of the conductive layer 30 for subsequent use.
  • the polymer residue 40 on the wall of the first groove 31 is removed.
  • Step S103 Remove part of the conductive layer corresponding to the groove wall and groove bottom of the first groove to form conductive lines and a second groove between adjacent conductive lines.
  • the conductive lines 20 can be formed.
  • the formed conductive lines 20 are redistribution lines, and the grooves between adjacent conductive lines 20 are the third conductive lines 20. Two grooves 33.
  • the polymer residue 40 deposited on the groove wall of the first groove 31 can be removed, thereby avoiding subsequent filling of the passivation layer 80 in the second groove 33 sealing in advance (even if there is still polymer residue on the side wall of the second groove 33, the volume of the polymer residue is much smaller than the volume of the polymer residue in one dry etching shown in Figure 1), thereby avoiding A gap appears inside the passivation layer 80, which is beneficial to improving the performance of the semiconductor structure.
  • the conductive layer 30 corresponding to the groove wall and groove bottom of the first groove 31 is removed to form the conductive line 20 and the second groove 33 located between the adjacent conductive lines 20 , including: forming a second mask layer 60 on the conductive layer 30 , the second mask layer 60 having a second etching opening 61 , the second etching opening 61 facing the first groove 31 , and the second etching opening 61
  • the orthographic projection area on the substrate 10 is larger than the orthographic projection area of the first etching opening 51 on the substrate 10 .
  • the second mask layer 60 may cover the first mask layer 50 , and the second etching opening 61 faces the first groove 31 , and since the first etching opening 51 faces the first groove 31 , the second etching opening 61 faces the first etching opening 51, and the orthographic projection area of the second etching opening 61 on the substrate 10 is larger than the orthographic projection area of the first etching opening 51 on the substrate 10, so as to facilitate the subsequent removal of the first recess.
  • the portion of the conductive layer 30 corresponding to the groove wall of the groove 31 is removed together with the polymer residue 40 deposited on the groove wall of the first groove 31 .
  • forming the second mask layer 60 on the conductive layer 30 includes: after forming the first groove 31, shrinking the first mask layer 50 to increase the area of the first etching opening 51 on the substrate. 10, a second mask layer 60 and a second etching opening 61 located on the second mask layer 60 are formed.
  • the second mask layer 60 is also the first mask layer 50 after shrinkage processing. Since the orthographic projection area of the first etching opening 51 on the substrate 10 increases, that is, the second etching opening 51 is formed.
  • the orthographic projection area of the opening 61 on the substrate 10 is larger than the orthographic projection area of the first etching opening 51 on the substrate 10 , so that when subsequent etching is performed using the second mask layer 60 as a mask, not only the first groove 31 can be etched
  • the part of the conductive layer 30 corresponding to the groove bottom can also be etched to the part of the conductive layer 30 corresponding to the groove wall of the first groove 31, so as to facilitate the subsequent removal of the part of the conductive layer 30 corresponding to the groove wall of the first groove 31, so that the part of the conductive layer 30 corresponding to the groove wall of the first groove 31 can be deposited on the first groove 31.
  • the polymer residue 40 on the wall of a groove 31 is also removed.
  • shrinking the first mask layer 50 includes etching the first mask layer 50 to remove the sidewalls of the first etching opening 51 .
  • the orthographic projection area of the first etching opening 51 on the substrate 10 can be increased, thereby forming the second etching opening 61 , and the formed second etching opening 61 faces the first groove. 31.
  • the first mask layer 50 may be dry etched to remove the sidewalls of the first etching opening 51 .
  • the first mask layer 50 is overall thinned from the upper surface and sidewalls of the first mask layer 50 through dry etching to expand the first etching opening 51 to obtain the first etching opening 51 .
  • the second mask layer 60 ie, the thinned first mask layer
  • the second etching opening 61 ie, the expanded first etching opening located in the second mask layer 60.
  • the etching gas for dry etching may include at least one of oxygen, hydrogen, and nitrogen.
  • the conductive layer 30 corresponding to the groove wall and groove bottom of the first groove 31 is removed to form the conductive line 20 and the second groove 33 between the adjacent conductive lines 20 , and also includes : After the second mask layer 60 is formed, the conductive layer 30 is etched using the second mask layer 60 as a mask to form the conductive lines 20 and the second grooves 33 .
  • the portion of the conductive layer 30 corresponding to the groove bottom of the first groove 31 will continue to be etched until the etching penetrates the conductive layer 30 to form the conductive line 20 .
  • the conductive layer 30 corresponding to the groove wall of the first groove 31 will continue to be etched to remove the polymer residue 40 deposited on the groove wall of the first groove 31 to avoid subsequent filling in the second groove 33
  • the passivation layer 80 is sealed in advance to further avoid gaps inside the passivation layer 80 and is beneficial to improving the performance of the semiconductor structure.
  • the distance D between the second etching opening 61 and the groove wall of the first groove 31 may include 50 nm-100 nm.
  • the volume of the removed polymer residue 40 may be adjusted. , in order to further remove the polymer residue 40 deposited on the groove wall of the first groove 31 to avoid premature sealing when the passivation layer 80 is subsequently filled in the second groove 33, thereby further improving the semiconductor structure performance.
  • the conductive layer 30 is etched using the second mask layer 60 as a mask to form the second groove 33 , which further includes: etching the conductive layer 30 using the second mask layer 60 as a mask; Part of the base 10 forms a second groove 33 .
  • the bottom of the formed second groove 33 is the base 10
  • the groove wall of the formed second groove 33 includes the base 10 and the conductive layer 30 .
  • etching the conductive layer 30 using the second mask layer 60 as a mask further includes etching the conductive layer 30 by dry etching using the second mask layer 60 as a mask.
  • plasma is used to bombard the conductive layer 30.
  • the plasma can also bombard the polymer residue 40 on the groove wall of the first groove 31, so that the polymer residue 40 is broken into debris, thereby Further removal of polymer residue 40.
  • the polymer residue 40 is removed, and at the same time, new polymer residue 40 may be formed on the groove wall of the second groove 33.
  • the volume of the residue 40 is smaller than the volume of the polymer residue 40 on the first groove 31 , which can avoid premature sealing when the passivation layer 80 is subsequently filled in the second groove 33 , thereby improving the performance of the semiconductor structure.
  • Step S104 Form a passivation layer and fill it in the second groove.
  • forming the passivation layer 80 which before filling the second groove 33 , further includes: removing the second mask layer 60 .
  • the second mask layer 60 can be removed by cleaning with a cleaning solution.
  • a cleaning solution When etching the portion of the conductive layer 30 corresponding to the groove wall of the first groove 31 , debris of the polymer residue 40 deposited on the groove wall of the first groove 31 may fall to the bottom of the second groove 33 .
  • debris dropped on the bottom of the second groove 33 can be further removed, which is beneficial to further improving the performance of the semiconductor structure.
  • the passivation layer 80 and filling it in the second groove 33 also includes: after removing the second mask layer 60, forming an insulating layer 70 covering the conductive line 20 and the groove of the second groove 33. wall and tank bottom. By forming the insulating layer 70, adjacent conductive lines 20 can be isolated.
  • the material of the insulating layer 70 may include, for example, nitride, oxide, oxynitride, and the like.
  • a passivation layer 80 covering the insulating layer 70 may be formed.
  • the passivation layer 80 is filled in the second groove 33 , and the passivation layer 80 also covers the conductive line 20 .
  • the passivation layer 80 may be made of, for example, polyimide, thereby buffering stress and protecting the conductive line 20 .
  • the passivation layer 80 can also play a planarizing role.
  • the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which includes: providing a substrate 10 covered with a conductive layer 30; dry etching to remove part of the conductive layer 30 to form a first groove 31.
  • the first groove 31 The depth is less than the thickness of the conductive layer 30, and polymer residue 40 is formed on the groove wall of the first groove 31; the corresponding portion of the conductive layer 30 on the groove wall and groove bottom of the first groove 31 is removed to form the conductive line 20 and the conductive layer 30 located on the groove wall.
  • the second groove 33 between adjacent conductive lines 20 forms a passivation layer 80 , which is filled in the second groove 33 .
  • the polymer residue 40 deposited on the groove wall of the first groove 31 can be removed at the same time, thereby avoiding subsequent filling of the passivation layer in the second groove 33. Sealing in advance at 80 o'clock can further avoid the occurrence of gaps inside the passivation layer 80 , which is beneficial to improving the performance of the semiconductor structure.
  • the first mask layer 50 is used as a mask to etch the conductive layer 30 to form the first groove 31 , and further includes: the depth H1 of the first groove 31 is the conductive layer 30 Thickness 1/3-1/2 of H2.
  • the polymer residue 40 formed on the wall of the first groove 31 facilitates subsequent etching of the wall of the first groove 31 , and peeling off the first groove 31 is beneficial to further removing the polymer residue 40, thereby further improving the performance of the semiconductor structure.
  • the depth of the formed first groove 31 can also be adjusted by controlling the etching time.
  • the conductive layer 30 is etched to form the first groove 31.
  • the etching time may be a first period, and the corresponding groove walls and groove bottoms of the first groove 31 are removed.
  • the etching time of part of the conductive layer 30 to form the conductive line 20 and the second groove 33 can be a second period.
  • the sum of the first period and the second period is the total etching time.
  • the performance of the semiconductor structure can make the first period 1/3-1/2 of the total etching time.
  • the second groove 33 is formed through one shrinking process and one etching process, thereby removing the polymer residue 40 on the first groove 31 .
  • the corresponding portion of the conductive layer 30 on the groove wall and groove bottom of the first groove 31 is removed.
  • Forming the conductive line 20 and the second groove 33 may also include intermediate etching. By providing an intermediate etching step, it is advantageous to further remove the polymer residue 40 on the groove wall of the first groove 31 .
  • the intermediate etching step may include: forming an intermediate mask layer 90 on the conductive layer 30 .
  • the intermediate mask layer 90 has an intermediate etching opening 91 .
  • the intermediate etching opening 91 is disposed facing the first groove 31 .
  • the orthogonal projected area of the etching opening 91 on the substrate 10 is larger than the orthographic projected area of the first etching opening 51 on the substrate 10
  • the orthogonal projected area of the middle etching opening 91 on the substrate 10 is smaller than that of the second etching opening 61 on the substrate 10 Orthographic projection area.
  • forming the intermediate mask layer 90 on the conductive layer 30 includes: after forming the first groove 31 , shrinking the first mask layer 50 to increase the opening of the first etching opening 51 on the substrate 10 An intermediate mask layer 90 and an intermediate etching opening 91 located on the intermediate mask layer 90 are formed on the orthographic projection area.
  • the intermediate mask layer 90 is also the first mask layer 50 after the shrinkage process. Since the orthographic projection area of the first etching opening 51 on the substrate 10 increases, that is, the formed intermediate etching opening 91 has a larger area on the substrate 10 . The orthographic projection area is larger than the orthographic projection area of the first etching opening 51 on the substrate 10 , so that when subsequent etching is performed using the intermediate mask layer 90 as a mask, not only the portion of the conductive layer 30 corresponding to the groove bottom of the first groove 31 can be etched , it can also etch the part of the conductive layer 30 corresponding to the groove wall of the first groove 31, so as to facilitate the subsequent removal of the part of the conductive layer 30 corresponding to the groove wall of the first groove 31, thereby making the deposited on the groove wall of the first groove 31 Polymer residue 40 is also removed.
  • Shrinking the intermediate mask layer 90 includes etching the first mask layer 50 to remove the sidewalls of the first etching opening 51 .
  • the orthogonal projected area of the first etching opening 51 on the substrate 10 can be increased, thereby forming a middle etching opening 91 , and the formed middle etching opening 91 faces the first groove 31 .
  • the first mask layer 50 may be dry etched to remove the sidewalls of the first etching opening 51 .
  • the first mask layer 50 is overall thinned from the upper surface and sidewalls of the first mask layer 50 through dry etching to expand the first etching opening 51 to obtain the middle
  • the mask layer 90 ie, the thinned first mask layer
  • the middle etching opening 91 ie, the enlarged first etching opening located in the middle mask layer 90 .
  • the etching gas for dry etching may include at least one of oxygen, hydrogen, and nitrogen.
  • the intermediate etching step further includes: after forming the intermediate mask layer 90 , etching the conductive layer 30 using the intermediate mask layer 90 as a mask to form the intermediate groove 32 . It is worth noting that by removing part of the conductive layer 30 corresponding to the groove wall of the first groove 31, part of the polymer residue 301 deposited on the groove wall of the first groove 31 is also removed. At the same time, during the process During the etching process, polymer residue 301 will continue to be formed on the groove wall of the middle groove 32. At this time, the volume of the polymer residue 301 is smaller than before.
  • the depth of the middle groove 32 is greater than the depth of the first groove 31 and less than the depth of the second groove 33 .
  • a portion of the conductive layer 30 corresponding to the bottom of the first groove 31 is removed, so that the depth of the middle groove 32 is greater than the depth of the first groove 31 .
  • the bottom of the middle groove 32 is continued to be etched.
  • the depth of the middle groove 32 is smaller than the depth of the second groove 33 .
  • the depth of the formed intermediate groove 32 can be controlled by controlling the etching time.
  • removing the conductive layer 30 corresponding to the groove wall and the groove bottom of the first groove 31 to form the conductive line 20 and the second groove 33 also includes: removing The conductive layer 30 corresponds to the groove wall of the middle groove 32 and the groove bottom to form the conductive line 20 and the second groove 33 .
  • a second mask layer 60 is formed on the conductive layer 30.
  • the second mask layer 60 has a second etching opening 61, and the second etching opening 61 is disposed facing the middle groove 32.
  • the orthogonal projected area of the second etching opening 61 on the substrate 10 is larger than the orthogonal projected area of the middle etching opening 91 on the substrate 10 .
  • the conductive layer 30 is etched using the second mask layer 60 as a mask to form the conductive lines 20 and the second grooves 33 to completely remove the polymer residue 40 . Referring to FIG. 13 , after the polymer residue 40 is completely removed, a passivation layer 80 filled in the second groove 33 is formed.
  • the intermediate etching in the above embodiment can be performed multiple times.
  • the orthogonal projected area of the intermediate etching opening 91 on the substrate 10 is larger than the area of the intermediate etching opening 91 on the substrate 10 in the previous intermediate etching.
  • Orthographic projection area According to the volume of the polymer residue 40 formed on the first groove 31 , the polymer residue 40 can be further removed by adjusting the number of intermediate etching steps.
  • By enlarging the projected area of the conductive layer 30 of the intermediate etching opening 91 in each intermediate etching compared to the previous time it is possible to remove the portion of the conductive layer corresponding to the groove wall of the intermediate groove 32 in each intermediate etching. 30, thereby allowing the polymer residue 40 deposited on the groove wall of the middle groove 32 to be removed together.
  • each intermediate etching step can be implemented using the steps in the above embodiments, and will not be described again here.
  • Embodiments of the present disclosure also provide a semiconductor structure, which is formed by the above-mentioned manufacturing method of the semiconductor structure.
  • the manufacturing method of the semiconductor structure includes: providing a substrate 10 covered with a conductive layer 30; dry etching to remove part of the conductive layer 30 to form a first groove 31, the depth of the first groove 31 is less than the thickness of the conductive layer 30 , polymer residue 40 is formed on the groove wall of the first groove 31; the corresponding portion of the conductive layer 30 on the groove wall and groove bottom of the first groove 31 is removed to form the conductive line 20 and the third conductive line 20 between adjacent conductive lines 20.
  • the polymer residue 40 deposited on the groove wall of the first groove 31 can be removed at the same time, thereby avoiding subsequent filling of the passivation layer in the second groove 33. Sealing in advance at 80 o'clock can further avoid the occurrence of gaps inside the passivation layer 80 , which is beneficial to improving the performance of the semiconductor structure.

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Abstract

本公开实施例属于半导体制造技术领域，具体涉及一种半导体结构的制作方法及半导体结构。该半导体结构的制作方法包括：提供基底，基底上覆盖有导电层；干法蚀刻去除部分导电层，以形成第一凹槽，第一凹槽的深度小于导电层的厚度，第一凹槽的槽壁上有聚合物残留；去除第一凹槽的槽壁和槽底对应的部分导电层，以形成导电线以及位于相邻导电线间的第二凹槽；形成钝化层，其填充在第二凹槽内。通过去除第一凹槽的槽壁对应的部分导电层，可以同时去除沉积在第一凹槽的槽壁上的聚合物残留，避免后续在第二凹槽内填充钝化层时提前封口，避免钝化层内部出现缝隙。

Description

半导体结构的制作方法及半导体结构
本公开要求于2022年04月11日提交中国专利局、申请号为202210373096.0、申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及半导体制造技术领域，尤其涉及一种半导体结构的制作方法及半导体结构。
背景技术
芯片在制作完成后，一般需要制作封装结构，以对芯片进行封装。封装结构包括重布线层，重布线层设置在芯片具有接触垫的侧面上，并且重布线层中具有多个金属线，每一金属线的一端与接触垫连接，金属线的另一端设置有焊接结构，合理的设置金属线的形状，可以改变焊接结构的排布。
发明内容
第一方面，本公开实施例提供一种半导体结构的制作方法，包括：
提供基底，所述基底上覆盖有导电层；
干法蚀刻去除部分所述导电层，以形成第一凹槽，所述第一凹槽的深度小于所述导电层的厚度，所述第一凹槽的槽壁上有聚合物残留；
去除所述第一凹槽的槽壁和槽底对应的部分所述导电层，以形成导电线以及位于相邻所述导电线间构成的第二凹槽；
形成钝化层，其填充在所述第二凹槽内。
在一种可能实现的方式中，干法蚀刻去除部分所述导电层，以形成所述第一凹槽，包括：
在所述导电层上形成第一掩膜层，所述第一掩膜层上具有第一蚀刻开口；
以所述第一掩膜层为掩膜，对所述导电层进行蚀刻，以形成所述第一凹槽。
在一种可能实现的方式中，去除所述第一凹槽的槽壁和槽底对应的部分所述导电层，以形成导电线以及位于相邻所述导电线间构成的第二凹槽；包括：
在所述导电层上形成第二掩膜层，所述第二掩膜层上具有第二蚀刻开口，所述第二蚀刻开口正对所述第一凹槽设置，且所述第二蚀刻开口在所述基底上的正投影面积大于所述第一蚀刻开口在所述基底上的正投影面积；
以所述第二掩膜层为掩膜蚀刻所述导电层，以形成所述导电线和所述第二凹槽。
在一种可能实现的方式中，在所述导电层上形成第二掩膜层包括：
在形成所述第一凹槽后，对所述第一掩膜层进行收缩处理，以增大所述第一蚀刻开口在所述基底上的正投影面积，形成所述第二掩膜层及位于所述第二掩膜层上的所 述第二蚀刻开口。
在一种可能实现的方式中，对所述第一掩膜层进行收缩处理包括：
对所述第一掩膜层进行蚀刻，以去除所述第一蚀刻开口的侧壁。
在一种可能实现的方式中，对所述第一掩膜层进行蚀刻包括干法蚀刻，所述干法蚀刻的蚀刻气体包括氧气、氢气、氮气中的至少一种。
在一种可能实现的方式中，以所述第一掩膜层为掩膜，对所述导电层进行蚀刻，以形成第一凹槽，所述第一凹槽的深度为所述导电层厚度的1/3-1/2。
在一种可能实现的方式中，所述第二蚀刻开口与所述第一凹槽的槽壁之间的距离包括50nm-100nm。
在一种可能实现的方式中，以所述第二掩膜层为掩膜蚀刻所述导电层，以形成第二凹槽包括：
以所述第二掩膜层为掩膜蚀刻所述导电层及部分所述基底，形成所述第二凹槽。
在一种可能实现的方式中，以所述第一掩膜层为掩膜，通过干法蚀刻的方式对所述导电层进行蚀刻；以所述第二掩膜层为掩膜通过干法蚀刻的方式对所述导电层进行蚀刻。
在一种可能实现的方式中，去除所述第一凹槽的槽壁和槽底对应的部分所述导电层，以形成所述导电线和所述第二凹槽，包括：中间蚀刻；所述中间蚀刻包括：
在所述导电层上形成中间掩膜层，所述中间掩膜层上具有中间蚀刻开口，所述中间蚀刻开口正对所述第一凹槽设置，所述中间蚀刻开口在所述基底上的正投影面积大于所述第一蚀刻开口在所述基底上的正投影面积，并且所述中间蚀刻开口在所述基底上的正投影面积小于所述第二蚀刻开口在所述基底上的正投影面积；
以所述中间掩膜层为掩膜，对所述导电层进行蚀刻，以形成中间凹槽，所述中间凹槽的深度大于所述第一凹槽的深度且小于所述第二凹槽的深度。
在一种可能实现的方式中，在形成中间凹槽以后，去除所述第一凹槽的槽壁和槽底对应的部分所述导电层，以形成导电线和所述第二凹槽，还包括：
去除所述中间凹槽的槽壁和槽底对应的部分所述导电层，以形成所述导电线和所述第二凹槽。
在一种可能实现的方式中，在所述导电层上形成中间掩膜层包括：
在形成所述第一凹槽后，对所述第一掩膜层进行收缩处理，以增大所述第一蚀刻开口在所述基底上的正投影面积，形成所述中间掩膜层及位于所述中间掩膜层上的所述第二蚀刻开口。
在一种可能实现的方式中，对所述中间掩膜层进行收缩处理包括：
对所述第一掩膜层进行蚀刻，以去除所述第一蚀刻开口的侧壁。
在一种可能实现的方式中，对所述中间掩膜层进行蚀刻包括干法蚀刻，所述干法蚀刻的蚀刻气体包括氧气、氢气、氮气中的至少一种。
在一种可能实现的方式中，所述中间蚀刻为多次，每一次所述中间蚀刻中，所述中间蚀刻开口在所述基底上的正投影面积均大于上一次所述中间蚀刻中所述中间蚀刻开口在所述基底上的正投影面积。
在一种可能实现的方式中，形成钝化层，其填充在所述第二凹槽内之前，还包括：
去除所述第二掩膜层。
在一种可能实现的方式中，形成钝化层，其填充在所述第二凹槽内之前，还包括：去除所述第二掩膜层之后，
形成绝缘层，其覆盖在所述导电线以及所述第二凹槽的槽壁和槽底。
在一种可能实现的方式中，所述导电层包括在所述基底上依次设置的多个子导电层。
第二方面，本公开实施例提供一种半导体结构，包括：上述的半导体结构的制作方法形成的半导体结构。
本公开实施例提供一种半导体结构的制作方法以及半导体结构，半导体结构的制作方法包括：提供基底，基底上覆盖有导电层；干法蚀刻去除部分导电层，以形成第一凹槽，第一凹槽的深度小于导电层的厚度，第一凹槽的槽壁上有聚合物残留；去除第一凹槽的槽壁和槽底对应的部分导电层，以形成导电线以及位于相邻导电线间的第二凹槽；形成钝化层，其填充在第二凹槽内。通过去除第一凹槽的槽壁对应的部分导电层，可以同时去除沉积在第一凹槽的槽壁上的聚合物，避免后续在第二凹槽内填充钝化层时提前封口，进一步避免钝化层内部出现缝隙，有利于提高半导体结构性能。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种干法蚀刻形成的导电线的结构示意图；
图2为一种在导电线上形成的钝化层的结构示意图；
图3为本公开实施例提供的一种半导体结构的制作方法的步骤流程图；
图4为本公开实施例提供的半导体结构的制作方法中形成第一掩膜层的结构示意图；
图5为本公开实施例提供的半导体结构的制作方法中形成第一凹槽的结构示意图；
图6为本公开实施例提供的半导体结构的制作方法中形成第二掩膜层的结构示意图一；
图7为本公开实施例提供的半导体结构的制作方法中形成第二凹槽的结构示意图一；
图8为本公开实施例提供的半导体结构的制作方法中形成钝化层的结构示意图一；
图9为本公开实施例提供的半导体结构的制作方法中形成中间掩膜层的结构示意图；
图10为本公开实施例提供的半导体结构的制作方法中形成中间凹槽的结构示意图；
图11为本公开实施例提供的半导体结构的制作方法中形成第二掩膜层的结构示意图二；
图12为本公开实施例提供的半导体结构的制作方法中形成第二凹槽的结构示意 图二；
图13为本公开实施例提供的半导体结构的制作方法中形成钝化层的结构示意图二。
具体实施方式
下面结合附图对本公开的几种可选地实现方式进行介绍，当本领域技术人员应当理解，下述实现方式仅是示意性的，并非是穷尽式的列举，在这些实现方式的基础上，本领域技术人员可以对某些特征或者某些示例进行替换、拼接或者组合，这些仍应视为本公开的公开内容。
通常，对重布线层中的金属层进行一次干法蚀刻，以得到金属线之后，需要形成覆盖金属线且填充相邻金属线之间的凹槽的钝化层，以对形成的金属线进行保护，同时确保相邻金属线之间彼此绝缘。然而，在研究的过程中，本公开的发明人注意到：通过上述工艺流程形成的钝化层的质量相对较低，性能相对较差。
图1为一种干法蚀刻形成的导电线的结构示意图，图2为一种在导电线上形成的钝化层的结构示意图。本公开的发明人发现，如图1所示，在对重布线层中的金属层进行一次干法蚀刻，以得到金属线20之后，相邻金属线20之间的凹槽的侧壁上容易形成聚合物残留40；如图2所示，由于聚合物残留40的存在，在后续形成钝化层60时，凹槽内的钝化层60容易提前封口，进而导致钝化层60内存在缝隙，使得钝化层60性能相对较差。
有鉴于此，本公开实施例提供一种半导体结构的制作方法以及半导体结构，半导体结构的制作方法包括：提供基底，基底上覆盖有导电层；干法蚀刻去除部分导电层，以形成第一凹槽，第一凹槽的深度小于导电层的厚度，第一凹槽的槽壁上有聚合物残留；去除第一凹槽的槽壁和槽底对应的部分导电层，以形成导电线以及位于相邻导电线间的第二凹槽；形成钝化层，其填充在第二凹槽内。通过去除第一凹槽的槽壁对应的部分导电层，可以同时去除沉积在第一凹槽的槽壁上的聚合物，避免后续在第二凹槽内填充钝化层时提前封口，进一步避免钝化层内部出现缝隙，有利于改善半导体结构性能。
请参照图3，本公开实施例提供一种半导体结构的制作方法，包括以下步骤S101至步骤S104。
步骤S101、提供基底，基底上覆盖有导电层。
本实施例中，参照图4，基底10可以为半导体衬底，例如单晶硅、多晶硅或非晶结构的硅或硅锗(SiGe)，也可以为混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合。本实施例在此不对其进行限制。
本实施例中，导电层30可以通过电镀或者沉积等方式形成。例如，导电层30可以与基底10内部具有的接触垫连接，以使后续能使半导体结构通过导电层30与外部电连接。在一种具体的实现方式中，导电层30的材质例如可以包括铝、钛、钨、氮化钛等导电金属和/或化合物。
例如，导电层30可以包括在基底10上依次设置的多个子导电层。例如，如图4 所示，导电层30可以包括在基底10上依次设置的三个子导电层，即第一子导电层301、第二子导电层302、第三子导电层303。例如，在一种具体的实现方式中，第一子导电层301的材质可以包括钛，第二子导电层302的材质可以包括铝，第三子导电层303的材质可以包括氮化钛。需要说明的是，本实施例包括但不限于此。
步骤S102、干法蚀刻去除部分导电层，以形成第一凹槽，第一凹槽的深度小于导电层的厚度，第一凹槽的槽壁上形成聚合物。
参照图4，干法蚀刻去除部分导电层30，包括：在导电层30上形成第一掩膜层50，第一掩膜层50上具有第一蚀刻开口51。
在一种具体的实现方式中，第一掩膜层50的材质可以包括光阻，通过曝光显影的工艺去除部分光阻，以形成第一蚀刻开口51。
本实施例中，参照图5，干法蚀刻去除部分导电层30，还包括：在导电层30上形成第一掩膜层50以后，以第一掩膜层50为掩膜，对导电层30进行蚀刻，以形成第一凹槽31。
值得说明的是，以第一掩膜层50为掩膜对导电层30进行干法蚀刻，干法蚀刻是一种使用等离子体进行薄膜蚀刻的技术，在蚀刻过程中，使等离子体轰击被蚀刻物体的表面，从而去除被蚀刻物体，达到蚀刻的目的。在本实施例中，干法蚀刻去除导电层30，等离子体轰击导电层30的过程中，会产生结合物，结合物会残留在第一凹槽31的槽壁上，该残留的结合物即为聚合物残留40。在干法蚀刻去除部分导电层30的过程中，可以通过控制干法蚀刻的时间进而控制形成的第一凹槽31的深度，使第一凹槽31的深度小于导电层30的厚度，以便后续通过继续蚀刻第一凹槽31，以去除第一凹槽31槽壁上的聚合物残留40。
步骤S103、去除第一凹槽的槽壁和槽底对应的部分导电层，以形成导电线以及位于相邻导电线间的第二凹槽。
例如，通过去除第一凹槽31的槽底对应的部分导电层30，可以形成导电线20，形成的导电线20即为重分布线，相邻的导电线20之间的凹槽即为第二凹槽33。通过去除第一凹槽31的槽壁对应的部分导电层30，可以去除沉积在第一凹槽31的槽壁上的聚合物残留40，避免后续在第二凹槽33内填充钝化层80时提前封口(即使第二凹槽33的侧壁上仍有聚合物残留，该聚合物残留的体积也远小于图1所示的一次干法刻蚀中的聚合物残留的体积)，从而避免钝化层80内部出现缝隙，有利于提高半导体结构性能。
本实施例中，参照图6和图7，去除第一凹槽31的槽壁和槽底对应的部分导电层30，以形成导电线20以及位于相邻导电线20间的第二凹槽33，包括：在导电层30上形成第二掩膜层60，第二掩膜层60上具有第二蚀刻开口61，第二蚀刻开口61正对第一凹槽31设置，且第二蚀刻开口61在基底10上的正投影面积大于第一蚀刻开口51在基底10上的正投影面积。
在一些实施例中，第二掩膜层60可以覆盖在第一掩膜层50上，第二蚀刻开口61正对第一凹槽31，且由于第一蚀刻开口51正对第一凹槽31，第二蚀刻开口61正对第一蚀刻开口51，并使第二蚀刻开口61在基底10上的正投影面积大于第一蚀刻开口51在基底10上的正投影面积，便于后续去除第一凹槽31的槽壁对应的部分导电层30， 进而使得沉积在第一凹槽31槽壁上的聚合物残留40被一同去除掉。
在本实施例中，在导电层30上形成第二掩膜层60包括：在形成第一凹槽31后，对第一掩膜层50进行收缩处理，以增大第一蚀刻开口51在基底10上的正投影面积，形成第二掩膜层60及位于第二掩膜层60上的第二蚀刻开口61。
本实施例中，第二掩膜层60也即为进行收缩处理后的第一掩膜层50，由于第一蚀刻开口51在基底10上的正投影面积增大，也即形成的第二蚀刻开口61在基底10上的正投影面积大于第一蚀刻开口51在基底10上的正投影面积，使得后续以第二掩膜层60做掩膜进行蚀刻时，不仅能蚀刻第一凹槽31的槽底对应的部分导电层30，还能蚀刻第一凹槽31的槽壁对应的部分导电层30，便于后续去除第一凹槽31的槽壁对应的部分导电层30，进而使得沉积在第一凹槽31槽壁上的聚合物残留40被一同去除掉。
在本实施例中，对第一掩膜层50进行收缩处理包括：对第一掩膜层50进行蚀刻，以去除第一蚀刻开口51的侧壁。
通过去除第一蚀刻开口51的侧壁，可以增大第一蚀刻开口51在基底10上的正投影面积，从而形成第二蚀刻开口61，并且形成的第二蚀刻开口61正对第一凹槽31。
可选地，可以对第一掩膜层50进行干法蚀刻，以去除第一蚀刻开口51的侧壁。在一种具体的实现方式中，通过干法蚀刻，从第一掩膜层50的上表面和侧壁对第一掩膜层50进行整体减薄，以扩大第一蚀刻开口51，从而得到第二掩膜层60(即减薄后的第一掩膜层)以及位于第二掩膜层60中的第二蚀刻开口61(即扩大的第一蚀刻开口)。可选地，干法蚀刻的蚀刻气体可以包括氧气、氢气、氮气中的至少一种。
本实施例中，参照图7，去除第一凹槽31的槽壁和槽底对应的部分导电层30，以形成导电线20以及位于相邻导电线20间的第二凹槽33，还包括：在形成第二掩膜层60以后，以第二掩膜层60为掩膜蚀刻导电层30，以形成导电线20和第二凹槽33。
以第二掩膜层60为掩膜蚀刻导电层30时，会继续蚀刻第一凹槽31的槽底对应的部分导电层30，直至蚀刻贯穿导电层30，从而形成导电线20。同时，还会继续蚀刻第一凹槽31的槽壁对应的部分导电层30，可以去除沉积在第一凹槽31的槽壁上的聚合物残留40，避免后续在第二凹槽33内填充钝化层80时提前封口，进一步避免钝化层80内部出现缝隙，有利于提高半导体结构性能。
例如，参照图6，第二蚀刻开口61与第一凹槽31的槽壁之间的距离D可以包括50nm-100nm，通过调节导电层30的蚀刻面积，可以调节去除的聚合物残留40的体积，以便通过进一步去除沉积在第一凹槽31的槽壁上的聚合物残留40，避免后续在第二凹槽33内填充钝化层80时提前封口，从而进一步改善半导体结构性能。
本实施例中，参照图7，以第二掩膜层60为掩膜蚀刻导电层30，以形成第二凹槽33，还包括：以第二掩膜层60为掩膜蚀刻导电层30及部分基底10，形成第二凹槽33。
以第二掩膜层60为掩膜蚀刻导电层30时，在蚀刻第一凹槽31的槽底对应的部分导电层30以后，还会继续蚀刻第一凹槽31的槽底对应的部分基底10，从而形成导电线20。本实施例中，形成的第二凹槽33的槽底即为基底10，形成的第二凹槽33的槽壁包括基底10和导电层30。
例如，以第二掩膜层60为掩膜蚀刻导电层30还包括：以第二掩膜层60为掩膜通 过干法蚀刻的方式对导电层30进行蚀刻。干法蚀刻的过程中，使用等离子体轰击导电层30，同时，等离子体还能够轰击第一凹槽31的槽壁上的聚合物残留40，使得聚合物残留40被击碎成碎屑，从而进一步去除聚合物残留40。值得说明的是，在干法蚀刻的过程中聚合物残留40被去除，同时，第二凹槽33的槽壁上有可能形成新的聚合物残留40，由于第二凹槽33上的聚合物残留40的体积小于第一凹槽31上聚合物残留40的体积，可以避免后续在第二凹槽33内填充钝化层80时提前封口，改善半导体结构性能。
步骤S104、形成钝化层，其填充在第二凹槽内。
本实施例中，参照图8，形成钝化层80，其填充在第二凹槽33内之前，还包括：去除第二掩膜层60。
例如，可以通过清洗液清洗去除第二掩膜层60。在蚀刻第一凹槽31的槽壁对应的部分导电层30时，沉积在第一凹槽31槽壁上的聚合物残留40的碎屑可能会掉落在第二凹槽33的槽底。在通过清洗液去除第二掩膜层60的过程中，可以进一步去除掉落在第二凹槽33的槽底的碎屑，有利于进一步提高半导体结构的性能。
在形成钝化层80，其填充在第二凹槽33内之前，还包括：在去除第二掩膜层60之后，形成绝缘层70，其覆盖在导电线20以及第二凹槽33的槽壁和槽底。通过形成绝缘层70，可以隔绝相邻的导电线20。绝缘层70的材质例如可以包括氮化物、氧化物以及氮氧化物等。
在形成绝缘层70之后，可以形成覆盖其的钝化层80，钝化层80填充在第二凹槽33内，且钝化层80还覆盖在导电线20上。钝化层80的材质例如可以包括聚酰亚胺，从而起到应力缓冲以及保护导电线20的作用。例如，钝化层80还能够起到平坦化的作用。
本公开实施例提供一种半导体结构的制作方法，包括：提供基底10，基底10上覆盖有导电层30；干法蚀刻去除部分导电层30，以形成第一凹槽31，第一凹槽31的深度小于导电层30的厚度，第一凹槽31的槽壁上形成聚合物残留40；去除第一凹槽31的槽壁和槽底对应的部分导电层30，以形成导电线20以及位于相邻导电线20间的第二凹槽33；形成钝化层80，其填充在第二凹槽33内。通过去除第一凹槽31的槽壁对应的部分导电层30，可以同时去除沉积在第一凹槽31的槽壁上的聚合物残留40，避免后续在第二凹槽33内填充钝化层80时提前封口，进一步避免钝化层80内部出现缝隙，有利于提高半导体结构性能。
本实施例中，参照图5，以第一掩膜层50为掩膜，对导电层30进行蚀刻，以形成第一凹槽31，还包括：第一凹槽31的深度H1为导电层30厚度H2的1/3-1/2。第一凹槽31的深度H1为导电层30厚度H2的1/3-1/2时，第一凹槽31槽壁上形成的聚合物残留40便于通过后续蚀刻第一凹槽31的槽壁，而从第一凹槽31上剥离，有利于进一步去除聚合物残留40，从而进一步提高半导体结构的性能。
例如，形成的第一凹槽31的深度，还可以通过控制蚀刻时间来调节。例如，以第一掩膜层50为掩膜，对导电层30进行蚀刻，以形成第一凹槽31的蚀刻时间可以为第一时段，去除第一凹槽31的槽壁和槽底对应的部分导电层30，以形成导电线20以及第二凹槽33的蚀刻时间可以为第二时段，第一时段与第二时段的和为总的蚀刻时间， 为进一步去除聚合物残留40，进一步提高半导体结构的性能，可使第一时段为总的蚀刻时间的1/3-1/2。
上述实施例中，通过一次收缩处理和一次蚀刻工艺形成第二凹槽33，从而实现了去除第一凹槽31上的聚合物残留40。参照图9至图13，在一些其他的实施例中，根据第一凹槽31上聚合物残留40的实际情况，去除第一凹槽31的槽壁和槽底对应的部分导电层30，以形成导电线20和第二凹槽33，还可以包括：中间蚀刻。通过设置中间蚀刻步骤，有利于进一步去除第一凹槽31的槽壁上的聚合物残留40。
请参照图9，中间蚀刻的步骤可以包括：在导电层30上形成中间掩膜层90，中间掩膜层90上具有中间蚀刻开口91，中间蚀刻开口91正对第一凹槽31设置，中间蚀刻开口91在基底10上的正投影面积大于第一蚀刻开口51在基底10上的正投影面积，并且中间蚀刻开口91在基底10上的正投影面积小于第二蚀刻开口61在基底10上的正投影面积。
在本实施例中，在导电层30上形成中间掩膜层90包括：在形成第一凹槽31后，对第一掩膜层50进行收缩处理，以增大第一蚀刻开口51在基底10上的正投影面积，形成中间掩膜层90及位于中间掩膜层90上的中间蚀刻开口91。
中间掩膜层90也即为进行收缩处理后的第一掩膜层50，由于第一蚀刻开口51在基底10上的正投影面积增大，也即形成的中间蚀刻开口91在基底10上的正投影面积大于第一蚀刻开口51在基底10上的正投影面积，使得后续以中间掩膜层90做掩膜进行蚀刻时，不仅能蚀刻第一凹槽31的槽底对应的部分导电层30，还能蚀刻第一凹槽31的槽壁对应的部分导电层30，便于后续去除第一凹槽31的槽壁对应的部分导电层30，进而使得沉积在第一凹槽31槽壁上的聚合物残留40被一同去除掉。
对中间掩膜层90进行收缩处理包括：对第一掩膜层50进行蚀刻，以去除第一蚀刻开口51的侧壁。
通过去除第一蚀刻开口51的侧壁，可以增大第一蚀刻开口51在基底10上的正投影面积，从而形成中间蚀刻开口91，并且形成的中间蚀刻开口91正对第一凹槽31。
可选地，可以对第一掩膜层50进行干法蚀刻，以去除第一蚀刻开口51的侧壁。在一种具体的实现方式中，通过干法蚀刻，从第一掩膜层50的上表面和侧壁对第一掩膜层50进行整体减薄，以扩大第一蚀刻开口51，从而得到中间掩膜层90(即减薄后的第一掩膜层)以及位于中间掩膜层90中的中间蚀刻开口91(即扩大的第一蚀刻开口)。可选地，干法蚀刻的蚀刻气体可以包括氧气、氢气、氮气中的至少一种。
参照图10，中间蚀刻的步骤还包括：在形成中间掩膜层90以后，以中间掩膜层90为掩膜，对导电层30进行蚀刻，以形成中间凹槽32。值得说明的是，通过去除第一凹槽31的槽壁对应的部分导电层30，进而使得沉积在第一凹槽31槽壁上的部分聚合物残留301被一同去除掉，同时，在进行中间蚀刻的过程中，中间凹槽32的槽壁上还会继续形成聚合物残留301，此时聚合物残留301的体积较之前减小。
参照图10，中间凹槽32的深度大于第一凹槽31的深度且小于第二凹槽33的深度。在蚀刻的过程中，去除第一凹槽31的槽底对应的部分导电层30，以使中间凹槽32的深度大于第一凹槽31的深度，后续通过继续蚀刻中间凹槽32的槽底对应的部分导电层30，中间凹槽32的深度小于第二凹槽33的深度。在蚀刻的过程中，可以通过 控制蚀刻的时间，进而控制形成的中间凹槽32的深度。
参照图11以及图12，在形成中间凹槽32以后，去除第一凹槽31的槽壁和槽底对应的部分导电层30，以形成导电线20和第二凹槽33，还包括：去除中间凹槽32的槽壁和槽底对应的部分导电层30，以形成导电线20和第二凹槽33。
具体地，在形成中间凹槽32以后，在导电层30上形成第二掩膜层60，第二掩膜层60上具有第二蚀刻开口61，第二蚀刻开口61正对中间凹槽32设置，且第二蚀刻开口61在基底10上的正投影面积大于中间蚀刻开口91在基底10上的正投影面积。在形成第二掩膜层60以后，以第二掩膜层60为掩膜蚀刻导电层30，以形成导电线20和第二凹槽33，以便完全去除聚合物残留40。参照图13，在完全去除聚合物残留40以后，再形成填充在第二凹槽33内的钝化层80。
可选地，上述实施例中的中间蚀刻可以为多次，每一次中间蚀刻中，中间蚀刻开口91在基底10上的正投影面积均大于上一次中间蚀刻中中间蚀刻开口91在基底10上的正投影面积。根据第一凹槽31上形成的聚合物残留40的体积，可以通过调节中间蚀刻步骤的次数，进一步去除聚合物残留40。通过将每次中间蚀刻的中间蚀刻开口91的导电层30上的投影面积相较上一次而进行扩大，可以使得每次中间蚀刻时，都能去除中间凹槽32的槽壁对应的部分导电层30，进而使得沉积在中间凹槽32的槽壁上的聚合物残留40被一同去除掉。值得说明的是，每次中间蚀刻步骤均可以采用上述实施例中的步骤实现，在此不再赘述。
本公开实施例还提供一种半导体结构，半导体结构由上述半导体结构的制作方法形成。半导体结构的制作方法包括：提供基底10，基底10上覆盖有导电层30；干法蚀刻去除部分导电层30，以形成第一凹槽31，第一凹槽31的深度小于导电层30的厚度，第一凹槽31的槽壁上形成聚合物残留40；去除第一凹槽31的槽壁和槽底对应的部分导电层30，以形成导电线20以及位于相邻导电线20间的第二凹槽33；形成钝化层80，其填充在第二凹槽33内。通过去除第一凹槽31的槽壁对应的部分导电层30，可以同时去除沉积在第一凹槽31的槽壁上的聚合物残留40，避免后续在第二凹槽33内填充钝化层80时提前封口，进一步避免钝化层80内部出现缝隙，有利于提高半导体结构性能。
本领域技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (20)

  1. 一种半导体结构的制作方法，包括：
    提供基底，所述基底上覆盖有导电层；
    干法蚀刻去除部分所述导电层，以形成第一凹槽，所述第一凹槽的深度小于所述导电层的厚度，所述第一凹槽的槽壁上有聚合物残留；
    去除所述第一凹槽的槽壁和槽底对应的部分所述导电层，以形成导电线以及位于相邻所述导电线间的第二凹槽；
    形成钝化层，其填充在所述第二凹槽内。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，干法蚀刻去除部分所述导电层，以形成所述第一凹槽，包括：
    在所述导电层上形成第一掩膜层，所述第一掩膜层上具有第一蚀刻开口；
    以所述第一掩膜层为掩膜，对所述导电层进行蚀刻，以形成所述第一凹槽。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，去除所述第一凹槽的槽壁和槽底对应的部分所述导电层，以形成所述导电线以及位于相邻所述导电线间的第二凹槽，包括：
    在所述导电层上形成第二掩膜层，所述第二掩膜层上具有第二蚀刻开口，所述第二蚀刻开口正对所述第一凹槽设置，且所述第二蚀刻开口在所述基底上的正投影面积大于所述第一蚀刻开口在所述基底上的正投影面积；
    以所述第二掩膜层为掩膜蚀刻所述导电层，以形成所述导电线和所述第二凹槽。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，在所述导电层上形成第二掩膜层包括：
    在形成所述第一凹槽后，对所述第一掩膜层进行收缩处理，以增大所述第一蚀刻开口在所述基底上的正投影面积，形成所述第二掩膜层及位于所述第二掩膜层上的所述第二蚀刻开口。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，对所述第一掩膜层进行收缩处理包括：
    对所述第一掩膜层进行蚀刻，以去除所述第一蚀刻开口的侧壁。
  6. 根据权利要求5所述的半导体结构的制作方法，其中，对所述第一掩膜层进行蚀刻包括干法蚀刻，所述干法蚀刻的蚀刻气体包括氧气、氢气、氮气中的至少一种。
  7. 根据权利要求2-6任一项所述的半导体结构的制作方法，其中，以所述第一掩膜层为掩膜，对所述导电层进行蚀刻，以形成第一凹槽，所述第一凹槽的深度为所述导电层厚度的1/3-1/2。
  8. 根据权利要求3-6任一项所述的半导体结构的制作方法，其中，所述第二蚀刻开口与所述第一凹槽的槽壁之间的距离包括50nm-100nm。
  9. 根据权利要求3-6任一项所述的半导体结构的制作方法，其中，以所述第二掩膜层为掩膜蚀刻所述导电层，以形成第二凹槽包括：
    以所述第二掩膜层为掩膜蚀刻所述导电层及部分所述基底，形成所述第二凹槽。
  10. 根据权利要求3-6任一项所述的半导体结构的制作方法，其中，以所述第二掩膜层为掩膜通过干法蚀刻的方式对所述导电层进行蚀刻。
  11. 根据权利要求3-6任一项所述的半导体结构的制作方法，其中，去除所述第一凹槽的槽壁和槽底对应的部分所述导电层，以形成所述导电线和所述第二凹槽，包括：中间蚀刻；所述中间蚀刻包括：
    在所述导电层上形成中间掩膜层，所述中间掩膜层上具有中间蚀刻开口，所述中间蚀刻开口正对所述第一凹槽设置，所述中间蚀刻开口在所述基底上的正投影面积大于所述第一蚀刻开口在所述基底上的正投影面积，并且所述中间蚀刻开口在所述基底上的正投影面积小于所述第二蚀刻开口在所述基底上的正投影面积；
    以所述中间掩膜层为掩膜，对所述导电层进行蚀刻，以形成中间凹槽，所述中间凹槽的深度大于所述第一凹槽的深度且小于所述第二凹槽的深度。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，在形成所述中间凹槽以后，去除所述第一凹槽的槽壁和槽底对应的部分所述导电层，以形成所述导电线和所述第二凹槽，还包括：
    去除所述中间凹槽的槽壁和槽底对应的部分所述导电层，以形成所述导电线和所述第二凹槽。
  13. 根据权利要求11所述的半导体结构的制作方法，其中，在所述导电层上形成中间掩膜层包括：
    在形成所述第一凹槽后，对所述第一掩膜层进行收缩处理，以增大所述第一蚀刻开口在所述基底上的正投影面积，形成所述中间掩膜层及位于所述中间掩膜层上的所述中间蚀刻开口。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，对所述中间掩膜层进行收缩处理包括：
    对所述第一掩膜层进行蚀刻，以去除所述第一蚀刻开口的侧壁。
  15. 根据权利要求14所述的半导体结构的制作方法，其中，
    对所述中间掩膜层进行蚀刻包括干法蚀刻，所述干法蚀刻的蚀刻气体包括氧气、氢气、氮气中的至少一种。
  16. 根据权利要求11所述的半导体结构的制作方法，其中，所述中间蚀刻为多次，每一次所述中间蚀刻中，所述中间蚀刻开口在所述基底上的正投影面积均大于上一次所述中间蚀刻中所述中间蚀刻开口在所述基底上的正投影面积。
  17. 根据权利要求3-6任一项所述的半导体结构的制作方法，其中，形成钝化层，其填充在所述第二凹槽内之前，还包括：
    去除所述第二掩膜层。
  18. 根据权利要求17所述的半导体结构的制作方法，其中，形成钝化层，其填充在所述第二凹槽内之前，还包括：去除所述第二掩膜层之后，
    形成绝缘层，其覆盖在所述导电线以及所述第二凹槽的槽壁和槽底。
  19. 根据权利要求1所述的半导体结构的制作方法，其中，所述导电层包括在所述基底上依次设置的多个子导电层。
  20. 一种半导体结构，包括：以权利要求1-19任一所述的半导体结构的制作方法形成的半导体结构。
PCT/CN2022/087494 2022-04-11 2022-04-18 半导体结构的制作方法及半导体结构 Ceased WO2023197340A1 (zh)

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