WO2023189480A1 - 半導体素子および半導体装置 - Google Patents

半導体素子および半導体装置 Download PDF

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Publication number
WO2023189480A1
WO2023189480A1 PCT/JP2023/009607 JP2023009607W WO2023189480A1 WO 2023189480 A1 WO2023189480 A1 WO 2023189480A1 JP 2023009607 W JP2023009607 W JP 2023009607W WO 2023189480 A1 WO2023189480 A1 WO 2023189480A1
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Prior art keywords
layer
thickness direction
opening
viewed
semiconductor device
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Ceased
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English (en)
French (fr)
Japanese (ja)
Inventor
博文 田中
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024511691A priority Critical patent/JPWO2023189480A1/ja
Publication of WO2023189480A1 publication Critical patent/WO2023189480A1/ja
Priority to US18/898,031 priority patent/US20250022821A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/417—Bonding materials between chips and die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to a semiconductor element and a semiconductor device.
  • Patent Document 1 discloses an example of a semiconductor element.
  • the semiconductor element includes a semiconductor substrate, a semiconductor layer, an interlayer insulating film, a wiring layer, a passivation film, an electrode, and a surface protection film.
  • a semiconductor layer, an interlayer insulating film, a wiring layer, and a passivation film are stacked on a semiconductor substrate, and an electrode conductive to the wiring layer is arranged in a recess of the passivation film.
  • the surface protection film covers the passivation film and has openings that expose the electrodes.
  • the wiring layer and the electrode contain Al.
  • a metal layer (including a Ni layer, for example) that is in contact with the wiring layer and partially overlaps the surface of the surface protective film is formed instead of the electrode, and this is used to bond the bonding wire.
  • Semiconductor elements have been developed that use pads for this purpose.
  • the metal layer and the surface protective film have different coefficients of thermal expansion due to the difference in materials, so thermal stress is applied to the surface protective film. Therefore, if the temperature of the semiconductor element changes repeatedly due to the external environment and self-heating during use of the semiconductor element, cracks may occur in the surface protective film.
  • An object of the present disclosure is to provide a semiconductor device that is improved over the conventional semiconductor device.
  • one object of the present disclosure is to provide a semiconductor element that can suppress the occurrence of cracks in a surface protective film, and a semiconductor device equipped with the semiconductor element.
  • a semiconductor element provided by one aspect of the present disclosure includes an element body having an element main surface facing one side in the thickness direction, and a wiring layer formed on the element main surface and electrically connected to the element main body. , an insulating layer that covers the main surface of the element and the wiring layer and has a first opening through which the wiring layer is exposed; and a surface protection having a second opening that covers the insulating layer and exposes the wiring layer. and a metal layer that contacts the wiring layer through the first opening and the second opening and overlaps the surface protection film when viewed in the thickness direction. When viewed in the thickness direction, the outer edge of the metal layer is curved.
  • a semiconductor device provided by another aspect of the present disclosure includes a semiconductor element provided by the first aspect, a conductive support member that supports the semiconductor element and is electrically connected to the semiconductor element, and a conductive support member that supports the semiconductor element and is electrically connected to the semiconductor element.
  • the device includes a connection member joined to the metal layer and the conductive support member, and a sealing resin that covers the semiconductor element, the connection member, and a portion of the conductive support member.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a plan view showing the semiconductor device of FIG. 1, and is a view through a sealing resin.
  • FIG. 3 is a bottom view showing the semiconductor device of FIG. 1.
  • FIG. 4 is a front view showing the semiconductor device of FIG. 1.
  • FIG. 5 is a right side view showing the semiconductor device of FIG. 1.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a cross-sectional view taken along line VII-VII in FIG.
  • FIG. 8 is a plan view showing the semiconductor element according to the first embodiment.
  • FIG. 9 is a partial enlarged view of a part of FIG. 8, in which the periphery of one metal layer is enlarged.
  • FIG. 10 is a cross-sectional view taken along line XX in FIG.
  • FIG. 11 is a partially enlarged plan view showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 12 is a partially enlarged plan view showing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 13 is a partially enlarged plan view showing a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. 14 is a partially enlarged plan view showing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 15 is a sectional view taken along line XV-XV in FIG. 14.
  • FIG. 16 is a partially enlarged plan view showing a semiconductor device according to a sixth embodiment of the present disclosure.
  • a thing A is formed on a thing B" and "a thing A is formed on a thing B” mean “a thing A is formed on a thing B" unless otherwise specified.
  • A is formed directly on something B
  • a thing A is formed on something B, with another thing interposed between them.” including.
  • "a certain thing A is placed on a certain thing B” and "a certain thing A is placed on a certain thing B” are used as "a certain thing A is placed on a certain thing B” unless otherwise specified.
  • ⁇ It is placed directly on something B,'' and ⁇ A thing A is placed on something B, with another thing interposed between them.'' include.
  • an object A is located on an object B
  • an object A is in contact with an object B, and an object A is located on an object B.
  • an object A overlaps an object B when viewed in a certain direction means, unless otherwise specified, “an object A overlaps all of an object B” and "an object A overlaps an object B”.
  • a certain thing A (constituent material) includes a certain material C means "a case where a certain thing A (constituent material) consists of a certain material C" and "a certain thing A (constituent material) includes a certain material C”. Including cases where the main component of is a certain material C.
  • First embodiment: 1 to 10 show a semiconductor element A1 according to a first embodiment and a semiconductor device B1 including the semiconductor element A1.
  • the outer shape of the sealing resin 7 is shown by an imaginary line (two-dot chain line) that is transmitted through the sealing resin 7.
  • the semiconductor device B1 includes a first lead 51, a plurality of second leads 52, a plurality of connection members 6, and a sealing resin 7 in addition to the semiconductor element A1.
  • the semiconductor device B1 is a module of the semiconductor element A1.
  • the shape and size of the semiconductor device B1 are not limited at all.
  • the thickness direction of the semiconductor device B1 will be referred to as the "thickness direction z.”
  • one side of the thickness direction z may be referred to as upper side, and the other side may be referred to as lower side.
  • descriptions such as “upper”, “lower”, “upper”, “lower”, “upper surface”, and “lower surface” indicate the relative positional relationship of each component etc. in the thickness direction z, and do not necessarily mean It is not a term that defines the relationship with the direction of gravity.
  • plane view refers to when viewed in the thickness direction z.
  • a direction perpendicular to the thickness direction z is referred to as a "first direction x.”
  • the first direction x is the left-right direction in the plan view of the semiconductor device B1 (see FIG. 2).
  • a direction perpendicular to the thickness direction z and the first direction x is referred to as a "second direction y.”
  • the second direction y is the vertical direction in the plan view of the semiconductor device B1 (see FIG. 2).
  • the semiconductor element A1 is an element that performs the electrical functions of the semiconductor device B1.
  • the semiconductor element A1 is a BiCDMOS (Bipolar CMOS DMOS), which is a semiconductor composite element in which a bipolar element, a CMOS (Complementary MOS) transistor, and a DMOS (Double diffusion MOS) transistor are formed on a common semiconductor substrate. ) element.
  • BiCDMOS Bipolar CMOS DMOS
  • CMOS Complementary MOS
  • DMOS Double diffusion MOS
  • the semiconductor element A1 is mounted on the first lead 51.
  • the semiconductor element A1 includes an element body 10, an insulating layer 13, a wiring layer 14, a back electrode 24, a plurality of metal layers 25, and a surface protective film 26.
  • the element body 10 has a rectangular shape in plan view, as shown in FIGS. 2 and 8.
  • the element body 10 has a main surface 10a and a back surface 10b, as shown in FIGS. 6 and 7.
  • the main surface 10a faces one side in the thickness direction z.
  • the back surface 10b faces the opposite side to the main surface 10a.
  • the element body 10 includes a semiconductor substrate 11 and a semiconductor layer 12.
  • the semiconductor substrate 11 supports the semiconductor layer 12.
  • the semiconductor substrate 11 is an n+ type semiconductor layer.
  • Semiconductor substrate 11 includes Si (silicon), SiC (silicon carbide), or the like.
  • the semiconductor layer 12 is laminated on the semiconductor substrate 11.
  • the semiconductor layer 12 is electrically connected to the semiconductor substrate 11 .
  • the surface of the semiconductor substrate 11 facing away from the surface on which the semiconductor layer 12 is stacked (the lower surface in FIG. 10) is the back surface 10b of the element body 10.
  • the surface of the semiconductor layer 12 facing away from the side where the semiconductor substrate 11 is located in the thickness direction z (the upper surface in FIG. 10) is the main surface 10a of the element body 10.
  • the wiring layer 14 is formed on the main surface 10a and is electrically connected to the semiconductor layer 12 of the element body 10.
  • the wiring layer 14 is made of, for example, an alloy of Al (aluminum) and Cu (copper) (AlCu).
  • the material of the wiring layer 14 is not limited, and may be other materials containing Al, such as Al or AlSi, or other materials containing Cu.
  • the wiring layer 14 is formed by sputtering, for example. Note that the method for forming the wiring layer 14 is not limited.
  • the shape of the wiring layer 14 in plan view is not limited, and is appropriately designed depending on the arrangement position of each circuit in the semiconductor layer 12, the arrangement position of the metal layer 25, and the like.
  • the insulating layer 13 is formed on the main surface 10a and covers the main surface 10a and the wiring layer 14.
  • the insulating layer 13 has electrical insulation properties and is composed of, for example, a silicon oxide film (SiO 2 ) and a silicon nitride film (Si 3 N 4 ) laminated on the silicon oxide film.
  • the insulating layer 13 is formed, for example, by plasma CVD (Chemical Vapor Deposition). Note that the structure, material, and method of forming the insulating layer 13 are not limited.
  • the insulating layer 13 has a plurality of openings 13a penetrating in the thickness direction z.
  • the wiring layer 14 is exposed through the opening 13a. As shown in FIG. 9, in this embodiment, the opening 13a when viewed in the thickness direction z has a circular shape.
  • each wiring layer 14 is shown for simplicity, but a plurality of wiring layers 14 may be stacked.
  • an interlayer insulating layer is interposed between each wiring layer 14, and each wiring layer 14 is electrically connected via a via provided in the interlayer insulating layer.
  • the surface protection film 26 is formed on the main surface 10a and covers the insulating layer 13. In this embodiment, the surface protection film 26 covers the inner edge of the opening 13a of the insulating layer 13 and is in contact with the wiring layer 14.
  • the surface protection film 26 has electrical insulation properties and includes, for example, polyimide resin. Note that the material of the surface protection film 26 is not limited, and other insulating materials may be used.
  • the surface protection film 26 has a plurality of openings 26a penetrating in the thickness direction z.
  • the wiring layer 14 is exposed through the opening 26a. As shown in FIG. 9, in this embodiment, the opening 26a when viewed in the thickness direction z has a circular shape. In this embodiment, the opening 26a is enclosed in the opening 13a when viewed in the thickness direction z.
  • the surface protection film 26 is formed, for example, by applying photolithography to a photosensitive resin material applied using a spin coater. Note that the method of forming the surface protection film 26 is not limited.
  • Each of the plurality of metal layers 25 is formed on the wiring layer 14 and is in contact with the wiring layer 14 through the opening 13a and the opening 26a.
  • Each metal layer 25 is electrically connected to the internal circuit of the semiconductor layer 12 via the wiring layer 14.
  • Each metal layer 25 overlaps a part of the surface protection film 26 when viewed in the thickness direction z.
  • the plurality of metal layers 25 function as pads to which the connection member 6 is bonded.
  • Each metal layer 25 is protected against cracks in the element body 10, corrosion at the boundary between the wiring layer 14 and the bonding wire, and poor bonding of the bonding wire, which may occur when the bonding wire is directly bonded to the wiring layer 14. This is provided to prevent such things.
  • each metal layer 25 is composed of a plurality of metal layers stacked upward from the wiring layer 14, and includes a first layer 251, a second layer 252, a third layer 253, and A base layer 254 is provided.
  • the base layer 254 is in contact with the wiring layer 14 and serves as a conductive path for forming the first layer 251, the second layer 252, and the third layer 253 by electrolytic plating.
  • the base layer 254 includes a Ti layer in contact with the wiring layer 14 and a Cu layer in contact with the Ti layer.
  • Base layer 254 is formed by sputtering. Note that the material and forming method of the base layer 254 are not limited.
  • the first layer 251 is in contact with the base layer 254 and contains Ni.
  • the second layer 252 is in contact with the first layer 251 and contains Pd.
  • the third layer 253 is in contact with the second layer 252 and contains Au.
  • the first layer 251, the second layer 252, and the third layer 253 are formed by electroplating. Note that the configuration, material, and formation method of the metal layer 25 are not limited at all. For example, the metal layer 25 may not include the third layer 253.
  • each metal layer 25 has a circular shape when viewed in the thickness direction z.
  • the opening 13a and the opening 26a are included in the metal layer 25 when viewed in the thickness direction z. That is, when viewed in the thickness direction z, the inner edge of the opening 13a and the inner edge of the opening 26a are located inside the outer edge 25a of the metal layer 25. Note that the inner edge of the opening 13a may be located outside the outer edge 25a of the metal layer 25.
  • the back electrode 24 is provided on the back surface 10b of the element body 10, as shown in FIGS. 6, 7, and 10.
  • the back electrode 24 is provided on the entire back surface 10b.
  • the back electrode 24 is electrically connected to the semiconductor layer 12 via the semiconductor substrate 11.
  • the material and structure of the back electrode 24 are not limited in any way, but include, for example, a layer containing silver (Ag) in contact with the semiconductor substrate 11 and a layer containing gold (Au) laminated on the Ag layer.
  • the back electrode 24 is bonded to the first lead 51 via a conductive bonding material 29.
  • the material of the conductive bonding material 29 is not limited at all, and may be, for example, solder, silver paste, or sintered silver.
  • the first lead 51 and the plurality of second leads 52 (hereinafter referred to as "conductive support member 5" when collectively shown) support the semiconductor element A1 and are used to mount the semiconductor device B1 on a wiring board. It serves as a terminal.
  • the conductive support member 5 is formed, for example, by etching or stamping a metal plate.
  • the conductive support member 5 is made of a metal selected from Cu, Ni, iron (Fe), etc., and an alloy thereof.
  • the conductive support member 5 may have a plating layer made of a metal selected from Ag, Ni, Pd, Au, etc. formed at an appropriate location.
  • the thickness of the conductive support member 5 is not limited at all, and is, for example, 0.12 mm or more and 0.2 mm or less.
  • the first lead 51 supports the semiconductor element A1.
  • the first lead 51 is electrically connected to the back electrode 24 of the semiconductor element A1 via the conductive bonding material 29. As shown in FIGS. 2, 6, and 7, the first lead 51 has a die pad portion 511 and two extension portions 512.
  • the die pad portion 511 is a portion that supports the semiconductor element A1.
  • the shape of the die pad portion 511 is not limited in any way, and in the example shown in FIG. 2, it is rectangular in plan view.
  • the die pad section 511 has a die pad main surface 511a and a die pad back surface 511b.
  • the die pad main surface 511a is a surface facing one side in the thickness direction z.
  • the die pad back surface 511b is a surface facing opposite to the die pad main surface 511a in the thickness direction z.
  • the die pad main surface 511a and the die pad back surface 511b are flat.
  • a semiconductor element A1 is bonded to the die pad main surface 511a.
  • the die pad back surface 511b is exposed from the sealing resin 7 (resin back surface 72, which will be described later), as shown in FIGS. 3, 6, and 7.
  • the two extending portions 512 extend from the die pad portion 511 to both sides in the first direction x, as shown in FIGS. 2 and 6.
  • the extending portion 512 is a portion extending from the die pad portion 511 along the first direction , and a portion extending from the portion along the first direction x, and has a bent shape as a whole.
  • each of the plurality of second leads 52 is separated from the first lead 51.
  • the plurality of second leads 52 are arranged around the first lead 51, and in the illustrated example, one is arranged on one side in the second direction y with respect to the first lead 51, and the other is arranged on one side in the second direction y with respect to the first lead 51. There is one placed on the other side of the The plurality of second leads 52 are spaced apart from each other in the first direction x on one side in the second direction y and on the other side in the second direction y.
  • each of the plurality of second leads 52 has a pad portion 521 and a terminal portion 522.
  • the pad portion 521 is connected to any one of the plurality of connection members 6. In the example shown in FIG. 7, the pad portion 521 is located closer to the die pad main surface 511a than the die pad portion 511 in the thickness direction z.
  • the terminal portion 522 extends outward from the pad portion 521 in the second direction y.
  • the terminal portion 522 is strip-shaped in plan view. As shown in FIG. 7, the terminal portion 522 is bent in a gullwing shape when viewed in the first direction x. As shown in FIG. 7, the terminal portion 522 has a tip portion (an end portion farthest from the die pad portion 511 in the second direction y) at approximately the same position as the die pad portion 511 in the thickness direction z.
  • Each terminal portion 522 of the plurality of second leads 52 is used as an external terminal of the semiconductor device B1.
  • External terminals include a control signal input terminal, a ground terminal, an output terminal connected to a load, a power supply terminal, a non-connect terminal, a self-diagnosis output terminal, and the like.
  • connection member 6 provides electrical continuity between parts that are spaced apart from each other.
  • the connection member 6 is, for example, a bonding wire, but is not limited thereto.
  • the connection member 6 contains, for example, Cu.
  • the material of the connecting member 6 is not limited, and may include, for example, Al or Au.
  • Each of the plurality of connection members 6 is joined to one of the plurality of metal layers 25 (pads) of the semiconductor element A1 and one of the pad portions 521 of the plurality of second leads 52.
  • Each of the plurality of connection members 6 connects the internal circuit of the semiconductor element A1 to each second lead 52.
  • the sealing resin 7 covers parts of the first lead 51 and the plurality of second leads 52, as well as the semiconductor element A1 and the plurality of connection members 6.
  • the sealing resin 7 is made of an insulating resin, and includes, for example, an epoxy resin mixed with a filler.
  • the sealing resin 7 has a resin main surface 71, a resin back surface 72, two resin side surfaces 73, and two resin side surfaces 74.
  • the resin main surface 71 faces the same side as the die pad main surface 511a in the thickness direction z.
  • the main resin surface 71 is, for example, a flat surface.
  • the resin back surface 72 faces the opposite side to the resin main surface 71 (the same side as the die pad back surface 511b) in the thickness direction z.
  • the resin back surface 72 is, for example, a flat surface.
  • the die pad back surface 511b is exposed from the resin back surface 72.
  • the two resin side surfaces 73 are located between the resin main surface 71 and the resin back surface 72 in the thickness direction z, and are spaced apart in the first direction x as shown in FIGS. 2 to 4. Each extending portion 512 is exposed from each of the two resin side surfaces 73.
  • the two resin side surfaces 74 are located between the resin main surface 71 and the resin back surface 72 in the thickness direction z, and are spaced apart in the second direction y, as shown in FIGS. 2, 3, and 5.
  • a plurality of second leads 52 protrude from either of the two resin side surfaces 74, respectively.
  • the functions and effects of the semiconductor element A1 and the semiconductor device B1 are as follows.
  • the semiconductor element A1 includes a surface protection film 26 and a metal layer 25 formed on the main surface 10a.
  • the metal layer 25 partially overlaps the surface protection film 26 when viewed in the thickness direction z.
  • Thermal stress is applied to the surface protection film 26 due to the difference in coefficient of thermal expansion due to the difference in materials between the metal layer 25 and the surface protection film 26 . Since the metal layer of a conventional semiconductor element has a rectangular shape when viewed in the thickness direction z, thermal stress is concentrated at the position of the surface protection film 26 that overlaps the corner of the metal layer when viewed in the thickness direction z. Therefore, cracks were likely to occur.
  • the metal layer 25 has a circular shape when viewed in the thickness direction z, the thermal stress is dispersed and not concentrated in one part. Thereby, in the semiconductor element A1, the occurrence of cracks in the surface protection film 26 can be suppressed compared to the case where the metal layer 25 has a rectangular shape when viewed in the thickness direction z.
  • the opening 26a of the surface protection film 26 is included in the opening 13a of the insulating layer 13 when viewed in the thickness direction z.
  • thermal stress caused by the difference in thermal expansion coefficient between the surface protection film 26 and the insulating layer 13 causes surface protection of the insulating layer 13 when viewed in the thickness direction z. Cracks were likely to occur at positions overlapping the openings 26a of the film 26.
  • the semiconductor element A1 since the opening 26a is included in the opening 13a, the occurrence of cracks in the insulating layer 13 can be suppressed.
  • thermal stress is applied to the surface protective film 26 due to the difference in thermal expansion coefficient between the insulating layer 13 and the surface protective film 26, but since the opening 13a is circular when viewed in the thickness direction z, the thermal stress is dispersed. Don't concentrate on one part. Thereby, in the semiconductor element A1, the occurrence of cracks in the surface protection film 26 can be suppressed compared to the case where the opening 13a has a rectangular shape when viewed in the thickness direction z.
  • the opening 26a of the surface protection film 26 when viewed in the thickness direction z has a circular shape that is similar to the opening 13a of the insulating layer 13.
  • the area in which the metal layer 25 is in contact with the wiring layer 14 can be increased compared to the case where the opening 26a has another shape such as a rectangular shape.
  • the semiconductor device B1 includes a semiconductor element A1.
  • the temperature of the semiconductor device B1 changes frequently depending on the environment in which it is used. For example, when mounted on a circuit board such as an automobile, it may be driven under all climatic conditions from cold regions to hot and humid regions, and when mounted in the engine room, temperature caused by the environment and driving pattern may change. Constantly exposed to change.
  • the semiconductor element A1 can suppress the occurrence of cracks due to temperature changes, the reliability of the semiconductor device B1 against temperature changes is improved. Therefore, the semiconductor device B1 can be used even in an environment where temperature changes occur frequently, and therefore has a wide range of uses.
  • the metal layer 25, the opening 13a, and the opening 26a have a circular shape when viewed in the thickness direction z, but the present invention is not limited to this.
  • the shape of the metal layer 25 in the thickness direction z may be any shape, such as an ellipse, in which the outer edge 25a has a curved line and does not include a stress concentration area.
  • the shape of the opening 13a as viewed in the thickness direction z is preferably a shape in which the inner edge is formed by a curve and does not include a stress concentration area, but other shapes may be used.
  • the shape of the opening 26a as viewed in the thickness direction z is preferably a shape in which the inner edge is a curved line and does not include a stress concentration area, but other shapes may be used. Furthermore, when viewed in the thickness direction z, it is desirable that the metal layer 25, the opening 13a, and the opening 26a have similar shapes to each other, but they do not have to have similar shapes.
  • FIG. 11 is a diagram for explaining a semiconductor element A2 according to a second embodiment of the present disclosure.
  • FIG. 11 is a partially enlarged plan view showing the semiconductor element A2, and corresponds to FIG. 9.
  • the semiconductor element A2 of this embodiment differs from the first embodiment in that the opening 13a of the insulating layer 13 when viewed in the thickness direction z is rectangular.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment.
  • the metal layer 25 has a circular shape when viewed in the thickness direction z
  • the thermal stress applied to the surface protection film 26 is dispersed and not concentrated in one part.
  • the occurrence of cracks in the surface protection film 26 can be suppressed compared to the case where the metal layer 25 has a rectangular shape when viewed in the thickness direction z.
  • the opening 26a of the surface protective film 26 is included in the opening 13a of the insulating layer 13 when viewed in the thickness direction z, the occurrence of cracks in the insulating layer 13 can be suppressed.
  • FIG. 12 is a diagram for explaining a semiconductor element A3 according to a third embodiment of the present disclosure.
  • FIG. 12 is a partially enlarged plan view showing the semiconductor element A3, and corresponds to FIG.
  • the semiconductor element A3 of this embodiment differs from the first embodiment in that the opening 26a when viewed in the thickness direction z has a rectangular shape.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first and second embodiments described above may be combined arbitrarily.
  • the metal layer 25 has a circular shape when viewed in the thickness direction z
  • the thermal stress applied to the surface protection film 26 is dispersed and not concentrated in one part.
  • the occurrence of cracks in the surface protection film 26 can be suppressed compared to the case where the metal layer 25 has a rectangular shape when viewed in the thickness direction z.
  • the opening 26a of the surface protective film 26 is included in the opening 13a of the insulating layer 13 when viewed in the thickness direction z, the occurrence of cracks in the insulating layer 13 can be suppressed.
  • the opening 13a is circular when viewed in the thickness direction z, thermal stress is dispersed and not concentrated in one part. Thereby, in the semiconductor element A3, the occurrence of cracks in the surface protection film 26 can be suppressed compared to the case where the opening 13a has a rectangular shape when viewed in the thickness direction z.
  • FIG. 13 is a diagram for explaining a semiconductor element A4 according to a fourth embodiment of the present disclosure.
  • FIG. 13 is a partially enlarged plan view showing the semiconductor element A4, and corresponds to FIG.
  • the semiconductor element A4 of this embodiment differs from the first embodiment in that the opening 13a and the opening 26a are rectangular when viewed in the thickness direction z.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first to third embodiments described above may be combined arbitrarily.
  • the metal layer 25 has a circular shape when viewed in the thickness direction z
  • the thermal stress applied to the surface protection film 26 is dispersed and not concentrated in one part.
  • the occurrence of cracks in the surface protection film 26 can be suppressed compared to the case where the metal layer 25 has a rectangular shape when viewed in the thickness direction z.
  • the opening 26a of the surface protection film 26 is included in the opening 13a of the insulating layer 13 when viewed in the thickness direction z, the occurrence of cracks in the insulating layer 13 can be suppressed.
  • FIG. 14 is a partially enlarged plan view showing the semiconductor element A5, and corresponds to FIG. 9.
  • FIG. 15 is a sectional view taken along the line XV-XV in FIG. 14, and corresponds to FIG. 10.
  • the semiconductor element A5 of this embodiment differs from the first embodiment in that the opening 13a is included in the opening 26a when viewed in the thickness direction z.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first to fourth embodiments described above may be combined arbitrarily.
  • the metal layer 25 has a circular shape when viewed in the thickness direction z
  • the thermal stress applied to the surface protection film 26 is dispersed and not concentrated in one part.
  • the occurrence of cracks in the surface protective film 26 can be suppressed compared to the case where the metal layer 25 has a rectangular shape when viewed in the thickness direction z.
  • the opening 13a of the insulating layer 13 is included in the opening 26a of the surface protection film 26 when viewed in the thickness direction z, the occurrence of cracks in the surface protection film 26 can be suppressed.
  • the opening 13a is enclosed in the opening 26a, since the opening 26a has a circular shape when viewed in the thickness direction z, thermal stress is dispersed and not concentrated in one part. Thereby, in the semiconductor element A5, the occurrence of cracks in the insulating layer 13 can be suppressed compared to the case where the opening 26a has a rectangular shape when viewed in the thickness direction z. Further, in the semiconductor element A5, the opening 13a of the insulating layer 13 when viewed in the thickness direction z has a circular shape similar to the opening 26a of the surface protection film 26. Thereby, in the semiconductor element A5, the area where the metal layer 25 is in contact with the wiring layer 14 can be increased compared to the case where the opening 13a is rectangular.
  • FIG. 16 is a diagram for explaining a semiconductor element A6 according to a sixth embodiment of the present disclosure.
  • FIG. 16 is a partially enlarged plan view showing the semiconductor element A6, and corresponds to FIG.
  • the semiconductor element A6 of this embodiment differs from the fifth embodiment in that the opening 13a when viewed in the thickness direction z has a rectangular shape.
  • the configuration and operation of other parts of this embodiment are similar to those of the fifth embodiment. Note that each part of the first to fifth embodiments described above may be combined arbitrarily.
  • the metal layer 25 has a circular shape when viewed in the thickness direction z
  • the thermal stress applied to the surface protection film 26 is dispersed and not concentrated in one part.
  • the occurrence of cracks in the surface protection film 26 can be suppressed compared to the case where the metal layer 25 has a rectangular shape when viewed in the thickness direction z.
  • the opening 13a of the insulating layer 13 is included in the opening 26a of the surface protection film 26 when viewed in the thickness direction z, the occurrence of cracks in the surface protection film 26 can be suppressed.
  • the opening 13a is enclosed in the opening 26a, since the opening 26a has a circular shape when viewed in the thickness direction z, thermal stress is dispersed and not concentrated in one part. Thereby, in the semiconductor element A6, the occurrence of cracks in the insulating layer 13 can be suppressed compared to the case where the opening 26a has a rectangular shape when viewed in the thickness direction z.
  • the semiconductor elements A1 to A6 are LSIs
  • the present invention is not limited to this.
  • the semiconductor elements A1 to A6 may be discrete semiconductor elements.
  • the aspect (type) of the semiconductor device B1 is not limited either.
  • the semiconductor element and semiconductor device according to the present disclosure are not limited to the embodiments described above.
  • the specific configuration of each part of the semiconductor element and semiconductor device of the present disclosure can be modified in various ways.
  • the present disclosure includes the embodiments described in the appendix below.
  • Appendix 1 an element body (10) having an element main surface (10a) facing one side in the thickness direction; a wiring layer (14) formed on the main surface of the element and electrically connected to the element main body; an insulating layer (13) that covers the main surface of the element and the wiring layer and has a first opening (13a) through which the wiring layer is exposed; a surface protection film (26) that covers the insulating layer and has a second opening (26a) through which the wiring layer is exposed; a metal layer (25) that is in contact with the wiring layer through the first opening and the second opening and overlaps the surface protection film when viewed in the thickness direction; Equipped with When viewed in the thickness direction, the outer edge (25a) of the metal layer is a curved line; Semiconductor element (A1).
  • Addendum 2 The metal layer has a circular shape when viewed in the thickness direction.
  • Appendix 3 When viewed in the thickness direction, the inner edge of the first opening is a curved line.
  • Appendix 4 The semiconductor device according to appendix 3, wherein the first opening has a shape similar to the shape of the metal layer when viewed in the thickness direction.
  • Appendix 5 When viewed in the thickness direction, the inner edge of the second opening is a curved line.
  • Appendix 6 When viewed in the thickness direction, the shape of the second opening is similar to the shape of the metal layer; The semiconductor device according to appendix 5.
  • Appendix 7 When viewed in the thickness direction, the second opening is included in the first opening.
  • Appendix 8 The metal layer is a first layer (251) containing Ni; a second layer (252) that is in contact with the surface of the first layer on the side facing the main surface of the element and contains Pd; It is equipped with The semiconductor device according to any one of Supplementary Notes 1 to 7.
  • Appendix 9 The metal layer further includes a third layer (253) that is in contact with the surface of the second layer on the side facing the main surface of the element and includes Au.
  • Appendix 10 The metal layer further includes a fourth layer (254) interposed between the first layer and the wiring layer.
  • Appendix 11 The surface protective film contains polyimide resin, The semiconductor device according to any one of Supplementary Notes 1 to 10.
  • Appendix 12 the wiring layer contains Al; The semiconductor device according to any one of Supplementary Notes 1 to 11.
  • Appendix 13 further comprising a back electrode (24) electrically connected to the element body, The element main body further has an element back surface (10b) facing opposite to the element main surface in the thickness direction, The back electrode is arranged on the back surface of the element, The semiconductor device according to any one of Supplementary Notes 1 to 12.
  • Appendix 14 A semiconductor device according to any one of Supplementary Notes 1 to 13; a conductive support member (5) that supports the semiconductor element and is electrically connected to the semiconductor element; a connecting member (6) joined to the metal layer of the semiconductor element and the conductive support member; a sealing resin (7) that covers the semiconductor element, the connection member, and a part of the conductive support member; It is equipped with Semiconductor device (B1).
  • Appendix 15 The connecting member is a bonding wire containing Cu. The semiconductor device according to appendix 14.
  • A1 to A6 Semiconductor element B1: Semiconductor device 10: Element body 10a: Main surface 10b: Back surface 11: Semiconductor substrate 12: Semiconductor layer 13: Insulating layer 13a: Opening 14: Wiring layer 24: Back electrode 25: Metal layer 25a: Outer edge 251: First layer 252: Second layer 253: Third layer 254: Base layer 26: Surface protective film 26a: Opening 29: Conductive bonding material 5: Conductive support member 51: First lead 511: Die pad portion 511a: Die pad main surface 511b: Die pad back surface 512: Extension portion 52: Second lead 521: Pad portion 522: Terminal portion 6: Connection member 7: Sealing resin 71: Resin main surface 72: Resin back surface 73: Resin side surface 74: Resin side

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  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
PCT/JP2023/009607 2022-03-31 2023-03-13 半導体素子および半導体装置 Ceased WO2023189480A1 (ja)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03153049A (ja) * 1989-11-10 1991-07-01 Fujitsu Ltd 半導体装置
JP2012253263A (ja) * 2011-06-06 2012-12-20 Denso Corp 半導体チップおよびその製造方法
JP2017191840A (ja) * 2016-04-12 2017-10-19 ローム株式会社 半導体装置および半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03153049A (ja) * 1989-11-10 1991-07-01 Fujitsu Ltd 半導体装置
JP2012253263A (ja) * 2011-06-06 2012-12-20 Denso Corp 半導体チップおよびその製造方法
JP2017191840A (ja) * 2016-04-12 2017-10-19 ローム株式会社 半導体装置および半導体装置の製造方法

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