WO2023189131A1 - Dispositif électroluminescent à semi-conducteur - Google Patents

Dispositif électroluminescent à semi-conducteur Download PDF

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Publication number
WO2023189131A1
WO2023189131A1 PCT/JP2023/007524 JP2023007524W WO2023189131A1 WO 2023189131 A1 WO2023189131 A1 WO 2023189131A1 JP 2023007524 W JP2023007524 W JP 2023007524W WO 2023189131 A1 WO2023189131 A1 WO 2023189131A1
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Prior art keywords
semiconductor light
light emitting
via electrodes
emitting device
main surface
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PCT/JP2023/007524
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English (en)
Japanese (ja)
Inventor
智一 岡▲崎▼
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ローム株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/024—Arrangements for thermal management
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

Definitions

  • the present disclosure relates to a semiconductor light emitting device.
  • Patent Document 1 discloses a substrate, a plurality of first plated conductive parts, a plurality of second plated conductive parts, a first intermediate conductive part, a second intermediate conductive part, a third plated conductive part, a fourth plated conductive part, and a plurality of plated conductive parts.
  • a semiconductor light emitting device including an LED chip is disclosed.
  • the semiconductor light emitting device of Patent Document 1 further includes a first plated wiring and a second plated wiring.
  • Each of the first plated wiring and the second plated wiring extends from a first edge of the substrate to a second edge of the substrate.
  • the plurality of LED chips are sandwiched between the first plated wiring and the second plated wiring in the first direction.
  • the first plated wiring and the second plated wiring are interposed between the surface of the substrate and the frame of the substrate. When viewed in the thickness direction, the first plated wiring and the second plated wiring are located apart from the recessed portion of the substrate.
  • An embodiment of the present disclosure provides a semiconductor light emitting device that can improve heat dissipation.
  • a semiconductor light emitting device includes a substrate having a first main surface on one side and a second main surface on the other side, and an occupation rate of the first main surface with respect to a surface area of 10% or more in plan view. a plurality of via electrodes buried in the substrate at intervals such that the via electrodes are buried at intervals of 60% or less; an electrode film that collectively covers the plurality of via electrodes on the first main surface; and a semiconductor light emitting chip disposed on the electrode film so as to face the via electrode.
  • FIG. 1 is a schematic plan view of a semiconductor light emitting device according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic bottom view of the semiconductor light emitting device.
  • FIG. 3 is a diagram showing a cross section taken along line III-III in FIG.
  • FIG. 4A is a plan view of a semiconductor light emitting device showing a first arrangement pattern of vias.
  • FIG. 4B is a bottom view of the semiconductor light emitting device showing the first array pattern of vias.
  • FIG. 5A is a plan view of a semiconductor light emitting device showing a second arrangement pattern of vias.
  • FIG. 5B is a bottom view of the semiconductor light emitting device showing a second array pattern of vias.
  • FIG. 5A is a plan view of a semiconductor light emitting device showing a second arrangement pattern of vias.
  • FIG. 6A is a plan view of a semiconductor light emitting device showing a third array pattern of vias.
  • FIG. 6B is a bottom view of the semiconductor light emitting device showing the third array pattern of vias.
  • FIG. 7A is a plan view of a semiconductor light emitting device showing a fourth arrangement pattern of vias.
  • FIG. 7B is a bottom view of the semiconductor light emitting device showing a fourth arrangement pattern of vias.
  • FIG. 8A is a plan view of a semiconductor light emitting device showing a fifth array pattern of vias.
  • FIG. 8B is a bottom view of the semiconductor light emitting device showing a fifth array pattern of vias.
  • FIG. 9 is a diagram showing the relationship between via area ratio and heat dissipation.
  • FIG. 10 is a diagram showing the relationship between substrate thickness and heat dissipation.
  • FIG. 11 is a diagram showing the relationship between the thickness of the electrode film and heat dissipation.
  • FIG. 1 is a schematic plan view of a semiconductor light emitting device 1 according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic bottom view of the semiconductor light emitting device 1.
  • FIG. 3 is a diagram showing a cross section taken along line III-III in FIG.
  • the semiconductor light emitting device 1 includes a case 2, a semiconductor light emitting chip 3, a diode chip 4, and a sealing resin 5.
  • the sealing resin 5 is omitted for convenience of understanding.
  • the case 2 is the base of the semiconductor light emitting device 1 and includes a base material 6 as an example of a substrate and wiring 7.
  • the case 2 has a size of about 5 to 10 mm square in plan view, and a thickness T1 (thickness between the first main surface 9 and the second main surface 10) of 50 ⁇ m or more and 500 ⁇ m or less.
  • the base material 6 has a thick plate shape that is substantially rectangular in plan view, and is made of, for example, a resin substrate or a ceramic substrate made of alumina or the like.
  • a resin substrate is used as the base material 6, preferably a resin build-up substrate (multilayer substrate).
  • a resin substrate can reduce costs compared to a ceramic substrate.
  • a housing recess 8 is formed in the center of the base material 6.
  • the accommodation recess 8 accommodates the semiconductor light emitting chip 3 and the diode chip 4, and has a rectangular shape in plan view.
  • the base material 6 has a first main surface 9 and a second main surface 10.
  • the depth of the accommodation recess 8 is, for example, about 500 ⁇ m.
  • the wiring 7 is used as a path for supplying DC power to the semiconductor light emitting chip 3.
  • the wiring 7 has a surface layer 11 as an example of an electrode film, an intermediate layer 12, a back layer 13, and a through wiring 14.
  • the surface layer 11 includes a plurality of anode pads 15 and a plurality of cathode pads 16.
  • the plurality of anode pads 15 and the plurality of cathode pads 16 are arranged as a pair of adjacent anode pads 15 and cathode pads 16, respectively.
  • the plurality of anode pads 15 and the plurality of cathode pads 16 may include a set of a first anode pad 17 and a first cathode pad 18, and a set of a second anode pad 19 and a second cathode pad 20.
  • the first anode pad 17 and the first cathode pad 18 are for mounting the semiconductor light emitting chip 3
  • the second anode pad 19 and the second cathode pad 20 are for mounting the diode chip 4. It may be for.
  • the first cathode pad 18 includes a cathode island portion 21 to which the semiconductor light emitting chip 3 is die-bonded, and a cathode extension portion 22 extending from the cathode island portion 21.
  • the cathode island portion 21 is formed approximately at the center of the first main surface 9 of the base material 6 .
  • the cathode extension part 22 is integrally connected to the cathode island part 21. In FIG. 1, the cathode extension portion 22 is formed into a substantially L-shape when viewed from above.
  • the cathode extension portion 22 has a straight portion 23 extending along the first peripheral edge and the second peripheral edge of the base material 6 .
  • a pair of cathode extension parts 22 are formed that extend from the cathode island part 21 in mutually opposite directions (directions along the third and fourth peripheral edges of the base material 6).
  • a diode region 24 for the second anode pad 19 and the second cathode pad 20 is defined between the pair of cathode extension portions 22 (linear portions 23).
  • the first anode pad 17 includes an anode pad portion 25 to which a wiring 7 member (for example, a wire 44 described below) extending from the semiconductor light emitting chip 3 is bonded, and an anode extension portion 26 extending from the anode pad portion 25.
  • the anode pad section 25 is formed linearly along the third peripheral edge of the base material 6 on the side of the cathode island section 21 .
  • the anode extension portion 26 includes a pair of linear anode extension portions 26 extending from the anode pad portion 25 along the first peripheral edge and the second peripheral edge of the base material 6 .
  • the anode extension part 26 is formed adjacent to the cathode extension part 22 so as to be located on the same straight line as the linear part 23 of the cathode extension part 22 .
  • the second anode pad 19 and the second cathode pad 20 are arranged in the diode region 24.
  • the second anode pad 19 and the second cathode pad 20 are both formed in an island shape, and are spaced apart from each other along the fourth peripheral edge of the base material 6.
  • surface layer 11 may be formed of a plurality of conductive layers.
  • surface layer 11 includes a first conductive layer 27 and a second conductive layer 28 .
  • the first conductive layer 27 is made of Cu, for example, and may be a Cu plating layer.
  • the second conductive layer 28 is made of Au, for example, and may be an Au plating layer.
  • the first conductive layer 27 has a thickness T2 of, for example, 10 ⁇ m or more and 200 ⁇ m or less.
  • the second conductive layer 28 has a thickness T3.
  • intermediate layer 12 is formed between first main surface 9 and second main surface 10 in the thickness direction of base material 6.
  • the intermediate layer 12 is made of Cu, for example.
  • the intermediate layer 12 includes a first relay wiring 29 and a second relay wiring 30.
  • the first relay wiring 29 is electrically connected to the first anode pad 17 and the first cathode pad 18.
  • the second relay wiring 30 is electrically connected to the second anode pad 19 and the second cathode pad 20. Note that in FIG. 3, only the first relay wiring 29 connected to the first cathode pad 18 and the second relay wiring 30 connected to the second cathode pad 20 are shown.
  • the back layer 13 is formed on the second main surface 10 of the base material 6 and includes a plurality of anode mounting electrodes 31 and a plurality of cathode mounting electrodes 32.
  • the plurality of anode mounting electrodes 31 and the plurality of cathode mounting electrodes 32 are used for surface mounting the semiconductor light emitting device 1 on, for example, a circuit board.
  • the plurality of anode mounting electrodes 31 and the plurality of cathode mounting electrodes 32 are made of Au.
  • the plurality of anode mounting electrodes 31 and the plurality of cathode mounting electrodes 32 are arranged as a pair of adjacent anode mounting electrodes 31 and cathode mounting electrodes 32, respectively.
  • the plurality of anode mounted electrodes 31 and the plurality of cathode mounted electrodes 32 include a set of a first anode mounted electrode 33 and a first cathode mounted electrode 34, and a set of a second anode mounted electrode 35 and a second cathode mounted electrode 36. It's okay to stay.
  • first anode mounting electrode 33 and first cathode mounting electrode 34 are electrically connected to first anode pad 17 and first cathode pad 18, respectively.
  • the second anode mounting electrode 35 and the second cathode mounting electrode 36 are electrically connected to the second anode pad 19 and the second cathode pad 20, respectively.
  • the through wiring 14 penetrates the base material 6 in the thickness direction and electrically connects the front layer 11 and the back layer 13.
  • the through wiring 14 is exposed from both the first main surface 9 and the second main surface 10 of the base material 6.
  • the through wiring 14 may electrically connect the front layer 11 and the back layer 13 via the intermediate layer 12.
  • the through wiring 14 is made of Cu.
  • the through wiring 14 may be referred to as a "via electrode”, “through via”, “connecting via”, or “buried via” based on its shape.
  • the through wiring 14 includes a plurality of first through wirings 37 and a plurality of second through wirings 38.
  • Some of the plurality of first through wirings 37 electrically connect between the first anode pad 17 and the first anode mounting electrode 33. The remainder of the plurality of first through wirings 37 may electrically connect between the first cathode pad 18 and the first cathode mounting electrode 34. Some of the plurality of second through wirings 38 electrically connect between the second anode pad 19 and the second anode mounting electrode 35. The remainder of the plurality of second through wirings 38 may electrically connect between the second cathode pad 20 and the second cathode mounting electrode 36.
  • the semiconductor light emitting chip 3 is a vertical cavity surface emitting laser chip.
  • the semiconductor light emitting chip 3 may be a VCSEL (Vertical Cavity Surface Emitting LASER).
  • the semiconductor light emitting chip 3 has a first main surface 39 and a second main surface 40.
  • the first main surface 39 is a laser emission end surface.
  • the semiconductor light emitting chip 3 has an anode electrode 41 on the first main surface 39 and a cathode electrode 42 (omitted in FIG. 3) on the second main surface 40.
  • the semiconductor light emitting chip 3 is die-bonded to the first cathode pad 18 by bonding the cathode electrode 42 to the first cathode pad 18 via a conductive bonding material layer 43 (for example, an Ag adhesive layer).
  • the anode electrode 41 of the semiconductor light emitting chip 3 is connected to the first anode pad 17 via a plurality of wires 44 .
  • the diode chip 4 is a photodiode chip and has a first main surface 45 and a second main surface 46.
  • the first main surface 45 is the light receiving surface of the photodiode.
  • the diode chip 4 has an anode electrode 47 on a first main surface 45 and a cathode electrode 48 (omitted in FIG. 3) on a second main surface 46.
  • the diode chip 4 is mounted on the second cathode pad 20 by bonding the cathode electrode 48 to the second cathode pad 20 via a conductive bonding material layer 49 (for example, an Ag adhesive layer).
  • the anode electrode 47 of the diode chip 4 is connected to the second anode pad 19 via a plurality of wires 50.
  • the sealing resin 5 fills the housing recess 8 of the case 2 and covers the plurality of semiconductor light emitting chips 3.
  • the sealing resin 5 is made of a transparent epoxy resin or silicone resin mixed with a fluorescent material.
  • the through wiring 14 conducts heat generated in the semiconductor light emitting chip 3 and the diode chip 4 from the first main surface 9 of the base material 6 to the first main surface 9 of the base material 6 . 2 to the main surface 10. Heat on the first main surface 9 side is transmitted to the anode mounting electrode 31 and the cathode mounting electrode 32 via the through wiring 14 . Thereby, the heat within the case 2 can be diffused to the mounting board (not shown).
  • FIG. 4A is a plan view of the semiconductor light emitting device 1 showing the first arrangement pattern of the through wiring 14 (via).
  • FIG. 4B is a bottom view of the semiconductor light emitting device 1 showing the first arrangement pattern of the through wiring 14 (via).
  • the arrangement position of the semiconductor light emitting chip 3 is shown by broken lines only in FIG. 4B.
  • the diode chip 4 is not mounted, and pads and electrodes related to the diode chip 4 are omitted.
  • the through wiring 14 includes a plurality of via electrodes 51.
  • Each via electrode 51 is formed into a circular shape in plan view.
  • the width (diameter) of each via electrode 51 in plan view may be, for example, 50 ⁇ m or more and 200 ⁇ m or less.
  • the plurality of via electrodes 51 include a first via electrode 52 and a second via electrode 53.
  • the first via electrode 52 connects the first cathode pad 18 and the first cathode mounting electrode 34, and may also be referred to as a cathode via electrode.
  • the second via electrode 53 connects the first anode pad 17 and the first anode mounting electrode 33, and may be referred to as an anode via electrode.
  • the plurality of first via electrodes 52 are provided over almost the entire area of the first cathode pad 18 and the first cathode mounting electrode 34.
  • the plurality of first via electrodes 52 are arranged in a first direction They are arranged in a staggered pattern with intervals in the direction.
  • the pitch of the plurality of first via electrodes 52 may be, for example, 50 ⁇ m or more and 200 ⁇ m or less.
  • semiconductor light emitting chip 3 is arranged to face a plurality of first via electrodes 52. As shown in FIG.
  • the plurality of second via electrodes 53 are arranged in a row at intervals along the longitudinal direction of the first anode pad 17 and the first anode mounting electrode 33. More specifically, they are arranged along the longitudinal direction of the anode pad section 25.
  • the pitch of the plurality of second via electrodes 53 may be, for example, 50 ⁇ m or more and 200 ⁇ m or less.
  • the total area occupation rate of the plurality of first via electrodes 52 and the plurality of second via electrodes 53 is 10% or more and 60% or less, preferably 25% or more and 35% or less.
  • the area occupation rate is the ratio of the total planar area of each via electrode 51 to the surface area of the first main surface 9 of the base material 6. If the area occupation rate of the via electrode 51 is within the above range, the heat dissipation of the semiconductor light emitting device 1 can be improved.
  • FIG. 5A is a plan view of the semiconductor light emitting device 1 showing a second arrangement pattern of the through wiring 14 (via).
  • FIG. 5B is a bottom view of the semiconductor light emitting device 1 showing the second arrangement pattern of the through wiring 14 (via). For clarity, the arrangement position of the semiconductor light emitting chip 3 is shown by broken lines only in FIG. 5B.
  • the diode chip 4 is not mounted, and pads and electrodes related to the diode chip 4 are omitted.
  • the through wiring 14 includes a plurality of via electrodes 61.
  • the plurality of via electrodes 61 include a first via electrode 62 and a second via electrode 63.
  • the first via electrode 62 connects the first cathode pad 18 and the first cathode mounting electrode 34, and may also be referred to as a cathode via electrode.
  • the second via electrode 63 connects the first anode pad 17 and the first anode mounting electrode 33, and may be referred to as an anode via electrode.
  • Each first via electrode 62 is formed into an elliptical shape in plan view.
  • the shape of each first via electrode 62 may be expressed as an elliptical shape in a plan view or a band shape in a plan view. That is, each first via electrode 62 has a shape having a long peripheral edge 64 in the longitudinal direction having a relatively long width W1 and a short peripheral edge 65 in the direction orthogonal to the longitudinal direction having a relatively short width W2. .
  • the width W2 of each first via electrode 62 in plan view may be, for example, 50 ⁇ m or more and 200 ⁇ m or less.
  • the plurality of first via electrodes 62 can be further classified into first type via electrodes 66 and second type via electrodes 67 based on the arrangement direction. For clarity, in FIG. 5A, the first type via electrode 66 is hatched and the second type via electrode 67 is shown in outline.
  • the plurality of first type via electrodes 66 are arranged so that the long peripheral edges 64 are parallel to the first direction X. Therefore, each first type via electrode 66 is formed in a band shape extending in the first direction X.
  • the plurality of second type via electrodes 67 are arranged so that the long peripheral edges 64 are parallel to the second direction Y. That is, the second type via electrodes 67 are arranged in such a manner that the first type via electrodes 66 are rotated by 90 degrees.
  • the plurality of first lines L1 are lines parallel to the first direction X
  • the plurality of second lines L2 are lines parallel to the second direction Y.
  • the plurality of first lines L1 and the plurality of second lines L2 are each set at intervals in a stripe shape.
  • At least one first-type via electrode 66 and one second-type via electrode 67 are arranged in a partitioned region 68 corresponding to a window portion of the lattice surrounded by a plurality of lines L1 and L2.
  • the plurality of first type via electrodes 66 are arranged at intervals along each of the first line L1 and the second line L2. ing.
  • the plurality of first type via electrodes 66 along the first line L1 are arranged such that adjacent short peripheral edges 65 face each other.
  • the plurality of first type via electrodes 66 along the second line L2 are arranged such that adjacent long peripheral edges 64 face each other.
  • the plurality of second type via electrodes 67 are arranged at intervals along each of the first line L1 and the second line L2.
  • the plurality of second type via electrodes 67 along the first line L1 are arranged such that adjacent long peripheral edges 64 face each other.
  • the plurality of second type via electrodes 67 along the second line L2 are arranged such that adjacent short peripheral edges 65 face each other.
  • semiconductor light emitting chip 3 is arranged to face a plurality of first type via electrodes 66 and a plurality of second type via electrodes 67.
  • the pitch between the plurality of first type via electrodes 66 and the plurality of second type via electrodes 67 may be, for example, 50 ⁇ m or more and 200 ⁇ m or less.
  • the plurality of second via electrodes 63 are arranged in a row at intervals along the longitudinal direction of the first anode pad 17 and the first anode mounting electrode 33. More specifically, they are arranged along the longitudinal direction of the anode pad section 25. Each second via electrode 63 is formed into a circular shape in plan view. The width (diameter) of each second via electrode 63 in plan view may be, for example, 50 ⁇ m or more and 200 ⁇ m or less. The pitch of the plurality of second via electrodes 63 may be, for example, 50 ⁇ m or more and 200 ⁇ m or less.
  • the total area occupation rate of the plurality of first via electrodes 62 and the plurality of second via electrodes 63 is 10% or more and 60% or less, preferably 40% or more and 50% or less.
  • the area occupation rate is the ratio of the total planar area of each via electrode 61 to the surface area of the first main surface 9 of the base material 6. If the area occupation rate of the via electrode 61 is within the above range, the heat dissipation of the semiconductor light emitting device 1 can be improved.
  • the area occupancy rate of the second via electrodes 63 is smaller.
  • FIG. 6A is a plan view of the semiconductor light emitting device 1 showing the third arrangement pattern of the through wiring 14 (via).
  • FIG. 6B is a bottom view of the semiconductor light emitting device 1 showing the third arrangement pattern of the through wiring 14 (via). For clarity, the arrangement position of the semiconductor light emitting chip 3 is shown by broken lines only in FIG. 6B.
  • the third arrangement pattern is the same as the first arrangement pattern, except that the total area occupation rate of the plurality of first via electrodes 52 and the plurality of second via electrodes 53 is larger than that of the first arrangement pattern.
  • the total area occupation rate of the plurality of first via electrodes 52 and the plurality of second via electrodes 53 may be 10% or more and 60% or less, preferably 30% or more and 40% or less. .
  • FIG. 7A is a plan view of the semiconductor light emitting device 1 showing a fourth arrangement pattern of the through wiring 14 (via).
  • FIG. 7B is a bottom view of the semiconductor light emitting device 1 showing the fourth arrangement pattern of the through wirings 14 (vias). For clarity, the arrangement position of the semiconductor light emitting chip 3 is shown by broken lines only in FIG. 7B.
  • the fourth array pattern is a modification of the second array pattern.
  • the arrangement direction of the first type via electrode 66 and the second type via electrode 67 is not only the direction along the first line L1 and the second line L2 but also the direction intersecting these (45° in FIG. 7A). including the direction along the third line L3 extending in the direction intersecting the third line L3.
  • the plurality of first type via electrodes 66 and the plurality of second type via electrodes 67 are arranged at intervals also in the diagonal direction along the third line L3.
  • the total area occupation rate of the plurality of first via electrodes 62 and the plurality of second via electrodes 63 is larger than that of the second arrangement pattern.
  • the total area occupation rate of the plurality of first via electrodes 62 and the plurality of second via electrodes 63 is 10% or more and 60% or less, preferably 45% or more and 55% or less.
  • FIG. 8A is a plan view of a semiconductor light emitting device showing a fifth arrangement pattern of through interconnections 14 (vias).
  • FIG. 8B is a bottom view of the semiconductor light emitting device showing the fifth arrangement pattern of the through wiring 14 (via).
  • the arrangement positions of the semiconductor light emitting chip 3 and the diode chip 4 are shown by broken lines only in FIG. 8B.
  • the fifth array pattern is a modification of the second array pattern.
  • the arrangement direction of the first type via electrode 66 and the second type via electrode 67 is not only the direction along the first line L1 and the second line L2, but also the direction intersecting these (45° in FIG. 8A). including the direction along the third line L3 extending in the direction intersecting the third line L3.
  • the plurality of first type via electrodes 66 and the plurality of second type via electrodes 67 are arranged at intervals also in the diagonal direction along the third line L3.
  • the plurality of via electrodes 61 include a third via electrode 69 and a fourth via electrode 70.
  • the third via electrode 69 connects the second cathode pad 20 and the second cathode mounting electrode 36, and may also be referred to as a second cathode via electrode.
  • the fourth via electrode 70 connects the second anode pad 19 and the second anode mounting electrode 35, and may be referred to as a second anode via electrode.
  • diode chip 4 is arranged to face a plurality of third via electrodes 69.
  • Each third via electrode 69 and each fourth via electrode 70 are formed into a circular shape in plan view.
  • the width (diameter) of each third via electrode 69 and each fourth via electrode 70 in plan view may be, for example, 50 ⁇ m or more and 200 ⁇ m or less.
  • the pitch of the plurality of third via electrodes 69 and the plurality of fourth via electrodes 70 may be, for example, 50 ⁇ m or more and 200 ⁇ m or less.
  • the total area occupation rate of the plurality of via electrodes 62, 63, 69, and 70 is 10% or more and 60% or less.
  • Heat dissipation simulation results Next, the area occupation rate of the through wiring 14 (via) on the first main surface 9, the thickness T1 of the base material 6 (substrate) (see FIG. 3), and the thickness T2+T3 of the surface layer 11 (see FIG. 3) The relationship between this and the heat dissipation properties of the semiconductor light emitting device 1 was investigated by simulation. In the following simulation, a resin build-up board (multilayer board) was set as the sample base material 6.
  • the relationship between the area occupation rate of the through wiring 14 (via) on the first main surface 9 and the heat dissipation performance will be shown.
  • FIG. 9 an example in which an AlN substrate (without through wiring) is used as the base material 6 is shown as a reference example.
  • the area occupancy rate of the through wiring 14 (via) is set to 8.3%, 9.3%, 12.3%, 26.1%, 33.5%, and 40.2%. . From the results shown in FIG. 9, it was found that by increasing the area occupation rate of the through wiring 14 (via), the temperature of the base material 6 (substrate) can be reduced and the heat dissipation performance can be improved.
  • the relationship between the thickness T1 of the base material 6 (substrate) and heat dissipation is shown.
  • FIG. 10 an example in which an AlN substrate (without through wiring) is used as the base material 6 is shown as a reference example.
  • the area occupation rate of the through wiring 14 (via) was set to 40.2%, and the thickness of the base material 6 was set to 100 ⁇ m and 225 ⁇ m. From the results shown in FIG. 10, it was found that even if the thickness of the base material 6 was increased, the temperature of the base material 6 (substrate) hardly changed.
  • FIG. 11 an example in which an AlN substrate (no through wiring, substrate thickness 225 ⁇ m) is used as the base material 6 is shown as a reference example.
  • the area occupation rate of the through wiring 14 (via) was set to 40.2%, and the thickness of the base material 6 was set to 100 ⁇ m (sample 1) and 225 ⁇ m (sample 2).
  • a single layer structure of Cu was set as the surface layer 11. From the results shown in FIG. 11, it was found that in the resin base material 6, the thicker the surface layer 11 (Cu pattern), the more the heat dissipation can be improved.
  • the AlN substrate of the reference example it was found that even if the surface layer 11 was made thicker, the temperature of the base material 6 (substrate) hardly changed.
  • the area occupation rate of the through wiring 14 (via) on the first main surface 9 is preferably 10% or more and 60% or less, and more preferably 25% or more and 60% or less.
  • the thickness of the surface layer 11 (Cu pattern) is preferably 10 ⁇ m or more and 200 ⁇ m or less, more preferably 60 ⁇ m or more and 200 ⁇ m or less.
  • Appendix 1-2 The semiconductor light emitting device according to appendix 1-1, wherein the semiconductor light emitting chip includes a vertical cavity surface emitting laser chip.
  • the plurality of via electrodes have at least one of a polygonal shape, a circular shape, an elliptical shape, and an elliptical shape when viewed in plan.
  • each of the plurality of via electrodes has a portion formed with a width of 50 ⁇ m or more and 200 ⁇ m or less in plan view.
  • Appendix 1-12 The semiconductor light emitting device according to appendix 1-11, wherein the conductive bonding material layer is an Ag adhesive layer.
  • a semiconductor light emitting device comprising: a semiconductor light emitting chip disposed on the electrode film so as to face the plurality of first type via electrodes and the plurality of second type via electrodes.
  • Appendix 1-18 The semiconductor light emitting device according to appendix 1-17, wherein at least one of the second type via electrodes is arranged in a region surrounded by the plurality of lines.

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  • Led Device Packages (AREA)

Abstract

Ce dispositif électroluminescent à semi-conducteur comprend : un substrat qui a une première surface principale sur un côté et une seconde surface principale sur l'autre côté ; une pluralité d'électrodes d'interconnexion incorporées dans le substrat à des intervalles tels que le rapport d'occupation par rapport à la surface de la première surface principale sur une vue en plan est de 10 % à 60 % ; une membrane d'électrode recouvrant collectivement la pluralité d'électrodes d'interconnexion sur la première surface principale ; et une puce électroluminescente à semi-conducteur disposée sur la membrane d'électrode de façon à faire face à la pluralité d'électrodes d'interconnexion.
PCT/JP2023/007524 2022-03-31 2023-03-01 Dispositif électroluminescent à semi-conducteur WO2023189131A1 (fr)

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JP2003124408A (ja) * 2001-10-11 2003-04-25 Tokuyama Corp 放熱性基板
JP2003197835A (ja) * 2001-12-26 2003-07-11 Tdk Corp 電力増幅モジュール及び電力増幅モジュール用要素集合体
JP2004311916A (ja) * 2003-02-21 2004-11-04 Kyocera Corp 発光素子収納用パッケージおよび発光装置
JP2011054736A (ja) * 2009-09-01 2011-03-17 Sharp Corp 発光装置、平面光源および液晶表示装置
JP2017017057A (ja) * 2015-06-26 2017-01-19 日立金属株式会社 多層基板及びそれを用いた通信モジュール
US20170287807A1 (en) * 2016-03-30 2017-10-05 Qorvo Us, Inc. Electronics package with improved thermal performance
US20210267043A1 (en) * 2018-06-15 2021-08-26 Lg Innotek Co., Ltd. Printed circuit board and camera device comprising same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003124408A (ja) * 2001-10-11 2003-04-25 Tokuyama Corp 放熱性基板
JP2003197835A (ja) * 2001-12-26 2003-07-11 Tdk Corp 電力増幅モジュール及び電力増幅モジュール用要素集合体
JP2004311916A (ja) * 2003-02-21 2004-11-04 Kyocera Corp 発光素子収納用パッケージおよび発光装置
JP2011054736A (ja) * 2009-09-01 2011-03-17 Sharp Corp 発光装置、平面光源および液晶表示装置
JP2017017057A (ja) * 2015-06-26 2017-01-19 日立金属株式会社 多層基板及びそれを用いた通信モジュール
US20170287807A1 (en) * 2016-03-30 2017-10-05 Qorvo Us, Inc. Electronics package with improved thermal performance
US20210267043A1 (en) * 2018-06-15 2021-08-26 Lg Innotek Co., Ltd. Printed circuit board and camera device comprising same

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