WO2023189131A1

WO2023189131A1 - Semiconductor light emitting device

Info

Publication number: WO2023189131A1
Application number: PCT/JP2023/007524
Authority: WO
Inventors: 智一岡▲崎▼
Original assignee: ローム株式会社
Priority date: 2022-03-31
Filing date: 2023-03-01
Publication date: 2023-10-05

Abstract

This semiconductor light emitting device comprises: a substrate that has a first principal surface on one side and a second principal surface on the other side; a plurality of via electrodes embedded in the substrate at intervals such that the occupying ratio with respect to the surface area of the first principal surface in plan view is 10%-60%; an electrode membrane collectively covering the plurality of via electrodes on the first principal surface; and a semiconductor light emitting chip disposed on the electrode membrane so as to face the plurality of via electrodes.

Description

semiconductor light emitting device

Related applications

This application corresponds to Japanese Patent Application No. 2022-061325 filed with the Japan Patent Office on March 31, 2022, and the entire disclosure of this application is hereby incorporated by reference.

The present disclosure relates to a semiconductor light emitting device.

Patent Document 1 discloses a substrate, a plurality of first plated conductive parts, a plurality of second plated conductive parts, a first intermediate conductive part, a second intermediate conductive part, a third plated conductive part, a fourth plated conductive part, and a plurality of plated conductive parts. A semiconductor light emitting device including an LED chip is disclosed. The semiconductor light emitting device of Patent Document 1 further includes a first plated wiring and a second plated wiring. Each of the first plated wiring and the second plated wiring extends from a first edge of the substrate to a second edge of the substrate. When viewed in the thickness direction, the plurality of LED chips are sandwiched between the first plated wiring and the second plated wiring in the first direction. The first plated wiring and the second plated wiring are interposed between the surface of the substrate and the frame of the substrate. When viewed in the thickness direction, the first plated wiring and the second plated wiring are located apart from the recessed portion of the substrate.

JP2022-33187A

An embodiment of the present disclosure provides a semiconductor light emitting device that can improve heat dissipation.

A semiconductor light emitting device according to an embodiment of the present disclosure includes a substrate having a first main surface on one side and a second main surface on the other side, and an occupation rate of the first main surface with respect to a surface area of 10% or more in plan view. a plurality of via electrodes buried in the substrate at intervals such that the via electrodes are buried at intervals of 60% or less; an electrode film that collectively covers the plurality of via electrodes on the first main surface; and a semiconductor light emitting chip disposed on the electrode film so as to face the via electrode.

FIG. 1 is a schematic plan view of a semiconductor light emitting device according to an embodiment of the present disclosure. FIG. 2 is a schematic bottom view of the semiconductor light emitting device. FIG. 3 is a diagram showing a cross section taken along line III-III in FIG. FIG. 4A is a plan view of a semiconductor light emitting device showing a first arrangement pattern of vias. FIG. 4B is a bottom view of the semiconductor light emitting device showing the first array pattern of vias. FIG. 5A is a plan view of a semiconductor light emitting device showing a second arrangement pattern of vias. FIG. 5B is a bottom view of the semiconductor light emitting device showing a second array pattern of vias. FIG. 6A is a plan view of a semiconductor light emitting device showing a third array pattern of vias. FIG. 6B is a bottom view of the semiconductor light emitting device showing the third array pattern of vias. FIG. 7A is a plan view of a semiconductor light emitting device showing a fourth arrangement pattern of vias. FIG. 7B is a bottom view of the semiconductor light emitting device showing a fourth arrangement pattern of vias. FIG. 8A is a plan view of a semiconductor light emitting device showing a fifth array pattern of vias. FIG. 8B is a bottom view of the semiconductor light emitting device showing a fifth array pattern of vias. FIG. 9 is a diagram showing the relationship between via area ratio and heat dissipation. FIG. 10 is a diagram showing the relationship between substrate thickness and heat dissipation. FIG. 11 is a diagram showing the relationship between the thickness of the electrode film and heat dissipation.

Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
[Overall structure of semiconductor light emitting device 1]
FIG. 1 is a schematic plan view of a semiconductor light emitting device 1 according to an embodiment of the present disclosure. FIG. 2 is a schematic bottom view of the semiconductor light emitting device 1. FIG. 3 is a diagram showing a cross section taken along line III-III in FIG.

The semiconductor light emitting device 1 includes a case 2, a semiconductor light emitting chip 3, a diode chip 4, and a sealing resin 5. In addition, in FIG. 1, the sealing resin 5 is omitted for convenience of understanding.

The case 2 is the base of the semiconductor light emitting device 1 and includes a base material 6 as an example of a substrate and wiring 7. The case 2 has a size of about 5 to 10 mm square in plan view, and a thickness T1 (thickness between the first main surface 9 and the second main surface 10) of 50 μm or more and 500 μm or less. The base material 6 has a thick plate shape that is substantially rectangular in plan view, and is made of, for example, a resin substrate or a ceramic substrate made of alumina or the like. In this embodiment, a resin substrate is used as the base material 6, preferably a resin build-up substrate (multilayer substrate). A resin substrate can reduce costs compared to a ceramic substrate.

A housing recess 8 is formed in the center of the base material 6. The accommodation recess 8 accommodates the semiconductor light emitting chip 3 and the diode chip 4, and has a rectangular shape in plan view. The base material 6 has a first main surface 9 and a second main surface 10. In this embodiment, the depth of the accommodation recess 8 is, for example, about 500 μm.

The wiring 7 is used as a path for supplying DC power to the semiconductor light emitting chip 3. The wiring 7 has a surface layer 11 as an example of an electrode film, an intermediate layer 12, a back layer 13, and a through wiring 14.

The surface layer 11 includes a plurality of anode pads 15 and a plurality of cathode pads 16. Referring to FIG. 1, the plurality of anode pads 15 and the plurality of cathode pads 16 are arranged as a pair of adjacent anode pads 15 and cathode pads 16, respectively. The plurality of anode pads 15 and the plurality of cathode pads 16 may include a set of a first anode pad 17 and a first cathode pad 18, and a set of a second anode pad 19 and a second cathode pad 20. In this embodiment, the first anode pad 17 and the first cathode pad 18 are for mounting the semiconductor light emitting chip 3, and the second anode pad 19 and the second cathode pad 20 are for mounting the diode chip 4. It may be for.

The first cathode pad 18 includes a cathode island portion 21 to which the semiconductor light emitting chip 3 is die-bonded, and a cathode extension portion 22 extending from the cathode island portion 21. The cathode island portion 21 is formed approximately at the center of the first main surface 9 of the base material 6 . The cathode extension part 22 is integrally connected to the cathode island part 21. In FIG. 1, the cathode extension portion 22 is formed into a substantially L-shape when viewed from above. The cathode extension portion 22 has a straight portion 23 extending along the first peripheral edge and the second peripheral edge of the base material 6 . In this embodiment, a pair of cathode extension parts 22 are formed that extend from the cathode island part 21 in mutually opposite directions (directions along the third and fourth peripheral edges of the base material 6). A diode region 24 for the second anode pad 19 and the second cathode pad 20 is defined between the pair of cathode extension portions 22 (linear portions 23).

The first anode pad 17 includes an anode pad portion 25 to which a wiring 7 member (for example, a wire 44 described below) extending from the semiconductor light emitting chip 3 is bonded, and an anode extension portion 26 extending from the anode pad portion 25. The anode pad section 25 is formed linearly along the third peripheral edge of the base material 6 on the side of the cathode island section 21 . The anode extension portion 26 includes a pair of linear anode extension portions 26 extending from the anode pad portion 25 along the first peripheral edge and the second peripheral edge of the base material 6 . The anode extension part 26 is formed adjacent to the cathode extension part 22 so as to be located on the same straight line as the linear part 23 of the cathode extension part 22 .

The second anode pad 19 and the second cathode pad 20 are arranged in the diode region 24. The second anode pad 19 and the second cathode pad 20 are both formed in an island shape, and are spaced apart from each other along the fourth peripheral edge of the base material 6.

Referring to FIG. 3, surface layer 11 may be formed of a plurality of conductive layers. In this embodiment, surface layer 11 includes a first conductive layer 27 and a second conductive layer 28 . The first conductive layer 27 is made of Cu, for example, and may be a Cu plating layer. The second conductive layer 28 is made of Au, for example, and may be an Au plating layer. The first conductive layer 27 has a thickness T2 of, for example, 10 μm or more and 200 μm or less. The second conductive layer 28 has a thickness T3.

Referring to FIG. 3, intermediate layer 12 is formed between first main surface 9 and second main surface 10 in the thickness direction of base material 6. The intermediate layer 12 is made of Cu, for example. The intermediate layer 12 includes a first relay wiring 29 and a second relay wiring 30. The first relay wiring 29 is electrically connected to the first anode pad 17 and the first cathode pad 18. The second relay wiring 30 is electrically connected to the second anode pad 19 and the second cathode pad 20. Note that in FIG. 3, only the first relay wiring 29 connected to the first cathode pad 18 and the second relay wiring 30 connected to the second cathode pad 20 are shown.

The back layer 13 is formed on the second main surface 10 of the base material 6 and includes a plurality of anode mounting electrodes 31 and a plurality of cathode mounting electrodes 32. The plurality of anode mounting electrodes 31 and the plurality of cathode mounting electrodes 32 are used for surface mounting the semiconductor light emitting device 1 on, for example, a circuit board. In this embodiment, the plurality of anode mounting electrodes 31 and the plurality of cathode mounting electrodes 32 are made of Au.

The plurality of anode mounting electrodes 31 and the plurality of cathode mounting electrodes 32 are arranged as a pair of adjacent anode mounting electrodes 31 and cathode mounting electrodes 32, respectively. The plurality of anode mounted electrodes 31 and the plurality of cathode mounted electrodes 32 include a set of a first anode mounted electrode 33 and a first cathode mounted electrode 34, and a set of a second anode mounted electrode 35 and a second cathode mounted electrode 36. It's okay to stay. In this embodiment, first anode mounting electrode 33 and first cathode mounting electrode 34 are electrically connected to first anode pad 17 and first cathode pad 18, respectively. The second anode mounting electrode 35 and the second cathode mounting electrode 36 are electrically connected to the second anode pad 19 and the second cathode pad 20, respectively.

The through wiring 14 penetrates the base material 6 in the thickness direction and electrically connects the front layer 11 and the back layer 13. The through wiring 14 is exposed from both the first main surface 9 and the second main surface 10 of the base material 6. The through wiring 14 may electrically connect the front layer 11 and the back layer 13 via the intermediate layer 12. In this embodiment, the through wiring 14 is made of Cu. Further, the through wiring 14 may be referred to as a "via electrode", "through via", "connecting via", or "buried via" based on its shape. The through wiring 14 includes a plurality of first through wirings 37 and a plurality of second through wirings 38.

Some of the plurality of first through wirings 37 electrically connect between the first anode pad 17 and the first anode mounting electrode 33. The remainder of the plurality of first through wirings 37 may electrically connect between the first cathode pad 18 and the first cathode mounting electrode 34. Some of the plurality of second through wirings 38 electrically connect between the second anode pad 19 and the second anode mounting electrode 35. The remainder of the plurality of second through wirings 38 may electrically connect between the second cathode pad 20 and the second cathode mounting electrode 36.

In this embodiment, the semiconductor light emitting chip 3 is a vertical cavity surface emitting laser chip. The semiconductor light emitting chip 3 may be a VCSEL (Vertical Cavity Surface Emitting LASER). The semiconductor light emitting chip 3 has a first main surface 39 and a second main surface 40. The first main surface 39 is a laser emission end surface. The semiconductor light emitting chip 3 has an anode electrode 41 on the first main surface 39 and a cathode electrode 42 (omitted in FIG. 3) on the second main surface 40. The semiconductor light emitting chip 3 is die-bonded to the first cathode pad 18 by bonding the cathode electrode 42 to the first cathode pad 18 via a conductive bonding material layer 43 (for example, an Ag adhesive layer). The anode electrode 41 of the semiconductor light emitting chip 3 is connected to the first anode pad 17 via a plurality of wires 44 .

In this embodiment, the diode chip 4 is a photodiode chip and has a first main surface 45 and a second main surface 46. The first main surface 45 is the light receiving surface of the photodiode. The diode chip 4 has an anode electrode 47 on a first main surface 45 and a cathode electrode 48 (omitted in FIG. 3) on a second main surface 46. The diode chip 4 is mounted on the second cathode pad 20 by bonding the cathode electrode 48 to the second cathode pad 20 via a conductive bonding material layer 49 (for example, an Ag adhesive layer). The anode electrode 47 of the diode chip 4 is connected to the second anode pad 19 via a plurality of wires 50.

The sealing resin 5 fills the housing recess 8 of the case 2 and covers the plurality of semiconductor light emitting chips 3. The sealing resin 5 is made of a transparent epoxy resin or silicone resin mixed with a fluorescent material.
[Explanation of arrangement pattern of through wiring 14 (via)]
In addition to electrically connecting the front layer 11 and the back layer 13 , the through wiring 14 conducts heat generated in the semiconductor light emitting chip 3 and the diode chip 4 from the first main surface 9 of the base material 6 to the first main surface 9 of the base material 6 . 2 to the main surface 10. Heat on the first main surface 9 side is transmitted to the anode mounting electrode 31 and the cathode mounting electrode 32 via the through wiring 14 . Thereby, the heat within the case 2 can be diffused to the mounting board (not shown). That is, the through wiring 14 contributes to the heat dissipation of the semiconductor light emitting device 1. In the following, a detailed explanation of a preferable arrangement pattern of the through wiring 14 will be added regarding the heat dissipation performance of the semiconductor light emitting device 1.
(1) First Arrangement Pattern FIG. 4A is a plan view of the semiconductor light emitting device 1 showing the first arrangement pattern of the through wiring 14 (via). FIG. 4B is a bottom view of the semiconductor light emitting device 1 showing the first arrangement pattern of the through wiring 14 (via). For clarity, the arrangement position of the semiconductor light emitting chip 3 is shown by broken lines only in FIG. 4B.

Referring to FIGS. 4A and 4B, in the semiconductor light emitting device 1 of this example, the diode chip 4 is not mounted, and pads and electrodes related to the diode chip 4 are omitted. In the first arrangement pattern, the through wiring 14 includes a plurality of via electrodes 51. Each via electrode 51 is formed into a circular shape in plan view. The width (diameter) of each via electrode 51 in plan view may be, for example, 50 μm or more and 200 μm or less.

The plurality of via electrodes 51 include a first via electrode 52 and a second via electrode 53. The first via electrode 52 connects the first cathode pad 18 and the first cathode mounting electrode 34, and may also be referred to as a cathode via electrode. The second via electrode 53 connects the first anode pad 17 and the first anode mounting electrode 33, and may be referred to as an anode via electrode.

The plurality of first via electrodes 52 are provided over almost the entire area of the first cathode pad 18 and the first cathode mounting electrode 34. The plurality of first via electrodes 52 are arranged in a first direction They are arranged in a staggered pattern with intervals in the direction. The pitch of the plurality of first via electrodes 52 may be, for example, 50 μm or more and 200 μm or less. Referring to FIG. 4B, semiconductor light emitting chip 3 is arranged to face a plurality of first via electrodes 52. As shown in FIG.

The plurality of second via electrodes 53 are arranged in a row at intervals along the longitudinal direction of the first anode pad 17 and the first anode mounting electrode 33. More specifically, they are arranged along the longitudinal direction of the anode pad section 25. The pitch of the plurality of second via electrodes 53 may be, for example, 50 μm or more and 200 μm or less.

In the first arrangement pattern, the total area occupation rate of the plurality of first via electrodes 52 and the plurality of second via electrodes 53 is 10% or more and 60% or less, preferably 25% or more and 35% or less. The area occupation rate is the ratio of the total planar area of each via electrode 51 to the surface area of the first main surface 9 of the base material 6. If the area occupation rate of the via electrode 51 is within the above range, the heat dissipation of the semiconductor light emitting device 1 can be improved.

Further, when comparing the area occupancy rate of the plurality of first via electrodes 52 and the area occupancy rate of the plurality of second via electrodes 53, the area occupancy rate of the second via electrode 53 is smaller. By increasing the occupancy of the vias on the cathode side, which is the electrode on which the semiconductor light emitting chip 3 is mounted, the heat dissipation performance of the semiconductor light emitting device 1 can be further improved.
(2) Second Arrangement Pattern FIG. 5A is a plan view of the semiconductor light emitting device 1 showing a second arrangement pattern of the through wiring 14 (via). FIG. 5B is a bottom view of the semiconductor light emitting device 1 showing the second arrangement pattern of the through wiring 14 (via). For clarity, the arrangement position of the semiconductor light emitting chip 3 is shown by broken lines only in FIG. 5B.

Referring to FIGS. 5A and 5B, in the semiconductor light emitting device 1 of this example, the diode chip 4 is not mounted, and pads and electrodes related to the diode chip 4 are omitted. In the second arrangement pattern, the through wiring 14 includes a plurality of via electrodes 61. The plurality of via electrodes 61 include a first via electrode 62 and a second via electrode 63. The first via electrode 62 connects the first cathode pad 18 and the first cathode mounting electrode 34, and may also be referred to as a cathode via electrode. The second via electrode 63 connects the first anode pad 17 and the first anode mounting electrode 33, and may be referred to as an anode via electrode.

Each first via electrode 62 is formed into an elliptical shape in plan view. The shape of each first via electrode 62 may be expressed as an elliptical shape in a plan view or a band shape in a plan view. That is, each first via electrode 62 has a shape having a long peripheral edge 64 in the longitudinal direction having a relatively long width W1 and a short peripheral edge 65 in the direction orthogonal to the longitudinal direction having a relatively short width W2. . The width W2 of each first via electrode 62 in plan view may be, for example, 50 μm or more and 200 μm or less.

The plurality of first via electrodes 62 can be further classified into first type via electrodes 66 and second type via electrodes 67 based on the arrangement direction. For clarity, in FIG. 5A, the first type via electrode 66 is hatched and the second type via electrode 67 is shown in outline.

The plurality of first type via electrodes 66 are arranged so that the long peripheral edges 64 are parallel to the first direction X. Therefore, each first type via electrode 66 is formed in a band shape extending in the first direction X. On the other hand, the plurality of second type via electrodes 67 are arranged so that the long peripheral edges 64 are parallel to the second direction Y. That is, the second type via electrodes 67 are arranged in such a manner that the first type via electrodes 66 are rotated by 90 degrees.

Here, consider a case where a plurality of lines L1 and L2 extending in a grid pattern so as to intersect both the first direction X and the second direction Y are set on the first main surface 9. The plurality of first lines L1 are lines parallel to the first direction X, and the plurality of second lines L2 are lines parallel to the second direction Y. The plurality of first lines L1 and the plurality of second lines L2 are each set at intervals in a stripe shape. At least one first-type via electrode 66 and one second-type via electrode 67 are arranged in a partitioned region 68 corresponding to a window portion of the lattice surrounded by a plurality of lines L1 and L2.

When looking at the first type via electrodes 66 and the second type via electrodes 67 individually, the plurality of first type via electrodes 66 are arranged at intervals along each of the first line L1 and the second line L2. ing. The plurality of first type via electrodes 66 along the first line L1 are arranged such that adjacent short peripheral edges 65 face each other. The plurality of first type via electrodes 66 along the second line L2 are arranged such that adjacent long peripheral edges 64 face each other. The plurality of second type via electrodes 67 are arranged at intervals along each of the first line L1 and the second line L2. The plurality of second type via electrodes 67 along the first line L1 are arranged such that adjacent long peripheral edges 64 face each other. The plurality of second type via electrodes 67 along the second line L2 are arranged such that adjacent short peripheral edges 65 face each other. Referring to FIG. 5B, semiconductor light emitting chip 3 is arranged to face a plurality of first type via electrodes 66 and a plurality of second type via electrodes 67. Further, the pitch between the plurality of first type via electrodes 66 and the plurality of second type via electrodes 67 may be, for example, 50 μm or more and 200 μm or less.

The plurality of second via electrodes 63 are arranged in a row at intervals along the longitudinal direction of the first anode pad 17 and the first anode mounting electrode 33. More specifically, they are arranged along the longitudinal direction of the anode pad section 25. Each second via electrode 63 is formed into a circular shape in plan view. The width (diameter) of each second via electrode 63 in plan view may be, for example, 50 μm or more and 200 μm or less. The pitch of the plurality of second via electrodes 63 may be, for example, 50 μm or more and 200 μm or less.

In the second arrangement pattern, the total area occupation rate of the plurality of first via electrodes 62 and the plurality of second via electrodes 63 is 10% or more and 60% or less, preferably 40% or more and 50% or less. The area occupation rate is the ratio of the total planar area of each via electrode 61 to the surface area of the first main surface 9 of the base material 6. If the area occupation rate of the via electrode 61 is within the above range, the heat dissipation of the semiconductor light emitting device 1 can be improved.

Furthermore, when comparing the area occupancy rate of the plurality of first via electrodes 62 and the area occupancy rate of the plurality of second via electrodes 63, the area occupancy rate of the second via electrodes 63 is smaller. By increasing the occupancy of the vias on the cathode side, which is the electrode on which the semiconductor light emitting chip 3 is mounted, the heat dissipation performance of the semiconductor light emitting device 1 can be further improved.

Furthermore, by mixing the first type via electrode 66 and the second type via electrode 67 that extend in different directions with respect to the first via electrode 62, the stress applied to the base material 6 can be dispersed in a plurality of directions.
(3) Third Arrangement Pattern FIG. 6A is a plan view of the semiconductor light emitting device 1 showing the third arrangement pattern of the through wiring 14 (via). FIG. 6B is a bottom view of the semiconductor light emitting device 1 showing the third arrangement pattern of the through wiring 14 (via). For clarity, the arrangement position of the semiconductor light emitting chip 3 is shown by broken lines only in FIG. 6B.

The third arrangement pattern is the same as the first arrangement pattern, except that the total area occupation rate of the plurality of first via electrodes 52 and the plurality of second via electrodes 53 is larger than that of the first arrangement pattern. In the third arrangement pattern, the total area occupation rate of the plurality of first via electrodes 52 and the plurality of second via electrodes 53 may be 10% or more and 60% or less, preferably 30% or more and 40% or less. .
(4) Fourth Arrangement Pattern FIG. 7A is a plan view of the semiconductor light emitting device 1 showing a fourth arrangement pattern of the through wiring 14 (via). FIG. 7B is a bottom view of the semiconductor light emitting device 1 showing the fourth arrangement pattern of the through wirings 14 (vias). For clarity, the arrangement position of the semiconductor light emitting chip 3 is shown by broken lines only in FIG. 7B.

The fourth array pattern is a modification of the second array pattern. Specifically, the arrangement direction of the first type via electrode 66 and the second type via electrode 67 is not only the direction along the first line L1 and the second line L2 but also the direction intersecting these (45° in FIG. 7A). including the direction along the third line L3 extending in the direction intersecting the third line L3. As a result, the plurality of first type via electrodes 66 and the plurality of second type via electrodes 67 are arranged at intervals also in the diagonal direction along the third line L3.

Furthermore, the total area occupation rate of the plurality of first via electrodes 62 and the plurality of second via electrodes 63 is larger than that of the second arrangement pattern. For example, in the fourth arrangement pattern, the total area occupation rate of the plurality of first via electrodes 62 and the plurality of second via electrodes 63 is 10% or more and 60% or less, preferably 45% or more and 55% or less. Good too.
(5) Fifth Arrangement Pattern FIG. 8A is a plan view of a semiconductor light emitting device showing a fifth arrangement pattern of through interconnections 14 (vias). FIG. 8B is a bottom view of the semiconductor light emitting device showing the fifth arrangement pattern of the through wiring 14 (via). For clarity, the arrangement positions of the semiconductor light emitting chip 3 and the diode chip 4 are shown by broken lines only in FIG. 8B.

The fifth array pattern is a modification of the second array pattern. Specifically, the arrangement direction of the first type via electrode 66 and the second type via electrode 67 is not only the direction along the first line L1 and the second line L2, but also the direction intersecting these (45° in FIG. 8A). including the direction along the third line L3 extending in the direction intersecting the third line L3. As a result, the plurality of first type via electrodes 66 and the plurality of second type via electrodes 67 are arranged at intervals also in the diagonal direction along the third line L3.

Furthermore, the plurality of via electrodes 61 include a third via electrode 69 and a fourth via electrode 70. The third via electrode 69 connects the second cathode pad 20 and the second cathode mounting electrode 36, and may also be referred to as a second cathode via electrode. The fourth via electrode 70 connects the second anode pad 19 and the second anode mounting electrode 35, and may be referred to as a second anode via electrode. Referring to FIG. 8B, diode chip 4 is arranged to face a plurality of third via electrodes 69.

Each third via electrode 69 and each fourth via electrode 70 are formed into a circular shape in plan view. The width (diameter) of each third via electrode 69 and each fourth via electrode 70 in plan view may be, for example, 50 μm or more and 200 μm or less. The pitch of the plurality of third via electrodes 69 and the plurality of fourth via electrodes 70 may be, for example, 50 μm or more and 200 μm or less.

In the fifth array pattern, the total area occupation rate of the plurality of via

electrodes

62, 63, 69, and 70 is 10% or more and 60% or less.
[Heat dissipation simulation results]
Next, the area occupation rate of the through wiring 14 (via) on the first main surface 9, the thickness T1 of the base material 6 (substrate) (see FIG. 3), and the thickness T2+T3 of the surface layer 11 (see FIG. 3) The relationship between this and the heat dissipation properties of the semiconductor light emitting device 1 was investigated by simulation. In the following simulation, a resin build-up board (multilayer board) was set as the sample base material 6.

First, with reference to FIG. 9, the relationship between the area occupation rate of the through wiring 14 (via) on the first main surface 9 and the heat dissipation performance will be shown. In FIG. 9, an example in which an AlN substrate (without through wiring) is used as the base material 6 is shown as a reference example. In the samples, the area occupancy rate of the through wiring 14 (via) is set to 8.3%, 9.3%, 12.3%, 26.1%, 33.5%, and 40.2%. . From the results shown in FIG. 9, it was found that by increasing the area occupation rate of the through wiring 14 (via), the temperature of the base material 6 (substrate) can be reduced and the heat dissipation performance can be improved.

Next, with reference to FIG. 10, the relationship between the thickness T1 of the base material 6 (substrate) and heat dissipation is shown. In FIG. 10, an example in which an AlN substrate (without through wiring) is used as the base material 6 is shown as a reference example. In the sample, the area occupation rate of the through wiring 14 (via) was set to 40.2%, and the thickness of the base material 6 was set to 100 μm and 225 μm. From the results shown in FIG. 10, it was found that even if the thickness of the base material 6 was increased, the temperature of the base material 6 (substrate) hardly changed.

Next, with reference to FIG. 11, the relationship between the thickness of the surface layer 11 and heat dissipation is shown. In FIG. 11, an example in which an AlN substrate (no through wiring, substrate thickness 225 μm) is used as the base material 6 is shown as a reference example. In

samples

1 and 2, the area occupation rate of the through wiring 14 (via) was set to 40.2%, and the thickness of the base material 6 was set to 100 μm (sample 1) and 225 μm (sample 2). . Furthermore, a single layer structure of Cu was set as the surface layer 11. From the results shown in FIG. 11, it was found that in the resin base material 6, the thicker the surface layer 11 (Cu pattern), the more the heat dissipation can be improved. On the other hand, in the AlN substrate of the reference example, it was found that even if the surface layer 11 was made thicker, the temperature of the base material 6 (substrate) hardly changed.

As described above, from the results shown in FIGS. 9 to 11, even when a resin substrate whose thermal conductivity is considerably lower than that of an AlN substrate is used as the base material 6, the area occupation rate of the through wiring 14 (via) on the first main surface 9 is It has been found that the heat dissipation property approaches that of the AlN substrate by adjusting the value to 10% or more and 60% or less. Furthermore, it was found that further improvement in heat dissipation performance could be achieved by appropriately adjusting the thickness of the surface layer 11 (Cu pattern).

From this simulation, the area occupation rate of the through wiring 14 (via) on the first main surface 9 is preferably 10% or more and 60% or less, and more preferably 25% or more and 60% or less. Moreover, the thickness of the surface layer 11 (Cu pattern) is preferably 10 μm or more and 200 μm or less, more preferably 60 μm or more and 200 μm or less.

Although embodiments of the present disclosure have been described, the present disclosure may be implemented in other forms.

As described above, the embodiments of the present disclosure are illustrative in all respects and should not be construed as limiting, and are intended to include changes in all respects.

The features described below can be extracted from the description of this specification and drawings.

[Appendix 1-1]
a substrate having a first main surface on one side and a second main surface on the other side;
a plurality of via electrodes embedded in the substrate at intervals such that the occupation rate with respect to the surface area of the first principal surface is 10% or more and 60% or less in plan view;
an electrode film that collectively covers the plurality of via electrodes on the first main surface;
and a semiconductor light emitting chip disposed on the electrode film so as to face the plurality of via electrodes.

[Appendix 1-2]
The semiconductor light emitting device according to appendix 1-1, wherein the semiconductor light emitting chip includes a vertical cavity surface emitting laser chip.

[Appendix 1-3]
The semiconductor light emitting device according to attachment 1-1 or attachment 1-2, wherein the plurality of via electrodes are exposed from the first main surface and the second main surface.

[Appendix 1-4]
According to any one of Supplementary Notes 1-1 to 1-3, the plurality of via electrodes have at least one of a polygonal shape, a circular shape, an elliptical shape, and an elliptical shape when viewed in plan. The semiconductor light emitting device described above.

[Appendix 1-5]
Supplementary notes 1-1 to 1-4, wherein the plurality of via electrodes are arranged in rows and columns or in a staggered manner with intervals in a first direction and a second direction intersecting the first direction when viewed in plan. The semiconductor light emitting device according to any one of the above.

[Appendix 1-6]
The semiconductor light emitting device according to any one of Supplementary notes 1-1 to 1-5, wherein the plurality of via electrodes are arranged at a pitch of 50 μm or more and 200 μm or less.

[Appendix 1-7]
The semiconductor light emitting device according to any one of Supplementary notes 1-1 to 1-6, wherein each of the plurality of via electrodes has a portion formed with a width of 50 μm or more and 200 μm or less in plan view.

[Appendix 1-8]
The semiconductor light emitting device according to any one of Supplementary notes 1-1 to 1-7, wherein the electrode film has a thickness of 10 μm or more and 200 μm or less.

[Appendix 1-9]
a plurality of second via electrodes buried in the substrate at intervals from the plurality of via electrodes;
a second electrode film that covers the plurality of second via electrodes at a distance from the electrode film on the first main surface;
The semiconductor light-emitting device according to any one of Supplementary Notes 1-1 to 1-8, further comprising a conductive wire connecting the semiconductor light-emitting chip and the second electrode film.

[Appendix 1-10]
Supplementary Note 1, wherein the plurality of second via electrodes are embedded in the substrate such that the occupancy of the surface area of the first main surface is smaller than the occupancy of the plurality of via electrodes in plan view. -9. The semiconductor light emitting device according to item 9.

[Appendix 1-11]
The semiconductor light emitting device according to any one of Supplementary Notes 1-1 to 1-10, further comprising a conductive bonding material layer interposed between the semiconductor light emitting chip and the electrode film.

[Appendix 1-12]
The semiconductor light emitting device according to appendix 1-11, wherein the conductive bonding material layer is an Ag adhesive layer.

[Appendix 1-13]
The semiconductor light emitting device according to any one of Supplementary notes 1-1 to 1-12, wherein the substrate includes a resin substrate.

[Appendix 1-14]
The semiconductor light emitting device according to any one of Supplementary notes 1-1 to 1-13, wherein at least one of the plurality of via electrodes and the electrode film contains a Cu-based metal.

[Appendix 1-15]
a substrate having a first main surface on one side and a second main surface on the other side;
a plurality of first type via electrodes each formed in a band shape extending in a first direction along the first main surface in plan view and embedded in the substrate;
The plurality of electrodes are each formed in a band shape extending in a second direction intersecting the first direction along the first main surface in a plan view, and are arranged so as to face at least one first type via electrode in the first direction. a plurality of second type via electrodes buried in the substrate at intervals from the first type via electrodes;
an electrode film that collectively covers the plurality of first type via electrodes and the plurality of second type via electrodes on the first main surface;
A semiconductor light emitting device, comprising: a semiconductor light emitting chip disposed on the electrode film so as to face the plurality of first type via electrodes and the plurality of second type via electrodes.

[Appendix 1-16]
When a plurality of lines extending in a stripe shape in the second direction in plan view are set on the first main surface, the plurality of first type via electrodes are arranged at intervals on the plurality of lines. The semiconductor light emitting device according to Supplementary Note 1-15.

[Appendix 1-17]
When a plurality of lines extending in a lattice shape so as to intersect both the first direction and the second direction in a plan view are set on the first main surface, the plurality of first type via electrodes are The semiconductor light emitting devices according to appendix 1-15, which are arranged on the line at intervals.

[Appendix 1-18]
The semiconductor light emitting device according to appendix 1-17, wherein at least one of the second type via electrodes is arranged in a region surrounded by the plurality of lines.

[Appendix 1-19]
The semiconductor light emitting device according to attachment 1-17 or attachment 1-18, wherein at least one of the first type via electrodes is arranged in a region surrounded by the plurality of lines.

[Appendix 1-20]
Supplementary Note 1-15~, wherein the total occupancy of the plurality of first type via electrodes and the plurality of second type via electrodes with respect to the surface area of the first principal surface in plan view is 10% or more and 50% or less. The semiconductor light emitting device according to any one of Supplementary Notes 1-19.

1: Semiconductor light emitting device 2: Case 3: Semiconductor light emitting chip 4: Diode chip 5: Sealing resin 6: Base material 7: Wiring 8: Accommodating recess 9: First main surface 10: Second main surface 11: Surface layer 12 : Intermediate layer 13 : Back layer 14 : Penetrating wiring 15 : Anode pad 16 : Cathode pad 17 : First anode pad 18 : First cathode pad 19 : Second anode pad 20 : Second cathode pad 21 : Cathode island part 22 : Cathode extension part 23 : Straight part 24 : Diode region 25 : Anode pad part 26 : Anode extension part 27 : First conductive layer 28 : Second conductive layer 29 : First relay wiring 30 : Second relay wiring 31 : Anode Mounted electrode 32 : Cathode mounted electrode 33 : First anode mounted electrode 34 : First cathode mounted electrode 35 : Second anode mounted electrode 36 : Second cathode mounted electrode 37 : First through wiring 38 : Second through wiring 39 : First 1 principal surface 40 : 2nd principal surface 41 : anode electrode 42 : cathode electrode 43 : conductive bonding material layer 44 : wire 45 : 1st principal surface 46 : 2nd principal surface 47 : anode electrode 48 : cathode electrode 49 : conductive bond Material layer 50: Wire 51: Via electrode 52: First via electrode 53: Second via electrode 61: Via electrode 62: First via electrode 63: Second via electrode 64: Long peripheral edge 65: Short peripheral edge 66: First type Via electrode 67 : Second type via electrode 68 : Division area 69 : Third via electrode 70 : Fourth via electrode L1 : First line L2 : Second line L3 : Third line T1 : Thickness T2 : Thickness T3 : Thickness W1: Width W2: Width

Claims

a substrate having a first main surface on one side and a second main surface on the other side;
a plurality of via electrodes embedded in the substrate at intervals such that the occupation rate with respect to the surface area of the first principal surface is 10% or more and 60% or less in plan view;
an electrode film that collectively covers the plurality of via electrodes on the first main surface;
and a semiconductor light emitting chip disposed on the electrode film so as to face the plurality of via electrodes.
The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting chip includes a vertical cavity surface emitting laser chip.
3. The semiconductor light emitting device according to claim 1, wherein the plurality of via electrodes are exposed from the first main surface and the second main surface.
The semiconductor light emitting device according to any one of claims 1 to 3, wherein the plurality of via electrodes have at least one of a polygonal shape, a circular shape, an elliptical shape, and an elliptical shape in plan view. Device.
5. The method according to claim 1, wherein the plurality of via electrodes are arranged in a matrix or in a staggered manner at intervals in a first direction and a second direction intersecting the first direction when viewed in plan. The semiconductor light-emitting device described in 2.
The semiconductor light emitting device according to any one of claims 1 to 5, wherein the plurality of via electrodes are arranged at a pitch of 50 μm or more and 200 μm or less.
The semiconductor light emitting device according to any one of claims 1 to 6, wherein each of the plurality of via electrodes has a portion formed with a width of 50 μm or more and 200 μm or less in plan view.
The semiconductor light emitting device according to any one of claims 1 to 7, wherein the electrode film has a thickness of 10 μm or more and 200 μm or less.
a plurality of second via electrodes buried in the substrate at intervals from the plurality of via electrodes;
a second electrode film that covers the plurality of second via electrodes at a distance from the electrode film on the first main surface;
9. The semiconductor light emitting device according to claim 1, further comprising a conductive wire connecting the semiconductor light emitting chip and the second electrode film.
2. The plurality of second via electrodes are embedded in the substrate so that the occupancy of the surface area of the first main surface is smaller than the occupancy of the plurality of via electrodes in plan view. 9. The semiconductor light emitting device according to 9.
The semiconductor light emitting device according to any one of claims 1 to 10, further comprising a conductive bonding material layer interposed between the semiconductor light emitting chip and the electrode film.
The semiconductor light emitting device according to claim 11, wherein the conductive bonding material layer is made of an Ag adhesive layer.
The semiconductor light emitting device according to any one of claims 1 to 12, wherein the substrate includes a resin substrate.
The semiconductor light emitting device according to any one of claims 1 to 13, wherein at least one of the plurality of via electrodes and the electrode film contains a Cu-based metal.
a substrate having a first main surface on one side and a second main surface on the other side;
a plurality of first type via electrodes each formed in a band shape extending in a first direction along the first main surface in plan view and embedded in the substrate;
The plurality of electrodes are each formed in a band shape extending in a second direction intersecting the first direction along the first main surface in a plan view, and are arranged so as to face at least one first type via electrode in the first direction. a plurality of second type via electrodes buried in the substrate at intervals from the first type via electrodes;
an electrode film that collectively covers the plurality of first type via electrodes and the plurality of second type via electrodes on the first main surface;
A semiconductor light emitting device, comprising: a semiconductor light emitting chip disposed on the electrode film so as to face the plurality of first type via electrodes and the plurality of second type via electrodes.
When a plurality of lines extending in a stripe shape in the second direction in plan view are set on the first main surface, the plurality of first type via electrodes are arranged at intervals on the plurality of lines. The semiconductor light emitting device according to claim 15.
When a plurality of lines extending in a lattice shape so as to intersect both the first direction and the second direction in a plan view are set on the first main surface, the plurality of first type via electrodes are The semiconductor light emitting device according to claim 15, wherein the semiconductor light emitting devices are arranged on the line at intervals.
The semiconductor light emitting device according to claim 17, wherein at least one of the second type via electrodes is arranged in a region surrounded by the plurality of lines.
The semiconductor light emitting device according to claim 17 or 18, wherein at least one of the first type via electrodes is arranged in a region surrounded by the plurality of lines.
Claims 15 to 19, wherein the total occupancy rate of the plurality of first type via electrodes and the plurality of second type via electrodes with respect to the surface area of the first principal surface in plan view is 10% or more and 50% or less. The semiconductor light emitting device according to any one of the above.