WO2023188755A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023188755A1
WO2023188755A1 PCT/JP2023/002429 JP2023002429W WO2023188755A1 WO 2023188755 A1 WO2023188755 A1 WO 2023188755A1 JP 2023002429 W JP2023002429 W JP 2023002429W WO 2023188755 A1 WO2023188755 A1 WO 2023188755A1
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WIPO (PCT)
Prior art keywords
source
trench
semiconductor device
gate
electrode
Prior art date
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Ceased
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PCT/JP2023/002429
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English (en)
French (fr)
Japanese (ja)
Inventor
賢樹 長田
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Rohm Co Ltd
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Rohm Co Ltd
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Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2024511306A priority Critical patent/JPWO2023188755A1/ja
Priority to CN202380029911.4A priority patent/CN118922948A/zh
Publication of WO2023188755A1 publication Critical patent/WO2023188755A1/ja
Priority to US18/890,814 priority patent/US20250015151A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/254—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 discloses a semiconductor device in which a plurality of source contact holes for forming source plug electrodes are arranged alternately with a plurality of gate trenches.
  • a source contact plug placed between gate trenches if the position of a source contact plug placed between gate trenches is shifted, variations in characteristics (eg, gate threshold voltage, on-resistance, etc.) may occur.
  • characteristics eg, gate threshold voltage, on-resistance, etc.
  • a semiconductor device includes a semiconductor layer including a first surface and a second surface opposite to the first surface, and a sidewall formed on the semiconductor layer and continuous with the second surface. a source trench, an insulating layer formed on the second surface of the semiconductor layer, a buried electrode disposed within the source trench and separated from the sidewall of the source trench by the insulating layer;
  • the semiconductor device includes a source wiring formed on an insulating layer, and a source contact plug that electrically connects the source wiring to the semiconductor layer.
  • the source contact plug contacts the buried electrode and also contacts the semiconductor layer through a part of the side wall of the source trench.
  • the semiconductor device of the present disclosure can suppress variations in characteristics due to misalignment of the source contact plug.
  • FIG. 1 is a schematic plan view of an exemplary semiconductor device according to a first embodiment.
  • FIG. 2 is a plan view showing the end portions of the gate trench and the source trench.
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment taken along line F3-F3 in FIG.
  • FIG. 4 is a schematic cross-sectional view of the semiconductor device according to the first embodiment taken along line F4-F4 in FIG.
  • FIG. 5 is a schematic cross-sectional view of the semiconductor device according to the first embodiment taken along line F5-F5 in FIG.
  • FIG. 6 is a schematic cross-sectional view showing an exemplary manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 7 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 6.
  • FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 7.
  • FIG. 9 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 8.
  • FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG.
  • FIG. 11 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 10.
  • FIG. 12 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 11.
  • FIG. 13 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 12.
  • FIG. 14 is a schematic cross-sectional view showing a comparative example of a semiconductor device.
  • FIG. 15 is a schematic cross-sectional view of an exemplary semiconductor device according to the second embodiment.
  • FIG. 16 is a schematic cross-sectional view of the semiconductor device according to the second embodiment taken along line F4-F4 in FIG.
  • FIG. 17 is a schematic cross-sectional view showing an exemplary manufacturing process of the semiconductor device according to the second embodiment.
  • FIG. 18 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 17.
  • FIG. 19 is a schematic cross-sectional view of an exemplary semiconductor device according to a first modification.
  • FIG. 20 is a schematic cross-sectional view of an exemplary semiconductor device according to a second modification.
  • FIG. 1 is a schematic plan view of an exemplary semiconductor device 10 according to a first embodiment.
  • planar view used in the present disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal XYZ axes shown in FIG. Unless explicitly stated otherwise, “planar view” refers to viewing the semiconductor device 10 from above along the Z-axis.
  • the semiconductor device 10 is, for example, a metal-insulator-semiconductor field effect transistor (MISFET) having a trench gate structure.
  • Semiconductor device 10 includes a semiconductor layer 12 and an insulating layer 14 formed on semiconductor layer 12.
  • the semiconductor layer 12 can be formed from silicon (Si), for example.
  • the semiconductor layer 12 includes a first surface 12A, which will be described later with reference to FIG. 3, and a second surface 12B opposite to the first surface 12A.
  • the Z-axis direction may be a direction perpendicular to the first surface 12A and the second surface 12B of the semiconductor layer 12. Since the semiconductor layer 12 is covered with the insulating layer 14, only the rectangular outer edge of the semiconductor layer 12 is shown in FIG.
  • the insulating layer 14 can be formed from a silicon oxide film (SiO 2 ), for example. Insulating layer 14 may additionally or alternatively include a layer formed from an insulating material other than SiO2 , such as silicon nitride (SiN).
  • the semiconductor device 10 may further include a gate wiring 16 formed on the insulating layer 14 and a source wiring 18 formed on the insulating layer 14.
  • the source wiring 18 is separated from the gate wiring 16.
  • the gate wiring 16 and the source wiring 18 are made of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy. It can be formed from one.
  • the gate wiring 16 can generally extend along the outer edge of the semiconductor layer 12.
  • the gate wiring 16 includes a first gate wiring part 16X1 and a second gate wiring part 16X2 extending in the X-axis direction, and a third gate wiring part 16Y1 and a fourth gate wiring part 16Y2 extending in the Y-axis direction.
  • the X-axis direction is also referred to as a first direction
  • the Y-axis direction is also referred to as a second direction.
  • the first gate wiring section 16X1 is connected between one end of the third gate wiring section 16Y1 and one end of the fourth gate wiring section 16Y2.
  • the second gate wiring section 16X2 is connected to the other end of the third gate wiring section 16Y1, but is not connected to the other end of the fourth gate wiring section 16Y2.
  • the gate wiring 16 may further include a gate pad portion 16P.
  • the other end of the fourth gate wiring section 16Y2 is connected to the gate pad section 16P.
  • the first gate wiring section 16X1, the second gate wiring section 16X2, the third gate wiring section 16Y1, the fourth gate wiring section 16Y2, and the gate pad section 16P may be integrally formed.
  • the source wiring 18 may include an inner source wiring part 18a that is at least partially surrounded by the gate wiring 16, and an outer source wiring part 18b that surrounds the gate wiring 16. Further, the source wiring 18 can further include a source connection part 18c that connects the inner source wiring part 18a and the outer source wiring part 18b.
  • the gate wiring 16 forms an open loop that partially surrounds the inner source wiring portion 18a.
  • the source connecting portion 18c is arranged at a location where the loop of the gate wiring 16 is open, so that the inner source wiring portion 18a can be connected to the outer source wiring portion 18b.
  • the inner source wiring portion 18a, the outer source wiring portion 18b, and the source connection portion 18c may be integrally formed. In the example of FIG.
  • the source connection portion 18c passes between the second gate wiring portion 16X2 and the gate pad portion 16P.
  • the loop of the gate wiring 16 may be opened at different locations.
  • the gate wiring 16 may form a closed loop in plan view.
  • the semiconductor device 10 may further include a gate trench 20 formed in the semiconductor layer 12.
  • the gate trench 20 refers to a trench in which a gate electrode 46, which will be described later with reference to FIG. 3, is arranged.
  • the gate trench 20 can be arranged so as to at least partially overlap both the gate wiring 16 and the source wiring 18 in a plan view.
  • the semiconductor device 10 may include a plurality of gate trenches 20, and some of the plurality of gate trenches 20 may be aligned parallel to each other at equal intervals.
  • the gate trench 20 extends in the X-axis direction and is arranged to intersect with the third gate interconnection section 16Y1 or the fourth gate interconnection section 16Y2 in plan view.
  • the semiconductor device 10 further includes a source trench 22 formed in the semiconductor layer 12.
  • the source trench 22 refers to a trench in which a buried electrode 52, which will be described later with reference to FIG. 3, is arranged.
  • the source trench 22 can be arranged so as to at least partially overlap both the gate wiring 16 and the source wiring 18 in plan view.
  • the semiconductor device 10 may include a plurality of source trenches 22, and some of the plurality of source trenches 22 may be aligned parallel to each other at equal intervals.
  • the source trench 22 extends in the X-axis direction and is arranged to intersect with the third gate wiring section 16Y1 or the fourth gate wiring section 16Y2 in plan view.
  • the source trench 22 may extend parallel to the gate trench 20 in plan view.
  • the gate trench 20 and the source trench 22 extend in the X-axis direction (first direction)
  • the gate trench 20 and the source trench 22 extend in the Y-axis direction (second direction perpendicular to the first direction) in plan view. They may be arranged alternately.
  • the width of the gate trench 20 (dimension in the Y-axis direction) is approximately the same as the width (dimension in the Y-axis direction) of the source trench 22.
  • the width of gate trench 20 may be different than the width of source trench 22.
  • source trench 22 may have a larger width than gate trench 20.
  • the semiconductor device 10 may further include a gate contact plug 24 and a source contact plug 26.
  • Gate contact plug 24 is connected to gate wiring 16.
  • the gate contact plug 24 can be placed in a region where the gate trench 20 and the gate wiring 16 intersect in plan view.
  • the source contact plug 26 is connected to the source wiring 18.
  • the source contact plug 26 can be arranged so as to overlap the inner source wiring portion 18a in plan view.
  • the source contact plug 26 may extend parallel to the source trench 22 in plan view. In the example of FIG. 1, the source contact plug 26 extends in the X-axis direction in plan view.
  • the source contact plug 26 may at least partially overlap the source trench 22 in plan view. Note that the source contact plug 26 may be arranged so as not to overlap the gate trench 20 in plan view.
  • the semiconductor device 10 may further include a first termination trench 28 and a second termination trench 30 formed in the semiconductor layer 12.
  • the first termination trench 28 overlaps the inner source wiring portion 18a in plan view.
  • the second termination trench 30 overlaps with the outer source wiring portion 18b in plan view.
  • Gate trench 20 and source trench 22 may extend between and communicate with first termination trench 28 and second termination trench 30.
  • the semiconductor device 10 may further include a first field plate contact plug 32 and a second field plate contact plug 34.
  • the first field plate contact plug 32 and the second field plate contact plug 34 extend in the Y-axis direction in the example of FIG.
  • the first field plate contact plug 32 may overlap the first termination trench 28 in plan view and may be connected to the inner source wiring portion 18a.
  • the second field plate contact plug 34 may overlap the second termination trench 30 in plan view and may be connected to the outer source wiring portion 18b.
  • Each of the gate contact plug 24, source contact plug 26, first field plate contact plug 32, and second field plate contact plug 34 can be formed from any metal material.
  • each contact plug 24, 26, 32, 34 may be formed from at least one of tungsten (W), titanium (Ti), and titanium nitride (TiN).
  • semiconductor device 10 may not include termination trenches 28 and 30.
  • field plate contact plugs 32 and 34 may be arranged to overlap with respective ends of gate trench 20 and source trench 22.
  • the semiconductor device 10 may not include the source wiring 18.
  • the field plate contact plug 30 may be arranged to overlap the end of each gate trench 20.
  • the semiconductor device 10 may further include a gate trench 20 and a source trench 22 extending in the Y-axis direction. In this case, the first gate wiring part 16X1 and the second gate wiring part 16X2 may intersect with the gate trench 20 and the source trench 22 extending in the Y-axis direction.
  • FIG. 2 is a plan view showing the end portions of the gate trench 20 and the source trench 22.
  • FIG. 2 shows an enlarged view of the region designated F2 in FIG. 1, where the gate trench 20 and the source trench 22 communicate with the second termination trench 30.
  • the gate wiring 16 and the source wiring 18 are omitted.
  • contact plugs 24, 26, and 34 formed in the insulating layer 14 are drawn with solid lines, and trenches 20, 22, and 30 formed in the semiconductor layer 12 under the insulating layer 14 are drawn with broken lines.
  • the gate contact plug 24 may have a width (in the illustrated example, the dimension in the Y-axis direction) that is smaller than the gate trench 20. Therefore, gate contact plug 24 is arranged within gate trench 20 in plan view.
  • the source contact plug 26 may have a larger width (in the illustrated example, the dimension in the Y-axis direction) than the source trench 22. That is, when the width of the source contact plug 26 is Wc and the width of the source trench 22 is Wt, Wc>Wt.
  • the source contact plug 26 may at least partially overlap the source trench 22 in plan view. As shown in FIG. 2, the source contact plug 26 can include a portion disposed within the source trench 22 and a portion disposed outside the source trench 22 in plan view. In this specification, a portion of the source contact plug 26 disposed within the source trench 22 in plan view is referred to as a main portion 26a. The width of the main portion 26a is Wt, similar to the width of the source trench 22. Further, in this specification, a portion of the source contact plug 26 located outside the source trench in plan view is referred to as an overhang portion 26b. As shown in FIG.
  • the width of the source contact plug 26 allows for at least two overhang portions 26b to exist (Wo1, Wo2>0) even when the maximum misalignment occurs with respect to the source trench 22. It can be determined as follows. Note that the width of each component mentioned in the above description may be, for example, the width in a plane that includes the second surface 12B of the semiconductor layer 12.
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment taken along line F3-F3 in FIG.
  • FIG. 3 shows gate trenches 20 and source trenches 22 alternately aligned in the Y-axis direction.
  • the semiconductor layer 12 may include a semiconductor substrate 36 and an epitaxial layer 38 formed on the semiconductor substrate 36.
  • the semiconductor substrate 36 includes the first surface 12A of the semiconductor layer 12, and the epitaxial layer 38 includes the second surface 12B of the semiconductor layer 12.
  • the semiconductor substrate 36 may be a Si substrate, for example.
  • the semiconductor substrate 36 corresponds to the drain region of the MISFET.
  • Epitaxial layer 38 may be a Si layer epitaxially grown on a Si substrate.
  • Epitaxial layer 38 may include a drift region 40 , a body region 42 formed on drift region 40 , and a source region 44 formed on body region 42 .
  • Source region 44 may include second surface 12B of semiconductor layer 12.
  • the drain region (semiconductor substrate 36) may be an n-type region containing n-type impurities.
  • the n-type impurity concentration of the drain region (semiconductor substrate 36) can be set to 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the drain region (semiconductor substrate 36) may have a thickness of 50 ⁇ m or more and 450 ⁇ m or less.
  • Drift region 40 may be an n-type region containing n-type impurities at a lower concentration than the drain region (semiconductor substrate 36).
  • the n-type impurity concentration of the drift region 40 can be set to 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • Drift region 40 may have a thickness of 1 ⁇ m or more and 25 ⁇ m or less.
  • Body region 42 may be a p-type region containing p-type impurities.
  • the p-type impurity concentration of the body region 42 can be set to 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the body region 42 may have a thickness of 0.2 ⁇ m or more and 1.0 ⁇ m or less.
  • Source region 44 may be an n-type region containing a higher concentration of n-type impurities than drift region 40 .
  • the n-type impurity concentration of the source region 44 can be set to 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the source region 44 may have a thickness of 0.1 ⁇ m or more and 1 ⁇ m or less.
  • the p-type is also referred to as a first conductivity type
  • the n-type is also referred to as a second conductivity type.
  • the n-type impurity may be, for example, phosphorus (P) or arsenic (As).
  • the p-type impurity may be, for example, boron (B), aluminum (Al), or the like.
  • the gate trench 20 has an opening in the second surface 12B of the semiconductor layer 12 and has a depth in the Z-axis direction. In this specification, the Z-axis direction is also referred to as the depth direction. Gate trench 20 extends through source region 44 and body region 42 of semiconductor layer 12 to drift region 40 . Gate trench 20 has sidewalls 20A and a bottom wall 20B, and bottom wall 20B is adjacent to drift region 40. The depth of the gate trench 20 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the sidewall 20A of the gate trench 20 may extend in a direction perpendicular to the second surface 12B of the semiconductor layer 12 (Z-axis direction), or may be inclined with respect to the Z-axis direction. In one example, the sidewall 20A may be inclined with respect to the Z-axis direction so that the width of the gate trench 20 becomes smaller toward the bottom wall 20B. Further, the bottom wall 20B of the gate trench 20 does not necessarily have to be flat, and may be partially or entirely curved, for example.
  • the semiconductor device 10 may further include a gate electrode 46 and a field plate electrode 48 arranged within the gate trench 20.
  • the gate electrode 46 is electrically connected to the gate wiring 16.
  • the gate electrode 46 can be electrically connected to the gate wiring 16 via the gate contact plug 24 (see FIG. 1).
  • Field plate electrode 48 is electrically connected to source wiring 18 .
  • Field plate electrode 48 can be electrically connected to source wiring 18 via first and second field plate contact plugs 32, 34 (see FIG. 1).
  • Gate electrode 46 and field plate electrode 48 may be formed of conductive polysilicon.
  • the gate electrode 46 includes a top surface 46A covered with the insulating layer 14 and a bottom surface 46B opposite to the top surface 46A.
  • Field plate electrode 48 may be located below gate electrode 46 within gate trench 20 . More specifically, field plate electrode 48 can be arranged between bottom surface 46B of gate electrode 46 and bottom wall 20B of gate trench 20. At least a portion of the bottom surface 46B of the gate electrode 46 may face the field plate electrode 48 with the insulating layer 14 in between.
  • Gate electrode 46 further includes a side surface 46C facing sidewall 20A of gate trench 20.
  • the upper surface 46A of the gate electrode 46 can be located below the second surface 12B of the semiconductor layer 12. Further, the bottom surface 46B of the gate electrode 46 is located relatively close to the interface between the drift region 40 and the body region 42 in the Z-axis direction, and preferably may be located below the interface.
  • the top surface 46A and bottom surface 46B of the gate electrode 46 may be flat or curved.
  • the gate electrode 46 and the field plate electrode 48 are surrounded by the insulating layer 14.
  • Field plate electrode 48 may have a smaller width than gate electrode 46. Due to the relatively small width of field plate electrode 48, the thickness of insulating layer 14 surrounding field plate electrode 48 is relatively large. Thereby, electric field concentration within the gate trench 20 can be alleviated.
  • the insulating layer 14 includes a gate insulating portion 50 interposed between the gate electrode 46 and the semiconductor layer 12 and covering the side wall 20A of the gate trench 20.
  • the gate insulating portion 50 is a part of the insulating layer 14 between the side surface 46C of the gate electrode 46 and the side wall 20A of the gate trench 20.
  • the gate insulating portion 50 is in contact with both the side surface 46C of the gate electrode 46 and the side wall 20A of the gate trench 20.
  • a predetermined voltage is applied to the gate electrode 46, a channel is formed in the p-type body region 42 adjacent to the gate insulating portion 50.
  • the semiconductor device 10 can control the flow of electrons in the Z-axis direction between the n-type source region 44 and the n-type drift region 40 via this channel.
  • the source trench 22 has an opening in the second surface 12B of the semiconductor layer 12 and has a depth in the Z-axis direction. Source trench 22 extends through source region 44 and body region 42 of semiconductor layer 12 to drift region 40 . Source trench 22 has sidewalls 22A and a bottom wall 22B, and bottom wall 20B is adjacent to drift region 40. The depth of the source trench 22 may be greater than or equal to 1 ⁇ m and less than or equal to 10 ⁇ m.
  • the sidewall 22A of the source trench 22 may extend in a direction perpendicular to the second surface 12B of the semiconductor layer 12 (Z-axis direction), or may be inclined with respect to the Z-axis direction. In one example, the sidewall 22A may be inclined with respect to the Z-axis direction so that the width of the source trench 22 becomes smaller toward the bottom wall 22B. Further, the bottom wall 22B of the source trench 22 does not necessarily have to be flat, and may be partially or entirely curved, for example.
  • the source trench 22 may have a similar shape to the gate trench 20.
  • source trench 22 may have the same width and depth as gate trench 20.
  • source trench 22 may have a different shape than gate trench 20.
  • source trench 22 may have a greater width and/or depth than gate trench 20.
  • the semiconductor device 10 may further include a buried electrode 52 and a field plate electrode 54 arranged in the source trench 22.
  • the buried electrode 52 can be electrically connected to the source wiring 18 via the source contact plug 26.
  • Field plate electrode 54 can be electrically connected to source wiring 18 via first and second field plate contact plugs 32, 34 (see FIG. 1). Note that in order to distinguish between the field plate electrode 48 disposed in the gate trench 20 and the field plate electrode 54 disposed in the source trench 22, the field plate electrode 48 and the field plate electrode 54 are respectively referred to as the first field plate. Also referred to as electrode 48 and second field plate electrode 54.
  • the buried electrode 52 and the field plate electrode 54 may be formed of conductive polysilicon.
  • the embedded electrode 52 includes a top surface 52A covered with the source contact plug 26, and a bottom surface 52B opposite to the top surface 52A.
  • Field plate electrode 54 may be arranged below buried electrode 52 within source trench 22 . More specifically, the field plate electrode 54 can be arranged between the bottom surface 52B of the buried electrode 52 and the bottom wall 22B of the source trench 22. At least a portion of the bottom surface 52B of the buried electrode 52 may face the field plate electrode 54 with the insulating layer 14 in between.
  • Embedded electrode 52 further includes a side surface 52C facing side wall 22A of source trench 22.
  • the upper surface 52A of the embedded electrode 52 can be located below the second surface 12B of the semiconductor layer 12. Further, the bottom surface 52B of the buried electrode 52 is located relatively close to the interface between the drift region 40 and the body region 42 in the Z-axis direction, and preferably may be located below the interface.
  • the top surface 52A and bottom surface 52B of the embedded electrode 52 may be flat or curved.
  • the buried electrode 52 and the field plate electrode 54 may have the same shape as the gate electrode 46 and the field plate electrode 48, respectively.
  • Field plate electrode 54 may have a smaller width than buried electrode 52.
  • the field plate electrode 54 is surrounded by the insulating layer 14, but the buried electrode 52 is surrounded not only by the insulating layer 14 but also by the source contact plug 26.
  • the upper surface 52A of the buried electrode 52 is adjacent to the source contact plug 26.
  • a bottom surface 52B of the buried electrode 52 is adjacent to the insulating layer 14.
  • a portion of the side surface 52C of the buried electrode 52 is adjacent to the source contact plug 26, and the remaining portion of the side surface 52C is adjacent to the insulating layer 14.
  • the source contact plug 26 electrically connects the source wiring 18 to the semiconductor layer 12.
  • the source contact plug 26 contacts the buried electrode 52 and also contacts the semiconductor layer 12 through a part of the side wall 22A of the source trench 22.
  • the source contact plug 26 includes a lower extension portion 56 embedded between the side wall 22A of the source trench 22 and the side surface 52C of the buried electrode 52.
  • the lower extension portion 56 includes a lower end surface 56A located between the upper surface 52A and the bottom surface 52B of the embedded electrode 52 in the Z-axis direction. Therefore, a portion of the side surface 52C of the buried electrode 52 is adjacent to the lower extension portion 56, and the remaining portion of the side surface 52C is adjacent to the insulating layer 14.
  • the lower end surface 56A of the lower extension part 56 may be located closer to the bottom surface 52B than the upper surface 52A of the embedded electrode 52 in the Z-axis direction.
  • the lower end surface 56A of the lower extending portion 56 may be located above the boundary between the body region 42 and the drift region 40 in the Z-axis direction.
  • the source contact plug 26 includes a main portion 26a disposed within the source trench 22 in plan view and an overhang portion 26b disposed outside the source trench in plan view. I'm here. Note that the aforementioned lower extending portion 56 is included in the main portion 26a. As shown in FIG. 3, the overhang portion 26b is in contact with the second surface 12B of the semiconductor layer 12. The overhang portion 26b may be a part of the source contact plug 26 extending between the second surface 12B of the semiconductor layer 12 and the source wiring 18. The overhang portion 26b extends over a portion of the second surface 12B that is continuous with the side wall 22A of the source trench 22. The width of the overhang portion 26b (the dimension in the Y-axis direction in FIG. 3) can be determined, for example, depending on the accuracy of alignment between the source trench 22 and the source contact plug 26 in the manufacturing process.
  • the semiconductor layer 12 may further include a contact region 58 formed adjacent to the source contact plug 26.
  • Contact region 58 extends along a portion of sidewall 22A of source trench 22 within semiconductor layer 12 . As shown in FIG. 3, since sidewall 22A of source trench 22 generally extends in the Z-axis direction, contact region 58 also generally extends in the Z-axis direction.
  • the contact region 58 may further extend within the semiconductor layer 12 along a part of the second surface 12B that is continuous with the sidewall 22A of the source trench 22. That is, the contact region 58 may be a region within the semiconductor layer 12 that includes a contact surface between the source contact plug 26 and the semiconductor layer 12. Contact region 58 is electrically connected to source wiring 18 formed on insulating layer 14 by source contact plug 26 .
  • Contact region 58 may be a p-type region containing p-type impurities.
  • the p-type impurity concentration of contact region 58 is higher than the p-type impurity concentration of body region 42 .
  • the p-type impurity concentration of the contact region 58 can be set to 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the semiconductor device 10 may further include a drain electrode 60 formed on the first surface 12A of the semiconductor layer 12.
  • the drain electrode 60 is adjacent to and electrically connected to the drain region (semiconductor substrate 36).
  • Drain electrode 60 is formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), copper alloy, and aluminum alloy. be able to.
  • FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 according to the first embodiment taken along line F4-F4 in FIG. FIG. 4 shows a cross section of the end of the source trench 22.
  • Source trench 22 communicates with second termination trench 30 at its end.
  • the semiconductor device 10 may further include a termination electrode 61 disposed within the second termination trench 30 and extending in the Y-axis direction. Termination electrode 61 may be connected to second field plate electrode 54 .
  • the termination electrode 61 can be formed integrally with the second field plate electrode 54.
  • the upper surface 61A of the termination electrode 61 can be arranged relatively close to the second surface 12B of the semiconductor layer 12 in the Z-axis direction.
  • the second field plate contact plug 34 can electrically connect the source wiring 18 (outer source wiring portion 18b) to the termination electrode 61.
  • the second field plate contact plug 34 may penetrate through the upper surface 61A of the termination electrode 61 and be partially embedded in the termination electrode 61.
  • the top surface 61A of the termination electrode 61 is located above the top surface 54A of the second field plate electrode 54, but the bottom surface 61B of the termination electrode 61 is located at approximately the same position as the bottom surface 54B of the second field plate electrode 54. It's good to be there.
  • the source contact plug 26 is in contact with the upper surface 52A of the buried electrode 52. Note that the lower extending portion 56 of the source contact plug 26 is not visible in FIG.
  • the embedded electrode 52 does not extend to the second termination trench 30 in the X-axis direction.
  • the buried electrode 52 is separated from the second field plate electrode 54 and the termination electrode 61 by the insulating layer 14 .
  • the embedded electrode 52 is electrically connected to the inner source wiring portion 18a
  • the termination electrode 61 is electrically connected to the outer source wiring portion 18b. Therefore, the embedded electrode 52, the second field plate electrode 54, and the termination electrode 61 may all be electrically connected to the source line 18.
  • FIG. 5 is a schematic cross-sectional view of the semiconductor device 10 according to the first embodiment taken along line F5-F5 in FIG.
  • FIG. 5 shows a cross section of the end of the gate trench 20.
  • Gate trench 20 communicates with second termination trench 30 at its end.
  • Termination electrode 61 may be connected to first field plate electrode 48 .
  • the termination electrode 61 can be formed integrally not only with the second field plate electrode 54 but also with the first field plate electrode 48 . That is, the first field plate electrode 48 and the second field plate electrode 54 are electrically connected to each other via the termination electrode 61.
  • the top surface 61A of the termination electrode 61 is located above the top surface 48A of the first field plate electrode 48, but the bottom surface 61B of the termination electrode 61 is located at approximately the same position as the bottom surface 48B of the first field plate electrode 48. It's good to be there.
  • the gate contact plug 24 electrically connects the gate wiring 16 (fourth gate wiring part 16Y2) to the gate electrode 46.
  • the gate contact plug 24 may penetrate through the upper surface 46A of the gate electrode 46 and be partially embedded in the gate electrode 46.
  • the gate electrode 46 does not extend to the second termination trench 30 in the X-axis direction. Gate electrode 46 is separated from first field plate electrode 48 and termination electrode 61 by insulating layer 14 .
  • FIGS. 6 to 13 are schematic cross-sectional views showing exemplary manufacturing steps of the semiconductor device 10.
  • the same reference numerals are given to the same components as those in FIG. 3.
  • the method for manufacturing the semiconductor device 10 includes forming a semiconductor layer 12 and forming a plurality of trenches 62 in the semiconductor layer 12.
  • Forming semiconductor layer 12 may include forming an epitaxial layer 38 over semiconductor substrate 36 .
  • the semiconductor substrate 36 may be a Si substrate containing n-type impurities.
  • the epitaxial layer 38 may be an n-type Si layer epitaxially grown on the semiconductor substrate 36 while doping with n-type impurities.
  • a part of the epitaxial layer 38 is selectively removed by etching using a mask (not shown) with a predetermined pattern formed on the epitaxial layer 38, and as a result, the second surface 12B of the semiconductor layer 12 is removed.
  • a plurality of trenches 62 having openings are formed.
  • FIG. 7 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 6.
  • the method includes forming a first insulating layer 64 on the semiconductor layer 12 and forming a first conductive layer 66 on the first insulating layer 64.
  • the first insulating layer 64 can be formed along the second surface 12B of the semiconductor layer 12 and the trench 62.
  • the first insulating layer 64 may be, for example, SiO 2 formed by a thermal oxidation method. In another example, the first insulating layer 64 may be SiO 2 formed by chemical vapor deposition (CVD).
  • a first conductive layer 66 is then formed on the first insulating layer 64 such that the trench 62 is filled with the first insulating layer 64 and the first conductive layer 66 .
  • the first conductive layer 66 may be, for example, conductive polysilicon.
  • FIG. 8 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 7.
  • the method includes etching away a portion of first conductive layer 66.
  • the first conductive layer 66 is etched to expose the first insulating layer 64 covering the second surface 12B of the semiconductor layer 12, while etching the surface of the first conductive layer 66 in the Z-axis direction. It can be located below the second surface 12B of the semiconductor layer 12 (in the middle of the trench 62).
  • FIG. 9 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 8.
  • the method includes forming a second insulating layer 68 over the first insulating layer 64 and the first conductive layer 66.
  • the surface of the first conductive layer 66 within the trench 62 is covered with the second insulating layer 68.
  • the second insulating layer 68 like the first insulating layer 64, may be SiO 2 .
  • the second insulating layer 68 may be SiO 2 formed by thermal oxidation, SiO 2 formed by CVD, or a combination thereof.
  • trench 62 is filled with first conductive layer 66 , first insulating layer 64 , and second insulating layer 68 .
  • FIG. 10 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 9.
  • the method includes partially removing first insulating layer 64 and second insulating layer 68 to expose a portion of trench 62 and second surface 12B of semiconductor layer 12. Removal of the first insulating layer 64 and the second insulating layer 68 is performed, for example, by chemical mechanical polishing, dry etching, and/or wet etching.
  • the first insulating layer 64 and the second insulating layer 68 left in the trench 62 are collectively referred to as a third insulating layer 70.
  • the surface of the third insulating layer 70 within the trench 62 may be located above the first conductive layer 66 in the Z-axis direction. Therefore, the first conductive layer 66 is surrounded by the third insulating layer 70 .
  • FIG. 11 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 10.
  • the method includes forming a fourth insulating layer 72 and forming a second conductive layer 74 over the fourth insulating layer 72.
  • the fourth insulating layer 72 may be, for example, SiO 2 formed by a thermal oxidation method. In another example, the fourth insulating layer 72 may be SiO 2 formed by CVD.
  • the fourth insulating layer 72 is formed to a relatively thin thickness along the second surface 12B of the semiconductor layer 12, the surface of the third insulating layer 70, and the portion of the trench 62 exposed in the step shown in FIG. I can do it.
  • the second conductive layer 74 can be formed by depositing a conductive material on the fourth insulating layer 72 so as to fill the trench 62, and then etching the conductive material to a desired depth. As a result, the fourth insulating layer 72 covering the second surface 12B of the semiconductor layer 12 is exposed, and the surface of the second conductive layer 74 is located below the second surface 12B of the semiconductor layer 12 in the Z-axis direction. do.
  • the second conductive layer 74 may be, for example, conductive polysilicon.
  • FIG. 12 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 11.
  • the method includes forming a drift region 40, a body region 42, a source region 44 in an epitaxial layer 38, and forming a fifth insulating layer 76 overlying a fourth insulating layer 72 and a second conductive layer 74. Including forming.
  • a p-type impurity is implanted from the surface of the epitaxial layer 38 (the second surface 12B of the semiconductor layer 12), which is an n-type Si layer, by ion implantation, and then an n-type impurity is implanted.
  • the fifth insulating layer 76 may be, for example, SiO 2 formed by a CVD method, SiN, or a combination thereof.
  • FIG. 13 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 12.
  • the method includes forming a source contact opening 78 in insulating layer 14 and forming contact region 58.
  • the insulating layer 14 includes the third insulating layer 70, the fourth insulating layer 72, and the fifth insulating layer 76 shown in FIG.
  • Source contact opening 78 may be formed by selectively removing insulating layer 14 over some of trenches 62 .
  • source contact openings 78 are formed over every other trench 62. Trench 62 in which source contact opening 78 is formed corresponds to source trench 22 shown in FIG.
  • Forming the source contact opening 78 includes exposing a portion of the sidewall 22A of the source trench 22.
  • the source contact opening 78 is formed such that the exposed portion of the sidewall 22A partially faces the second conductive layer 74 corresponding to the buried electrode 52.
  • Source contact opening 78 does not need to be formed deeper than the boundary between body region 42 and drift region 40 in the Z-axis direction. Further, since the source contact opening 78 has a width larger than that of the trench 62 in the Y-axis direction, forming the source contact opening 78 means that the second surface 12B of the semiconductor layer 12 that is continuous with the sidewall 22A is It also includes exposing a part of it.
  • the contact region 58 can be formed by performing ion implantation from the exposed portion of the side wall 22A of the source trench 22. More specifically, the p-type impurity is implanted from the exposed portion of the side wall 22A of the source trench 22 and the exposed portion of the second surface 12B of the semiconductor layer 12, so that the p-type impurity concentration is higher than that of the body region 42. A contact region 58 is formed. Contact region 58 may be formed along an exposed portion of second surface 12B of semiconductor layer 12 and along an exposed portion of sidewall 22A of source trench 22.
  • the source contact plug 26 shown in FIG. 3 can be formed by filling the source contact opening 78 with metal (for example, W, Ti, TiN, or any combination thereof). .
  • metal for example, W, Ti, TiN, or any combination thereof.
  • the method for manufacturing semiconductor device 10 is described above as including multiple manufacturing steps performed sequentially, some manufacturing steps may be performed in parallel and/or in a different order. Please understand that it is okay to do so. Further, some manufacturing steps may be omitted, and processing different from the above example may be performed in any of the manufacturing steps.
  • the semiconductor device 10 includes a source contact plug 26 that electrically connects the source wiring 18 to the semiconductor layer 12.
  • the source contact plug 26 is in contact with a buried electrode 52 disposed in the source trench 22 and also in contact with the semiconductor layer 12 through a part of the side wall 22A of the source trench 22.
  • the position where the source contact plug 26 contacts the semiconductor layer 12 is aligned with the position of the side wall 22A of the source trench 22, so that the characteristics of the semiconductor device 10 due to the positional deviation of the source contact plug 26 (for example, Variations in gate threshold voltage, on-resistance, etc.) can be suppressed.
  • the contact surface between the source contact plug 26 and the semiconductor layer 12 also generally extends in the Z-axis direction. Therefore, even if the source contact plug 26 is displaced in the Y-axis direction, the contact area between the source contact plug 26 and the semiconductor layer 12 can be maintained.
  • the widths of the two overhang portions 26b will not be equal to each other (Wo1 ⁇ Wo2). Even in this case, since the source contact plug 26 is arranged at a position overlapping the side wall 22A of the source trench 22 in plan view, the position where the source contact plug 26 contacts the semiconductor layer 12 is set on the side wall 22A of the source trench 22. It can be aligned to the position.
  • FIG. 14 is a schematic cross-sectional view of a semiconductor device 100 of a comparative example.
  • the same components as those of the semiconductor device 10 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
  • the semiconductor device 100 does not include the source trench 22 and source contact plug 26 as shown in FIG. In FIG. 3, a plurality of gate trenches 20 are formed in the semiconductor layer 12.
  • the semiconductor device 100 includes a source contact plug 102 that electrically connects the source wiring 18 to the semiconductor layer 12.
  • the source contact plug 102 extends parallel to the gate trenches 20 and is arranged between the two gate trenches 20 .
  • the semiconductor layer 12 includes a contact region 104.
  • Contact region 104 is a p-type region containing p-type impurities, similar to contact region 58 shown in FIG.
  • Source contact plug 102 extends through insulating layer 14 and source region 44 to body region 42 and is in contact with contact region 104 . Thereby, the source contact plug 102 can electrically connect the source wiring 18 formed on the insulating layer 14 to the contact region 104 of the semiconductor layer 12.
  • the position where the source contact plug 102 contacts the semiconductor layer 12 directly depends on the position of the source contact plug 102. Therefore, the characteristics of the semiconductor device 100 are easily affected by the misalignment of the source contact plug 102.
  • the semiconductor device 10 of the present embodiment even if the source contact plug 26 is misaligned, the position where the source contact plug 26 contacts the semiconductor layer 12 is the position of the side wall 22A of the source trench 22. It can be matched. Therefore, variations in characteristics due to misalignment of the source contact plug 26 of the semiconductor device 10 can be suppressed.
  • the source contact plug 102 is arranged between the two gate trenches 20, so when considering the dimensions and positional deviation of the source contact plug 102, it is difficult to reduce the distance between the gate trenches 20. It is difficult to do so.
  • the source contact plug 26 is not disposed between the trenches 20 and 22, so it is relatively easy to reduce the distance between the trenches 20 and 22.
  • the semiconductor device 10 of this embodiment has the following advantages.
  • the semiconductor device 10 includes a source contact plug 26 that electrically connects the source wiring 18 to the semiconductor layer 12.
  • the source contact plug 26 is in contact with a buried electrode 52 disposed in the source trench 22 and also in contact with the semiconductor layer 12 through a part of the side wall 22A of the source trench 22. Thereby, the position where the source contact plug 26 contacts the semiconductor layer 12 is aligned with the position of the side wall 22A of the source trench 22, so that variations in characteristics due to positional deviation of the source contact plug 26 of the semiconductor device 10 can be suppressed. can.
  • the source contact plug 26 may include a lower extension portion 56 embedded between the side wall 22A of the source trench 22 and the side surface 52C of the buried electrode 52. Thereby, the source contact plug 26 can be extended to a relatively deep position, so that the current generated during the turn-off operation of the semiconductor device 10 due to the inductive load can be efficiently released from the source contact plug 26. As a result, the inductive load resistance of the semiconductor device 10 can be improved.
  • the lower extending portion 56 includes a lower end surface 56A located between the upper surface 52A and the bottom surface 52B of the embedded electrode 52 in the depth direction, and the lower end surface 56A is located between the embedded electrode 52 in the depth direction. It may be located closer to the bottom surface 52B than to the top surface 52A. Thereby, the source contact plug 26 can be extended to a deeper position, so that the inductive load resistance of the semiconductor device 10 can be further improved.
  • the source contact plug 26 may include an overhang portion 26b that is in contact with the second surface 12B of the semiconductor layer 12. This ensures a margin for positioning the source contact plug 26 with respect to the source trench 22, so that the source contact plug 26 can be brought into reliable contact with the semiconductor layer 12.
  • the semiconductor layer 12 includes a first conductivity type contact region 58 formed adjacent to the source contact plug 26, and the contact region 58 extends along a part of the side wall 22A of the source trench 22. It's okay to stay. Thereby, the electrical connection of the source contact plug 26 to the semiconductor layer 12 can be improved.
  • the contact region 58 may further extend along a portion of the second surface 12B of the semiconductor layer 12. Thereby, the contact area between the source contact plug 26 and the contact region 58 of the semiconductor layer 12 can be increased, so that the electrical connection of the source contact plug 26 to the semiconductor layer 12 can be further improved.
  • the semiconductor device 10 may include a field plate electrode 48 disposed below the gate electrode 46 in the gate trench 20. Thereby, even if the impurity concentration in the epitaxial layer 38 is increased to reduce the on-resistance of the semiconductor device 10, the breakdown voltage can be maintained. Furthermore, since the gate-drain capacitance can be reduced, the switching speed of the semiconductor device 10 can be improved.
  • the contact region 58 can be formed by performing ion implantation from the exposed portion of the side wall 22A of the source trench 22. This allows the contact region 58 to extend along a portion of the sidewall 22A of the source trench 22.
  • FIG. 15 is a schematic cross-sectional view of an exemplary semiconductor device 200 according to the second embodiment.
  • the same components as those of the semiconductor device 10 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
  • a buried electrode 52 is arranged in the source trench 22, but a second field plate electrode 54 as shown in FIG. 3 is not arranged. Therefore, in the second embodiment, the bottom surface 52B of the buried electrode 52 can be located closer to the bottom wall 22B of the source trench 22 than in the first embodiment.
  • the bottom surface 52B of the buried electrode 52 is located closer to the interface between the drift region 40 and the body region 42 than the bottom wall 22B of the source trench 22 in the Z-axis direction.
  • the bottom surface 52B of the buried electrode 52 can be located closer to the bottom wall 22B of the source trench 22 than the interface between the drift region 40 and the body region 42 in the Z-axis direction.
  • the arrangement of the gate electrode 46 and the first field plate electrode 48 in the gate trench 20 is similar to that of the semiconductor device 10 of the first embodiment.
  • FIG. 16 is a schematic cross-sectional view of the semiconductor device 200 according to the second embodiment taken along line F4-F4 in FIG.
  • FIG. 16 shows a cross section of the end of the source trench 22.
  • the termination electrode 61 was connected to the second field plate electrode 54, but in the semiconductor device 200, the termination electrode 61 may be connected to the buried electrode 52.
  • the termination electrode 61 can be formed integrally with the embedded electrode 52.
  • the top surface 61A and bottom surface 61B of the termination electrode 61 may be located at approximately the same position as the top surface 52A and bottom surface 52B of the embedded electrode 52.
  • the integrally formed embedded electrode 52 and termination electrode 61 can pass below the gate line 16 to electrically connect the inner source line portion 18a and the outer source line portion 18b of the source line 18.
  • the method for manufacturing the semiconductor device 200 includes the steps shown in FIGS. 6 and 7, similar to the method for manufacturing the first embodiment.
  • the semiconductor device 200 of the second embodiment only one electrode made of the first conductive layer 66 is formed in every other trench 62 in the steps after the step shown in FIG. 8 of the first embodiment. It can be manufactured by doing as follows. In the process shown in FIG. 17, a trench 62 is filled with two electrodes formed from the first conductive layer 66 and a second conductive layer 74, and one electrode formed from the first conductive layer 66 is buried. The trenches 62 are alternately arranged.
  • FIG. 18 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 17.
  • the method includes forming a source contact opening 78 in insulating layer 14 and forming contact region 58.
  • the source contact opening 78 can be formed by selectively removing the insulating layer 14 above the trench 62 in which one electrode formed from the first conductive layer 66 is buried among the plurality of trenches 62. can.
  • source contact openings 78 are formed over every other trench 62.
  • the trench 62 in which the source contact opening 78 is formed corresponds to the source trench 22 shown in FIG. 15, and the trench 62 in which the source contact opening 78 is not formed corresponds to the gate trench 20 shown in FIG. Therefore, the first conductive layer 66 in the trench 62 (source trench 22) in which the source contact opening 78 is formed corresponds to the buried electrode 52 shown in FIG.
  • Forming the source contact opening 78 includes exposing a portion of the sidewall 22A of the source trench 22.
  • the source contact opening 78 is formed such that the exposed portion of the sidewall 22A partially faces the first conductive layer 66 corresponding to the buried electrode 52.
  • source contact opening 78 is not formed deeper than the boundary between body region 42 and drift region 40 in the Z-axis direction.
  • forming the source contact opening 78 means that the second surface 12B of the semiconductor layer 12 that is continuous with the sidewall 22A is It also includes exposing a part of it.
  • the contact region 58 is formed by performing ion implantation from the exposed second surface 12B and sidewall 22A of the semiconductor layer 12. More specifically, p-type impurities are implanted from the exposed second surface 12B and sidewall 22A of the semiconductor layer 12 to form a contact region 58 having a higher p-type impurity concentration than the body region 42. Contact region 58 can be formed along exposed second surface 12B and sidewall 22A of semiconductor layer 12.
  • the source contact plug 26 shown in FIG. 15 can be formed by filling the source contact opening 78 with metal (for example, W, Ti, TiN, or any combination thereof). .
  • metal for example, W, Ti, TiN, or any combination thereof.
  • the semiconductor device 200 includes a source contact plug 26 that electrically connects the source wiring 18 to the semiconductor layer 12.
  • the source contact plug 26 is in contact with a buried electrode 52 disposed in the source trench 22 and also in contact with the semiconductor layer 12 through a part of the side wall 22A of the source trench 22.
  • the position where the source contact plug 26 contacts the semiconductor layer 12 is aligned with the position of the side wall 22A of the source trench 22, so that the characteristics of the semiconductor device 200 (for example, the gate threshold voltage , on-resistance, etc.) can be suppressed.
  • the semiconductor device 200 of the second embodiment also has the same advantages (1) to (8) as the semiconductor device 10 of the first embodiment.
  • FIG. 19 is a schematic cross-sectional view of a semiconductor device 300 according to a first modification example.
  • the same components as those of the semiconductor device 200 are given the same reference numerals. Further, detailed description of the same components as those of the semiconductor device 200 will be omitted.
  • a lower end surface 56A of the lower extension portion 56 of the semiconductor device 300 shown in FIG. 19 can be located below the boundary between the body region 42 and the drift region 40 in the Z-axis direction. More specifically, the lower end surface 56A can be located between the boundary between the body region 42 and the drift region 40 and the bottom surface 52B of the buried electrode 52 in the Z-axis direction.
  • the source contact plug 26 can be extended further downward in the Z-axis direction than in the case of the semiconductor device 200. Thereby, the inductive load resistance of the semiconductor device 300 can be further improved. In addition, it becomes easier to extend the depletion layer in the semiconductor layer 12, so that the on-resistance of the semiconductor device 300 can be reduced and the breakdown voltage can be improved.
  • the semiconductor device 400 of the second modification may include a source contact plug 402 different from the example of FIG.
  • FIG. 20 is a schematic cross-sectional view of a semiconductor device 400 according to a second modification example.
  • the same components as those of the semiconductor device 10 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
  • the upper surface 52A of the buried electrode 52 is partially covered by the source contact plug 402, and the source contact plug 402 has a width smaller than that of the source trench 22.
  • the center portion of the upper surface 52A of the buried electrode 52 is covered with the insulating layer 14, and the remaining portion of the upper surface 52A is covered with the source contact plug 402.
  • the source contact plug 402 can electrically connect the source wiring 18 to the semiconductor layer 12.
  • the source contact plug 402 also contacts the buried electrode 52 and also contacts the semiconductor layer 12 through a part of the side wall 22A of the source trench 22.
  • the position where the source contact plug 402 contacts the semiconductor layer 12 is aligned with the position of the side wall 22A of the source trench 22, so that the source contact plug Variations in the characteristics (eg, gate threshold voltage, on-resistance, etc.) of the semiconductor device 400 due to positional deviation of the semiconductor device 402 can be suppressed.
  • the second modification may be used, in one example, when source trench 22 has a relatively large width.
  • the gate electrode 46 and the first field plate electrode 48 are arranged in the gate trench 20, but the first field plate electrode 48 does not necessarily have to be arranged in the gate trench 20.
  • each region within the semiconductor layer 12 may be reversed. That is, the p-type region may be made into an n-type region, and the n-type region may be made into a p-type region.
  • the various examples described herein can be combined to the extent not technically inconsistent.
  • connection can mean a direct or indirect connection between two or more elements. That is, other elements may or may not be present between two or more connected elements. Note that in this specification, the terms “connect” and “couple” are interchangeable.
  • the term “on” includes the meanings of “on” and “over” unless the context clearly indicates otherwise.
  • the phrase “the first layer is formed on the second layer” refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term “on” does not exclude structures in which other layers are formed between the first layer and the second layer.
  • the Z-axis direction used in this specification does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction.
  • the X-axis direction may be a vertical direction
  • the Y-axis direction may be a vertical direction.
  • Device is
  • the semiconductor layer (12) includes a first conductivity type contact region (58) formed adjacent to the source contact plug (26), and the contact region (58) is connected to the source trench (22).
  • the buried electrode (52) includes an upper surface (52A) covered with the source contact plug (26) and a side surface (52C) opposite to the side wall (22A) of the source trench (22), The semiconductor device described in .
  • the source contact plug (26) has a lower extension (56) embedded between the side wall (22A) of the source trench (22) and the side surface (52C) of the buried electrode (52).
  • the semiconductor device according to appendix 3, comprising:
  • the embedded electrode (52) further includes a bottom surface (52B) opposite to the top surface (52A),
  • the lower extending portion (56) is located between the upper surface (52A) and the bottom surface (52B) of the embedded electrode (52) in a depth direction perpendicular to the second surface (12B).
  • the semiconductor device according to appendix 4 including the lower end surface (56A).
  • the semiconductor layer (12) includes a second conductivity type drift region (40), a first conductivity type body region (42) formed on the drift region (40), and a first conductivity type body region (42) formed on the body region (42). and a source region (44) of a second conductivity type formed in the source region (44), and the source trench (22) is formed to penetrate the source region (44) and the body region (42). 6.
  • the semiconductor device according to 5 or 6.
  • the contact region (58) is adjacent to the source region (44) and the body region (42), and the contact region (58) has a first conductivity type impurity concentration that is higher than the first conductivity type impurity concentration of the body region (42).
  • the source contact plug (26) includes a main portion (26a) disposed within the source trench (22) in plan view, and an overhang portion (26b) disposed outside the source trench (22) in plan view.
  • the semiconductor device according to any one of appendices 4 to 9, wherein the lower extending portion (56) is included in the main portion (26a).
  • the contact region (58) further extends along a part of the second surface (12B) of the semiconductor layer (12), according to any one of appendices 2 to 10. Semiconductor equipment.
  • the source contact plug (26) includes an overhang portion (26b) in contact with the second surface (12B) of the semiconductor layer (12), as described in any one of Supplementary Notes 1 to 9. semiconductor devices.
  • Appendix 14 a gate trench (20) formed in the semiconductor layer (12); further comprising a gate electrode (46) disposed within the gate trench (20); 14.
  • the source trench (22) is one of a plurality of source trenches (22) formed in the semiconductor layer (12), and the gate trench (20) is formed in the semiconductor layer (12). one of the plurality of gate trenches (20); 16.
  • Appendix 17 Further comprising a second field plate electrode (54) disposed below the buried electrode (52) in the source trench (22), the second field plate electrode (54) being connected to the source wiring (18).
  • the semiconductor device according to any one of appendices 1 to 16, which is electrically connected.
  • the buried electrode (52) includes a top surface (52A) partially covered by the source contact plug (402), and a side surface (52C) opposite to the side wall (22A) of the source trench (22). , the semiconductor device according to appendix 1.
  • the insulating layer (14) is formed on the second surface (12B) of the semiconductor layer (12), and the embedded electrode (52) is disposed within the source trench (22) and is connected to the insulating layer (14).
  • the source contact plug (26) contacts the buried electrode (52) and the semiconductor layer (12) through a part of the side wall (22A) of the source trench (22).
  • Forming the source contact plug (26) includes forming a source contact opening (78) in the insulating layer (14), and forming the source contact opening (78) includes forming the source contact opening (78) in the source trench ( 22)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120261746A1 (en) * 2011-03-14 2012-10-18 Maxpower Semiconductor, Inc. Double-Trench Vertical Devices and Methods with Self-Alignment Between Gate and Body Contact
US20130164895A1 (en) * 2011-12-12 2013-06-27 Maxpower Semiconductor, Inc. Trench-Gated Power Devices with Two Types of Trenches and Reliable Polycidation
WO2016175152A1 (ja) * 2015-04-27 2016-11-03 ローム株式会社 半導体装置および半導体装置の製造方法
JP2017045776A (ja) * 2015-08-24 2017-03-02 ローム株式会社 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120261746A1 (en) * 2011-03-14 2012-10-18 Maxpower Semiconductor, Inc. Double-Trench Vertical Devices and Methods with Self-Alignment Between Gate and Body Contact
US20130164895A1 (en) * 2011-12-12 2013-06-27 Maxpower Semiconductor, Inc. Trench-Gated Power Devices with Two Types of Trenches and Reliable Polycidation
WO2016175152A1 (ja) * 2015-04-27 2016-11-03 ローム株式会社 半導体装置および半導体装置の製造方法
JP2017045776A (ja) * 2015-08-24 2017-03-02 ローム株式会社 半導体装置およびその製造方法

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