WO2023184845A1 - 一种峰值电流负载控制电路 - Google Patents

一种峰值电流负载控制电路 Download PDF

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Publication number
WO2023184845A1
WO2023184845A1 PCT/CN2022/115674 CN2022115674W WO2023184845A1 WO 2023184845 A1 WO2023184845 A1 WO 2023184845A1 CN 2022115674 W CN2022115674 W CN 2022115674W WO 2023184845 A1 WO2023184845 A1 WO 2023184845A1
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Prior art keywords
reference voltage
peak load
constant current
mode
control signal
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PCT/CN2022/115674
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English (en)
French (fr)
Inventor
成东波
丁雪征
朱颖
董金华
Original Assignee
上海新进芯微电子有限公司
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Priority claimed from CN202220729267.4U external-priority patent/CN217739799U/zh
Priority claimed from CN202210331067.8A external-priority patent/CN114756075A/zh
Application filed by 上海新进芯微电子有限公司 filed Critical 上海新进芯微电子有限公司
Publication of WO2023184845A1 publication Critical patent/WO2023184845A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/027—Details with automatic disconnection after a predetermined time
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/06—Details with automatic reconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used

Definitions

  • the invention relates to the field of power electronics technology, and in particular to a peak current load control circuit.
  • the instantaneous output power of the smart speaker at this time will be several times that of normal playback.
  • the rated output power marked on its charger is 12V2A (24W).
  • the peak output current is as high as 3.8A
  • the instantaneous output power is as high as 45.6W.
  • the output voltage of the charger drops significantly, which will cause the smart speaker to power off and restart.
  • the purpose of the present invention is to provide a peak current load control circuit to avoid power outage and restart of the load caused by a significant drop in the output voltage of the charger in situations of instantaneous high output power, and to improve the stability of the output voltage of the charger.
  • the present invention provides a peak current load control circuit, including:
  • a reference voltage adjustment circuit used to generate a reference voltage control signal based on the constant current mode signal and/or the constant voltage mode signal of the primary side control chip;
  • a peak load detection module configured to adjust the reference voltage for peak load detection according to the reference voltage control signal; and to perform peak load detection on the primary side control chip according to the reference voltage, and adjust the peak load detection of the primary side control chip.
  • Control mode wherein, the control mode includes a constant current loop control mode and a constant voltage loop control mode, the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage, and the peak load reference voltage is the overcurrent protection reference voltage. k times the reference voltage, k is greater than 1.
  • the reference voltage adjustment circuit is specifically configured to generate, according to the constant current mode signal and/or the constant voltage mode signal, when the primary side control chip is in the constant current loop control mode.
  • the first control signal corresponding to the peak load reference voltage; when the primary side control chip is in the constant voltage loop control mode and the reference voltage is the peak load reference voltage, the overcurrent protection reference voltage is generated
  • the corresponding second control signal wherein the reference voltage control signal includes the first control signal and the second control signal.
  • the reference voltage adjustment circuit includes:
  • a constant current adjustment circuit configured to generate the first control chip after the primary side control chip enters the constant current loop control mode according to the constant current mode start signal and the constant current mode end signal corresponding to the constant current mode signal.
  • the constant current adjustment circuit includes: a first AND gate device, a first RS flip-flop, a D-type flip-flop and an inverting amplifier;
  • the first input terminal of the first AND gate device is connected to the output terminal of the constant current mode end signal
  • the second input terminal of the first AND gate device is connected to the Q output terminal of the D-type flip-flop.
  • the output end of the first AND gate device is connected to the R input end of the first RS flip-flop;
  • the S input end of the first RS flip-flop is connected to the output end of the constant current mode start signal
  • the Q output terminal of the first RS flip-flop is connected to the D input terminal of the D-type flip-flop;
  • the clock input terminal of the D-type flip-flop is connected to the turn-on pulse signal of the driving cycle of the primary-side control chip.
  • the output terminal is connected, the Q output terminal of the D-type flip-flop is connected to the input terminal of the inverting amplifier, and the output terminal of the inverting amplifier is connected to the input terminal of the reference voltage control signal of the peak load detection module. connect.
  • the first RS flip-flop includes: a first NOR gate device and a second NOR gate device;
  • the first input terminal of the first NOR gate device is connected to the output terminal of the constant current mode start signal, and the second input terminal of the first NOR gate device is connected to the second NOR gate device.
  • the output terminal of the first NOR gate device is connected to the first input terminal of the second NOR gate device; the second input terminal of the second NOR gate device is connected to the first input terminal of the first NOR gate device.
  • the output terminal of the AND gate device is connected, and the common terminal connected between the output terminal of the second NOR gate device and the second input terminal of the first NOR gate device serves as the Q output terminal of the first RS flip-flop.
  • the D input of the D type flip-flop is connected.
  • the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the medium and high reference voltage and a medium and low reference voltage.
  • the reference voltage adjustment circuit is specifically configured to adjust the reference voltage according to the constant current mode signal and/or the constant voltage mode signal when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in In the constant current loop control mode, the fourth control signal is generated; when the reference voltage is the middle and low reference voltage and the primary side control chip is in the constant voltage loop control mode, the fourth control signal is generated.
  • the second control signal when the reference voltage is the mid-low reference voltage and the primary side control chip is in the constant current loop control mode, the third control signal is generated; when the reference voltage is The fourth control signal is generated when the reference voltage is the mid-to-high reference voltage and the primary-side control chip is in the constant voltage loop control mode; when the reference voltage is the mid-to-high reference voltage and the primary-side control chip is in the constant voltage loop control mode In the constant current loop control mode, the first control signal is generated; when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant voltage loop control mode, the first control signal is generated. Describe the third control signal.
  • the peak current load control circuit also includes:
  • Timing circuit used to time the peak load duration and/or overcurrent protection duration, and output a peak load protection restart control signal when the peak load duration reaches a first threshold and/or output a peak load protection restart control signal when the overcurrent protection duration reaches a first threshold.
  • the overcurrent protection restart control signal is output.
  • the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage
  • the timing circuit is specifically configured to operate according to the primary side Control the constant current mode signal of the chip, time the peak load duration and the overcurrent protection duration, and output the peak load protection restart control signal when the peak load duration reaches the first threshold.
  • the overcurrent protection restart control signal is output when the overcurrent protection duration reaches the second threshold; wherein the peak load reference voltage is the reference voltage is the peak load reference voltage and the original
  • the maintenance time of the side control chip in the constant current loop control mode, the overcurrent protection duration is when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop.
  • the control mode or the reference voltage is the maintenance time of the peak load reference voltage.
  • the timing circuit includes: a peak load timing circuit and an overcurrent protection timing circuit; wherein,
  • the overcurrent protection timing circuit includes a second AND gate device, a second RS flip-flop and a first timer; the first input end of the second AND gate device and the reference voltage control of the reference voltage adjustment circuit
  • the output end of the signal is connected, the second input end of the second AND gate device is connected to the output end of the constant current mode end delay signal corresponding to the constant current mode signal, and the output end of the second AND gate device is connected to the output end of the constant current mode end delay signal.
  • the R input terminal of the second RS flip-flop is connected; the S input terminal of the second RS flip-flop is connected to the output terminal of the constant current mode start signal corresponding to the constant current mode signal, and the S input terminal of the second RS flip-flop is connected.
  • the Q output terminal is connected to the enable terminal of the first timer; the output terminal of the first timer serves as the output terminal of the overcurrent protection timing circuit, and is used to wait until the duration of the received enable signal reaches the required
  • the overcurrent protection restart control signal is output when the second threshold is reached; the delayed turn-on signal is a pulse signal after a preset number of continuous turn-on pulse signals after the end of the constant current mode control mode;
  • the peak load timing circuit includes a third AND gate device and a second timer; the first input end of the third AND gate device is connected to the output end of the constant current mode signal, and the first input end of the third AND gate device is connected to the output end of the constant current mode signal.
  • the second input terminal is connected to the output terminal of the inverted signal corresponding to the reference voltage control signal, and the output terminal of the third AND gate device is connected to the enable terminal of the second timer; the second timer
  • the output terminal serves as the output terminal of the peak load timing circuit and is used to output the peak load protection restart control signal when the duration of the received enable signal reaches the first threshold.
  • the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the medium and high reference voltage and a medium and low reference voltage.
  • the timing circuit is specifically configured to time the peak load duration and the overcurrent protection duration according to the constant current mode signal of the primary side control chip, and when the peak load duration reaches The peak load protection restart control signal is output when the first threshold is reached, and the overcurrent protection restart control signal is output when the overcurrent protection duration reaches the second threshold;
  • the peak load reference voltage is the The reference voltage is the peak load reference voltage and the primary-side control chip is in the constant current loop control mode.
  • the over-current protection duration is the reference voltage is the over-current protection reference voltage and The primary-side control chip is in the constant current loop control mode or the reference voltage is the maintenance time of the medium-low reference voltage, the medium-high reference voltage or the peak load reference voltage.
  • a peak current load control circuit includes: a reference voltage adjustment circuit, used to generate a reference voltage control signal according to the constant current mode signal and/or constant voltage mode signal of the primary side control chip; a peak load detection module , used to adjust the reference voltage for peak load detection based on the reference voltage control signal; and based on the reference voltage, perform peak load detection on the primary side control chip, and adjust the control mode of the primary side control chip; where the control mode includes a constant current loop In control mode and constant voltage loop control mode, the reference voltage includes the over-current protection reference voltage and the peak load reference voltage.
  • the peak load reference voltage is k times the over-current protection reference voltage, and k is greater than 1;
  • the present invention controls and adjusts the reference voltage of the peak load detection of the primary control chip according to the constant current mode signal and/or the constant voltage mode signal of the primary control chip through the setting of the reference voltage adjustment circuit to control the primary control chip. Switching between the constant current loop control mode and the constant voltage loop control mode can avoid the load restart caused by the obvious drop in the output voltage of the primary feedback charger in instantaneous high output power situations, and improve the primary feedback charger Output voltage stability when peak current loads are detected.
  • Figure 1 is a structural block diagram of a peak current load control circuit provided by an embodiment of the present invention
  • Figure 2 is a schematic diagram of the control mode switching principle of a primary-side control chip
  • Figure 3 is a schematic diagram of peak load detection for two-gear reference voltage switching provided by an embodiment of the present invention.
  • Figure 4 is a schematic diagram of peak load detection for four-gear reference voltage switching provided by an embodiment of the present invention.
  • Figure 5 is a schematic diagram of a reference voltage adjustment circuit in a peak current load control circuit provided by an embodiment of the present invention
  • Figure 6 is a schematic diagram of an overcurrent protection timing circuit in a peak current load control circuit provided by an embodiment of the present invention
  • Figure 7 is a schematic diagram of a peak load timing circuit in a peak current load control circuit provided by an embodiment of the present invention.
  • FIG. 8 is a schematic timing diagram of relevant signals of a constant current mode signal in a peak current load control circuit provided by an embodiment of the present invention.
  • FIG. 1 is a structural block diagram of a peak current load control circuit provided by an embodiment of the present invention.
  • the peak current load control circuit may include:
  • the reference voltage adjustment circuit 10 is used to generate a reference voltage control signal according to the constant current mode signal and/or the constant voltage mode signal of the primary side control chip;
  • the peak load detection module 20 is used to adjust the reference voltage for peak load detection according to the reference voltage control signal; and perform peak load detection on the primary side control chip according to the reference voltage, and adjust the control mode of the primary side control chip; wherein, the control mode It includes constant current loop control mode and constant voltage loop control mode.
  • the reference voltage includes overcurrent protection reference voltage and peak load reference voltage.
  • the peak load reference voltage is k times the overcurrent protection reference voltage, and k is greater than 1.
  • the principle of whether the load of the primary side feedback (PSR) system is controlled by a CV (constant voltage, i.e. constant voltage) loop or by a CC (constant current, i.e. constant current) loop is corresponding to the constant current point
  • the load capacity determined by the reference voltage (VrefCC) detects the weight of the load in real time; if the load can be carried, the CV loop will be used to control the entire PSR system; if the load cannot be carried, the CC loop will be used to control the entire PSR system .
  • sections A to B belong to the constant voltage CV section, and the output of the primary feedback system is controlled by the CV loop; sections B to C belong to the constant current CC section, and the CV loop cannot drive this section. load, the system output is controlled by the CC loop.
  • the peak load detection performed by the peak load detection module 20 on the primary side control chip can adopt the following formula:
  • Iout is the average output current controlled by the CC loop of the primary control chip
  • Np is the number of turns of the primary coil of the transformer
  • Ns is the number of turns of the secondary coil of the transformer
  • Rcs is the resistance of the peak current sampling resistor
  • VrefCC is the reference voltage, which is the reference voltage controlled by the CC loop.
  • the peak load detection module 20 can control the adjusted reference voltage (VrefCC) according to the reference voltage adjustment circuit 10, and perform the peak load on the primary side control chip in the same or similar manner as the peak load detection method in the prior art. Detect and adjust the constant current loop control mode or constant voltage loop control mode used by the primary side control chip.
  • VrefCC adjusted reference voltage
  • the peak load detection module 20 can adjust the reference voltage of the peak load detection according to the reference voltage control signal sent by the connected reference voltage adjustment circuit 10 to adjust the loading capacity of the switching primary side control chip, and according to Depending on the current load situation, adjust the control mode of the primary-side control chip, that is, switch between the constant-current loop control mode and the constant-voltage loop control mode, to improve the stability of the output voltage of the primary-side feedback charger.
  • the reference voltage can include the output current of over-current protection (OCP).
  • OCP over-current protection
  • the reference voltage control signal sent by the reference voltage adjustment circuit 10 to the peak load detection module 20 may include the first control signal corresponding to the peak load reference voltage and the overcurrent.
  • the second control signal corresponding to the protection reference voltage; where, Pk Load/OCP k, that is, the peak load reference voltage is k times the overcurrent protection reference voltage, and k is greater than 1; that is, when k is larger, the load
  • the overcurrent protection reference voltage (VrefCCL) and the peak load reference voltage (VrefCCH) can be used to control the peak load detection, so that the reference voltage (VrefCC) that determines the constant current point Switch back and forth between VrefCCL and VrefCCH; accordingly, the peak load detection module 20 can also control the control mode of the primary side control chip between the constant current loop control mode (CC Mode) and the constant voltage loop control mode (CV Mode). Switching back and forth, compared with the peak load detection of fixed reference voltage in the existing technology, it can avoid the situation where the output voltage drops too much.
  • the reference voltage (VrefCC) that determines the constant current point in this embodiment can also include a preset reference voltage between the overcurrent protection reference voltage and the peak load reference voltage to further improve the primary side by increasing the VrefCC level. Control the ripple during the control mode switching process of the chip.
  • the reference voltage (VrefCC) can include four levels: peak load reference voltage (VrefCCH), overcurrent protection reference voltage (VrefCCL), medium and high reference voltage (VrefCCMHigh) and medium and low reference voltage (VrefCCMLow); where, VrefCCH>VrefCCMHigh > VrefCCMLow > VrefCCL;
  • VrefCCH>VrefCCMHigh > VrefCCMLow > VrefCCL As shown in Figure 4, when the ⁇ VrefCC between two adjacent gears is the same, the VrefCC settings of the four gears can make the ⁇ VrefCC that VrefCC changes between two adjacent gears each time only the original two gears. 1/3 of VrefCC, which will improve ripple.
  • the constant current mode signal of the primary side control chip in this embodiment can be the signal of the constant current loop control mode used by the primary side control chip, such as the CCMode signal in Figure 8, which is the control mode of the primary side control chip.
  • the CCMode signal When it is the constant current loop control mode, the CCMode signal is high level.
  • the control mode of the primary side control chip is the constant voltage loop control mode, the CCMode signal is low level.
  • the constant voltage mode signal of the primary side control chip can be The signal of the constant voltage loop control mode used by the primary side control chip.
  • the control mode of the primary side control chip is constant current loop control mode
  • the constant voltage mode signal can be low level.
  • the control mode of the primary side control chip is In constant voltage loop control mode, the constant voltage mode signal can be high level.
  • the reference voltage adjustment circuit 10 in this embodiment can generate a reference voltage control signal according to the constant current mode signal and/or the constant voltage mode signal to control the reference voltage for peak load detection adjusted by the peak load detection module 20 .
  • the reference voltage adjustment circuit 10 can be specifically configured to control the chip in a constant current state on the primary side according to the constant current mode signal and/or the constant voltage mode signal.
  • the first control signal corresponding to the peak load reference voltage is generated;
  • the second control signal corresponding to the overcurrent protection reference voltage is generated. signal; wherein, the reference voltage control signal includes a first control signal and a second control signal.
  • the constant current point corresponding to the overcurrent protection reference voltage (VrefCCL) is the OCP point
  • the constant current point corresponding to the peak load reference voltage (VrefCCH) is the Pk Load point;
  • the reference voltage adjustment circuit 10 will control the peak load detection module 20 to switch the reference voltage from VrefCCL to VrefCCH, that is, the PSR device
  • the load capacity is increased from the OCP point to the Pk Load point; and after switching to VrefCCH, the PSR device can drive the load between A and B at this time, and the peak load detection module 20 will change the control mode of the primary side control chip from CC Mode Switch to CV Mode.
  • the reference voltage adjustment circuit 10 can control the peak load detection module 20 to switch the reference voltage from VrefCCH to VrefCCL, that is, the load capacity of the PSR system is reduced from the Pk Load point to the OCP point; after this, it will Repeating the above process, the reference voltage (VrefCC) that determines the constant current point switches back and forth between VrefCCH and VrefCCL.
  • the specific circuit structure of the reference voltage adjustment circuit 10 in this embodiment can be set by the designer according to practical scenarios and user needs.
  • the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage
  • the reference voltage adjustment The circuit 10 may include a constant current adjustment circuit.
  • the constant current adjustment circuit may be used to generate a third constant current mode start signal and a constant current mode end signal after the primary side control chip enters the constant current loop control mode according to the constant current mode start signal and the constant current mode end signal.
  • the constant current mode start signal corresponding to the constant current mode signal can be the pulse signal at the beginning of the constant current loop control mode (CC Mode), such as the CCMode_beginpulse signal in Figure 8; the constant current mode end signal corresponding to the constant current mode signal It can be the pulse signal at the end of the constant current loop control mode, such as the CCMode_endpulse signal in Figure 8.
  • the reference voltage adjustment circuit 10 may also include a signal conversion circuit for converting the constant current mode signal of the primary side control chip into a constant current mode start signal and a constant current mode end signal, so that the constant current adjustment circuit can convert according to the signal. The circuit outputs a constant current mode start signal and a constant current mode end signal to generate a reference voltage control signal.
  • the above-mentioned constant current adjustment circuit may include a first AND gate device 11 (and2, that is, a two-input AND gate device), a third An RS flip-flop 12 (two nor2, that is, an RS flip-flop composed of two two-input NOR gate devices), a D-type flip-flop 13 (DFF) and an inverting amplifier 14; among them, the first AND gate device 11
  • the first input terminal is connected to the output terminal of the constant current mode end signal
  • the second input terminal of the first AND gate device 11 is connected to the Q output terminal of the D-type flip-flop 13
  • the output terminal of the first AND gate device 11 is connected to the first
  • the R input terminal of the RS flip-flop 12 is connected;
  • the S input terminal of the first RS flip-flop 12 is connected with the output terminal of the constant current mode start signal, and the Q output terminal of the first RS flip-flop 12 is connected with the D input of
  • the second input terminal of the first AND gate device 11 can be connected to the Q output terminal of the D-type flip-flop 13, so that the constant current adjustment circuit can be used to adjust the constant current mode start signal and the constant current mode end signal according to the input, Generate a reference voltage control signal; the second input terminal of the first AND gate device 11 can also be connected to the input terminal of the usage status signal of the peak load reference voltage, so that the constant current adjustment circuit can be used to start the constant current mode according to the input signal , the constant current mode end signal and the usage status signal of the peak load reference voltage, to generate a reference voltage control signal.
  • This embodiment does not impose any restrictions on this.
  • the first RS flip-flop 12 may include: a first NOR gate device and a second NOR gate device; where , the first input terminal of the first NOR gate device is connected to the output terminal of the constant current mode start signal, the second input terminal of the first NOR gate device is connected to the output terminal of the second NOR gate device, and the first NOR gate device The output terminal of the gate device is connected to the first input terminal of the second NOR gate device; the second input terminal of the second NOR gate device is connected to the output terminal of the first AND gate device 11, and the output terminal of the second NOR gate device The common terminal connected to the second input terminal of the first NOR gate device serves as the Q output terminal of the first RS flip-flop 12 and is connected to the D input terminal of the D-type flip-flop 13 .
  • the reference voltage control signal may include the peak value.
  • the reference voltage adjustment circuit 10 can be specifically Used to generate a fourth control signal based on the constant current mode signal and/or the constant voltage mode signal when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode; when the reference voltage is medium or low When the reference voltage is the reference voltage and the primary-side control chip is in the constant-voltage loop control mode, the second control signal is generated; when the reference voltage is the medium-low reference voltage and the primary-side control chip is in the constant-current loop control mode, the third control signal is generated; When the reference voltage is a medium-to-high reference voltage and the primary-side control chip is in the constant-voltage loop control mode, a fourth control signal is generated; when the reference voltage is a medium-to-high reference voltage and the primary-side control chip is in
  • the constant current point corresponding to the overcurrent protection reference voltage (VrefCCL) is the OCP point
  • the constant current point corresponding to the peak load reference voltage (VrefCCH) is the Pk Load point
  • the constant current point corresponding to the medium and low reference voltage (VrefCCMLow) is point B
  • the constant current point corresponding to the medium and high reference voltage (VrefCCMHigh) is point C
  • the reference voltage for peak load detection (VrefCC) can be switched back and forth between the four gears of VrefCCL, VrefCCMLow, VrefCCMHigh and VrefCCH: 1) VrefCCL ⁇ VrefCCMLow: In VrefCCL state, CC Mode trigger is detected, VrefCC can be switched from VrefCCL to VrefCCMLow; 2) VrefCCMLow ⁇ VrefCCL: In VrefCCMLow state, CC Mode end is detected (i.e.
  • CV Mode trigger indicating PSR in VrefCCMLow state
  • the device can drive the current load, VrefCC switches from VrefCCMLow to VrefCCL; 3) VrefCCMLow ⁇ VrefCCMHigh: In the VrefCCMLow state, CC Mode trigger is detected, indicating that VrefCCMLow is not enough to drive the current load, VrefCC switches from VrefCCMLow to VrefCCMHigh; 4) VrefCCMHigh ⁇ VrefCCMLow : In the VrefCCMHigh state, the end of CC Mode is detected, indicating that VrefCCMHigh can drive the current load, and VrefCC can be switched from VrefCCMHigh to VrefCCMLow; 5) VrefCCMHigh ⁇ VrefCCH: In the VrefCCMHigh state, the CC Mode trigger is detected, indicating that VrefCCMHigh is not enough to drive the current load.
  • VrefCC can be switched from VrefCCMHigh to VrefCCH; 6) VrefCCH ⁇ VrefCCMHigh: In the VrefCCH state, the end of CC Mode is detected, indicating that VrefCCH can drive the current load, and VrefCC can be switched from VrefCCH to VrefCCMHigh; 7) In the VrefCCL state, the detection At the end of CV Mode, it means that VrefCCL can drive the current load and VrefCC can maintain VrefCCL.
  • the specific circuit structure of the reference voltage adjustment circuit 10 may be the same as the above-mentioned reference voltage including an over-current protection reference voltage and
  • the reference voltage adjustment circuit 10 of the two levels of the peak load reference voltage is set in a similar manner, and this embodiment does not impose any restrictions on this.
  • the peak current load control circuit may also include: a timing circuit for timing the peak load duration and/or the overcurrent protection duration, and when the peak load duration reaches the first threshold Output the peak load protection restart control signal and/or output the overcurrent protection restart control signal when the overcurrent protection duration reaches the second threshold to restart the charger system; wherein the peak load duration can be that the load required current is greater than or equal to The duration of the constant current point (such as the Pk Load point) corresponding to the peak load reference voltage.
  • the overcurrent protection duration can be the duration when the load required current is greater than or equal to the constant current point (such as the OCP point) corresponding to the overcurrent protection reference voltage. time.
  • the timing circuit can be specifically used to time the peak load duration and over-current protection duration, and output the peak load protection restart control signal when the peak load duration reaches the first threshold, so that the PSR device triggers the peak load protection restart. ;
  • the overcurrent protection duration reaches the second threshold, the overcurrent protection restart control signal is output, so that the PSR device triggers OCP protection restart.
  • the timing circuit can be specifically used to adjust the peak value according to the constant current mode signal of the primary side control chip.
  • the load duration and the over-current protection duration are timed, and the peak load protection restart control signal is output when the peak load duration reaches the first threshold, and the over-current protection restart control signal is output when the over-current protection duration reaches the second threshold;
  • the peak load reference voltage is the reference voltage is the peak load reference voltage and the primary-side control chip is in the constant current loop control mode.
  • the over-current protection duration is the reference voltage is the over-current protection reference voltage and the primary-side control chip is in The constant current loop control mode or the reference voltage is the maintenance time of the peak load reference voltage; as shown in Figure 3, the timing circuit can start timing the overcurrent protection duration (ie, OCP timing) at point A, and end the overcurrent at point D. Timing of the protection duration, when the overcurrent protection duration is greater than or equal to the second threshold (such as 1.5s), the OCP protection restart of the PSR device is triggered. When the overcurrent protection duration is less than the second threshold, the PSR device continues to work; timing circuit You can start the timing of the peak load duration at point B (i.e.
  • PK Load timing end the timing of the peak load duration at point C, and trigger the peakload of the PSR device when the peak load duration is greater than or equal to the first threshold (such as 150ms). Protection restarts, and the PSR device continues to work when the peak load duration is less than the first threshold; that is, as shown in the output current (Output Current) on the left side of Figure 3, the output current of the PSR device exceeds the OCP point and starts OCP timing, and reaches the The PK Load point starts another PK Load timing, but the duration of the PK Load timing does not reach 150ms and will not trigger the peakload protection restart.
  • the first threshold such as 150ms
  • the OCP timing is still continuing, and the OCP protection is triggered after reaching 1.5s; as shown on the right side of Figure 3 Output current display, the output current of the PSR device exceeds the OCP point and starts the OCP timing. In the middle, it reaches the PK Load point and starts another PK Load timing. The duration of the PK Load timing reaches 150ms and triggers the peakload protection restart. At this time, the OCP timing is ended at the same time. Less than 1.5s.
  • the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the medium and high reference voltage, and a fourth control signal corresponding to the medium and low reference voltage.
  • the timing circuit can be specifically used to time the peak load duration and overcurrent protection duration according to the constant current mode signal of the primary side control chip, and output the peak load protection restart control when the peak load duration reaches the first threshold.
  • the over-current protection restart control signal is output when the over-current protection duration reaches the second threshold;
  • the peak load reference voltage is the reference voltage, the peak load reference voltage is the maintenance time and the primary-side control chip is in the constant current loop control mode.
  • the current protection duration is the maintenance time when the reference voltage is the over-current protection reference voltage and the primary control chip is in the constant current loop control mode or the reference voltage is the medium-low reference voltage, medium-high reference voltage or peak load reference voltage; as shown in Figure 4 Indicates that the timing circuit can start timing the overcurrent protection duration (i.e. OCP timing) at point A and end the timing of the overcurrent protection duration at point F.
  • OCP timing overcurrent protection duration
  • the overcurrent protection duration is greater than or equal to the second threshold (such as 1.5s ) triggers the OCP protection restart of the PSR device, and the PSR device continues to work when the overcurrent protection duration is less than the second threshold; the timing circuit can start timing the peak load duration (i.e.
  • the timing of the peak load duration triggers the peakload protection restart of the PSR device when the peak load duration is greater than or equal to the first threshold (such as 150ms).
  • the PSR device continues to work when the peak load duration is less than the first threshold.
  • VrefCC After it is lower than the constant current point corresponding to VrefCCMHigh, it switches to Switch between VrefCCMHigh and VrefCCMLow, and then switch between VrefCCMLow and VrefCCL after it is lower than the constant current point corresponding to VrefCCMLow. After the load is lower than the OCP point, VrefCC stabilizes at VrefCCL and exits Tocp timing.
  • the timing circuit can include a peak load timing circuit and an overcurrent protection timing circuit; among them, the peak load timing circuit can be used for Timing the peak load duration, and outputting the peak load protection restart control signal when the peak load duration reaches the first threshold; the overcurrent protection timing circuit can be used to time the overcurrent protection duration, and output the peak load protection restart control signal when the overcurrent protection continues. When the time reaches the second threshold, the overcurrent protection restart control signal is output.
  • the overcurrent protection timing circuit may include a second AND gate device 21 (and2), the second RS flip-flop 22 (two nor2) and the first timer 23 (Time Counter1); the first input end of the second AND gate device 21 and the reference voltage control signal of the reference voltage adjustment circuit 10
  • the output terminal (the output terminal of the inverting amplifier 14 in Figure 5 ) is connected, and the second input terminal of the second AND gate device 21 is connected to the output terminal of the constant current mode end delay signal (CV_EN_12Pulse) corresponding to the constant current mode signal.
  • the output terminal of the two AND gate device 21 is connected to the R input terminal of the second RS flip-flop 22; the S input terminal of the second RS flip-flop 22 is connected to the output terminal of the constant current mode start signal corresponding to the constant current mode signal, and the second The Q output terminal of the RS flip-flop 22 is connected to the enable terminal of the first timer 23; the output terminal of the first timer 23 serves as the output terminal of the over-current protection timing circuit, and is used to wait until the duration of the received enable signal reaches
  • the peak load protection restart control signal (Tocp_pro) is output at the second threshold; the delayed turn-on signal is the pulse signal after a preset number of consecutive turn-on pulse signals after the end of the constant current mode control mode, such as CV_EN_12pulse in Figure 8, that is, CCMode After the end, continuously count the pulse signals after 12 turn-on pulse signals (ie, CV mode switching pulse signals, such as the PFM signal in Figure 5).
  • the peak load timing circuit may include a third AND gate device 31 (and2) and the second timer 32 (Time Counter2); the first input terminal of the third AND gate device 31 is connected to the output terminal of the constant current mode signal, and the second input terminal of the third AND gate device 31 is connected to the reference voltage control
  • the output terminal of the inverted signal corresponding to the signal (the input terminal of the inverting amplifier 14 in Figure 5) is connected, and the output terminal of the third AND gate device 31 is connected to the enable terminal of the second timer 32; the second timer 32
  • the output terminal serves as the output terminal of the peak load timing circuit, and is used to output the peak load protection restart control signal (Tpeakload_pro) when the duration of the received enable signal reaches the first threshold.
  • the embodiment of the present invention controls and adjusts the reference voltage for peak load detection of the primary control chip according to the constant current mode signal and/or the constant voltage mode signal of the primary control chip through the setting of the reference voltage adjustment circuit 10.
  • the embodiment of the present invention controls and adjusts the reference voltage for peak load detection of the primary control chip according to the constant current mode signal and/or the constant voltage mode signal of the primary control chip through the setting of the reference voltage adjustment circuit 10.

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Abstract

一种峰值电流负载控制电路，包括：参考电压调整电路(10)，用于根据原边控制芯片的恒流模式信号和/或恒压模式信号，生成参考电压控制信号；峰值负载检测模块(20)，用于根据参考电压控制信号，调整峰值负载检测的参考电压；并根据参考电压，对原边控制芯片进行峰值负载检测，调整原边控制芯片的控制模式；其中，控制模式包括恒流环路控制模式和恒压环路控制模式；提升了原边反馈充电器在检测到峰值电流负载时的输出电压的稳定性。

Description

一种峰值电流负载控制电路
本申请要求于2022年03月31日提交中国专利局、申请号为202210331067.8、发明创造名称为“一种峰值电流负载控制电路”，以及于2022年03月31日提交中国专利局、申请号为202220729267.4、发明创造名称为“一种峰值电流负载控制电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电力电子技术领域，特别涉及一种峰值电流负载控制电路。
背景技术
在智能音箱应用中，在低重音场合中，会使此时的智能音箱瞬间输出功率几倍于正常播放时的输出功率。以天猫精灵X5音箱为例，其充电器标示的额定输出功率是12V2A(24W)，在低重音播放中，发现其输出电流峰值高达3.8A，此时瞬间输出功率高达45.6W；在这种瞬间高输出功率场合中，充电器的输出电压明显下降会导致智能音箱断电重启。
因此，如何能够避免瞬间高输出功率场合中，充电器的输出电压明显下降所导致的智能音箱断电重启，提升充电器的输出电压的稳定性，是现今急需解决的问题。
发明内容
本发明的目的是提供一种峰值电流负载控制电路，以避免瞬间高输出功率场合中，充电器的输出电压明显下降所导致的负载断电重启，提升充电器的输出电压的稳定性。
为解决上述技术问题，本发明提供一种峰值电流负载控制电路，包括：
参考电压调整电路，用于根据原边控制芯片的恒流模式信号和/或恒压模式信号，生成参考电压控制信号；
峰值负载检测模块，用于根据所述参考电压控制信号，调整峰值负载检测的参考电压；并根据所述参考电压，对所述原边控制芯片进行峰值负 载检测，调整所述原边控制芯片的控制模式；其中，所述控制模式包括恒流环路控制模式和恒压环路控制模式，所述参考电压包括过电流保护参考电压和峰值负载参考电压，峰值负载参考电压为所述过电流保护参考电压的k倍，k大于1。
可选的，所述参考电压调整电路具体用于根据所述恒流模式信号和/或所述恒压模式信号，在所述原边控制芯片处于所述恒流环路控制模式时，生成所述峰值负载参考电压对应的第一控制信号；在所述原边控制芯片处于所述恒压环路控制模式且所述参考电压为所述峰值负载参考电压时，生成所述过电流保护参考电压对应的第二控制信号；其中，所述参考电压控制信号包括所述第一控制信号和所述第二控制信号。
可选的，所述参考电压调整电路，包括：
恒流调整电路，用于根据所述恒流模式信号对应的恒流模式开始信号和恒流模式结束信号，在所述原边控制芯片进入所述恒流环路控制模式后，生成所述第一控制信号；在所述参考电压为所述峰值负载参考电压且所述原边控制芯片结束所述恒流环路控制模式后，生成所述第二控制信号。
可选的，所述恒流调整电路，包括：第一与门器件、第一RS触发器、D类型触发器和倒相放大器；
其中，所述第一与门器件的第一输入端与所述恒流模式结束信号的输出端连接，所述第一与门器件的第二输入端与所述D类型触发器的Q输出端连接，所述第一与门器件的输出端与所述第一RS触发器的R输入端连接；所述第一RS触发器的S输入端与所述恒流模式开始信号的输出端连接，所述第一RS触发器的Q输出端与所述D类型触发器的D输入端连接；所述D类型触发器的时钟输入端与所述原边控制芯片的驱动周期开通的开通脉冲信号的输出端连接，所述D类型触发器的Q输出端与所述倒相放大器的输入端连接，所述倒相放大器的输出端与所述峰值负载检测模块的所述参考电压控制信号的输入端连接。
可选的，所述第一RS触发器，包括：第一或非门器件和第二或非门器件；
其中，所述第一或非门器件的第一输入端与所述恒流模式开始信号的 输出端连接，所述第一或非门器件的第二输入端与所述第二或非门器件的输出端连接，所述第一或非门器件的输出端与所述第二或非门器件的第一输入端连接；所述第二或非门器件的第二输入端与所述第一与门器件的输出端连接，所述第二或非门器件的输出端与所述第一或非门器件的第二输入端连接的公共端作为所述第一RS触发器的Q输出端与所述D类型触发器的D输入端连接。
可选的，所述参考电压控制信号包括所述峰值负载参考电压对应的第一控制信号、所述过电流保护参考电压对应的第二控制信号、中高参考电压对应的第三控制信号和中低参考电压对应的第四控制信号；其中，所述峰值负载参考电压大于所述中高参考电压大于所述中低参考电压大于过电流保护参考电压；
对应的，所述参考电压调整电路具体用于根据所述恒流模式信号和/或所述恒压模式信号，在所述参考电压为所述过电流保护参考电压且所述原边控制芯片处于所述恒流环路控制模式时，生成所述第四控制信号；在所述参考电压为所述中低参考电压且所述原边控制芯片处于所述恒压环路控制模式时，生成所述第二控制信号；在所述参考电压为所述中低参考电压且所述原边控制芯片处于所述恒流环路控制模式时，生成所述第三控制信号；在所述参考电压为所述中高参考电压且所述原边控制芯片处于所述恒压环路控制模式时，生成所述第四控制信号；在所述参考电压为所述中高参考电压且所述原边控制芯片处于所述恒流环路控制模式时，生成所述第一控制信号；在所述参考电压为所述峰值负载参考电压且所述原边控制芯片处于所述恒压环路控制模式时，生成所述第三控制信号。
可选的，该峰值电流负载控制电路还包括：
计时电路，用于对所述峰值负载持续时间和/或过电流保护持续时间进行计时，并在所述峰值负载持续时间达到第一阈值时输出峰值负载保护重启控制信号和/或在所述过电流保护持续时间达到第二阈值时输出过电流保护重启控制信号。
可选的，所述参考电压控制信号包括所述峰值负载参考电压对应的第一控制信号和所述过电流保护参考电压对应的第二控制信号，所述计时电 路具体用于根据所述原边控制芯片的恒流模式信号，对所述峰值负载持续时间和所述过电流保护持续时间进行计时，并在所述峰值负载持续时间达到所述第一阈值时输出所述峰值负载保护重启控制信号，在所述过电流保护持续时间达到所述第二阈值时输出所述过电流保护重启控制信号；其中，所述峰值负载参考电压为所述参考电压为所述峰值负载参考电压且所述原边控制芯片处于所述恒流环路控制模式的维持时间，所述过电流保护持续时间为所述参考电压为所述过电流保护参考电压且所述原边控制芯片处于所述恒流环路控制模式或所述参考电压为所述峰值负载参考电压的维持时间。
可选的，所述计时电路，包括：峰值负载计时电路和过电流保护计时电路；其中，
所述过电流保护计时电路包括第二与门器件、第二RS触发器和第一计时器；所述第二与门器件的第一输入端与所述参考电压调整电路的所述参考电压控制信号的输出端连接，所述第二与门器件的第二输入端与所述恒流模式信号对应的恒流模式结束延迟信号的输出端连接，所述第二与门器件的输出端与所述第二RS触发器的R输入端连接；所述第二RS触发器的S输入端与所述恒流模式信号对应的恒流模式开始信号的输出端连接，所述第二RS触发器的Q输出端与所述第一计时器的使能端连接；所述第一计时器的输出端作为所述过电流保护计时电路的输出端，用于在接收的使能信号的持续时间达到所述第二阈值时输出所述过电流保护重启控制信号；所述延迟开通信号为所述恒流模式控制模式结束后连续预设数量个周期的开通脉冲信号后的脉冲信号；
所述峰值负载计时电路包括第三与门器件和第二计时器；所述第三与门器件的第一输入端与所述恒流模式信号的输出端连接，所述第三与门器件的第二输入端与所述参考电压控制信号对应的倒相信号的输出端连接，所述第三与门器件的输出端与所述第二计时器的使能端连接；所述第二计时器的输出端作为所述峰值负载计时电路的输出端，用于在接收的使能信号的持续时间达到所述第一阈值时输出所述峰值负载保护重启控制信号。
可选的，所述参考电压控制信号包括所述峰值负载参考电压对应的第 一控制信号、所述过电流保护参考电压对应的第二控制信号、中高参考电压对应的第三控制信号和中低参考电压对应的第四控制信号；其中，所述峰值负载参考电压大于所述中高参考电压大于所述中低参考电压大于过电流保护参考电压；
对应的，所述计时电路具体用于根据所述原边控制芯片的恒流模式信号，对所述峰值负载持续时间和所述过电流保护持续时间进行计时，并在所述峰值负载持续时间达到所述第一阈值时输出所述峰值负载保护重启控制信号，在所述过电流保护持续时间达到所述第二阈值时输出所述过电流保护重启控制信号；所述峰值负载参考电压为所述参考电压为所述峰值负载参考电压且所述原边控制芯片处于所述恒流环路控制模式的维持时间，所述过电流保护持续时间为所述参考电压为所述过电流保护参考电压且所述原边控制芯片处于所述恒流环路控制模式或所述参考电压为所述中低参考电压、所述中高参考电压或所述峰值负载参考电压的维持时间。
本发明所提供的一种峰值电流负载控制电路，包括：参考电压调整电路，用于根据原边控制芯片的恒流模式信号和/或恒压模式信号，生成参考电压控制信号；峰值负载检测模块，用于根据参考电压控制信号，调整峰值负载检测的参考电压；并根据参考电压，对原边控制芯片进行峰值负载检测，调整原边控制芯片的控制模式；其中，控制模式包括恒流环路控制模式和恒压环路控制模式，参考电压包括过电流保护参考电压和峰值负载参考电压，峰值负载参考电压为过电流保护参考电压的k倍，k大于1；
可见，本发明通过参考电压调整电路的设置，根据原边控制芯片的恒流模式信号和/或恒压模式信号，控制调整原边控制芯片的峰值负载检测的参考电压，以控制原边控制芯片的恒流环路控制模式和恒压环路控制模式的切换，从而避免瞬间高输出功率场合中，原边反馈充电器的输出电压明显下降所导致的负载断电重启，提升原边反馈充电器在检测到峰值电流负载时的输出电压的稳定性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对 实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例所提供的一种峰值电流负载控制电路的结构框图；
图2为一种原边控制芯片的控制模式切换的原理示意图；
图3为本发明实施例所提供的一种两档位参考电压切换的峰值负载检测的示意图；
图4为本发明实施例所提供的一种四档位参考电压切换的峰值负载检测的示意图；
图5为本发明实施例所提供的一种峰值电流负载控制电路中的参考电压调整电路的示意图；
图6为本发明实施例所提供的一种峰值电流负载控制电路中的过电流保护计时电路的示意图；
图7为本发明实施例所提供的一种峰值电流负载控制电路中的峰值负载计时电路的示意图；
图8为本发明实施例所提供的一种峰值电流负载控制电路中恒流模式信号的相关信号的时序示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参考图1，图1为本发明实施例所提供的一种峰值电流负载控制电路的结构框图。该峰值电流负载控制电路可以包括：
参考电压调整电路10，用于根据原边控制芯片的恒流模式信号和/或恒压模式信号，生成参考电压控制信号；
峰值负载检测模块20，用于根据参考电压控制信号，调整峰值负载检 测的参考电压；并根据参考电压，对原边控制芯片进行峰值负载检测，调整原边控制芯片的控制模式；其中，控制模式包括恒流环路控制模式和恒压环路控制模式，参考电压包括过电流保护参考电压和峰值负载参考电压，峰值负载参考电压为过电流保护参考电压的k倍，k大于1。
可以理解的是，原边反馈(PSR)系统的负载是由CV(恒定电压，即恒压)环路控制还是由CC(恒定电流，即恒流)环路控制的原理是由恒流点对应的参考电压(VrefCC)决定的带载能力实时检测负载的轻重；若带得动负载，就会采用CV环路控制整个PSR系统；若带不动负载，就会采用CC环路控制整个PSR系统。如图2所示，在A～B段，属于恒压CV段，原边反馈系统的输出由CV环路控制；在B～C段，属于恒流CC段，CV环路带不动此段的负载，系统输出由CC环路控制。
具体的，峰值负载检测模块20对原边控制芯片进行的峰值负载检测可以采用如下公式：
Figure PCTCN2022115674-appb-000001
上式中，Iout为原边控制芯片的CC环路控制的平均输出电流，Np为变压器的原边线圈匝数，Ns为变压器的副边线圈匝数，Rcs为峰值电流采样电阻的阻值；VrefCC为参考电压，即CC环路控制的参考电压。
也就是说，峰值负载检测模块20可以根据参考电压调整电路10控制调整的参考电压(VrefCC)，采用与现有技术中的峰值负载检测方法相同或相似的方式，对原边控制芯片进行峰值负载检测，调整切换原边控制芯片所采用的恒流环路控制模式或恒压环路控制模式。
对应的，本实施例中峰值负载检测模块20可以根据连接的参考电压调整电路10发送的参考电压控制信号，调整峰值负载检测的参考电压，以调整切换原边控制芯片的带载能力，并根据当前的负载轻重情况，调整原边控制芯片的控制模式，即恒流环路控制模式和恒压环路控制模式的切换，，提升原边反馈充电器的输出电压的稳定性。
需要说明的是，对于本实施例中峰值负载检测的参考电压的具体设置数量和数值，可以由设计人员根据实用场景和用户需求自行设置，如参考 电压可以包括过电流保护(OCP)的输出电流点(即OCP点，如图3中的A点和D点)对应的参考电压(即过电流保护参考电压)和峰值负载的输出电流点(即Pk Load点，如图3中的B点和C点)对应的参考电压(即峰值负载参考电压)；对应的，参考电压调整电路10向峰值负载检测模块20发送的参考电压控制信号可以包括峰值负载参考电压对应的第一控制信号和过电流保护参考电压对应的第二控制信号；其中，Pk Load/OCP＝k，即峰值负载参考电压为过电流保护参考电压的k倍，k大于1；也就是说，当k越大时，对负载的输出电流介于OCP点与Pk Load点时，可以用过电流保护参考电压(VrefCCL)和峰值负载参考电压(VrefCCH)两档来控制峰值负载检测，使决定恒流点的参考电压(VrefCC)在VrefCCL和VrefCCH之间来回切换；相应的，峰值负载检测模块20也可以控制原边控制芯片的控制模式在恒流环路控制模式(CC Mode)和恒压环路控制模式(CV Mode)之间来回切换，相较于现有技术中固定参考电压的峰值负载检测，可以避免输出的电压下跌过大的情况。
进一步的，本实施例中决定恒流点的参考电压(VrefCC)还可以包括过电流保护参考电压与峰值负载参考电压之间的预设参考电压，以通过增加VrefCC的档位来进一步改善原边控制芯片的控制模式切换过程中的纹波(ripple)，VrefCC的档位越多，ripple表现越好；例如过电流保护参考电压与峰值负载参考电压之间的预设参考电压的数量为2时，参考电压(VrefCC)可以包括峰值负载参考电压(VrefCCH)、过电流保护参考电压(VrefCCL)、中高参考电压(VrefCCMHigh)和中低参考电压(VrefCCMLow)这四个档位；其中，VrefCCH＞VrefCCMHigh＞VrefCCMLow＞VrefCCL；如图4所示，相邻两个档位之间的ΔVrefCC相同时，四个档位的VrefCC设置可以使VrefCC每次在相邻两档之间变化的ΔVrefCC只有原先两档VrefCC时的1/3，由此会改善ripple。
可以理解的是，本实施例中原边控制芯片的恒流模式信号可以为原边控制芯片采用的恒流环路控制模式的信号，如图8中的CCMode信号，即原边控制芯片的控制模式为恒流环路控制模式时，CCMode信号为高电平，原边控制芯片的控制模式为恒压环路控制模式时，CCMode信号为低电平； 原边控制芯片的恒压模式信号可以为原边控制芯片采用的恒压环路控制模式的信号，如原边控制芯片的控制模式为恒流环路控制模式时，恒压模式信号可以为低电平，原边控制芯片的控制模式为恒压环路控制模式时，恒压模式信号可以为高电平。
对应的，本实施例中的参考电压调整电路10可以根据恒流模式信号和/或恒压模式信号，生成参考电压控制信号，以控制峰值负载检测模块20调整的峰值负载检测的参考电压。
例如，峰值负载检测的参考电压包括峰值负载参考电压和过电流保护参考电压时，参考电压调整电路10可以具体用于根据恒流模式信号和/或恒压模式信号，在原边控制芯片处于恒流环路控制模式时，生成峰值负载参考电压对应的第一控制信号；在原边控制芯片处于恒压环路控制模式且参考电压为峰值负载参考电压时，生成过电流保护参考电压对应的第二控制信号；其中，参考电压控制信号包括第一控制信号和第二控制信号。如图3所示，过电流保护参考电压(VrefCCL)对应的恒流点是OCP点，峰值负载参考电压(VrefCCH)对应的恒流点是Pk Load点；1)当负载低于OCP点时，即在A点以下时，PSR设备的输出电流是在VrefCCL决定的OCP点以下，工作在CV段，即PSR设备控制模式为CV Mode(即恒压环路控制模式)。
2)当负载高于OCP点，低于Pk Load点时，即负载介于A点与B点之间时，以VrefCCL决定的带载能力带不动此负载，峰值负载检测模块20会将原边控制芯片的控制模式由CV Mode切换为CC Mode(即恒流环路控制模式)，此时参考电压调整电路10会控制峰值负载检测模块20将参考电压由VrefCCL切换到VrefCCH，即把PSR设备的带载能力从OCP点提高到Pk Load点；而切换到VrefCCH后，此时PSR设备可以带动A～B之间的负载，峰值负载检测模块20会将原边控制芯片的控制模式由CC Mode切换为CV Mode，此时参考电压调整电路10可以控制峰值负载检测模块20将参考电压由VrefCCH切换到VrefCCL，即把PSR系统的带载能力从Pk Load点降低到OCP点；这之后，就会重复上述过程，决定恒流点的参考电压(VrefCC)就在VrefCCH与VrefCCL之间来回切换。
3)当负载高于Pk Load点时，即负载介于B点与C点之间时，PSR设备 的带载能力切换到VrefCCH决定的Pk Load点，此时PSR设备是带不动负载的，VrefCC就会稳定在VrefCCH，原边控制芯片的控制模式会持续处于CC Mode。
4)当负载继续变化低于Pk Load点时，即负载介于C点与D点之间时，就会重复上述2)的过程。
5)当负载继续降低到低于OCP点时，即负载低于D点时，VrefCC就会稳定在VrefCCL，原边控制芯片的控制模式会持续处于CV Mode。
对应的，对于本实施例中参考电压调整电路10的具体电路结构，可以由设计人员根据实用场景和用户需求自行设置，如参考电压包括过电流保护参考电压和峰值负载参考电压时，参考电压调整电路10可以包括恒流调整电路，恒流调整电路可以用于根据恒流模式信号对应的恒流模式开始信号和恒流模式结束信号，在原边控制芯片进入恒流环路控制模式后，生成第一控制信号；在参考电压为峰值负载参考电压且原边控制芯片结束恒流环路控制模式后，生成第二控制信号。其中，恒流模式信号对应的恒流模式开始信号可以为恒流环路控制模式(CC Mode)开始时的脉冲信号，如图8中的CCMode_beginpulse信号；恒流模式信号对应的恒流模式结束信号可以为恒流环路控制模式结束时的脉冲信号，如图8中的CCMode_endpulse信号。对应的，参考电压调整电路10还可以包括信号转换电路，用于将原边控制芯片的恒流模式信号转换为恒流模式开始信号和恒流模式结束信号，使恒流调整电路可以根据信号转换电路输出的恒流模式开始信号和恒流模式结束信号，生成参考电压控制信号。
具体的，如图5所示，参考电压包括过电流保护参考电压和峰值负载参考电压时，上述恒流调整电路可以包括第一与门器件11(and2，即两输入端与门器件)、第一RS触发器12(两个nor2，即两个两输入端或非门器件组成的RS触发器)、D类型触发器13(DFF)和倒相放大器14；其中，第一与门器件11的第一输入端与恒流模式结束信号的输出端连接，第一与门器件11的第二输入端与D类型触发器13的Q输出端连接，第一与门器件11的输出端与第一RS触发器12的R输入端连接；第一RS触发器12的S输入端与恒流模式开始信号的输出端连接，第一RS触发器12的Q输出端与D类型触发 器13的D输入端连接；D类型触发器13的时钟输入端(clk)与原边控制芯片的驱动周期开通的开通脉冲信号(PFM)的输出端连接，D类型触发器13的Q输出端与倒相放大器14的输入端连接，倒相放大器14的输出端与峰值负载检测模块20的参考电压控制信号的输入端连接；其中，原边控制芯片的驱动周期开通的开通脉冲信号可以为原边控制芯片的驱动每周期的开通信号，D类型触发器13的复位输入端(reset)可以与相应的复位信号(Reset)的输出端连接。
对应的，第一与门器件11的第二输入端可以与D类型触发器13的Q输出端连接，使恒流调整电路可以用于根据输入的恒流模式开始信号和恒流模式结束信号，生成参考电压控制信号；第一与门器件11的第二输入端也可以与峰值负载参考电压的使用状态信号的输入端连接，以使恒流调整电路可以用于根据输入的恒流模式开始信号、恒流模式结束信号和峰值负载参考电压的使用状态信号，生成参考电压控制信号。本实施例对此不做任何限制。
相应的，本实施例并不限定第一RS触发器1212的具体电路结构，如图5所示，第一RS触发器12可以包括：第一或非门器件和第二或非门器件；其中，第一或非门器件的第一输入端与恒流模式开始信号的输出端连接，第一或非门器件的第二输入端与第二或非门器件的输出端连接，第一或非门器件的输出端与第二或非门器件的第一输入端连接；第二或非门器件的第二输入端与第一与门器件11的输出端连接，第二或非门器件的输出端与第一或非门器件的第二输入端连接的公共端作为第一RS触发器12的Q输出端与D类型触发器13的D输入端连接。
例如，峰值负载检测的参考电压包括峰值负载参考电压、过电流保护参考电压和过电流保护参考电压与峰值负载参考电压之间的中低参考电压和中高参考电压时，参考电压控制信号可以包括峰值负载参考电压对应的第一控制信号、过电流保护参考电压对应的第二控制信号、中高参考电压对应的第三控制信号和中低参考电压对应的第四控制信号；参考电压调整电路10可以具体用于根据恒流模式信号和/或恒压模式信号，在参考电压为过电流保护参考电压且原边控制芯片处于恒流环路控制模式时，生成第四 控制信号；在参考电压为中低参考电压且原边控制芯片处于恒压环路控制模式时，生成第二控制信号；在参考电压为中低参考电压且原边控制芯片处于恒流环路控制模式时，生成第三控制信号；在参考电压为中高参考电压且原边控制芯片处于恒压环路控制模式时，生成第四控制信号；在参考电压为中高参考电压且原边控制芯片处于恒流环路控制模式时，生成第一控制信号；在参考电压为峰值负载参考电压且原边控制芯片处于恒压环路控制模式时，生成第三控制信号。
如图4所示，过电流保护参考电压(VrefCCL)对应的恒流点是OCP点，峰值负载参考电压(VrefCCH)对应的恒流点是Pk Load点，中低参考电压(VrefCCMLow)对应的恒流点为B点，中高参考电压(VrefCCMHigh)对应的恒流点为C点；峰值负载检测的参考电压(VrefCC)可以在VrefCCL、VrefCCMLow、VrefCCMHigh和VrefCCH这四挡之间来回切换：1)VrefCCL→VrefCCMLow:在VrefCCL状态下，检测到CC Mode触发，VrefCC可以由VrefCCL切换为VrefCCMLow；2)VrefCCMLow→VrefCCL:在VrefCCMLow状态下，检测到CC Mode结束(即CV Mode触发)，表示VrefCCMLow状态下PSR设备可以带动当前负载，VrefCC由VrefCCMLow切换为VrefCCL；3)VrefCCMLow→VrefCCMHigh：在VrefCCMLow状态下，检测到CC Mode触发，表示VrefCCMLow不足以带动当前负载，VrefCC由VrefCCMLow切换为VrefCCMHigh；4)VrefCCMHigh→VrefCCMLow：在VrefCCMHigh状态下，检测到CC Mode结束，表示VrefCCMHigh可以带动当前负载，VrefCC可以由VrefCCMHigh切换为VrefCCMLow；5)VrefCCMHigh→VrefCCH:在VrefCCMHigh状态下，检测到CC Mode触发，表示VrefCCMHigh不足以带动当前负载，VrefCC可以由VrefCCMHigh切换为VrefCCH；6)VrefCCH→VrefCCMHigh：在VrefCCH状态下，检测到CC Mode结束，表示VrefCCH可以带动当前负载，VrefCC可以由VrefCCH切换为VrefCCMHigh；7)在VrefCCL状态下，检测到CV Mode结束，表示VrefCCL可以带动当前负载，VrefCC可以维持VrefCCL。
对应的，参考电压包括过电流保护参考电压、峰值负载参考电压、中低参考电压和中高参考电压时，参考电压调整电路10的具体电路结构，可 以采用与上述参考电压包括过电流保护参考电压和峰值负载参考电压这两个档位的参考电压调整电路10相似的方式进行设置，本实施例对此不做任何限制。
进一步的，本实施例所提供的峰值电流负载控制电路还可以包括：计时电路，用于对峰值负载持续时间和/或过电流保护持续时间进行计时，并在峰值负载持续时间达到第一阈值时输出峰值负载保护重启控制信号和/或在过电流保护持续时间达到第二阈值时输出过电流保护重启控制信号，以重启充电器系统；其中，峰值负载持续时间可以为负载所需电流大于或等于峰值负载参考电压对应的恒流点(如Pk Load点)的持续时间，过电流保护持续时间可以为负载所需电流大于或等于过电流保护参考电压对应的恒流点(如OCP点)的持续时间。
对应的，计时电路可以具体用于对峰值负载持续时间和过电流保护持续时间进行计时，并在峰值负载持续时间达到第一阈值时输出峰值负载保护重启控制信号，以使PSR设备触发peakload保护重启；在过电流保护持续时间达到第二阈值时输出过电流保护重启控制信号，以使PSR设备触发OCP保护重启。
例如，参考电压控制信号包括峰值负载参考电压对应的第一控制信号和过电流保护参考电压对应的第二控制信号时，计时电路可以具体用于根据原边控制芯片的恒流模式信号，对峰值负载持续时间和过电流保护持续时间进行计时，并在峰值负载持续时间达到第一阈值时输出峰值负载保护重启控制信号，在过电流保护持续时间达到第二阈值时输出过电流保护重启控制信号；其中，峰值负载参考电压为参考电压为峰值负载参考电压且原边控制芯片处于恒流环路控制模式的维持时间，过电流保护持续时间为参考电压为过电流保护参考电压且原边控制芯片处于恒流环路控制模式或参考电压为峰值负载参考电压的维持时间；如图3所示，计时电路可以在A点开始过电流保护持续时间的计时(即OCP计时)，在D点结束过电流保护持续时间的计时，在过电流保护持续时间大于或等于第二阈值(如1.5s)时触发PSR设备的OCP保护重启，在过电流保护持续时间小于第二阈值时PSR设备继续工作；计时电路可以在B点开始峰值负载持续时间的计时(即 PK Load计时)，在C点结束峰值负载持续时间的计时，在峰值负载持续时间大于或等于第一阈值(如150ms)时触发PSR设备的peakload保护重启，在峰值负载持续时间小于第一阈值时PSR设备继续工作；也就是说，如图3左边的输出电流(Output Current)展示，PSR设备的输出电流超过OCP点开始OCP计时，中间出现达到PK Load点开始另外的PK Load计时，但PK Load计时的持续时间未达到150ms不会触发peakload保护重启，此时OCP计时还在继续，并在达到1.5s后触发OCP保护；如图3右边的输出电流展示，PSR设备的输出电流超过OCP点开始OCP计时，中间出现达到PK Load点开始另外的PK Load计时，PK Load计时的持续时间达到150ms触发peakload保护重启，此时OCP计时同时被结束而小于1.5s。
例如，参考电压控制信号包括峰值负载参考电压对应的第一控制信号、过电流保护参考电压对应的第二控制信号、中高参考电压对应的第三控制信号和中低参考电压对应的第四控制信号时，计时电路可以具体用于根据原边控制芯片的恒流模式信号，对峰值负载持续时间和过电流保护持续时间进行计时，并在峰值负载持续时间达到第一阈值时输出峰值负载保护重启控制信号，在过电流保护持续时间达到第二阈值时输出过电流保护重启控制信号；峰值负载参考电压为参考电压为峰值负载参考电压且原边控制芯片处于恒流环路控制模式的维持时间，过电流保护持续时间为参考电压为过电流保护参考电压且原边控制芯片处于恒流环路控制模式或参考电压为中低参考电压、中高参考电压或峰值负载参考电压的维持时间；如图4所示，计时电路可以在A点开始过电流保护持续时间的计时(即OCP计时)，在F点结束过电流保护持续时间的计时，在过电流保护持续时间大于或等于第二阈值(如1.5s)时触发PSR设备的OCP保护重启，在过电流保护持续时间小于第二阈值时PSR设备继续工作；计时电路可以在D点开始峰值负载持续时间的计时(即PK Load计时)，在E点结束峰值负载持续时间的计时，在峰值负载持续时间大于或等于第一阈值(如150ms)时触发PSR设备的peakload保护重启，在峰值负载持续时间小于第一阈值时PSR设备继续工作。
也就是说，如图4，在A点，负载超过OCP点，VrefCCL→VrefCCMLow， Tocp(即过电流保护持续时间)计时开始；在A～B区间，VrefCC在VrefCCL与VrefCCMLow之间来回切换检测负载；在B～C区间，VrefCC在VrefCCMLow与VrefCCMHigh之间来回切换检测负载；在C～D区间，VrefCC先在VrefCCMHigh与VrefCCH，接着在VrefCCMLow与VrefCCMHigh，最后在VrefCCMHigh与VrefCCH之间来回切换检测负载；在D～E区间，Tpeakload(即峰值负载持续时间)在此区间内进行计时；在E～F区间，VrefCC先是在VrefCCH与VrefCCMHigh之间来回切换，低于VrefCCMHigh对应的恒流点后，转为VrefCCMHigh与VrefCCMLow之间切换，再低于VrefCCMLow对应的恒流点后，转为VrefCCMLow与VrefCCL之间切换，负载低于OCP点后，VrefCC稳定在VrefCCL，且退出Tocp计时。
对应的，对于上述计时电路的具体电路结构，可以由设计人员根据实用场景和用户需求自行设置，如计时电路可以包括峰值负载计时电路和过电流保护计时电路；其中，峰值负载计时电路可以用于对峰值负载持续时间进行计时，并在峰值负载持续时间达到第一阈值时输出峰值负载保护重启控制信号；过电流保护计时电路可以用于对过电流保护持续时间进行计时，并在过电流保护持续时间达到第二阈值时输出过电流保护重启控制信号。
具体的，参考电压控制信号包括峰值负载参考电压对应的第一控制信号和过电流保护参考电压对应的第二控制信号时，如图6所示，过电流保护计时电路可以包括第二与门器件21(and2)、第二RS触发器22(两个nor2)和第一计时器23(Time Counter1)；第二与门器件21的第一输入端与参考电压调整电路10的参考电压控制信号的输出端(如图5中倒相放大器14的输出端)连接，第二与门器件21的第二输入端与恒流模式信号对应的恒流模式结束延迟信号(CV_EN_12Pulse)的输出端连接，第二与门器件21的输出端与第二RS触发器22的R输入端连接；第二RS触发器22的S输入端与恒流模式信号对应的恒流模式开始信号的输出端连接，第二RS触发器22的Q输出端与第一计时器23的使能端连接；第一计时器23的输出端作为过电流保护计时电路的输出端，用于在接收的使能信号的持续时间达到第二阈值时输出峰值负载保护重启控制信号(Tocp_pro)；延迟开通信号为恒流模式控 制模式结束后连续预设数量个周期的开通脉冲信号后的脉冲信号，如图8中的CV_EN_12pulse，即CCMode结束后连续计数12个开通脉冲信号(即CV模式开关脉冲信号，如图5中的PFM信号)后的脉冲信号。
具体的，参考电压控制信号包括峰值负载参考电压对应的第一控制信号和过电流保护参考电压对应的第二控制信号时，如图7所示，峰值负载计时电路可以包括第三与门器件31(and2)和第二计时器32(Time Counter2)；第三与门器件31的第一输入端与恒流模式信号的输出端连接，第三与门器件31的第二输入端与参考电压控制信号对应的倒相信号的输出端(如图5中倒相放大器14的输入端)连接，第三与门器件31的输出端与第二计时器32的使能端连接；第二计时器32的输出端作为峰值负载计时电路的输出端，用于在接收的使能信号的持续时间达到第一阈值时输出峰值负载保护重启控制信号(Tpeakload_pro)。
本实施例中，本发明实施例通过参考电压调整电路10的设置，根据原边控制芯片的恒流模式信号和/或恒压模式信号，控制调整原边控制芯片的峰值负载检测的参考电压，以控制原边控制芯片的恒流环路控制模式和恒压环路控制模式的切换，从而避免瞬间高输出功率场合中，原边反馈充电器的输出电压明显下降所导致的负载断电重启，提升原边反馈充电器在检测到峰值电流负载时的输出电压的稳定性。
说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
以上对本发明所提供的一种峰值电流负载控制电路进行了详细介绍。本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本发明进行若干改进和修饰，这些改进和修饰也落入本发明权利要求的保护范围内。

Claims (10)

  1. 一种峰值电流负载控制电路，其特征在于，包括：
    参考电压调整电路，用于根据原边控制芯片的恒流模式信号和/或恒压模式信号，生成参考电压控制信号；
    峰值负载检测模块，用于根据所述参考电压控制信号，调整峰值负载检测的参考电压；并根据所述参考电压，对所述原边控制芯片进行峰值负载检测，调整所述原边控制芯片的控制模式；其中，所述控制模式包括恒流环路控制模式和恒压环路控制模式，所述参考电压包括过电流保护参考电压和峰值负载参考电压，峰值负载参考电压为所述过电流保护参考电压的k倍，k大于1。
  2. 根据权利要求1所述的峰值电流负载控制电路，其特征在于，所述参考电压调整电路具体用于根据所述恒流模式信号和/或所述恒压模式信号，在所述原边控制芯片处于所述恒流环路控制模式时，生成所述峰值负载参考电压对应的第一控制信号；在所述原边控制芯片处于所述恒压环路控制模式且所述参考电压为所述峰值负载参考电压时，生成所述过电流保护参考电压对应的第二控制信号；其中，所述参考电压控制信号包括所述第一控制信号和所述第二控制信号。
  3. 根据权利要求2所述的峰值电流负载控制电路，其特征在于，所述参考电压调整电路，包括：
    恒流调整电路，用于根据所述恒流模式信号对应的恒流模式开始信号和恒流模式结束信号，在所述原边控制芯片进入所述恒流环路控制模式后，生成所述第一控制信号；在所述参考电压为所述峰值负载参考电压且所述原边控制芯片结束所述恒流环路控制模式后，生成所述第二控制信号。
  4. 根据权利要求3所述的峰值电流负载控制电路，其特征在于，所述恒流调整电路，包括：第一与门器件、第一RS触发器、D类型触发器和倒相放大器；
    其中，所述第一与门器件的第一输入端与所述恒流模式结束信号的输出端连接，所述第一与门器件的第二输入端与所述D类型触发器的Q输出端连接，所述第一与门器件的输出端与所述第一RS触发器的R输入端连 接；所述第一RS触发器的S输入端与所述恒流模式开始信号的输出端连接，所述第一RS触发器的Q输出端与所述D类型触发器的D输入端连接；所述D类型触发器的时钟输入端与所述原边控制芯片的驱动周期开通的开通脉冲信号的输出端连接，所述D类型触发器的Q输出端与所述倒相放大器的输入端连接，所述倒相放大器的输出端与所述峰值负载检测模块的所述参考电压控制信号的输入端连接。
  5. 根据权利要求4所述的峰值电流负载控制电路，其特征在于，所述第一RS触发器，包括：第一或非门器件和第二或非门器件；
    其中，所述第一或非门器件的第一输入端与所述恒流模式开始信号的输出端连接，所述第一或非门器件的第二输入端与所述第二或非门器件的输出端连接，所述第一或非门器件的输出端与所述第二或非门器件的第一输入端连接；所述第二或非门器件的第二输入端与所述第一与门器件的输出端连接，所述第二或非门器件的输出端与所述第一或非门器件的第二输入端连接的公共端作为所述第一RS触发器的Q输出端与所述D类型触发器的D输入端连接。
  6. 根据权利要求1所述的峰值电流负载控制电路，其特征在于，所述参考电压控制信号包括所述峰值负载参考电压对应的第一控制信号、所述过电流保护参考电压对应的第二控制信号、中高参考电压对应的第三控制信号和中低参考电压对应的第四控制信号；其中，所述峰值负载参考电压大于所述中高参考电压大于所述中低参考电压大于过电流保护参考电压；
    对应的，所述参考电压调整电路具体用于根据所述恒流模式信号和/或所述恒压模式信号，在所述参考电压为所述过电流保护参考电压且所述原边控制芯片处于所述恒流环路控制模式时，生成所述第四控制信号；在所述参考电压为所述中低参考电压且所述原边控制芯片处于所述恒压环路控制模式时，生成所述第二控制信号；在所述参考电压为所述中低参考电压且所述原边控制芯片处于所述恒流环路控制模式时，生成所述第三控制信号；在所述参考电压为所述中高参考电压且所述原边控制芯片处于所述恒压环路控制模式时，生成所述第四控制信号；在所述参考电压为所述中高参考电压且所述原边控制芯片处于所述恒流环路控制模式时，生成所述 第一控制信号；在所述参考电压为所述峰值负载参考电压且所述原边控制芯片处于所述恒压环路控制模式时，生成所述第三控制信号。
  7. 根据权利要求1至6任一项所述的峰值电流负载控制电路，其特征在于，还包括：
    计时电路，用于对所述峰值负载持续时间和/或过电流保护持续时间进行计时，并在所述峰值负载持续时间达到第一阈值时输出峰值负载保护重启控制信号和/或在所述过电流保护持续时间达到第二阈值时输出过电流保护重启控制信号。
  8. 根据权利要求7所述的峰值电流负载控制电路，其特征在于，所述参考电压控制信号包括所述峰值负载参考电压对应的第一控制信号和所述过电流保护参考电压对应的第二控制信号，所述计时电路具体用于根据所述原边控制芯片的恒流模式信号，对所述峰值负载持续时间和所述过电流保护持续时间进行计时，并在所述峰值负载持续时间达到所述第一阈值时输出所述峰值负载保护重启控制信号，在所述过电流保护持续时间达到所述第二阈值时输出所述过电流保护重启控制信号；其中，所述峰值负载参考电压为所述参考电压为所述峰值负载参考电压且所述原边控制芯片处于所述恒流环路控制模式的维持时间，所述过电流保护持续时间为所述参考电压为所述过电流保护参考电压且所述原边控制芯片处于所述恒流环路控制模式或所述参考电压为所述峰值负载参考电压的维持时间。
  9. 根据权利要求8所述的峰值电流负载控制电路，其特征在于，所述计时电路，包括：峰值负载计时电路和过电流保护计时电路；其中，
    所述过电流保护计时电路包括第二与门器件、第二RS触发器和第一计时器；所述第二与门器件的第一输入端与所述参考电压调整电路的所述参考电压控制信号的输出端连接，所述第二与门器件的第二输入端与所述恒流模式信号对应的恒流模式结束延迟信号的输出端连接，所述第二与门器件的输出端与所述第二RS触发器的R输入端连接；所述第二RS触发器的S输入端与所述恒流模式信号对应的恒流模式开始信号的输出端连接，所述第二RS触发器的Q输出端与所述第一计时器的使能端连接；所述第一计时器的输出端作为所述过电流保护计时电路的输出端，用于在接 收的使能信号的持续时间达到所述第二阈值时输出所述过电流保护重启控制信号；所述延迟开通信号为所述恒流模式控制模式结束后连续预设数量个周期的开通脉冲信号后的脉冲信号；
    所述峰值负载计时电路包括第三与门器件和第二计时器；所述第三与门器件的第一输入端与所述恒流模式信号的输出端连接，所述第三与门器件的第二输入端与所述参考电压控制信号对应的倒相信号的输出端连接，所述第三与门器件的输出端与所述第二计时器的使能端连接；所述第二计时器的输出端作为所述峰值负载计时电路的输出端，用于在接收的使能信号的持续时间达到所述第一阈值时输出所述峰值负载保护重启控制信号。
  10. 根据权利要求7所述的峰值电流负载控制电路，其特征在于，所述参考电压控制信号包括所述峰值负载参考电压对应的第一控制信号、所述过电流保护参考电压对应的第二控制信号、中高参考电压对应的第三控制信号和中低参考电压对应的第四控制信号；其中，所述峰值负载参考电压大于所述中高参考电压大于所述中低参考电压大于过电流保护参考电压；
    对应的，所述计时电路具体用于根据所述原边控制芯片的恒流模式信号，对所述峰值负载持续时间和所述过电流保护持续时间进行计时，并在所述峰值负载持续时间达到所述第一阈值时输出所述峰值负载保护重启控制信号，在所述过电流保护持续时间达到所述第二阈值时输出所述过电流保护重启控制信号；所述峰值负载参考电压为所述参考电压为所述峰值负载参考电压且所述原边控制芯片处于所述恒流环路控制模式的维持时间，所述过电流保护持续时间为所述参考电压为所述过电流保护参考电压且所述原边控制芯片处于所述恒流环路控制模式或所述参考电压为所述中低参考电压、所述中高参考电压或所述峰值负载参考电压的维持时间。
PCT/CN2022/115674 2022-03-31 2022-08-30 一种峰值电流负载控制电路 WO2023184845A1 (zh)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005033906A (ja) * 2003-07-11 2005-02-03 Toko Inc スイッチング定電流電源装置
US20080259656A1 (en) * 2007-04-23 2008-10-23 Active-Semi International, Inc. Regulating output current from a primary side power converter by clamping an error signal
CN202121839U (zh) * 2011-06-20 2012-01-18 上海新进半导体制造有限公司 一种开关电源的重新装载判断电路
US20170201181A1 (en) * 2016-01-13 2017-07-13 Fuji Electric Co., Ltd. Switching power supply apparatus
CN109696938A (zh) * 2017-10-21 2019-04-30 国神光电科技（上海）有限公司 一种用于电流源控制的电子装置和控制方法
CN112087061A (zh) * 2020-09-02 2020-12-15 东南大学 一种可自动恒流-恒压切换的三线圈电池无线充电系统
CN114070105A (zh) * 2020-08-05 2022-02-18 深圳市芯茂微电子有限公司 正激恒流控制装置、开关电源、控制方法及芯片
CN114756075A (zh) * 2022-03-31 2022-07-15 上海新进芯微电子有限公司 一种峰值电流负载控制电路

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005033906A (ja) * 2003-07-11 2005-02-03 Toko Inc スイッチング定電流電源装置
US20080259656A1 (en) * 2007-04-23 2008-10-23 Active-Semi International, Inc. Regulating output current from a primary side power converter by clamping an error signal
CN202121839U (zh) * 2011-06-20 2012-01-18 上海新进半导体制造有限公司 一种开关电源的重新装载判断电路
US20170201181A1 (en) * 2016-01-13 2017-07-13 Fuji Electric Co., Ltd. Switching power supply apparatus
CN109696938A (zh) * 2017-10-21 2019-04-30 国神光电科技（上海）有限公司 一种用于电流源控制的电子装置和控制方法
CN114070105A (zh) * 2020-08-05 2022-02-18 深圳市芯茂微电子有限公司 正激恒流控制装置、开关电源、控制方法及芯片
CN112087061A (zh) * 2020-09-02 2020-12-15 东南大学 一种可自动恒流-恒压切换的三线圈电池无线充电系统
CN114756075A (zh) * 2022-03-31 2022-07-15 上海新进芯微电子有限公司 一种峰值电流负载控制电路

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