WO2021226978A1 - 电源管理电路、芯片和设备 - Google Patents

电源管理电路、芯片和设备 Download PDF

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Publication number
WO2021226978A1
WO2021226978A1 PCT/CN2020/090398 CN2020090398W WO2021226978A1 WO 2021226978 A1 WO2021226978 A1 WO 2021226978A1 CN 2020090398 W CN2020090398 W CN 2020090398W WO 2021226978 A1 WO2021226978 A1 WO 2021226978A1
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Prior art keywords
circuit
output
output terminal
control circuit
control
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PCT/CN2020/090398
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English (en)
French (fr)
Inventor
黄龙
张均军
王程左
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2020/090398 priority Critical patent/WO2021226978A1/zh
Priority to CN202080001573.XA priority patent/CN111837326B/zh
Publication of WO2021226978A1 publication Critical patent/WO2021226978A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This application relates to the technical field of power circuits, and in particular to a power management circuit, chip and device.
  • the existing single-inductor multi-output circuit DC-DC circuit takes the single-inductor dual-output (Single Inductor Dual Output, referred to as SIDO) step-down converter circuit (BUCK) as an example.
  • Conduction Mode (DCM) SIDO BUCK and Continuous Conduction Mode (Continuous Conduction Mode, CCM) SIDO BUCK are suitable for a wider load range, and its structure is more complicated, and cross-effects of the output need to be considered.
  • the SIDO BUCK in DCM mode is more widely used because of its simple structure and no output cross-effect.
  • SIDO BUCK in DCM mode a fixed on-time control mode is usually adopted, that is, the on-time of the power tube is fixed in each cycle, which makes the SIDO inductor current peak value passively determined by the real-time input and output voltage.
  • the peak value of the inductor current directly determines the size of the output ripple of the SIDO BUCK and affects the work efficiency to a certain extent.
  • the present application provides a power management circuit, chip, and device to achieve adjustable peak current, thereby improving work efficiency.
  • this application provides a power management circuit, including:
  • a power stage circuit connected to a power source, the power stage circuit including at least one output terminal for outputting voltage;
  • the current control circuit is connected to the power supply, the logic control circuit, and the at least one output terminal, and the current control circuit is configured to receive each output voltage output from the at least one output terminal, according to the output voltage and the output terminal.
  • the first control signal output by the logic control circuit detects the current of the power stage circuit, and outputs a second control signal to the logic control circuit after the current reaches a preset peak value;
  • the logic control circuit is connected to the at least one output terminal, and the logic control circuit is configured to output the first control signal to the current control circuit according to the respective output voltages, and the first control signal is used for the
  • the current control circuit starts the detection of the current of the power stage circuit, and the logic control circuit outputs a third control signal to the power stage circuit according to the second control signal to control the current peak value of the power stage circuit to Preset peak value.
  • the current peak value of the power stage circuit is controlled, so that the output ripple and efficiency of the power stage circuit can be better balanced by the current peak value control, and the current peak value is controlled to the preset value.
  • the peak value can reduce the output ripple and improve the working efficiency of the circuit.
  • the first control signal is also used to control the current control circuit to turn off detection of the current of the power stage circuit to reduce power consumption.
  • the current control circuit is also used to adjust the preset peak value.
  • the current control circuit includes:
  • the output terminal of the peak current control circuit is used to output the second control signal to the logic control circuit
  • the output terminal of the current zero-crossing detection circuit is used to output a fourth control signal to the logic control circuit
  • the logic control circuit outputs a fifth control signal to the power stage circuit according to the fourth control signal, so as to control the output of the power stage circuit
  • the input terminals of the peak current control circuit are respectively connected to the power supply, the first output terminal and the second output terminal of the logic control circuit, and the input terminals of the current zero-crossing detection circuit are respectively connected to the power stage circuit and the power stage circuit.
  • the first output terminal of the logic control circuit wherein the first output terminal is used to output the first control signal, and the second output terminal is used to output the third control signal to the peak current control circuit
  • the peak current control circuit outputs the second control signal according to the third control signal
  • the power stage circuit controls the current peak value to a preset peak value according to the third control signal .
  • the power management circuit does not need to contain a clock module, and a logic control circuit is used to increase the reliability of clockless control, and most of the modules in the current control circuit and the logic control circuit are in a standby state when the circuit meets certain conditions. Low consumption.
  • the peak current control circuit includes:
  • a clamp circuit a current mirror circuit, a first resistor, a first capacitor, a selection circuit and a first sub-control circuit
  • the first end of the first resistor is connected to the power source, and the second end of the first resistor is connected to the clamp circuit;
  • the clamping circuit is connected to the selection circuit and the current mirror circuit, and receives the first control signal output from the first output terminal of the logic control circuit;
  • the selection circuit is connected to at least one output terminal of the power stage circuit, and receives the sixth control signal output by the third output terminal of the logic control circuit;
  • the current mirror circuit is also connected to the power supply, the first end of the first capacitor, and the first sub-control circuit;
  • Both ends of the first capacitor are respectively connected to the first sub-control circuit, and the first sub-control circuit receives the third control signal output by the second output terminal of the logic control circuit, and the first The output terminal of the sub-control circuit is used as the output terminal of the peak current control circuit;
  • the clamping circuit is configured to clamp the voltage at the second end of the first resistor so that the voltage at the second end of the first resistor is equal to the output voltage of the selection circuit;
  • the mirror current circuit is used to mirror the current of the first resistor
  • the selection circuit is configured to select the output voltage of the power stage circuit according to the sixth control signal output by the third output terminal of the logic control circuit;
  • the first sub-control circuit is configured to control the output terminal of the peak current control circuit to output the second control signal according to the third control signal output from the second output terminal of the logic control circuit.
  • the peak current control circuit further includes: a second sub-control circuit
  • the second sub-control circuit is respectively connected to the first output terminal of the logic control circuit, the current mirror circuit, the second terminal of the first capacitor, and the first sub-control circuit;
  • the second sub-control circuit is used to control the on or off of the peak current control circuit according to the first control signal output from the first output terminal of the logic control circuit.
  • the clamping circuit includes:
  • the first input terminal of the operational amplifier is connected to the second terminal of the first resistor
  • the second input terminal of the operational amplifier is connected to the selection circuit
  • the third input terminal of the operational amplifier is connected to the logic
  • the first output terminal of the control circuit the output terminal of the operational amplifier is connected to the first terminal of the first power tube
  • the second terminal of the first power tube is connected to the second terminal of the first resistor
  • the The third end of the first power tube is connected to the mirror current circuit.
  • the selection circuit includes:
  • a first inverter at least one transmission gate
  • the input terminal of the first inverter is connected to the third output terminal of the logic control circuit
  • the output terminal of the first inverter is respectively connected to the first control terminal of each transmission gate; the second control terminal of each transmission gate is respectively connected to the third output terminal of the logic control circuit;
  • the input terminals of the gates are respectively connected to the output terminals of the power stage circuit, and the output terminal of each transmission gate is used as the output terminal of the selection circuit; the number of transmission gates and the number of output terminals of the power stage circuit same.
  • the current mirror circuit includes:
  • the second power tube, the third power tube, the fourth power tube, and the fifth power tube are connected to the second power tube, the third power tube, the fourth power tube, and the fifth power tube;
  • the first end of the second power tube is connected to the first end of the third power tube, the first end and the second end of the second power tube are short-circuited, and the first end of the second power tube is short-circuited.
  • the two ends are connected to the clamping circuit, and the third end of the second power tube is grounded;
  • the second end of the third power tube is connected to the second end of the fourth power tube, and the third end of the third power tube is grounded;
  • the second end of the fourth power tube is shorted to the first end, the first end of the fourth power tube is also connected to the first end of the fifth power tube, and the third end of the fourth power tube is connected to The power supply;
  • the second end of the fifth power tube is connected to the first capacitor; the third end of the fifth power tube is connected to the power supply.
  • the first sub-control circuit includes: a first logic unit, a sixth power tube, and a first comparator;
  • the first input terminal of the first logic unit is connected to the second output terminal of the logic control circuit
  • the second input terminal of the first logic unit is connected to the output terminal of the first comparator
  • the second input terminal of the first logic unit is connected to the output terminal of the first comparator.
  • the output terminal of a logic unit is connected to the first terminal of the sixth power tube; the output terminal of the first logic unit serves as the output terminal of the peak current control circuit;
  • the second end and the third end of the sixth power tube are respectively connected to both ends of the first capacitor, and the second end of the sixth power tube is grounded;
  • the first input terminal of the first comparator is connected to the mirror current circuit, and the second input terminal of the first comparator is connected to a first reference voltage.
  • the second sub-control circuit includes: a seventh power tube, the first terminal of the seventh power tube receives the first control signal output by the first output terminal of the logic control circuit, and the second The second end of the seventh power tube is connected to the mirror current circuit, and the third end of the seventh power tube is grounded.
  • the first logic unit includes:
  • the first D flip-flop, the second D flip-flop and the first AND gate are The first D flip-flop, the second D flip-flop and the first AND gate
  • the first terminal of the first D flip-flop serves as the second input terminal of the first logic unit
  • the second terminal of the first D flip-flop is connected to a power source
  • the third terminal of the first D flip-flop is Terminal is connected to the output terminal of the first AND gate
  • the output terminal of the first D flip-flop is connected to the first input terminal of the first AND gate and serves as the output terminal of the first logic unit
  • the first end of the second D flip-flop is used as the first input end of the first logic unit, the second end of the second D flip-flop is connected to a power source, and the third end of the second D flip-flop is connected to The output terminal of the second D flip-flop, and the output terminal of the second D flip-flop is connected to the second input terminal of the first AND gate.
  • the resistance of the first resistor is variable or the capacitance of the first capacitor is variable.
  • the first reference voltage is variable.
  • the logic control circuit includes:
  • a third sub-control circuit and at least one second comparator; the number of the second comparators is the same as the number of output terminals of the power stage circuit;
  • each second comparator is connected to each output terminal of the power stage circuit; the second input terminal of each second comparator is respectively input with a second reference voltage;
  • the first output terminal of the third sub-control circuit is used to output the first control signal to the current control circuit according to the signal output by the output terminal of each of the second comparators.
  • the second output terminal is used to output the third control signal to the current control circuit and the power stage circuit according to the signal output from the output terminal of each of the second comparators, and the fourth control signal of the third sub-control circuit
  • the output terminal is used to output the fifth control signal to the power stage circuit.
  • the power management circuit does not need to contain a clock module, and a logic control circuit is used to increase the reliability of clockless control, and a current zero-crossing detection circuit is used to detect the current.
  • a flip signal is output as the power supply Before the next second comparator inversion signal, the power management circuit is in a standby state, and only the second comparator is in the working state, and the power consumption is greatly reduced.
  • the third sub-control circuit includes:
  • a second logic unit a third logic unit, a logic control unit, a first delay unit, and a first output control unit;
  • the first input terminal of the second logic unit is connected to the output terminal of the first delay unit, and the second input terminal of the second logic unit and the input terminal of the first delay unit respectively receive The fourth control signal output by the output terminal of the current zero-crossing detection circuit;
  • the output terminal of the second logic unit is connected to the input terminal of the first output control unit, and the output terminal of the first output control unit serves as the first output terminal of the third sub-control circuit;
  • the first input terminal of the third logic unit is connected to the output terminal of the peak current control circuit, the second input terminal of the third logic unit is connected to the output terminal of the first output control unit, and the third logic unit is The output terminal of the unit serves as the second output terminal of the third sub-control circuit;
  • the first input terminal of the logic control unit receives the fourth control signal output from the output terminal of the current zero-crossing detection circuit, and the second input terminal of the logic control unit is connected to the output of the first output control unit
  • the second input terminal of the logic control unit is connected to the output terminal of each of the second comparators, and the output terminal of the logic control unit serves as the fourth output terminal of the third sub-control circuit.
  • the first output terminal LOOP_EN of the logic control circuit is clamped within the time T1 after the rising edge of the output terminal ZCD_OUT of the current zero-crossing detection circuit arrives.
  • the power management circuit will be forced to enter the standby state for a period of time to prevent the power management circuit from continuously working under heavy load without clock control from generating logic errors and improve the reliability of the control logic sex.
  • the third sub-control circuit further includes: a second delay unit;
  • the input terminal of the second delay unit is connected to the output terminal of the first output control unit, and the output terminal of the second delay unit is respectively connected to the third logic unit and the first output terminal of the logic control unit. Two input terminals.
  • the delay generated by the second delay unit is to give the peak current control circuit enough startup time to ensure the accuracy of the peak current control.
  • the first output control unit includes:
  • the input terminal of the second inverter is connected to the output terminal of the second logic unit, the output terminal of the second inverter is connected to the first input terminal of the second AND gate, and the first 2.
  • the second input terminal of the AND gate is connected to the output terminal of the OR gate;
  • the input terminals of the OR gate are respectively connected to the output terminals of each of the second comparators, and the output terminal of the second AND gate is used as the output terminal of the first output control unit.
  • the power stage circuit includes: an input control unit, an inductor, and at least one second output control unit;
  • the input control unit is respectively connected to the power supply and the first end of the inductor, and the input control unit is further configured to receive a third control signal output by the second output end of the logic control circuit, the The second end of the inductor is respectively connected to each of the second output control units; each of the second output control units is also used to receive the fifth control signal output by the fourth output end of the logic control circuit.
  • it also includes:
  • the second output terminal of the logic control circuit is connected to the power stage circuit through the first drive circuit
  • the fourth output terminal of the logic control circuit is connected to the power stage circuit through the second drive circuit.
  • the input control unit includes:
  • the eighth power tube and the ninth power tube are connected to The eighth power tube and the ninth power tube;
  • the first end of the eighth power tube is connected to the first drive circuit
  • the second end of the eighth power tube is connected to the power source
  • the third end of the eighth power tube is connected to the inductor First end
  • the first end of the ninth power tube is connected to the first drive circuit, the second end of the ninth power tube is connected to the first end of the inductor, and the third end of the ninth power tube is grounded.
  • the second output control unit includes:
  • the first end of the tenth power tube is connected to the second drive circuit
  • the second end of the tenth power tube is connected to the second end of the inductor
  • the third end of the tenth power tube is connected to The first end of the second capacitor, the second capacitor and the second end of the load are grounded, and the first end of the second capacitor is also connected to the first end of the load.
  • the present application provides a power management chip, which includes the power management circuit as described in the first aspect or an optional manner of the first aspect.
  • this application provides an electronic device, including:
  • the power management chip according to any one of the second aspect.
  • the power management circuit includes: a current control circuit, a logic control circuit, and a power stage circuit; Control, so that the output ripple and efficiency of the power stage circuit can be better balanced by the control of the current peak value.
  • Control By controlling the current peak value to the preset peak value, the output ripple can be reduced and the working efficiency of the circuit can be improved.
  • FIG. 1 is a schematic structural diagram of a power management circuit provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a power management circuit provided by another embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a power management circuit provided by another embodiment of this application.
  • FIG. 4 is a schematic structural diagram of a power management circuit provided by another embodiment of this application.
  • FIG. 5 is a schematic structural diagram of a power management circuit provided by another embodiment of this application.
  • FIG. 6 is a schematic structural diagram of a power management circuit provided by another embodiment of this application.
  • FIG. 7 is a schematic structural diagram of a power management circuit provided by another embodiment of this application.
  • FIG. 8 is a schematic structural diagram of a peak current control circuit provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a peak current control circuit provided by another embodiment of the application.
  • FIG. 10 is a schematic structural diagram of a peak current control circuit provided by another embodiment of this application.
  • FIG. 11 is a working waveform diagram of the peak current control circuit provided by any embodiment in FIGS. 8-10;
  • FIG. 12 is a schematic structural diagram of a logic unit provided by an embodiment of this application.
  • FIG. 13 is a working waveform diagram of a logic unit provided by an embodiment of this application.
  • FIG. 14 is a schematic structural diagram of a logic control circuit provided by an embodiment of this application.
  • 15 is a schematic structural diagram of a logic control circuit provided by another embodiment of the application.
  • FIG. 16 is a working waveform diagram of a logic control circuit provided by an embodiment of the application.
  • SIDO circuit In the related art SIDO circuit, a fixed on-time control mode is usually adopted, that is, the on-time of the power tube is fixed in each cycle, which makes the SIDO inductor current peak value passively determined by the real-time input and output voltage.
  • the peak current of the inductor current directly determines the size of the SIDO's output ripple and affects the work efficiency to a certain extent.
  • SIDO saves the number of inductors but increases the number of power tubes, its operating efficiency is generally lower than the traditional single-inductor single-output DC-DC architecture.
  • this application provides a power management circuit, chip and device.
  • the current control circuit is used to effectively control the current of the power stage circuit, and the logic control circuit is introduced to control whether the power management circuit enters the standby mode to reduce power consumption, and the two delay time introduced in the logic control circuit assist Without clock control, the reliability of the circuit without clock is higher.
  • the power management circuit can be applied to the power management chip of electronic equipment, where the electronic equipment includes terminal devices such as mobile phones, tablet computers, wearable devices, notebook computers, etc.
  • the power management circuit can be used to provide different loads in the electronic equipment ( For example, MCU, audio IC, I/O, etc.) power supply, which can save the volume of components outside the power management chip.
  • the current of the power stage circuit in the embodiments of the present application refers to the current of the inductor included in the power stage circuit
  • the current peak value of the power stage circuit refers to the current peak value of the inductor included in the power stage circuit.
  • the power management circuit has two output terminals outputting different voltages as an example for description in conjunction with the figure.
  • Fig. 1 is a schematic structural diagram of a power management circuit provided by an embodiment of the application. As shown in Fig. 1, the power management circuit includes:
  • the power stage circuit is connected to the power supply V IN ;
  • the power stage circuit includes at least one output terminal (two output terminals V OUT1 and V OUT2 are taken as an example in Fig. 1), and each output terminal is used for outputting voltage.
  • the output terminal is used, the output voltage is used to supply power to different circuit modules;
  • the current control circuit is connected to the power supply V IN , the logic control circuit, and at least one output terminal, and receives each output voltage output from the power stage circuit.
  • the current control circuit is used for each output voltage and the first output voltage of the logic control circuit
  • the control signal detects the current of the power stage circuit, and outputs a second control signal to the logic control circuit after the current reaches a preset peak value;
  • the logic control circuit is connected to the at least one output terminal, and the logic control circuit is used to output a first control signal to the current control circuit according to each output voltage, and the first control signal is used for the current control circuit to turn on the power stage circuit
  • the logic control circuit outputs a third control signal to the power stage circuit according to the second control signal output by the current control circuit, so as to control the current peak value of the power stage circuit to a preset peak value.
  • the power stage circuit may be, for example, a single-inductor multi-output circuit.
  • the following uses a single-inductor dual-output circuit for example.
  • the logic control circuit compares the output terminals V OUT1 and V OUT2 of the power stage circuit with reference voltages V REF1 and V REF2 respectively. If any one of V OUT1 or V OUT2 is lower than the corresponding reference voltage, the logic control circuit controls and The output terminal LOOP_EN connected to the current control circuit outputs a first control signal.
  • the first control signal may be a transition signal. For example, if the output terminal LOOP_EN is originally low, it outputs a high level, and the current control circuit enters the working state; at the same time; When any one of V OUT1 or V OUT2 is lower than the corresponding reference voltage, the logic control circuit controls the output terminal Dn connected to the power stage circuit to output a third control signal.
  • the third control signal may be a jump signal, such as output If the original terminal is low, the output is high to drive the power stage circuit, so that the current in the power stage circuit rises slowly, and the current control circuit detects the current value of the current. When the current value reaches the preset peak value, the output terminal CS_OUT outputs The second control signal is sent to the logic control circuit, and the logic control circuit outputs a third control signal to control the power stage circuit through the output terminal Dn connected to the power stage circuit according to the received second control signal, so that the current is slowly reduced, so as to realize the control of the power stage. Control of the peak current in the circuit.
  • the preset peak value can be pre-determined according to the requirements of output ripple and output voltage. For example, the larger the peak value, the larger the output ripple. However, if the current peak value of the power stage circuit is reduced, the output voltage will be affected.
  • the working efficiency of the power management circuit in practical applications, can determine the preset peak value according to actual requirements so that the output ripple and the working efficiency of the power management circuit reach a certain balance.
  • each output terminal of the power stage circuit can be used to supply power to different power supply modules. For example, it can output different voltages. It can be controlled by the reference voltage corresponding to each output terminal. The voltage of each output terminal is generally controlled at the corresponding reference voltage. In other embodiments, each output terminal can also output the same voltage, which is not limited in the embodiment of the present application.
  • the preset peak value corresponding to each output terminal is the same. In other embodiments, the preset peak value corresponding to each output terminal may also be different, which is not limited in the embodiment of the present application.
  • the preset peak value can also be adjusted according to the actual operating conditions of the circuit, and the current control circuit can adjust some parameters in the current control circuit to realize the adjustment of the preset peak value.
  • the circuit of this embodiment realizes the control of the current peak value of the power stage circuit through the current control circuit and the logic control circuit, so that the output ripple and efficiency of the power stage circuit can achieve a better balance through the control of the current peak value. Controlling the current peak value to the preset peak value can reduce the output ripple and improve the working efficiency of the circuit.
  • the current control circuit includes:
  • the output terminal of the peak current control circuit is used to output the second control signal to the logic control circuit
  • the output terminal of the current zero-crossing detection circuit is used to output a fourth control signal to the logic control circuit
  • the logic control circuit Output a fifth control signal to the power stage circuit according to the fourth control signal to control the output of the power stage circuit
  • the input terminals of the peak current control circuit are respectively connected to the power supply V IN , the first output terminal LOOP_EN and the second output terminal D1 of the logic control circuit, and the input terminals of the current zero-crossing detection circuit are respectively connected to the power
  • the first output terminal LOOP_EN of the first stage circuit and the logic control circuit wherein the first output terminal is used to output the first control signal, and the second output terminal is used to output the third control signal to all
  • the peak current control circuit outputs the second control signal according to the third control signal
  • the power stage circuit controls the current peak value according to the third control signal Control to the preset peak value.
  • the output terminal CS_OUT of the peak current control circuit outputs the second control signal
  • the output terminal ZCD_OUT of the current zero-crossing detection circuit outputs the fourth control signal.
  • the current zero-crossing detection circuit is used to detect whether the current of the power stage circuit reaches zero, and if it drops to zero, the output terminal ZCD_OUT outputs a fourth control signal, so that the power tube at the output terminal of the power stage circuit is turned off and stops outputting.
  • the fourth control signal of the output terminal ZCD_OUT is output to the logic control circuit, and the logic control circuit outputs the fifth control signal according to the fourth control signal so that the power tube at the output terminal of the power stage circuit is turned off.
  • the logic control circuit in FIG. 2 The output terminal Dx outputs the fifth control signal. At this time, the output terminal Dn in FIG. 1 is the second output terminal D1 in FIG. 2.
  • the peak current control circuit is used to control the peak current of the power stage circuit. Specifically, the logic control circuit compares the output terminals V OUT1 and V OUT2 of the power stage circuit with the reference voltages V REF1 and V REF2 respectively. If V OUT1 or V Any one of OUT2 is lower than the corresponding reference voltage, the second output terminal D1 controlled by the logic control circuit outputs a third control signal, which may be a transition signal, for example, the second output terminal D1 was originally at low level.
  • the output is high, that is, when the rising edge of the third control signal output from the second output terminal D1 of the logic control circuit comes, the power tube of the power stage circuit is turned on, the current of the power stage circuit rises, and the peak current control circuit according to the first Three control signals detect the current value of the current output by the power stage circuit.
  • the peak current control circuit makes the second control signal output by the output terminal CS_OUT set high, thereby enabling logic control
  • the third control signal output by the second output terminal D1 of the circuit becomes low level, the third control signal is input to the power stage circuit, and the power tube at the input terminal of the power stage circuit is controlled to be turned off, so that the current of the power stage circuit is reduced, thereby Realize the control of peak current.
  • the current control circuit can also continuously detect the current value of the current in the power stage circuit.
  • the output terminal ZCD_OUT of the current control circuit outputs the fourth control signal
  • the logic control circuit outputs the fifth control signal according to the fourth control signal at the output terminal ZCD_OUT to control the power stage circuit to be turned off (that is, the power tube of the output control unit in the power stage circuit is turned off, and the power stage circuit is input The power tube of the control unit is also turned off).
  • the logic control circuit controls the current control circuit to enter the standby state to save power consumption, such as changing the first output terminal LOOP_EN connected to the current control circuit from high level to low level, So that the current control circuit enters the standby state.
  • the above scheme realizes the low power consumption scheme of the power management circuit without introducing a clock signal, and the overall power consumption is greatly reduced when entering the standby state.
  • the power tube in the power stage circuit does not work, and the current control circuit does not work, so the power consumption is relatively low.
  • the clock module is turned off in the standby state, the power tube in the power stage circuit cannot be controlled to turn on. Therefore, the clock module cannot be turned off in the normal operation or the standby state, and the loss caused by the clock module
  • the power consumption of the circuit will be much greater than that of the circuit of the embodiment of the present application.
  • FIG. 3 it is a circuit structure diagram of the power management circuit of an embodiment, which is roughly the same as the power management circuit shown in FIG. 2, except that the power stage circuit can adopt the following Specific structure:
  • the power stage circuit includes: an input control unit, an inductor, and at least one second output control unit (in Figure 3, two second output terminals are used as an example for illustration);
  • the input control unit is connected to the first end of the power supply V IN and the inductor L (that is, the input control unit is connected between the power supply V IN and the first end of the inductor L), and the input control unit is also connected to the second end of the logic control circuit.
  • the output terminal D1 is connected to receive the third control signal output by the second output terminal D1 of the logic control circuit.
  • the second terminals of the inductor L are respectively connected to each second output control unit; each second output control unit is also connected to the logic control
  • the fourth output terminals D2 and D3 of the circuit are connected to receive the fifth control signal output by the fourth output terminal of the logic control circuit.
  • the output terminal of each second output control unit is used as the output terminal of the power stage circuit. At this time, the output terminal Dx in FIG. 2 is the fourth output terminal D2 or D3 in FIG. 3.
  • the logic control circuit compares the output terminals V OUT1 and V OUT2 of the power stage circuit with the reference voltages V REF1 and V REF2 respectively, if any one of V OUT1 or V OUT2 is lower than the corresponding reference voltage ,
  • the logic control circuit controls the first output terminal LOOP_EN to output the first control signal
  • the first control signal may be a transition signal, for example, the first output terminal LOOP_EN was originally low level, then output high level
  • the current control circuit That is, the peak current control circuit and the current zero-crossing detection circuit
  • the logic control circuit controls the second output terminal D1 to output the third control signal and the fourth output terminal D2 to output the first Five control signals, which respectively control the input control unit and the second output control unit of the power stage circuit, so that the power supply V IN and the inductor are turned on, and V OUT1 outputs voltage.
  • V OUT1 and V OUT2 do not output voltage at the same time, for example, V OUT1 first
  • the fourth output terminal D2 outputs a fifth control signal, so that the second output control unit controls the output voltage of V OUT1.
  • the peak current control circuit also inputs the third control signal (for example, high level), and the peak current control circuit detects the current value of the current in the inductor. After the current value reaches the preset peak value, the output terminal CS_OUT outputs the second control signal to the logic control circuit.
  • the logic control circuit controls the third control signal of the second output terminal D1 according to the second control signal.
  • the third control signal may be a jump Changing the signal, for example, the second output terminal D1 changes from a high level to a low level, and the input control unit in the power stage circuit is controlled so that the power supply V IN and the inductor are not conducted, and the current in the inductor decreases slowly.
  • the current zero-crossing detection circuit detects the current value of the current in the inductor. When the current value drops to zero, the output terminal ZCD_OUT of the current zero-crossing detection circuit outputs a fourth control signal to the logic control circuit, and the logic control circuit controls the fourth control signal according to the fourth control signal.
  • the fourth output terminal D2 outputs a fifth control signal.
  • the fifth control signal may be a transition signal.
  • the second output terminal D2 changes from a high level to a low level, and controls the second output control unit to stop V OUT1 from outputting voltage.
  • the logic control circuit controls the first control signal of the first output terminal LOOP_EN to jump.
  • the first output terminal LOOP_EN changes from a high level to a low level, and the peak current control circuit and the current zero-crossing detection circuit enter the standby state to save Power consumption.
  • the power management circuit further includes:
  • the second output terminal D1 of the logic control circuit is connected to the power stage circuit through the first drive circuit, such as connected to the input control unit of the power stage circuit;
  • the fourth output terminal D2 or D3 of the logic control circuit is connected to the power stage circuit through the second drive circuit, such as the second output control unit connected to the power stage circuit.
  • the first drive circuit drives the power tube of the input control unit of the power stage circuit to turn on or off according to the level of the second output terminal D1 of the logic control circuit; the second drive circuit drives the power tube of the power stage circuit to turn on or off according to the fourth output terminal D2 of the logic control circuit Or the level of D3 drives the on or off of the power tube of the output control unit of the power stage circuit.
  • the first drive circuit and the second drive circuit realize the reliability of the input control unit and the first output control unit to control the output voltage of each output terminal of the power stage circuit.
  • the input control unit in the circuit structure shown in FIG. 3 or FIG. 4 may adopt the following structure, and the input control unit includes:
  • the first terminal of the eighth power tube M1 for example, the gate is connected to the output terminal of the first driving circuit
  • the second terminal of the eighth power tube M1 for example, the source is connected to the power source V IN
  • the third terminal of the eighth power tube M1 is Terminal, for example, the drain is connected to the first terminal of the inductor L;
  • the second output terminal D1 of the logic control circuit is connected to the input terminal of the first drive circuit, and outputs a third control signal to the first drive circuit;
  • the first terminal of the ninth power tube M2 for example, the gate is connected to the output terminal of the first driving circuit
  • the second terminal of the ninth power tube for example, the drain is connected to the first terminal of the inductor L
  • the third terminal of the ninth power tube for example, the source is grounded.
  • the fourth output terminal D2 or D3 of the logic control circuit is connected to the input terminal of the second drive circuit, and outputs the fifth control signal to the second drive circuit.
  • the drain of the ninth power tube M2 can be used as the output terminal SW of the input control unit Connected to the first end of the inductor L and connected to the current zero-crossing detection circuit.
  • the first driving circuit decides to control the eighth power tube M1 or the ninth power tube M2 according to the level of the third control signal output by the second output terminal D1 of the logic control circuit.
  • each second output control unit may be the same or different.
  • the following takes the same structure as an example for description.
  • each second output control unit adopts the following structure.
  • the second output control unit includes:
  • the first end of the tenth power tube for example, the gate is connected to the second drive circuit
  • the second end of the tenth power tube for example, the drain is connected to the second end of the inductor
  • the third end of the tenth power tube for example, the source
  • the pole is connected to the first end of the second capacitor, the second capacitor and the second end of the load are grounded, and the first end of the second capacitor is also connected to the first end of the load.
  • the tenth power tube in the second output control unit corresponding to V OUT1 is M3
  • the tenth power tube in the second output control unit corresponding to V OUT2 is M4.
  • the second driving circuit decides to control the tenth power tube M3 or the tenth power tube M4 according to the level output by the fourth output terminal D2 or the fourth output terminal D3 of the logic control circuit.
  • the second capacitors may be capacitors C O1 and C O2 .
  • the load is represented by resistors R L1 and R L2 .
  • the logic control circuit compares the output terminals V OUT1 and V OUT2 of the power stage circuit with the reference voltages V REF1 and V REF2 respectively, if V OUT1 or V OUT2 If any channel is lower than the corresponding reference voltage, the logic control circuit controls the first output terminal LOOP_EN to output the first control signal.
  • the first control signal may be a transition signal. For example, if the first output terminal LOOP_EN is originally low, it outputs At high level, the current control circuit (that is, the peak current control circuit and the current zero-crossing detection circuit) enters the working state.
  • the logic control circuit controls the second output terminal D1 to output the third control signal and the fourth output terminal D2 or D3 to output the third control signal.
  • Five control signals which respectively drive the input control unit and the second output control unit of the power stage circuit through the first drive circuit and the second drive circuit, so that the eighth power tube M1 and the tenth power tube (M3 or M4) in the power stage circuit Turn on, where M3 and M4 are not turned on at the same time.
  • the specific turn-on conditions are determined by the output of V OUT1 and V OUT2 . If V OUT1 is lower than the reference voltage before V OUT2 , M3 is turned on.
  • the current of the inductor L in the power stage circuit slowly rises, and the peak current control circuit detects the current value of the current in the inductor.
  • the output terminal CS_OUT outputs the second
  • the control signal is sent to the logic control circuit, and the logic control circuit controls the second output terminal D1 to output a third control signal.
  • the control signal may be a transition signal.
  • the second output terminal D1 changes from a high level to a low level.
  • a driving circuit turns off the eighth power tube M1 and turns on the ninth power tube M2; at this time, the ninth power tube M2 and the tenth power tube M3 are turned on at the same time, and the current in the inductor decreases slowly.
  • the current zero-crossing detection circuit detects the current value of the current in the inductor (ie, detects the current value at SW).
  • the output terminal ZCD_OUT outputs the fourth control signal to the logic control circuit, and the logic control circuit controls the fourth output terminal D2 outputs the fifth control signal.
  • the fifth control signal can be a transition signal.
  • the second output terminal D2 changes from a high level to a low level, and the second drive circuit turns off the power tube M3.
  • the logic control The circuit controls the first output terminal LOOP_EN to change from a high level to a low level, and the peak current control circuit and the current zero-crossing detection circuit enter the standby state to save power consumption.
  • the eighth power tube M1 and the ninth power tube M2 are controlled by the second output terminal D1 of the logic control circuit, and the states are mutually exclusive, that is, when the eighth power tube M1 is turned on, the ninth power tube M2 is turned off; the ninth power tube M2 The eighth power tube M1 is turned off when it is turned on.
  • the reliability of the power management circuit operating in a clockless module is increased through the logic control circuit, that is, the logic control circuit realizes the control of the operation of the current control circuit and the control of the power stage circuit.
  • the logic control circuit may specifically include:
  • the third sub-control circuit and at least one second comparator; the number of the second comparators is the same as the number of the output terminals of the power stage circuit, and may also be the same as the number of the second output control units;
  • each second comparator is respectively connected to each output terminal of the power stage circuit; the second input terminal of each second comparator is respectively input with a second reference voltage;
  • each second comparator is respectively connected to the third sub-control circuit
  • the first output terminal LOOP_EN of the third sub-control circuit is used to output the first control signal to the current control circuit according to the signal output from the output terminal of each of the second comparators; the second output terminal D1 of the third sub-control circuit
  • the third control signal is used to output the third control signal to the current control circuit and the power stage circuit according to the signal output from the output terminal of each of the second comparators, and the fourth output terminal of the third sub-control circuit is used for
  • the fifth control signal is output to the power stage circuit.
  • the second comparators CMP1 and CMP2 respectively compare the output terminals V OUT1 and V OUT2 of the power stage circuit with the reference voltages V REF1 and V REF2 .
  • the output voltage CMP_OUT1 or CMP_OUT2 of the second comparator CMP1 or CMP2 changes from low When it flips to high, it means that V OUT1 or V OUT2 is lower than the reference voltage.
  • the third sub-control circuit detects the low-to-high transition of CMP_OUT1 or CMP_OUT2
  • the third sub-control circuit controls the first output terminal LOOP_EN to change to a high level.
  • the second output terminal D1 of the logic control circuit outputs a third control signal, such as flipping from a low level to a high level, and the input control unit of the power stage circuit is driven by the first drive circuit, so that the power supply V IN and the inductor conduct
  • a third control signal such as flipping from a low level to a high level
  • the circuit provided by the embodiment of the present application uses a current zero-crossing detection circuit to detect the current. When the current is lower than zero, the switching signal is output as a signal for power-off of the power management circuit. Before the next second comparator inversion, the entire power management Most of the circuit structures in the circuit are in the standby state, such as the current control circuit, the third sub-control circuit, and the input control unit and output control unit in the power stage circuit. Only the second comparator is in operation, and the overall static power consumption is greatly reduced.
  • the peak current control circuit includes:
  • a clamp circuit a current mirror circuit, a first resistor R, a first capacitor C, a selection circuit, and a first sub-control circuit;
  • the first end of the first resistor R is connected to the power supply V IN , and the second end of the first resistor R is connected to the clamping circuit;
  • the clamping circuit is connected to the selection circuit and the current mirror circuit, and receives the first control signal output from the first output terminal LOOP_EN of the logic control circuit;
  • the selection circuit is connected to each output terminal (such as V OUT1 and V OUT2 ) of the power stage circuit, and receives the sixth control signal output by the third output terminal V OUT_SEL of the logic control circuit;
  • the current mirror circuit is also connected to the power supply V IN , the first end of the first capacitor C and the first sub-control circuit;
  • Both ends of the first capacitor C are respectively connected to the first sub-control circuit, the first sub-control circuit receives the third control signal output from the second output terminal D1 of the logic control circuit, and the output terminal of the first sub-control circuit serves as the peak value The output terminal CS_OUT of the current control circuit;
  • a clamp circuit for the second end of the first resistor R the voltage V C is clamped, such that a first end of a second resistor R the voltage V C is equal to the output voltage V OUT_IN selection circuit;
  • a current mirror circuit a first resistor R I C current mirror
  • the selection circuit is used to select the output voltage V OUT_IN of the power stage circuit according to the sixth control signal output by the third output terminal V OUT_SEL of the logic control circuit;
  • the first sub-control circuit is configured to control the output terminal CS_OUT of the peak current control circuit to output a second control signal according to the third control signal output from the second output terminal of the logic control circuit.
  • the third output terminal V OUT_SEL of the logic control circuit outputs a high level when V OUT1 is lower than the reference voltage, that is, when the output voltage of the second comparator CMP_OUT1 switches from low to high, the output voltage of the selection circuit is selected V OUT_IN is equal to V OUT1 ; the third output terminal V OUT_SEL outputs low level when V OUT2 is lower than the reference voltage, that is, when the output voltage of the second comparator CMP_OUT2 turns from low to high, the output voltage of the selection circuit V OUT_IN is equal to V OUT2 .
  • the peak current control circuit uses a clamping circuit to clamp the voltage V C so that V C is equal to V OUT_IN , and after current mirroring, I C charges the first capacitor C.
  • V OUT1 or V OUT2 is lower than the reference voltage
  • the output voltage CMP_OUT1 or CMP_OUT2 of the second comparator CMP1 or CMP2 switches from low to high
  • the third control signal output by the second output terminal D1 of the logic control circuit controls the input control unit of the power stage circuit, so that the power supply V IN and the inductor are conducted, and the first sub-control circuit according to the third output terminal D1 output
  • the control signal makes the second control signal output by the output terminal CS_OUT set low, the first sub-control circuit controls the first capacitor C to charge, and after V C gradually rises to the first reference voltage V REF , the first sub-control circuit controls the output terminal CS_OUT to set High, the logic control circuit controls the
  • the peak current control circuit may further include: a second sub-control circuit
  • the second sub-control circuit is respectively connected to the first output terminal LOOP_EN of the logic control circuit, the current mirror circuit, the second end of the first capacitor C, and the first sub-control circuit;
  • the second sub-control circuit is used to control the peak current control circuit to be turned on or off according to the first control signal output from the first output terminal LOOP_EN of the logic control circuit.
  • the power consumption of the power management circuit can be reduced by controlling the opening or closing of the peak current control circuit.
  • the peak current control circuit controls the falling edge of the second output terminal D1 of the logic control circuit to determine the current peak value of the inductor.
  • the current peak value of the inductor can be adjusted by controlling the values of R, C, V REF and L, that is, the preset peak value is adjusted.
  • the resistance of the first resistor R is variable or the capacitance of the first capacitor C is variable; in one embodiment, the first reference voltage V REF is variable.
  • a resistor R with adjustable resistance values of multiple gears can be used to indirectly realize the design of the inductor current with adjustable peak values of multiple gears.
  • the peak current control circuit uses a clamping circuit to clamp the voltage V C so that V C is equal to V OUT_IN , and V OUT_IN can be set to V OUT1 or V OUT2 through the selection circuit, which can be specifically controlled by the third part of the logic control circuit.
  • the sixth control signal output by the output terminal V OUT_SEL is determined.
  • the current I C (V IN -V OUT_IN )/R, after the current is mirrored, I C charges the capacitor C.
  • the output terminal CS_OUT of the first sub-control circuit When the rising edge of the third control signal output by the second output terminal D1 of the logic control circuit comes, the output terminal CS_OUT of the first sub-control circuit is set low, MN4 is turned off, so that the first capacitor is charged, and V C gradually rises to the first reference After the voltage V REF , the first sub-control circuit controls the output terminal CS_OUT to be set high, and then controls the third control signal output from the second output terminal D1 to turn low.
  • the above process is a typical working process of the peak current control circuit, and the output terminal CS_OUT is the output of the peak current control circuit, which is used to control the duty ratio of D1.
  • the above-mentioned peak current control circuit changes the resistance of the first resistor R, the capacitance of the first capacitor C or the first reference voltage so that the current peak value can be adjusted, which indirectly adjusts the output ripple and working efficiency of the circuit.
  • the peak value of the current through the current control circuit I C can be achieved in the detection of the current value of the inductor current.
  • the clamping circuit includes:
  • the first input terminal of the operational amplifier EA (as shown in the negative input terminal in FIG. 10) is connected to the second end of the first resistor R, and the second input terminal of the operational amplifier EA (as shown in the positive input terminal in FIG. 10) is connected to the selection circuit
  • the output terminal V OUT_IN of the operational amplifier EA is connected to the first output terminal LOOP_EN of the logic control circuit, and the output terminal of the operational amplifier EA is connected to the first terminal (such as the gate) of the first power tube MP1.
  • the second end (such as the source) of the tube MP1 is connected to the second end of the first resistor R, and the third end (such as the drain) of the first power tube MP1 is connected to the mirror current circuit (as shown in Figure 10, the first power tube
  • the drain of MP1 is connected to the drain of the second power tube MN1 of the mirror current circuit).
  • the second end (such as the source) of the first power tube MP1 is also connected to the negative input end of the operational amplifier EA.
  • the selection circuit includes:
  • the input terminal of the first inverter INV1 is connected to the third output terminal V OUT_SEL of the logic control circuit;
  • the output terminal of the first inverter INV1 is respectively connected to the first control terminal of each transmission gate; the second control terminal of each transmission gate is respectively connected to the third output terminal V OUT_SEL of the logic control circuit; the input terminals of each transmission gate are respectively connected correspondingly Each output terminal of the power stage circuit and the output terminal of each transmission gate are used as the output terminal V OUT_IN of the selection circuit.
  • the number of transmission gates is the same as the number of output terminals of the power stage circuit
  • the power stage circuit has two output terminals corresponding to two transmission gates G1 and G2 as an example for description.
  • the input terminal of the first inverter INV1 is connected to the input signal V OUT_SEL of the peak current control circuit (that is, the sixth control signal output by the third output terminal V OUT_SEL of the logic control circuit), and the output terminal of the first inverter INV1 is connected for transmission
  • the negative control terminal of gate G1; the positive control terminal of transmission gate G1 is connected to the input signal V OUT_SEL of the peak current control circuit, the input terminal of transmission gate G1 is connected to the input signal V OUT1 of the peak current control circuit, and the output terminal of transmission gate G1 is connected to transmission
  • the output terminal V OUT_IN of the gate G2; the positive control terminal of the transmission gate G2 is connected to the output terminal of the first inverter INV1, the negative control terminal of the transmission gate G2 is connected to the input signal V OUT_SEL of the peak current control circuit, and the input terminal of the transmission gate G2 Connect the input signal V OUT2 of the peak current control circuit. That is, the voltage of the output terminal V OUT_
  • the current mirror circuit includes:
  • the first end (such as the gate) of the second power tube MN1 is connected to the first end (such as the gate) of the third power tube MN2, and the first end (such as the gate) of the second power tube MN1 is connected to the second end (such as the gate) of the second power tube MN1.
  • Terminal (such as the drain) the second terminal of the second power tube MN1 is connected to the clamp circuit (such as the drain of the first power tube MP1 of the clamp circuit), and the third terminal of the second power tube (source Pole) ground;
  • the second end (drain) of the third power tube MN2 is connected to the second end (drain) of the fourth power tube MP2, and the third end (source) of the third power tube MN2 is grounded;
  • the second end (drain) of the fourth power tube MP2 and the first end (gate) are short-circuited, and the first end (gate) of the fourth power tube MP2 is also connected to the first end (gate) of the fifth power tube MP3. ), the third end (source) of the four power tubes is connected to the power supply V IN ;
  • the second end (drain) of the fifth power tube MP3 is connected to the first capacitor C; the third end (source) of the fifth power tube MP3 is connected to the power supply V IN .
  • the first sub-control circuit includes: a first logic unit, a sixth power tube MN4, and a first comparator Comp;
  • the first input terminal DOWN_IN of the first logic unit is connected to the second output terminal D1 of the logic control circuit, the second input terminal UP_IN of the first logic unit is connected to the output terminal V C_OUT of the first comparator, and the output of the first logic unit
  • the terminal CS_OUT is connected to the first terminal (gate) of the sixth power tube MN4; the output terminal CS_OUT of the first logic unit is used as the output terminal CS_OUT of the peak current control circuit;
  • the second end (source) and the third end (drain) of the sixth power tube MN4 are respectively connected to the two ends of the capacitor C, and the second end (source) of the sixth power tube MN4 is grounded;
  • the drain is connected to the first input terminal (positive input terminal) of the first comparator Comp;
  • the first input terminal of the first comparator Comp is connected to the mirror current circuit. As shown in FIG. 10, the first input terminal of the first comparator Comp is connected to the second terminal (drain) of the fifth power tube MP3 of the mirror current circuit. The second input terminal (negative input terminal) of the first comparator Comp is connected to the first reference voltage V REF .
  • the upper plate of the first capacitor C is connected to the positive input terminal of the first comparator Comp, and the lower plate of the first capacitor C is grounded.
  • the second sub-control circuit includes: a seventh power tube MN3, and the first end (gate) of the seventh power tube MN3 is connected to the first output terminal LOOP_EN of the logic control circuit,
  • the second terminal (drain) of the seventh power tube MN3 is connected to the mirror current circuit (ie, the first terminal of the third power tube MN2), and the third terminal (source) of the seventh power tube MN3 is grounded.
  • the drain of the seventh power tube MN3 is connected to the gate of the third power tube MN2.
  • the signal V OUT_SEL is the input signal of the peak current control circuit. When it is high, the V OUT1 branch in the power stage circuit is working; when it is low, the V OUT2 branch in the power stage circuit is working. Lu is working.
  • the signal V OUT_SEL can switch the signal V OUT_IN back and forth between V OUT1 and V OUT2 in real time to achieve precise current control.
  • the logical relationship shown in Figure 11 is that the rising edge of D1 controls CS_OUT to go low, and the peak current control circuit starts to charge the capacitor C.
  • V C_OUT When V C rises to V REF , V C_OUT generates a pulse to make CS_OUT go high, and CS_OUT is output to the logic control
  • the circuit makes D1 turn low. The whole process makes the holding time of the high level of D1 equal to the time required to charge the capacitor C. Among them, the rising edge of D1 is controlled by the second comparator.
  • the first logic unit includes:
  • the first D flip-flop, the second D flip-flop and the first AND gate are The first D flip-flop, the second D flip-flop and the first AND gate
  • the first terminal CLK of the first D flip-flop is used as the second input terminal UP_IN of the first logic unit, the second terminal D of the first D flip-flop is connected to the power supply VDD, and the third terminal CLR of the first D flip-flop is connected to the An output terminal of an AND gate, the output terminal Q of the first D flip-flop is connected to the first input terminal of the first AND gate and serves as the output terminal OUT of the first logic unit;
  • the first terminal CLK of the second D flip-flop is used as the first input terminal DOWN_IN of the first logic unit
  • the second terminal D of the second D flip-flop is connected to the power supply VDD
  • the third terminal CLR of the second D flip-flop is connected to the second D
  • the output terminal Q of the flip-flop and the output terminal Q of the second D flip-flop are connected to the second input terminal of the first AND gate.
  • Figure 13 shows the working waveforms of the logic unit circuit.
  • the UP_IN and DOWN_IN signals control the output signal OUT up and down respectively.
  • the following second logic unit, third logic unit, and fourth logic unit may all adopt the circuit structure of the above-mentioned first logic unit.
  • the third sub-control circuit includes:
  • a second logic unit a third logic unit, a logic control unit, a first delay unit, and a first output control unit;
  • the first input terminal DOWN_IN of the second logic unit is connected to the output terminal of the first delay unit, and the second input terminal UP_IN of the second logic unit and the input terminal of the first delay unit are respectively connected to the current zero-crossing detection circuit
  • the output terminal ZCD_OUT respectively receives the fourth control signal output by the output terminal ZCD_OUT of the current zero-crossing detection circuit
  • the output terminal OUT of the second logic unit is connected to the input terminal of the first output control unit, and the output terminal of the first output control unit serves as the first output terminal LOOP_EN of the third sub-control circuit;
  • the first input terminal DOWN_IN of the third logic unit is connected to the output terminal CS_OUT of the peak current control circuit, the second input terminal UP_IN of the third logic unit is connected to the output terminal of the first output control unit, and the output terminal OUT of the third logic unit As the second output terminal D1 of the third sub-control circuit;
  • the first input terminal of the logic control unit is connected to the output terminal ZCD_OUT of the current zero-crossing detection circuit, receives the fourth control signal output by the output terminal ZCD_OUT of the current zero-crossing detection circuit, and the second input terminal of the logic control unit is connected to the first The output terminal LOOP_EN of an output control unit, the third input terminal of the logic control unit is connected to the output terminals of each second comparator (such as CMP_OUT1, CMP_OUT2), and the output terminal OUT of the logic control unit serves as the third sub-control circuit The fourth output terminal D2 or D3.
  • the logic control unit may include, for example, at least two logic units. Similar to the structure in FIG. 12, one logic unit corresponds to a second comparator. For example, when the output terminal CMP_OUT1 of the second comparator is at a high level, The fourth output terminal D2 of the third sub-control circuit is controlled to output a signal, and the second output control unit corresponding to V OUT1 in the power stage circuit is controlled.
  • the first output control unit is also connected to the output terminals (such as CMP_OUT1, CMP_OUT2) of each second comparator.
  • the first delay unit includes a resistor R1 and a capacitor C1.
  • the third sub-control circuit further includes: a second delay unit;
  • the input terminal of the second delay unit is connected to the output terminal LOOP_EN of the first output control unit, and the output terminal of the second delay unit is connected to the second input terminal UP_IN of the third logic unit and the fourth logic unit, respectively.
  • the second delay unit includes a resistor R2 and a capacitor C2.
  • the first output control unit includes:
  • the input terminal of the second inverter INV2 is connected to the output terminal OUT of the second logic unit, the output terminal of the second inverter INV2 is connected to the first input terminal of the second AND gate, and the second input terminal of the second AND gate The terminal is connected to the output terminal of the OR gate;
  • the input terminals of the OR gate are respectively connected to the output terminals of each second comparator (such as CMP_OUT1, CMP_OUT2), and the output terminal of the second AND gate is used as the output terminal LOOP_EN of the first output control unit.
  • the rising edge of ZCD_OUT will control LOOP_EN to output low level.
  • the current control module and logic control module in the circuit enter the standby low power consumption state; when at least one of CMP_OUT1 and CMP_OUT2 is high, the output LOOP_EN changes to a high level, at this time the loop works again. Due to the existence of the T1 delay generated by R1 and C1, LOOP_EN is clamped to low level within T1 after the rising edge of ZCD_OUT.
  • this design is to prevent the loop from continuously working without clock control under heavy load to produce logic errors, and to improve the reliability of the control logic.
  • Figure 16 shows the working waveform of the logic control circuit.
  • the main working logic is that the rising edges of D1 and D2 are jointly determined by ZCD_OUT, CMP_OUT1, and CMP_OUT2.
  • ZCD_OUT ensures that the inductor current drops to zero in each working cycle; due to the introduction of T1 and T2 delay, the interval between every two rising edges of D1 or D2 is at least the duration of T1+T2, which limits the maximum operating frequency ⁇ 1/(T1+T2).
  • the circuit of the embodiment of the present application is described with a single-inductor dual-output SIDO as an example.
  • the control logic of the current control circuit and the logic control circuit can also be applied to other types of single-inductor and multiple-output circuits, such as single-inductor and multiple-output circuits. BOOST, BUCK-BOOST circuit and so on.
  • the difference from the traditional common SIDO circuit is that the circuit of the embodiment of the present application does not require a clock to be controlled, which saves corresponding power consumption; the peak current control circuit is introduced to control the current peak in real time, and realizes the multi-stage current peak. adjustable.
  • a logic control circuit is introduced, which is inserted into each work cycle by delaying T1 and T2; the peak current control circuit samples the input and output voltage of the power stage circuit and controls the duty cycle of D1 In order to achieve current peak control.
  • the present application also provides a power management chip, which may include the power management circuit described in any of the foregoing embodiments.
  • circuit modules may also be included, which is not limited in this application.
  • the present application also provides an electronic device, which may include the power management chip described in any of the foregoing embodiments.
  • electronic devices include, for example, terminal devices such as mobile phones, tablet computers, and wearable devices.
  • the electronic device also includes, for example, a power supply, a processor, a memory, and the like.

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Abstract

一种电源管理电路、芯片和设备，电源管理电路包括：功率级电路连接至电源，功率级电路包括至少一个输出端；电流控制电路用于根据至少一个输出端输出的各个输出电压以及逻辑控制电路输出的第一控制信号检测功率级电路的电流，并在电流达到预设峰值后输出第二控制信号至逻辑控制电路；逻辑控制电路，用于根据各个输出电压向电流控制电路输出第一控制信号，第一控制信号用于电流控制电路开启对功率级电路的电流的检测，逻辑控制电路根据第二控制信号输出第三控制信号至功率级电路以将功率级电路的电流峰值控制到预设峰值。电源管理电路实现了对电流峰值的有效控制，而且不需要时钟进行控制，节省了相应的功耗。

Description

电源管理电路、芯片和设备 技术领域
本申请涉及电源电路技术领域，尤其涉及一种电源管理电路、芯片和设备。
背景技术
在电源管理集成电路当中，通常需要多个输出电压分别对相应的模块进行供电，例如，手机中对其内的MCU、音频集成电路(integrated circuit，简称IC)、输入/输出I/O供电等等，而多个不同模块所需的供电电压是不同的。因而，需要多路输出才能满足使用的需求。但通常情况下，一个电压转换电路只有一路输出，那么要对不同电压需求的多个模块进行供电的话，也就需要多个电压转换电路才能满足需求。为了提高电路的集成程度、降低成本，单电感多输出电路便应运而生了。现有的单电感多输出电路DC-DC电路，以单电感双输出(Single Inductor Dual Output，简称SIDO)降压式变换电路(BUCK)为例，SIDO Buck的方案主要包括断续导电模式(Discontinuous Conduction Mode，DCM)的SIDO BUCK和连续导电模式(Continuous Conduction Mode，CCM)的SIDO BUCK两种。其中CCM模式的SIDO BUCK适用于更宽的负载范围，其结构也更加复杂、需要考虑输出交叉影响。在轻载应用中，DCM模式的SIDO BUCK以其结构简单、无输出交叉影响的特点而被更广泛的使用。
在DCM模式的SIDO BUCK中，通常采用固定导通时间的控制模式，即每个周期内功率管的导通时间固定，这使得SIDO的电感电流峰值由实时的输入输出电压被动决定。而电感电流的峰值大小直接决定了SIDO BUCK的输出纹波的大小并一定程度影响工作效率。
发明内容
本申请提供一种电源管理电路、芯片和设备，以实现电流峰值可调节， 从而提高工作效率。
第一方面，本申请提供一种电源管理电路，包括：
功率级电路，连接至电源，所述功率级电路包括至少一个输出端，用于输出电压；
电流控制电路，连接至所述电源、逻辑控制电路和所述至少一个输出端，所述电流控制电路用于接收从所述至少一个输出端输出的各个输出电压，根据所述各个输出电压以及所述逻辑控制电路输出的第一控制信号检测所述功率级电路的电流，并在所述电流达到预设峰值后输出第二控制信号至所述逻辑控制电路；
所述逻辑控制电路，连接至所述至少一个输出端，所述逻辑控制电路用于根据所述各个输出电压向电流控制电路输出所述第一控制信号，所述第一控制信号用于所述电流控制电路开启对所述功率级电路的电流的检测，所述逻辑控制电路根据所述第二控制信号输出第三控制信号至所述功率级电路以将所述功率级电路的电流峰值控制到预设峰值。
通过电流控制电路和逻辑控制电路实现了对功率级电路的电流峰值的控制，使得功率级电路的输出纹波与效率可以通过电流峰值的控制来达到较好的平衡，通过电流峰值控制到预设峰值可减小输出纹波并提高电路的工作效率。
可选的，所述第一控制信号还用于控制所述电流控制电路关闭对所述功率级电路的电流的检测，减少功耗。
可选的，所述电流控制电路，还用于对所述预设峰值进行调节。
可选的，所述电流控制电路，包括：
峰值电流控制电路和电流过零检测电路；
其中，所述峰值电流控制电路的输出端用于输出所述第二控制信号至所述逻辑控制电路，所述电流过零检测电路的输出端用于输出第四控制信号至所述逻辑控制电路，所述逻辑控制电路根据所述第四控制信号输出第五控制信号至所述功率级电路，以控制所述功率级电路的输出；
所述峰值电流控制电路的输入端分别连接所述电源、所述逻辑控制电路的第一输出端和第二输出端，所述电流过零检测电路的输入端分别连接所述功率级电路和所述逻辑控制电路的第一输出端，其中，所述第一输出端用于 输出所述第一控制信号，所述第二输出端用于输出所述第三控制信号至所述峰值电流控制电路和所述功率级电路，所述峰值电流控制电路根据所述第三控制信号输出所述第二控制信号，所述功率级电路根据所述第三控制信号将所述电流峰值控制到预设峰值。
上述实施方式中，该电源管理电路无需含有时钟模块，使用逻辑控制电路来增加无时钟控制的可靠性，而且在电路满足一定条件下电流控制电路和逻辑控制电路中大部分模块处于待机状态，功耗较低。
可选的，所述峰值电流控制电路，包括：
钳位电路、电流镜像电路、第一电阻、第一电容、选择电路和第一子控制电路；
其中，所述第一电阻的第一端连接所述电源，所述第一电阻的第二端连接所述钳位电路；
所述钳位电路与所述选择电路、所述电流镜像电路连接，并接收从所述逻辑控制电路的第一输出端输出的所述第一控制信号；
所述选择电路与所述功率级电路的至少一个输出端连接，并接收所述逻辑控制电路的第三输出端输出的第六控制信号；
所述电流镜像电路还与所述电源、所述第一电容的第一端和所述第一子控制电路连接；
所述第一电容的两端分别与所述第一子控制电路连接，所述第一子控制电路接收所述逻辑控制电路的第二输出端输出的所述第三控制信号，所述第一子控制电路的输出端作为所述峰值电流控制电路的输出端；
所述钳位电路，用于对所述第一电阻的第二端的电压进行钳位，使得所述第一电阻的第二端的电压等于所述选择电路的输出电压；
所述镜像电流电路，用于对所述第一电阻的电流进行镜像；
所述选择电路，用于根据所述逻辑控制电路的第三输出端输出的第六控制信号，选择所述功率级电路的输出电压；
所述第一子控制电路，用于根据所述逻辑控制电路的第二输出端输出的所述第三控制信号控制所述峰值电流控制电路的输出端输出所述第二控制信号。
可选的，所述峰值电流控制电路，还包括：第二子控制电路；
其中，所述第二子控制电路分别与所述逻辑控制电路的第一输出端、所述电流镜像电路、所述第一电容的第二端以及所述第一子控制电路连接；
所述第二子控制电路，用于根据所述逻辑控制电路的第一输出端输出的第一控制信号，控制所述峰值电流控制电路的开启或关闭。
可选的，所述钳位电路，包括：
运算放大器和第一功率管；
其中，所述运算放大器的第一输入端连接所述第一电阻的第二端，所述运算放大器的第二输入端连接所述选择电路，所述运算放大器的第三输入端连接所述逻辑控制电路的第一输出端，所述运算放大器的输出端连接所述第一功率管的第一端，所述第一功率管的第二端连接所述第一电阻的第二端，所述第一功率管的第三端连接所述镜像电流电路。
可选的，所述选择电路，包括：
第一反相器、至少一个传输门；
其中，所述第一反相器的输入端连接所述逻辑控制电路的第三输出端；
所述第一反相器的输出端分别连接各个所述传输门的第一控制端；各个所述传输门的第二控制端分别连接所述逻辑控制电路的第三输出端；各个所述传输门的输入端分别对应连接所述功率级电路的各个输出端，各个所述传输门的输出端作为所述选择电路的输出端；所述传输门的数量与所述功率级电路的输出端的数量相同。
可选的，所述电流镜像电路，包括：
第二功率管、第三功率管、第四功率管和第五功率管；
其中，所述第二功率管的第一端与所述第三功率管的第一端连接，所述第二功率管的第一端和第二端短接，所述第二功率管的第二端连接所述钳位电路，所述第二功率管的第三端接地；
所述第三功率管的第二端连接所述第四功率管的第二端，所述第三功率管的第三端接地；
所述第四功率管的第二端和第一端短接，所述第四功率管的第一端还连接所述第五功率管的第一端，所述四功率管的第三端连接所述电源；
所述第五功率管的第二端连接所述第一电容；所述第五功率管的第三端连接所述电源。
可选的，所述第一子控制电路，包括：第一逻辑单元、第六功率管和第一比较器；
其中，所述第一逻辑单元的第一输入端连接所述逻辑控制电路的第二输出端，所述第一逻辑单元的第二输入端连接所述第一比较器的输出端，所述第一逻辑单元的输出端连接所述第六功率管的第一端；所述第一逻辑单元的输出端作为所述峰值电流控制电路的输出端；
所述第六功率管的第二端和第三端分别连接所述第一电容的两端，所述第六功率管的第二端接地；
所述第一比较器的第一输入端连接所述镜像电流电路，所述第一比较器的第二输入端接入第一参考电压。
可选的，所述第二子控制电路，包括：第七功率管，所述第七功率管的第一端接收所述逻辑控制电路的第一输出端输出的第一控制信号，所述第七功率管的第二端连接所述镜像电流电路，所述第七功率管的第三端接地。
可选的，所述第一逻辑单元包括：
第一D触发器、第二D触发器以及第一与门；
其中，所述第一D触发器的第一端作为所述第一逻辑单元的第二输入端，所述第一D触发器的第二端连接电源，所述第一D触发器的第三端连接所述第一与门的输出端，所述第一D触发器的输出端连接所述第一与门的第一输入端并作为所述第一逻辑单元的输出端；
所述第二D触发器的第一端作为所述第一逻辑单元的第一输入端，所述第二D触发器的第二端连接电源，所述第二D触发器的第三端连接所述第二D触发器的输出端，所述第二D触发器的输出端连接所述第一与门的第二输入端。
可选的，所述第一电阻的阻值可变或所述第一电容的电容可变。
可选的，所述第一参考电压可变。
可选的，所述逻辑控制电路，包括：
第三子控制电路，以及至少一个第二比较器；所述第二比较器的数量与所述功率级电路的输出端的数量相同；
其中，各个所述第二比较器的第一输入端分别与所述功率级电路的各个输出端连接；各个所述第二比较器的第二输入端分别输入第二参考电压；
各个所述第二比较器的输出端分别与所述第三子控制电路连接；
所述第三子控制电路的第一输出端用于根据各个所述第二比较器的输出端输出的信号输出所述第一控制信号至所述电流控制电路，所述第三子控制电路的第二输出端用于根据各个所述第二比较器的输出端输出的信号输出所述第三控制信号至所述电流控制电路和所述功率级电路，所述第三子控制电路的第四输出端用于输出所述第五控制信号至所述功率级电路。
上述实施方式中，该电源管理电路无需含有时钟模块，使用逻辑控制电路来增加无时钟控制的可靠性，使用电流过零检测电路对电流进行检测，当电流低于零时，输出翻转信号作为电源管理电路断电的信号，在下一次第二比较器翻转前，整个电源管理电路处于待机状态，只有第二比较器处于工作状态，功耗大幅降低。
可选的，所述第三子控制电路，包括：
第二逻辑单元、第三逻辑单元、逻辑控制单元、第一延时单元和第一输出控制单元；
其中，所述第二逻辑单元的第一输入端连接所述第一延时单元的输出端，所述第二逻辑单元的第二输入端和所述第一延时单元的输入端分别接收所述电流过零检测电路的输出端输出的所述第四控制信号；
所述第二逻辑单元的输出端连接所述第一输出控制单元的输入端，所述第一输出控制单元的输出端作为所述第三子控制电路的第一输出端；
所述第三逻辑单元的第一输入端连接所述峰值电流控制电路的输出端，所述第三逻辑单元的第二输入端连接所述第一输出控制单元的输出端，所述第三逻辑单元的输出端作为所述第三子控制电路的第二输出端；
所述逻辑控制单元的第一输入端接收所述电流过零检测电路的输出端输出的所述第四控制信号，所述逻辑控制单元的第二输入端连接所述第一输出控制单元的输出端，所述逻辑控制单元的第二输入端连接各个所述第二比较器的输出端，所述逻辑控制单元的输出端作为所述第三子控制电路的第四输出端。
上述实施方式中，由于第一延时单元产生的T1延时的存在，电流过零检测电路的输出端ZCD_OUT的上升沿到来后的T1时间内，逻辑控制电路的第一输出端LOOP_EN被钳位到低电平，这个时段内无论CMP_OUT1以及 CMP_OUT2的情况如何，电源管理电路都会强制进入待机状态一段时间，防止重载下电源管理电路在无时钟控制下连续工作产生逻辑错误，提高控制逻辑的可靠性。
可选的，所述第三子控制电路，还包括：第二延时单元；
其中，所述第二延时单元的输入端连接所述第一输出控制单元的输出端，所述第二延时单元的输出端分别连接所述第三逻辑单元和所述逻辑控制单元的第二输入端。
上述实施方式中，第二延时单元产生的延迟是为了给峰值电流控制电路足够的启动时间，以保障峰值电流控制的准确度。
可选的，所述第一输出控制单元包括：
第二反相器、第二与门和或门；
其中，所述第二反相器的输入端与所述第二逻辑单元的输出端连接，所述第二反相器的输出端与所述第二与门的第一输入端，所述第二与门的第二输入端连接所述或门的输出端；
所述或门的输入端分别连接各个所述第二比较器的输出端，所述第二与门的输出端作为所述第一输出控制单元的输出端。
可选的，所述功率级电路包括：输入控制单元、电感和至少一个第二输出控制单元；
其中，所述输入控制单元分别与所述电源和所述电感的第一端连接，所述输入控制单元还用于接收所述逻辑控制电路的第二输出端输出的第三控制信号，所述电感的第二端分别与各个所述第二输出控制单元连接；各个所述第二输出控制单元还用于接收所述逻辑控制电路的第四输出端输出的所述第五控制信号。
可选的，还包括：
第一驱动电路和第二驱动电路；
其中，所述逻辑控制电路的第二输出端通过所述第一驱动电路连接所述功率级电路；
所述逻辑控制电路的第四输出端通过所述第二驱动电路连接所述功率级电路。
可选的，所述输入控制单元，包括：
第八功率管和第九功率管；
其中，所述第八功率管的第一端连接所述第一驱动电路，所述第八功率管的第二端连接所述电源，所述第八功率管的第三端连接所述电感的第一端；
所述第九功率管的第一端连接所述第一驱动电路，所述第九功率管的第二端连接所述电感的第一端，所述第九功率管的第三端接地。
可选的，所述第二输出控制单元，包括：
第十功率管、第二电容、负载；
其中，所述第十功率管的第一端连接所述第二驱动电路，所述第十功率管的第二端连接所述电感的第二端，所述第十功率管的第三端连接所述第二电容的第一端，所述第二电容和所述负载的第二端接地，所述第二电容的第一端还连接所述负载的第一端。
下面将提供芯片和设备，其内容和效果可参考第一方面或第一方面的可选方式对应的内容和效果。
第二方面，本申请提供一种电源管理芯片，该芯片包括：如第一方面或第一方面的可选方式所述的电源管理电路。
第三方面，本申请提供一种电子设备，包括：
如第二方面中任一项所述的电源管理芯片。
本申请提供一种电源管理电路、芯片和设备，该电源管理电路，包括：电流控制电路、逻辑控制电路和功率级电路；通过电流控制电路和逻辑控制电路实现了对功率级电路的电流峰值的控制，使得功率级电路的输出纹波与效率可以通过电流峰值的控制来达到较好的平衡，通过电流峰值控制到预设峰值可减小输出纹波并提高电路的工作效率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的电源管理电路的结构示意图；
图2为本申请另一实施例提供的电源管理电路的结构示意图；
图3为本申请又一实施例提供的电源管理电路的结构示意图；
图4为本申请又一实施例提供的电源管理电路的结构示意图；
图5为本申请又一实施例提供的电源管理电路的结构示意图；
图6为本申请又一实施例提供的电源管理电路的结构示意图；
图7为本申请又一实施例提供的电源管理电路的结构示意图；
图8为本申请一实施例提供的峰值电流控制电路的结构示意图；
图9为本申请另一实施例提供的峰值电流控制电路的结构示意图；
图10为本申请又一实施例提供的峰值电流控制电路的结构示意图；
图11为图8-10中任意实施例提供的峰值电流控制电路的工作波形图；
图12为本申请一实施例提供的逻辑单元的结构示意图；
图13为本申请一实施例提供的逻辑单元的工作波形图；
图14为本申请一实施例提供的逻辑控制电路的结构示意图；
图15为本申请另一实施例提供的逻辑控制电路的结构示意图；
图16为本申请一实施例提供的逻辑控制电路的工作波形图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例，例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
相关技术的SIDO电路中，通常采用固定导通时间的控制模式，即每个 周期内功率管的导通时间固定，这使得SIDO的电感电流峰值由实时的输入输出电压被动决定。而电感电流的峰值电流大小直接决定了SIDO的输出纹波的大小并一定程度影响工作效率。而且由于SIDO节省了电感使用数量却增加了功率管数量，其工作效率通常低于传统单电感单输出的DC-DC架构。
如上所述，如何对电感电流进行有效控制成为本申请亟待解决的技术问题。为了解决该技术问题，本申请提供一种电源管理电路、芯片和设备。
本申请中通过电流控制电路对功率级电路的电流进行有效控制，并通过引入逻辑控制电路控制该电源管理电路是否进入待机模式，降低功耗，而且该逻辑控制电路中引入的两段延迟时间辅助无时钟控制，使得无时钟下电路的可靠性较高。
该电源管理电路可以应用于电子设备的电源管理芯片中，其中，电子设备例如包括手机、平板电脑、可穿戴设备、笔记本电脑等终端设备，电源管理电路可以用于给电子设备中不同的负载(例如MCU、音频IC、I/O等)供电，可节约电源管理芯片外的元器件体积。
本申请实施例中的功率级电路的电流指的是功率级电路中包括的电感的电流，功率级电路的电流峰值指的是功率级电路中包括的电感的电流峰值。
本申请以下实施例中结合图示以电源管理电路具有两个输出端分别输出不同电压为例进行说明。
图1为本申请一实施例提供的电源管理电路的结构示意图，如图1所示，该电源管理电路，包括：
电流控制电路、逻辑控制电路和功率级电路；
其中，功率级电路连接至电源V IN；功率级电路包括至少一个输出端(图1中以两个输出端V OUT1、V OUT2为例)，各个输出端分别用于输出电压，在具有多个输出端时，用于输出电压向不同的电路模块供电；
电流控制电路，连接至电源V IN、逻辑控制电路和至少一个输出端，并接收从功率级电路输出的各个输出电压，电流控制电路用于根据各个输出电压以及所述逻辑控制电路输出的第一控制信号检测功率级电路的电流，并在所述电流达到预设峰值后输出第二控制信号至逻辑控制电路；
逻辑控制电路，连接至所述至少一个输出端，逻辑控制电路用于根据各个输出电压向电流控制电路输出第一控制信号，所述第一控制信号用于所述 电流控制电路开启对功率级电路的电流的检测，逻辑控制电路根据所述电流控制电路输出的第二控制信号输出第三控制信号至所述功率级电路，以将所述功率级电路的电流峰值控制到预设峰值。
其中，功率级电路例如可以是单电感多输出电路，以下通过单电感双输出电路进行举例说明。
具体的，逻辑控制电路分别将功率级电路的输出端V OUT1和V OUT2与参考电压V REF1和V REF2进行比较，若V OUT1或V OUT2任意一路低于对应的参考电压，逻辑控制电路控制与电流控制电路连接的输出端LOOP_EN输出第一控制信号，该第一控制信号可以是一个跳变信号，例如输出端LOOP_EN原为低电平，则输出高电平，电流控制电路进入工作状态；同时，当V OUT1或V OUT2任意一路低于对应的参考电压时，逻辑控制电路控制与功率级电路连接的输出端Dn输出第三控制信号，该第三控制信号可以是一个跳变信号，例如输出端原为低电平，则输出高电平，驱动功率级电路，使得功率级电路中的电流缓慢上升，电流控制电路检测该电流的电流值，当电流值到达预设峰值后输出端CS_OUT输出第二控制信号到逻辑控制电路，逻辑控制电路根据接收到的第二控制信号通过与功率级电路连接的输出端Dn输出第三控制信号控制功率级电路，使得电流缓慢下降，从而实现对功率级电路中电流峰值的控制。
其中，预设峰值可根据输出纹波以及输出电压等需求预先确定，例如峰值越大可能导致输出纹波越大，但若减小功率级电路的电流峰值则会影响输出电压的大小，从而影响电源管理电路的工作效率，在实际应用中，可根据实际需求确定预设峰值使得输出纹波以及电源管理电路的工作效率达到一定的平衡。
对于功率级电路的各个输出端，可用于给不同的供电模块进行供电，例如可输出不同的电压，可通过各个输出端对应的参考电压进行控制，各个输出端的电压一般被控制在对应的参考电压，在其他实施例中，各个输出端也可输出相同的电压，本申请实施例对此并不限定。
在一实施例中，各个输出端对应的预设峰值相同，在其他实施例中各个输出端对应的预设峰值也可不同，本申请实施例对此并不限定。
进一步的，预设峰值也可根据电路实际运行情况进行调节，电流控制电 路可通过对该电流控制电路中的部分参数进行调节，从而实现对预设峰值的调节。
本实施例的电路，通过电流控制电路和逻辑控制电路实现了对功率级电路的电流峰值的控制，使得功率级电路的输出纹波与效率可以通过电流峰值的控制来达到较好的平衡，通过将电流峰值控制到预设峰值可减小输出纹波并提高电路的工作效率。
进一步的，相关技术中需要基于时钟模块的输出来实现SIDO，即存在需要常开的耗电模块(时钟模块)，这使得待机模式下SIDO电路的功耗受限于时钟模块。而本申请中为了减少功耗可采用如下的电路结构：在图1所示实施例的基础上，如图2所示，电流控制电路，包括：
峰值电流控制电路和电流过零检测电路；
其中，峰值电流控制电路的输出端用于输出所述第二控制信号至所述逻辑控制电路，电流过零检测电路的输出端用于输出第四控制信号至逻辑控制电路，所述逻辑控制电路根据所述第四控制信号输出第五控制信号至所述功率级电路，以控制所述功率级电路的输出；
所述峰值电流控制电路的输入端分别连接所述电源V IN、所述逻辑控制电路的第一输出端LOOP_EN和第二输出端D1，所述电流过零检测电路的输入端分别连接所述功率级电路和所述逻辑控制电路的第一输出端LOOP_EN，其中，所述第一输出端用于输出所述第一控制信号，所述第二输出端用于输出所述第三控制信号至所述峰值电流控制电路和所述功率级电路，所述峰值电流控制电路根据所述第三控制信号输出所述第二控制信号，所述功率级电路根据所述第三控制信号将所述电流峰值控制到预设峰值。
其中，峰值电流控制电路的输出端CS_OUT输出第二控制信号，电流过零检测电路的输出端ZCD_OUT输出第四控制信号。
电流过零检测电路用于检测功率级电路的电流是否到零，若降到零，则输出端ZCD_OUT输出第四控制信号，使得功率级电路的输出端的功率管关断，停止输出。具体的，输出端ZCD_OUT的第四控制信号输出到逻辑控制电路，逻辑控制电路根据所述第四控制信号输出第五控制信号使得功率级电路的输出端的功率管关断，图2中逻辑控制电路的输出端Dx输出第五控制信号。此时，图1中输出端Dn为图2中第二输出端D1。
峰值电流控制电路用于控制功率级电路的电流的峰值，具体的，逻辑控制电路分别将功率级电路的输出端V OUT1和V OUT2与参考电压V REF1和V REF2进行比较，若V OUT1或V OUT2任意一路低于对应的参考电压，逻辑控制电路控制的第二输出端D1输出第三控制信号，该第三控制信号可以是一个跳变信号，例如第二输出端D1原为低电平，则输出高电平，即从逻辑控制电路的第二输出端D1输出的第三控制信号上升沿来临时，功率级电路的功率管导通，功率级电路的电流上升，峰值电流控制电路根据第三控制信号对功率级电路输出的电流的电流值进行检测当该电流的电流值达到预设峰值(VREF)后峰值电流控制电路使得输出端CS_OUT输出的第二控制信号置高，进而使得逻辑控制电路的第二输出端D1输出的第三控制信号变为低电平，第三控制信号输入至功率级电路，控制功率级电路的输入端的功率管关断，使得功率级电路的电流下降，从而实现了对峰值电流的控制。
本申请实施例中在电流下降过程中，电流控制电路还可以持续检测功率级电路中电流的电流值，当该电流的电流值降到零时，电流控制电路的输出端ZCD_OUT输出第四控制信号到逻辑控制电路，逻辑控制电路根据输出端ZCD_OUT的第四控制信号输出第五控制信号控制功率级电路关断(即功率级电路中输出控制单元的功率管关断，此时功率级电路中输入控制单元的功率管也是关断的)，同时，逻辑控制电路控制电流控制电路进入待机状态节省功耗，例如将与电流控制电路连接的第一输出端LOOP_EN从高电平变为低电平，从而使得电流控制电路进入待机状态。上述方案实现了电源管理电路无需引入时钟信号的低功耗方案，在进入待机状态下整体的功耗大幅降低，此时功率级电路中功率管不工作，电流控制电路不工作，因此功耗较少，而现有的方案中如果在待机状态下关闭时钟模块，则无法控制功率级电路中功率管的导通，因此无论在正常工作还是待机状态均无法关闭时钟模块，时钟模块所产生的损耗将使得电路的功耗远大于本申请实施例的电路。
在一实施例中，如图3所示，是一种实施例的电源管理电路的电路结构图，其与图2所示的电源管理电路大致相同，不同之处主要在于功率级电路可以采用以下具体结构：
功率级电路包括：输入控制单元、电感和至少一个第二输出控制单元(图3中以两个第二输出端为例进行说明)；
其中，输入控制单元分别与电源V IN和电感L的第一端连接(即，输入控制单元连接在电源V IN和电感L第一端之间)，输入控制单元还与逻辑控制电路的第二输出端D1连接，用于接收逻辑控制电路的第二输出端D1输出的第三控制信号，电感L的第二端分别与各个第二输出控制单元连接；各个第二输出控制单元还与逻辑控制电路的第四输出端D2、D3连接，用于接收逻辑控制电路的第四输出端输出的第五控制信号。每个第二输出控制单元的输出端作为功率级电路的输出端。此时，图2中输出端Dx为图3中第四输出端D2或D3。
具体的，如图3所示，逻辑控制电路分别将功率级电路的输出端V OUT1和V OUT2与参考电压V REF1和V REF2进行比较，若V OUT1或V OUT2任意一路低于对应的参考电压，逻辑控制电路控制第一输出端LOOP_EN输出第一控制信号，该第一控制信号可以是一个跳变信号，例如第一输出端LOOP_EN原为低电平，则输出高电平，电流控制电路(即峰值电流控制电路和电流过零检测电路)进入工作状态，假设是V OUT1先低于对应的参考电压，逻辑控制电路控制第二输出端D1输出第三控制信号和第四输出端D2输出第五控制信号，分别控制功率级电路的输入控制单元和第二输出控制单元，使得电源V IN与电感导通，V OUT1输出电压，其中，V OUT1和V OUT2不同时输出电压，例如V OUT1先于V OUT2低于参考电压时，则第四输出端D2输出第五控制信号，以使第二输出控制单元控制V OUT1输出电压。假设V OUT1输出电压，功率级电路中电感L的电流缓慢上升，此时峰值电流控制电路同样输入第三控制信号(例如高电平)，峰值电流控制电路检测电感中电流的电流值，当电流的电流值到达预设峰值后输出端CS_OUT输出第二控制信号到逻辑控制电路，逻辑控制电路根据第二控制信号控制第二输出端D1的第三控制信号，该第三控制信号可以是一个跳变信号，例如第二输出端D1由高电平变为低电平，控制功率级电路中输入控制单元使得电源V IN与电感不导通，电感中电流缓慢下降。电流过零检测电路检测电感中电流的电流值，当电流值降到零时，电流过零检测电路的输出端ZCD_OUT输出第四控制信号到逻辑控制电路，逻辑控制电路根据第四控制信号控制第四输出端D2输出第五控制信号，该第五控制信号可以是一个跳变信号，例如第二输出端D2由高电平变为低电平，控制第二输出控制单元使得V OUT1停止输出电压，同时，逻辑控制电路控制第一 输出端LOOP_EN的第一控制信号跳变，例如第一输出端LOOP_EN由高电平变为低电平，峰值电流控制电路以及电流过零检测电路进入待机状态节省功耗。
在一实施例中，如图4所示，该电源管理电路，还包括：
第一驱动电路和第二驱动电路；
其中，逻辑控制电路的第二输出端D1通过第一驱动电路连接功率级电路，如连接功率级电路的输入控制单元；
逻辑控制电路的第四输出端D2或D3通过第二驱动电路连接功率级电路，如连接功率级电路的第二输出控制单元。
第一驱动电路根据逻辑控制电路的第二输出端D1的电平高低驱动功率级电路的输入控制单元的功率管的导通或关断；第二驱动电路根据逻辑控制电路的第四输出端D2或D3的电平高低驱动功率级电路的输出控制单元的功率管的导通启或关断。
上述实施方式中，通过第一驱动电路和第二驱动电路，实现了输入控制单元和第一输出控制单元对功率级电路各个输出端输出电压控制的可靠性。
其中，如图5所示，图3或图4所示电路结构中的输入控制单元可以采用如下结构，该输入控制单元包括：
第八功率管M1和第九功率管M2；
其中，第八功率管M1的第一端，例如栅极连接第一驱动电路的输出端，第八功率管M1的第二端，例如源极连接电源V IN，第八功率管M1的第三端，例如漏极连接电感L的第一端；其中，逻辑控制电路的第二输出端D1连接第一驱动电路的输入端，输出第三控制信号至第一驱动电路；
第九功率管M2的第一端，例如栅极连接第一驱动电路的输出端，第九功率管的第二端，例如漏极连接电感L的第一端，第九功率管的第三端，例如源极接地。其中，逻辑控制电路的第四输出端D2或D3连接第二驱动电路的输入端，输出第五控制信号至第二驱动电路，第九功率管M2的漏极可以作为输入控制单元的输出端SW连接到电感L的第一端，并连接到电流过零检测电路。
第一驱动电路根据逻辑控制电路的第二输出端D1输出的第三控制信号的电平，决定控制第八功率管M1或第九功率管M2。
其中，各个第二输出控制单元的结构可以相同或不同，以下以结构相同为例进行说明，例如每个第二输出控制单元采用如下结构，如图5所示，该第二输出控制单元包括：
第十功率管M3或M4、第二电容C O1或C O2、负载；
其中，第十功率管的第一端，例如栅极连接第二驱动电路，第十功率管的第二端，例如漏极连接电感的第二端，第十功率管的第三端，例如源极连接第二电容的第一端，第二电容和负载的第二端接地，第二电容的第一端还连接负载的第一端。
如图5所示，V OUT1对应的第二输出控制单元中的第十功率管为M3，V OUT2对应的第二输出控制单元中的第十功率管为M4。
第二驱动电路根据逻辑控制电路的第四输出端D2或第四输出端D3输出的电平，决定控制第十功率管M3或第十功率管M4。
其中，如图6、7所示，第二电容可以为电容C O1、C O2，如图7所示，负载表示为电阻R L1、R L2。
对于图6、图7中所示的电源管理电路实现原理如下：逻辑控制电路分别将功率级电路的输出端V OUT1和V OUT2与参考电压V REF1和V REF2进行比较，若V OUT1或V OUT2任意一路低于对应的参考电压，逻辑控制电路控制第一输出端LOOP_EN输出第一控制信号，该第一控制信号可以是一个跳变信号，例如第一输出端LOOP_EN原为低电平，则输出高电平，电流控制电路(即峰值电流控制电路和电流过零检测电路)进入工作状态，同时，逻辑控制电路控制第二输出端D1输出第三控制信号和第四输出端D2或D3输出第五控制信号，分别通过第一驱动电路和第二驱动电路驱动功率级电路的输入控制单元和第二输出控制单元，使得功率级电路中第八功率管M1和第十功率管(M3或M4)导通，其中，M3与M4不同时开启，其具体开启情况由V OUT1和V OUT2的输出决定，如V OUT1先于V OUT2低于参考电压时，则M3开启。设此时为M1和M3开启，则功率级电路中电感L的电流缓慢上升，峰值电流控制电路检测电感中电流的电流值，当该电流的电流值到达预设峰值后输出端CS_OUT输出第二控制信号到逻辑控制电路，逻辑控制电路控制第二输出端D1输出第三控制信号，该控制信号可以是一个跳变信号，例如第二输出端D1由高电平变为低电平，通过第一驱动电路关闭第八功率管M1并开启第 九功率管M2；此时第九功率管M2与第十功率管M3同时开启，电感中电流缓慢下降。电流过零检测电路检测电感中电流的电流值(即检测SW处的电流值)，当电流值降到零时输出端ZCD_OUT输出第四控制信号到逻辑控制电路，逻辑控制电路控制第四输出端D2输出第五控制信号，该第五控制信号可以是一个跳变信号，例如第二输出端D2由高电平变为低电平，通过第二驱动电路关断功率管M3，同时，逻辑控制电路控制第一输出端LOOP_EN由高电平变为低电平，峰值电流控制电路以及电流过零检测电路进入待机状态节省功耗。其中，第八功率管M1和第九功率管M2通过逻辑控制电路的第二输出端D1控制，状态互斥，即第八功率管M1开启时，第九功率管M2关闭；第九功率管M2开启时第八功率管M1关闭。
本申请实施例中通过逻辑控制电路增加了电源管理电路在无时钟模块下运行的可靠性，即通过逻辑控制电路实现对电流控制电路工作的控制，以及对功率级电路的控制。
在一实施例中，如图6、图7所示，逻辑控制电路具体可以包括：
第三子控制电路，以及至少一个第二比较器；第二比较器的数量与功率级电路的输出端的数量相同，也可以与第二输出控制单元的数量相同；
其中，各个第二比较器的第一输入端分别与功率级电路的各个输出端连接；各个第二比较器的第二输入端分别输入第二参考电压；
各个第二比较器的输出端分别与第三子控制电路连接；
第三子控制电路的第一输出端LOOP_EN用于根据各个所述第二比较器的输出端输出的信号输出所述第一控制信号至电流控制电路；第三子控制电路的第二输出端D1用于根据各个所述第二比较器的输出端输出的信号输出所述第三控制信号至所述电流控制电路和所述功率级电路，所述第三子控制电路的第四输出端用于输出所述第五控制信号至功率级电路。
具体的，第二比较器CMP1和CMP2分别将功率级电路的输出端V OUT1和V OUT2与参考电压V REF1和V REF2进行比较，当第二比较器CMP1或CMP2的输出电压CMP_OUT1或CMP_OUT2由低翻转至高时，代表V OUT1或V OUT2低于参考电压，第三子控制电路检测到CMP_OUT1或CMP_OUT2的由低到高翻转变化后，第三子控制电路控制第一输出端LOOP_EN变为高电平，此时逻辑控制电路的第二输出端D1输出第三控制信号，例如由低电平翻转到 高电平，通过第一驱动电路驱动功率级电路的输入控制单元，使得电源V IN与电感导通，后续控制逻辑可参考前述实施例，此处不再赘述。
本申请实施例提供的电路使用电流过零检测电路对电流进行检测，当电流低于零时，输出翻转信号作为该电源管理电路断电的信号，在下一次第二比较器翻转前，整个电源管理电路中大部分电路结构处于待机状态，如电流控制电路、第三子控制电路以及功率级电路中的输入控制单元和输出控制单元，只有第二比较器处于工作状态，整体静态功耗大幅降低。
在一实施例中，如图8所示，峰值电流控制电路包括：
钳位电路、电流镜像电路、第一电阻R、第一电容C、选择电路、第一子控制电路；
其中，第一电阻R的第一端连接电源V IN，第一电阻R的第二端连接钳位电路；
钳位电路与选择电路、电流镜像电路连接，并接收从逻辑控制电路的第一输出端LOOP_EN输出的所述第一控制信号；
选择电路与功率级电路的各个输出端(如V OUT1和V OUT2)连接，并接收逻辑控制电路的第三输出端V OUT_SEL输出的第六控制信号；
电流镜像电路还与电源V IN、第一电容C的第一端和第一子控制电路连接；
第一电容C的两端分别与第一子控制电路连接，第一子控制电路接收逻辑控制电路的第二输出端D1输出的所述第三控制信号，第一子控制电路的输出端作为峰值电流控制电路的输出端CS_OUT；
钳位电路，用于对第一电阻R的第二端的电压V C进行钳位，使得第一电阻R的第二端的电压V C等于选择电路的输出电压V OUT_IN；
镜像电流电路，用于对第一电阻R的电流I C进行镜像；
选择电路，用于根据逻辑控制电路的第三输出端V OUT_SEL输出的第六控制信号，选择功率级电路的输出电压V OUT_IN；
第一子控制电路，用于根据所述逻辑控制电路的第二输出端输出的所述第三控制信号控制所述峰值电流控制电路的输出端CS_OUT输出第二控制信号。
在一实施例中，逻辑控制电路的第三输出端V OUT_SEL在V OUT1低于参考电 压，即第二比较器CMP_OUT1输出电压由低翻转至高时，输出高电平，此时选择电路的输出电压V OUT_IN等于V OUT1；第三输出端V OUT_SEL在V OUT2低于参考电压，即第二比较器CMP_OUT2输出电压由低翻转至高时，输出低电平，此时选择电路的输出电压V OUT_IN等于V OUT2。
峰值电流控制电路使用钳位电路对电压V C进行钳位，使得V C等于V OUT_IN，经过电流镜像后I C给第一电容C进行充电。当逻辑控制电路的第二输出端D1输出的第三控制信号上升沿来临时，即V OUT1或V OUT2低于参考电压，第二比较器CMP1或CMP2的输出电压CMP_OUT1或CMP_OUT2由低翻转至高时，逻辑控制电路的第二输出端D1输出的第三控制信号控制功率级电路的输入控制单元，使得电源V IN与电感导通，并且第一子控制电路根据第二输出端D1输出的第三控制信号使得输出端CS_OUT输出的第二控制信号置低，第一子控制电路控制第一电容C进行充电，V C逐渐上升至第一参考电压V REF后第一子控制电路控制输出端CS_OUT置高，逻辑控制电路根据输出端CS_OUT的电平控制第二输出端D1的电平翻低，并且逻辑控制电路的第二输出端D1输出的第三控制信号控制功率级电路的输入控制单元，使得电源V IN与电感不导通。
进一步的，如图9所示，峰值电流控制电路，还可以包括：第二子控制电路；
其中，第二子控制电路分别与逻辑控制电路的第一输出端LOOP_EN、电流镜像电路、第一电容C的第二端以及第一子控制电路连接；
第二子控制电路，用于根据逻辑控制电路的第一输出端LOOP_EN输出的第一控制信号，控制峰值电流控制电路的开启或关闭。通过控制峰值电流控制电路的开启或关闭可降低电源管理电路的功耗。
具体的，峰值电流控制电路对逻辑控制电路的第二输出端D1的下降沿形成控制，可决定电感的电流峰值，该电流峰值IL_peak可以表示为IL_peak＝(R×C×V REF)/L，其中L为功率级电路的电感，V REF为第一子控制电路输入的第一参考电压。可以通过控制R、C、V REF以及L的值来对电感的电流峰值进行调节，即对预设峰值进行调节。
在一实施例中第一电阻R的阻值可变或所述第一电容C的电容可变；在一实施例中，第一参考电压V REF可变。
在本实施例中，可以使用多档位阻值可调的电阻R以间接实现多档位峰值可调的电感电流设计。
具体的，峰值电流控制电路使用钳位电路对电压V C进行钳位，使得V C等于V OUT_IN，而V OUT_IN通过选择电路可设为V OUT1或V OUT2，具体可通过逻辑控制电路的第三输出端V OUT_SEL输出的第六控制信号确定。电流I C＝(V IN-V OUT_IN)/R，经过电流镜像后I C给电容C进行充电。当逻辑控制电路的第二输出端D1输出的第三控制信号上升沿来临时，第一子控制电路输出端CS_OUT置低，MN4关闭，使得第一电容进行充电，V C逐渐上升至第一参考电压V REF后第一子控制电路控制输出端CS_OUT置高，进而控制第二输出端D1输出的第三控制信号翻低。上述过程为峰值电流控制电路的一个典型工作过程，输出端CS_OUT即为峰值电流控制电路的输出，用于控制D1的占空比。输出端CS_OUT的高电平时长可以表示为T＝V REF×R×C/(V IN-V OUT_IN)，故电感的电流峰值IL_peak＝T×(V IN-V OUT_IN)/L＝V REF×R×C/L。
上述峰值电流控制电路，通过改变第一电阻R的阻值、第一电容C的电容或第一参考电压，进而使得电流峰值可调节，间接地调节了电路的输出纹波以及工作效率。
具体的，峰值电流控制电路通过电流I C的值可实现对电感中电流的电流值的检测。
在一实施例中，钳位电路，包括：
运算放大器EA和第一功率管MP1；
其中，运算放大器EA的第一输入端(如图10中负输入端)连接第一电阻R的第二端，所述运算放大器EA的第二输入端(如图10中正输入端)连接选择电路的输出端V OUT_IN，运算放大器EA的第三输入端连接逻辑控制电路的第一输出端LOOP_EN，运算放大器EA的输出端连接第一功率管MP1的第一端(如栅极)，第一功率管MP1的第二端(如源极)连接第一电阻R的第二端，第一功率管MP1的第三端(如漏极)连接镜像电流电路(如图10所示，第一功率管MP1的漏极连接镜像电流电路的第二功率管MN1的漏极)。
其中，如图10所示，第一功率管MP1的第二端(如源极)还与运算放大器EA的负输入端连接。
在一实施例中，选择电路，包括：
第一反相器INV1、至少一个传输门；
其中，第一反相器INV1的输入端连接逻辑控制电路的第三输出端V OUT_SEL；
第一反相器INV1的输出端分别连接各个传输门的第一控制端；各个传输门的第二控制端分别连接逻辑控制电路的第三输出端V OUT_SEL；各个传输门的输入端分别对应连接功率级电路的各个输出端，各个传输门的输出端作为选择电路的输出端V OUT_IN。其中，传输门的数量与功率级电路的输出端的数量相同
具体的，图10中以功率级电路具有两个输出端，对应两个传输门G1和G2为例进行说明。
第一反相器INV1的输入端连接峰值电流控制电路的输入信号V OUT_SEL(即逻辑控制电路的第三输出端V OUT_SEL输出的第六控制信号)，第一反相器INV1的输出端接传输门G1的负控制端；传输门G1的正控制端接峰值电流控制电路的输入信号V OUT_SEL，传输门G1的输入端接峰值电流控制电路的输入信号V OUT1，传输门G1的输出端接传输门G2的输出端V OUT_IN；传输门G2的正控制端接第一反相器INV1的输出端，传输门G2的负控制端接峰值电流控制电路的输入信号V OUT_SEL，传输门G2的输入端接峰值电流控制电路的输入信号V OUT2。即选择电路的输出端V OUT_IN的电压要么等于V OUT1的电压，要么等于V OUT2的电压。
在一实施例中，如图10所示，电流镜像电路，包括：
第二功率管MN1、第三功率管MN2、第四功率管MP2和第五功率管MP3；
其中，第二功率管MN1的第一端(如栅极)与第三功率管MN2的第一端(如栅极)连接，第二功率管MN1的第一端(如栅极)和第二端(如漏极)短接，第二功率管MN1的第二端连接钳位电路(如钳位电路的第一功率管MP1的漏极)，所述第二功率管的第三端(源极)接地；
第三功率管MN2的第二端(漏极)连接第四功率管MP2的第二端(漏极)，第三功率管MN2的第三端(源极)接地；
第四功率管MP2的第二端(漏极)和第一端(栅极)短接，第四功率管 MP2的第一端(栅极)还连接第五功率管MP3的第一端(栅极)，所述四功率管的第三端(源极)连接所述电源V IN；
第五功率管MP3的第二端(漏极)连接第一电容C；第五功率管MP3的第三端(源极)连接电源V IN。
在一实施例中，第一子控制电路，包括：第一逻辑单元、第六功率管MN4和第一比较器Comp；
其中，第一逻辑单元的第一输入端DOWN_IN连接逻辑控制电路的第二输出端D1，第一逻辑单元的第二输入端UP_IN连接第一比较器的输出端V C_OUT，第一逻辑单元的输出端CS_OUT连接第六功率管MN4的第一端(栅极)；第一逻辑单元的输出端CS_OUT作为峰值电流控制电路的输出端CS_OUT；
第六功率管MN4的第二端(源极)和第三端(漏极)分别连接电容C的两端，第六功率管的第二端(源极)接地；即第六功率管MN4的漏极接第一比较器Comp的第一输入端(正输入端)；
第一比较器Comp的第一输入端连接镜像电流电路，如图10所示，第一比较器Comp的第一输入端连接镜像电流电路的第五功率管MP3的第二端(漏极)，第一比较器Comp的第二输入端(负输入端)接入第一参考电压V REF。
其中，如图10所示，第一电容C的上极板接第一比较器Comp的正输入端，第一电容C的下极板接地。
在一实施例中，如图10所示，第二子控制电路，包括：第七功率管MN3，第七功率管MN3的第一端(栅极)连接逻辑控制电路的第一输出端LOOP_EN，第七功率管MN3的第二端(漏极)连接镜像电流电路(即第三功率管MN2的第一端)，第七功率管MN3的第三端(源极)接地。第七功率管MN3的漏极连接第三功率管MN2的栅极。
如图11所示，信号V OUT_SEL为峰值电流控制电路的输入信号，当其为高电平时，功率级电路中V OUT1支路正在工作；当其为低电平时，功率级电路中V OUT2支路正在工作。信号V OUT_SEL可以实时地将信号V OUT_IN从V OUT1和V OUT2之间来回切换以实现精确的电流控制。图11中展示的逻辑关系为，D1上升沿控制CS_OUT翻低，峰值电流控制电路开始对电容C充电，当V C上 升至V REF时，V C_OUT产生脉冲使得CS_OUT翻高，CS_OUT输出到逻辑控制电路使得D1翻低。整个过程使得D1的高电平的保持时间等同于电容C充电所需时间。其中，D1上升沿由第二比较器控制。
在一实施例中，如图12所示，第一逻辑单元包括：
第一D触发器、第二D触发器以及第一与门；
其中，第一D触发器的第一端CLK作为第一逻辑单元的第二输入端UP_IN，第一D触发器的第二端D连接电源VDD，第一D触发器的第三端CLR连接第一与门的输出端，所述第一D触发器的输出端Q连接第一与门的第一输入端并作为所述第一逻辑单元的输出端OUT，；
第二D触发器的第一端CLK作为第一逻辑单元的第一输入端DOWN_IN，第二D触发器的第二端D连接电源VDD，第二D触发器的第三端CLR连接第二D触发器的输出端Q，第二D触发器的输出端Q连接第一与门的第二输入端。
如图12所示，在第一逻辑单元中，通过使用两个含异步清零的D触发器以及与门，使得当UP_IN上升沿来临时，OUT信号翻高；当DOWN_IN信号上升沿来临时，OUT信号翻低。
图13为逻辑单元电路工作波形，UP_IN和DOWN_IN信号分别控制输出信号OUT的翻高和翻低。在本申请实施例中，以下第二逻辑单元、第三逻辑单元、第四逻辑单元均可以采用上述第一逻辑单元的电路结构。
在一实施例中，如图14所示，第三子控制电路，包括：
第二逻辑单元、第三逻辑单元、逻辑控制单元、第一延时单元和第一输出控制单元；
其中，第二逻辑单元的第一输入端DOWN_IN连接所述第一延时单元的输出端，第二逻辑单元的第二输入端UP_IN和第一延时单元的输入端分别连接电流过零检测电路的输出端ZCD_OUT，分别接收电流过零检测电路的输出端ZCD_OUT输出的所述第四控制信号；
第二逻辑单元的输出端OUT连接第一输出控制单元的输入端，第一输出控制单元的输出端作为第三子控制电路的第一输出端LOOP_EN；
所述第三逻辑单元的第一输入端DOWN_IN连接峰值电流控制电路的输出端CS_OUT，第三逻辑单元的第二输入端UP_IN连接第一输出控制单元的 输出端，第三逻辑单元的输出端OUT作为第三子控制电路的第二输出端D1；
逻辑控制单元的第一输入端连接所述电流过零检测电路的输出端ZCD_OUT，接收电流过零检测电路的输出端ZCD_OUT输出的所述第四控制信号，逻辑控制单元的第二输入端连接第一输出控制单元的输出端LOOP_EN，逻辑控制单元的第三输入端与各个第二比较器的输出端(如CMP_OUT1、CMP_OUT2)连接，逻辑控制单元的输出端OUT作为所述第三子控制电路的第四输出端D2或D3。
在一实施例中，逻辑控制单元例如可以包括至少两个逻辑单元，与图12中结构类似，一个逻辑单元对应一个第二比较器，例如当第二比较器的输出端CMP_OUT1为高电平时，控制第三子控制电路的第四输出端D2输出信号，控制功率级电路中V OUT1对应的第二输出控制单元。
其中，第一输出控制单元还与各个第二比较器的输出端(如CMP_OUT1、CMP_OUT2)连接。
其中，如图15所示，第一延时单元包括一电阻R1和一电容C1。
在一实施例中，如图14所示，第三子控制电路，还包括：第二延时单元；
其中，第二延时单元的输入端连接第一输出控制单元的输出端LOOP_EN，第二延时单元的输出端分别连接第三逻辑单元和第四逻辑单元的第二输入端UP_IN。
其中，如图15所示，第二延时单元包括一电阻R2和一电容C2。
其中，第一输出控制单元包括：
第二反相器INV2、第二与门以及或门；
其中，第二反相器INV2的输入端与第二逻辑单元的输出端OUT连接，第二反相器INV2的输出端与第二与门的第一输入端，第二与门的第二输入端连接或门的输出端；
或门的输入端分别连接各个第二比较器的输出端(如CMP_OUT1、CMP_OUT2)，第二与门的输出端作为第一输出控制单元的输出端LOOP_EN。
如图15所示，ZCD_OUT的上升沿将控制LOOP_EN输出低电平，此时电路中电流控制模块和逻辑控制模块进入待机的低功耗状态；当CMP_OUT1和CMP_OUT2至少有一个为高电平时，输出LOOP_EN变为高电平，此时环路重新工作。由于R1和C1产生的T1延时的存在，ZCD_OUT的上升沿到 来后的T1时间内，LOOP_EN被钳位到低电平，这个时段内无论CMP_OUT1以及CMP_OUT2的情况如何，电源管理电路会强制进入待机状态一段时间，这个设计是为了防止重载下环路在无时钟控制下连续工作产生逻辑错误，提高控制逻辑的可靠性。
进一步的，当LOOP_EN翻高后，经过R2和C2产生的T2延时后，D1和D2翻高，功率管开启，T2延迟是为了给峰值电流控制电路足够的启动时间，以保障峰值电流控制的准确度。此外，D1和D2的下降沿分别由CS_OUT和ZCD_OUT的上升沿控制。
图16为逻辑控制电路的工作波形，主要的工作逻辑为，D1和D2的上升沿由ZCD_OUT、CMP_OUT1和CMP_OUT2共同决定，其中ZCD_OUT保障了每个工作周期电感电流降至零；由于引入了T1和T2延迟，每两个D1或D2的上升沿之间至少间隔T1+T2的时长，限制了最大工作频率<1/(T1+T2)。
图16中当CMP_OUT1由低翻转至高时，T1之后LOOP_EN翻高(由于ZCD_OUT的上升沿到来后的T1时间内，LOOP_EN被钳位到低电平)，逻辑控制电路控制D1与D2变为高电平(延迟T2)。D1和D2的下降沿分别由CS_OUT和ZCD_OUT的上升沿控制，其中CS_OUT控制D1下降沿使得功率管M1关闭，间接控制了电流峰值；ZCD_OUT控制功率M3或M4关闭，防止电流反流。对于CMP_OUT2的情况类似，此处不再赘述。
上述逻辑控制电路中，引入了两段独立的延迟来辅助无时钟控制，使得无时钟下环路控制稳定可靠。
本申请实施例的电路以单电感双输出的SIDO为例进行说明，所述的电流控制电路和逻辑控制电路的控制逻辑还可以应用于其他种类的单电感多输出电路，如单电感多输出的BOOST、BUCK-BOOST电路等等。与传统常见的SIDO电路不同点在于，本申请实施例的电路不需要时钟进行控制，节省了相应的功耗；引入了峰值电流控制电路实时的对电流峰值进行控制，并实现了电流峰值的多段可调节。为了提高无时钟控制的可靠性，引入了逻辑控制电路，该电路通过延迟T1和T2插入到每个工作周期中；峰值电流控制电路采样功率级电路的输入、输出电压并控制D1的占空比以实现电流的峰值控制。
本申请还提供一种电源管理芯片，该芯片可包括前述任一实施例所述的电源管理电路。
其中，还可以包括其他电路模块，本申请对此并不限定。
本实施例的内容和效果可参考前述电源管理电路实施例部分，对此不再赘述。
本申请还提供一种电子设备，该电子设备可包括前述任一实施例所述的电源管理芯片。
其中，电子设备例如包括手机、平板电脑、可穿戴设备等终端设备。该电子设备例如还包括电源、处理器、存储器等。
本实施例的内容和效果可参考前述电源管理电路实施例部分，对此不再赘述。

Claims (24)

  1. 一种电源管理电路，其特征在于，包括：
    功率级电路，连接至电源，所述功率级电路包括至少一个输出端，用于输出电压；
    电流控制电路，连接至所述电源、逻辑控制电路和所述至少一个输出端，所述电流控制电路用于接收从所述至少一个输出端输出的各个输出电压，根据所述各个输出电压以及所述逻辑控制电路输出的第一控制信号检测所述功率级电路的电流，并在所述电流达到预设峰值后输出第二控制信号至所述逻辑控制电路；
    所述逻辑控制电路，连接至所述至少一个输出端，所述逻辑控制电路用于根据所述各个输出电压向电流控制电路输出所述第一控制信号，所述第一控制信号用于所述电流控制电路开启对所述功率级电路的电流的检测，所述逻辑控制电路根据所述第二控制信号输出第三控制信号至所述功率级电路以将所述功率级电路的电流峰值控制到预设峰值。
  2. 根据权利要求1所述的电路，其特征在于，所述第一控制信号还用于控制所述电流控制电路关闭对所述功率级电路的电流的检测。
  3. 根据权利要求1或2所述的电路，其特征在于，所述电流控制电路，还用于对所述预设峰值进行调节。
  4. 根据权利要求1-3任一项所述的电路，其特征在于，所述电流控制电路包括：
    峰值电流控制电路和电流过零检测电路；
    其中，所述峰值电流控制电路的输出端用于输出所述第二控制信号至所述逻辑控制电路，所述电流过零检测电路的输出端用于输出第四控制信号至所述逻辑控制电路，所述逻辑控制电路根据所述第四控制信号输出第五控制信号至所述功率级电路，以控制所述功率级电路的输出；
    所述峰值电流控制电路的输入端分别连接所述电源、所述逻辑控制电路的第一输出端和第二输出端，所述电流过零检测电路的输入端分别连接所述功率级电路和所述逻辑控制电路的第一输出端，其中，所述第一输出端用于输出所述第一控制信号，所述第二输出端用于输出所述第三控制信号至所述峰值电流控制电路和所述功率级电路，所述峰值电流控制电路根据所述第三 控制信号输出所述第二控制信号，所述功率级电路根据所述第三控制信号将所述电流峰值控制到预设峰值。
  5. 根据权利要求4所述的电路，其特征在于，所述峰值电流控制电路，包括：
    钳位电路、电流镜像电路、第一电阻、第一电容、选择电路和第一子控制电路；
    其中，所述第一电阻的第一端连接所述电源，所述第一电阻的第二端连接所述钳位电路；
    所述钳位电路与所述选择电路、所述电流镜像电路连接，并接收从所述逻辑控制电路的第一输出端输出的所述第一控制信号；
    所述选择电路与所述功率级电路的至少一个输出端连接，并接收所述逻辑控制电路的第三输出端输出的第六控制信号；
    所述电流镜像电路还与所述电源、所述第一电容的第一端和所述第一子控制电路连接；
    所述第一电容的两端分别与所述第一子控制电路连接，所述第一子控制电路接收所述逻辑控制电路的第二输出端输出的所述第三控制信号，所述第一子控制电路的输出端作为所述峰值电流控制电路的输出端；
    所述钳位电路，用于对所述第一电阻的第二端的电压进行钳位，使得所述第一电阻的第二端的电压等于所述选择电路的输出电压；
    所述镜像电流电路，用于对所述第一电阻的电流进行镜像；
    所述选择电路，用于根据所述逻辑控制电路的第三输出端输出的第六控制信号，选择所述功率级电路的输出电压；
    所述第一子控制电路，用于根据所述逻辑控制电路的第二输出端输出的所述第三控制信号控制所述峰值电流控制电路的输出端输出所述第二控制信号。
  6. 根据权利要求5所述的电路，其特征在于，所述峰值电流控制电路，还包括：第二子控制电路；
    其中，所述第二子控制电路分别与所述逻辑控制电路的第一输出端、所述电流镜像电路、所述第一电容的第二端以及所述第一子控制电路连接；
    所述第二子控制电路，用于根据所述逻辑控制电路的第一输出端输出的 第一控制信号，控制所述峰值电流控制电路的开启或关闭。
  7. 根据权利要求5或6所述的电路，其特征在于，所述钳位电路，包括：
    运算放大器和第一功率管；
    其中，所述运算放大器的第一输入端连接所述第一电阻的第二端，所述运算放大器的第二输入端连接所述选择电路，所述运算放大器的第三输入端连接所述逻辑控制电路的第一输出端，所述运算放大器的输出端连接所述第一功率管的第一端，所述第一功率管的第二端连接所述第一电阻的第二端，所述第一功率管的第三端连接所述镜像电流电路。
  8. 根据权利要求5-7任一项所述的电路，其特征在于，所述选择电路，包括：
    第一反相器、至少一个传输门；
    其中，所述第一反相器的输入端连接所述逻辑控制电路的第三输出端；
    所述第一反相器的输出端分别连接各个所述传输门的第一控制端；各个所述传输门的第二控制端分别连接所述逻辑控制电路的第三输出端；各个所述传输门的输入端分别对应连接所述功率级电路的各个输出端，各个所述传输门的输出端作为所述选择电路的输出端；所述传输门的数量与所述功率级电路的输出端的数量相同。
  9. 根据权利要求5-8任一项所述的电路，其特征在于，所述电流镜像电路，包括：
    第二功率管、第三功率管、第四功率管和第五功率管；
    其中，所述第二功率管的第一端与所述第三功率管的第一端连接，所述第二功率管的第一端和第二端短接，所述第二功率管的第二端连接所述钳位电路，所述第二功率管的第三端接地；
    所述第三功率管的第二端连接所述第四功率管的第二端，所述第三功率管的第三端接地；
    所述第四功率管的第二端和第一端短接，所述第四功率管的第一端还连接所述第五功率管的第一端，所述四功率管的第三端连接所述电源；
    所述第五功率管的第二端连接所述第一电容；所述第五功率管的第三端连接所述电源。
  10. 根据权利要求5-9任一项所述的电路，其特征在于，所述第一子控 制电路，包括：第一逻辑单元、第六功率管和第一比较器；
    其中，所述第一逻辑单元的第一输入端连接所述逻辑控制电路的第二输出端，所述第一逻辑单元的第二输入端连接所述第一比较器的输出端，所述第一逻辑单元的输出端连接所述第六功率管的第一端；所述第一逻辑单元的输出端作为所述峰值电流控制电路的输出端；
    所述第六功率管的第二端和第三端分别连接所述第一电容的两端，所述第六功率管的第二端接地；
    所述第一比较器的第一输入端连接所述镜像电流电路，所述第一比较器的第二输入端接入第一参考电压。
  11. 根据权利要求6所述的电路，其特征在于，所述第二子控制电路，包括：第七功率管，所述第七功率管的第一端接收所述逻辑控制电路的第一输出端输出的第一控制信号，所述第七功率管的第二端连接所述镜像电流电路，所述第七功率管的第三端接地。
  12. 根据权利要求10所述的电路，其特征在于，所述第一逻辑单元包括：
    第一D触发器、第二D触发器以及第一与门；
    其中，所述第一D触发器的第一端作为所述第一逻辑单元的第二输入端，所述第一D触发器的第二端连接电源，所述第一D触发器的第三端连接所述第一与门的输出端，所述第一D触发器的输出端连接所述第一与门的第一输入端并作为所述第一逻辑单元的输出端；
    所述第二D触发器的第一端作为所述第一逻辑单元的第一输入端，所述第二D触发器的第二端连接电源，所述第二D触发器的第三端连接所述第二D触发器的输出端，所述第二D触发器的输出端连接所述第一与门的第二输入端。
  13. 根据权利要求5-12任一项所述的电路，其特征在于，所述第一电阻的阻值可变或所述第一电容的电容可变。
  14. 根据权利要求10或12任一项所述的电路，其特征在于，所述第一参考电压可变。
  15. 根据权利要求1-14任一项所述的电路，其特征在于，所述逻辑控制电路，包括：
    第三子控制电路，以及至少一个第二比较器；所述第二比较器的数量与 所述功率级电路的输出端的数量相同；
    其中，各个所述第二比较器的第一输入端分别与所述功率级电路的各个输出端连接；各个所述第二比较器的第二输入端分别输入第二参考电压；
    各个所述第二比较器的输出端分别与所述第三子控制电路连接；
    所述第三子控制电路的第一输出端用于根据各个所述第二比较器的输出端输出的信号输出所述第一控制信号至所述电流控制电路，所述第三子控制电路的第二输出端用于根据各个所述第二比较器的输出端输出的信号输出所述第三控制信号至所述电流控制电路和所述功率级电路，所述第三子控制电路的第四输出端用于输出所述第五控制信号至所述功率级电路。
  16. 根据权利要求15所述的电路，其特征在于，所述第三子控制电路，包括：
    第二逻辑单元、第三逻辑单元、逻辑控制单元、第一延时单元和第一输出控制单元；
    其中，所述第二逻辑单元的第一输入端连接所述第一延时单元的输出端，所述第二逻辑单元的第二输入端和所述第一延时单元的输入端分别接收所述电流过零检测电路的输出端输出的所述第四控制信号；
    所述第二逻辑单元的输出端连接所述第一输出控制单元的输入端，所述第一输出控制单元的输出端作为所述第三子控制电路的第一输出端；
    所述第三逻辑单元的第一输入端连接所述峰值电流控制电路的输出端，所述第三逻辑单元的第二输入端连接所述第一输出控制单元的输出端，所述第三逻辑单元的输出端作为所述第三子控制电路的第二输出端；
    所述逻辑控制单元的第一输入端接收所述电流过零检测电路的输出端输出的所述第四控制信号，所述逻辑控制单元的第二输入端连接所述第一输出控制单元的输出端，所述逻辑控制单元的第二输入端连接各个所述第二比较器的输出端，所述逻辑控制单元的输出端作为所述第三子控制电路的第四输出端。
  17. 根据权利要求16所述的电路，其特征在于，所述第三子控制电路，还包括：第二延时单元；
    其中，所述第二延时单元的输入端连接所述第一输出控制单元的输出端，所述第二延时单元的输出端分别连接所述第三逻辑单元和所述逻辑控制单元 的第二输入端。
  18. 根据权利要求16或17所述的电路，其特征在于，所述第一输出控制单元包括：
    第二反相器、第二与门和或门；
    其中，所述第二反相器的输入端与所述第二逻辑单元的输出端连接，所述第二反相器的输出端与所述第二与门的第一输入端，所述第二与门的第二输入端连接所述或门的输出端；
    所述或门的输入端分别连接各个所述第二比较器的输出端，所述第二与门的输出端作为所述第一输出控制单元的输出端。
  19. 根据权利要求1-17任一项所述的电路，其特征在于，所述功率级电路包括：输入控制单元、电感和至少一个第二输出控制单元；
    其中，所述输入控制单元分别与所述电源和所述电感的第一端连接，所述输入控制单元还用于接收所述逻辑控制电路的第二输出端输出的第三控制信号，所述电感的第二端分别与各个所述第二输出控制单元连接；各个所述第二输出控制单元还用于接收所述逻辑控制电路的第四输出端输出的所述第五控制信号。
  20. 根据权利要求19所述的电路，其特征在于，还包括：
    第一驱动电路和第二驱动电路；
    其中，所述逻辑控制电路的第二输出端通过所述第一驱动电路连接所述功率级电路；
    所述逻辑控制电路的第四输出端通过所述第二驱动电路连接所述功率级电路。
  21. 根据权利要求20所述的电路，其特征在于，所述输入控制单元，包括：
    第八功率管和第九功率管；
    其中，所述第八功率管的第一端连接所述第一驱动电路的输出端，所述第八功率管的第二端连接所述电源，所述第八功率管的第三端连接所述电感的第一端；
    所述第九功率管的第一端连接所述第一驱动电路的输出端，所述第九功率管的第二端连接所述电感的第一端，所述第九功率管的第三端接地。
  22. 根据权利要求20所述的电路，其特征在于，所述第二输出控制单元，包括：
    第十功率管、第二电容、负载；
    其中，所述第十功率管的第一端连接所述第二驱动电路，所述第十功率管的第二端连接所述电感的第二端，所述第十功率管的第三端连接所述第二电容的第一端，所述第二电容和所述负载的第二端接地，所述第二电容的第一端还连接所述负载的第一端。
  23. 一种电源管理芯片，其特征在于，包括：
    如权利要求1-22任一项所述的电源管理电路。
  24. 一种电子设备，其特征在于，包括：
    如权利要求23所述的电源管理芯片。
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