Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
  • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
  • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
  • H01J37/32082—Radio frequency generated discharge
  • H01J37/32174—Circuits specially adapted for controlling the RF discharge
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32431—Constructional details of the reactor
  • H01J37/3244—Gas supply means
  • H01J37/32449—Gas control, e.g. control of the gas flow
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32431—Constructional details of the reactor
  • H01J37/32697—Electrostatic control
  • H01J37/32706—Polarising the substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
  • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
  • H01J2237/32—Processing objects by plasma generation
  • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
  • H01J2237/334—Etching

Definitions

• the present invention relates generally to a system and method of semiconductor fabrication, and, in particular embodiments, to a system and method for etching dielectric materials with phosphorus-halide gases.
• a semiconductor device such as an integrated circuit (IC) is fabricated by sequentially depositing and patterning layers of dielectric, conductive, and semiconductor materials over a substrate to form a network of electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated in a monolithic structure.
• IC integrated circuit
• interconnect elements e.g., transistors, resistors, capacitors, metal lines, contacts, and vias
• a method of processing a substrate includes: patterning a mask over a dielectric layer, the dielectric layer disposed over the substrate; etching openings in the dielectric layer, the etching including flowing an etchant, a polar or H-containing gas, and a phosphorus-halide gas; and forming contacts by filling the openings with a conductive material.
• a method of processing a substrate includes: performing a cyclic etching process, where each cycle of the cyclic etching process
• -i- includes: flowing an etchant over a dielectric layer on the substrate, the substrate being in a process chamber; forming a catalyst in the process chamber by flowing a polar or H- containing gas and a phosphorus-halide gas over the dielectric layer in the process chamber; and purging the catalyst from the process chamber.
• a method of processing a substrate in a process chamber includes: flowing an etchant and a polar or H-containing gas over a dielectric layer including an exposed surface of the substrate; and performing a cyclic tuning process, where each cycle of the cyclic tuning process includes: adjusting a temperature of the process chamber; and flowing a phosphorus-halide gas over the dielectric layer.
• Figures 1-5 illustrate cross sectional views of a substrate during an example process of semiconductor fabrication including an etch process to form a high aspect ratio (HAR) feature on the substrate in accordance with various embodiments, wherein Figure 1 illustrates an incoming substrate including a dielectric layer and a patterned hardmask layer, Figures 2-3 illustrate the substrate during the formation of the high aspect ratio feature by the etch process, Figure 4 illustrates the substrate after completing the etch process, and Figure 5 illustrates the substrate after the high aspect ratio feature is formed;
• Figure 1 illustrates an incoming substrate including a dielectric layer and a patterned hardmask layer
• Figures 2-3 illustrate the substrate during the formation of the high aspect ratio feature by the etch process
• Figure 4 illustrates the substrate after completing the etch process
• Figure 5 illustrates the substrate after the high aspect ratio feature is formed;
• Figure 6A illustrates a catalysation of oxide etching by the presence of water, in accordance with various embodiments
• Figure 6B illustrates a formation of an acid by the combination of a phosphorus- halide with a hydroxyl group, in accordance with various embodiments
• Figure 6C illustrates an increase of surface water retention by the presence of acid molecules, in accordance with various embodiments
• Figure 6D illustrates achieved etch rates versus flow rates for different fluorine- containing gases, in accordance with various embodiments
• Figure 6E illustrates quadrupole mass spectrometer (QMS) intensities versus temperature for H 2 0, HF, and PF 2 0H, in accordance with various embodiments;
• Figure 7 illustrates a process flow chart diagram of a method for etch processing in accordance with various embodiments;
• Figure 8 illustrates a process flow chart diagram of a method for etch processing in accordance with various embodiments
• Figure 9 illustrates a process flow chart diagram of a method for etch processing in accordance with various embodiments.
• Figure 10 illustrates a plasma system for performing a process of semiconductor fabrication in accordance with various embodiments.
• references to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is included in at least one embodiment.
• phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.
• particular conformations, structures, or characteristics maybe combined in any adequate way in one or more embodiments.
• this application relates to fabrication of semiconductor devices, for example, integrated circuits including semiconductor devices, and more particularly to high capacity three-dimensional (3D) memory devices, such as a 3D-NAND (or vertical-NAND), 3D-NOR, or dynamic random access memory (DRAM) device.
• 3D-NAND or vertical-NAND
• 3D-NOR or dynamic random access memory
• DRAM dynamic random access memory
• the fabrication of such devices may generally require forming conformal, high aspect ratio features (e.g., a contact hole) of a circuit element.
• features with aspect ratio (ratio of height of the feature to the width of the feature) higher than 50:1 are generally considered to be high aspect ratio features, and in some cases fabricating a higher aspect ratio such as 100:1 maybe desired for advanced 3D semiconductor devices.
• conventional high aspect ratio etch methods may usually include tens and sometimes hundreds of processing steps, which thereby complicates the process optimization and etch throughput. A simple yet effective high aspect ratio process may therefore be desired.
• Embodiments of the present application disclose methods of fabricating high aspect ratio features by etch processes based on a combination of etchants, polar or H-containing gases, and phosphorus-halide gases. The etch processes may be further applied to fabricating other semiconductor features that are not high aspect ratio features, e.g. with isotropic etch processes. The increased etch rate of the disclosed etch processes may enable faster production time and decreased costs.
• the methods of etching described in this disclosure may overcome various challenges posed for etching processes for high aspect ratio features.
• the etch processes using a combination of etchants, polar or H-containing gases, and phosphorus-halide gases provide increased etch rates that may be useful for anisotropic etching of high aspect ratio features.
• the disclosed etch processes may also be useful for achieving enhanced etch rates for isotropic etch processes on dielectric materials.
• Figures 1 through 5 first illustrate an exemplary etch process to form a desired high aspect ratio feature in accordance with various embodiments. The effects of the etch chemistry on etch rates are described. Next, principles behind the etch chemistry are described in Figures 6A-6E. Example process flow diagrams are then illustrated in Figures 7, 8, and 9. Figure 10 provides an example plasma system for performing a process of semiconductor fabrication in accordance with various embodiments. All figures are drawn for illustration purpose only and not to scale.
• Figures 1 through 5 illustrate cross sectional views of a substrate too during an example process of semiconductor fabrication including an etch process to form a high aspect ratio feature on the substrate in accordance with various embodiments.
• Figure 1 illustrates an incoming substrate too including a dielectric layer 110 and a patterned hardmask layer 120 (also referred to as a mask).
• the substrate too may be a silicon wafer, or a silicon-on-insulator (SOI) wafer.
• the substrate may include a silicon germanium wafer, silicon carbide wafer, gallium arsenide wafer, gallium nitride wafer and other compound semiconductors.
• the substrate includes heterogeneous layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, as well layers of silicon on a silicon or SOI substrate.
• the substrate too is a part of a semiconductor device, and may have undergone a number of steps of processing following, for example, a conventional process.
• the semiconductor structure may include a substrate too in which various device regions are formed.
• the substrate too may include isolation regions such as shallow trench isolation (STI) regions as well as other regions formed therein.
• STI shallow trench isolation
• the dielectric layer 110 may be formed over the substrate too.
• the dielectric layer 110 is a target layer that is to be patterned into one or more high aspect ratio features.
• the high aspect ratio feature being etched into the dielectric layer 110 may be a contact hole, slit, or other suitable structures including a recess.
• the dielectric layer 110 includes an oxide (e.g., silicon oxide), silicon nitride, silicon oxynitride, an O/N/O/N stack (stacked layers of oxide and nitride), or the like.
• the dielectric layer 110 maybe deposited using an appropriate technique such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), as well as other plasma processes such as plasma enhanced CVD (PECVD) and other processes.
• the dielectric layer 110 is an O/N/O/N stack and has a total thickness in a range of 1 pm to 10 pm with each layer of the stack having a thickness between 50 nm and 2.5 pm.
• the patterned hardmask layer 120 is formed over the dielectric layer 110.
• the patterned hardmask layer 120 may include amorphous carbon layer (ACL).
• ACL amorphous carbon layer
• the patterned hardmask layer 120 maybe formed by first depositing a hardmask layer using, for example, an appropriate spin-coating technique or a vapor deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), as well as other plasma processes such as plasma enhanced CVD (PECVD) and other processes.
• CVD chemical vapor deposition
• PVD physical vapor deposition
• ALD atomic layer deposition
• PECVD plasma enhanced CVD
• the deposited hardmask layer may then be patterned using a lithography process and an anisotropic etch process.
• the relative thicknesses of the patterned hardmask layer 120 and the dielectric layer 110 may have any suitable relationship.
• the patterned hardmask layer 120 may be thicker than the dielectric layer 110, thinner than the dielectric layer 110, or the same thickness as the dielectric layer 110.
• the patterned hardmask layer 120 has a thickness in a range of 1 pm to 4 pm.
• the patterned hardmask layer 120 and/ or the dielectric layer 110 may be collectively considered as a part of the substrate too. Further, the substrate too may also include other layers. For example, for the purpose of patterning the hardmask layer, a trilayer structure including a photoresist layer, SiON layer, and optical planarization layer (OPL) may be present.
• Figure 2 illustrates the substrate too during a start of an etch process for the formation of one or more high aspect ratio features (e.g., contact plugs formed through dielectric layers or stacks for memory arrays).
• the etch process maybe performed in a process chamber such as a plasma processing chamber 510 (see below, Figure 10). However, any suitable process chamber maybe used.
• fabricating the high aspect ratio features in the dielectric layer 110 is performed by an etch process using a combination of gases in accordance with various embodiments. Specifically, an etchant 130, a polar or H-containing gas 140, and a phosphorus-halide gas 150 are used. In order to achieve the high aspect ratio needed, it is advantageous for the etch process to have an increased etch rate. However, the geometry of the high aspect ratio openings formed may suppress the supply of etchant radicals at the etching interfaces on the bottom surfaces of the high aspect ratio openings. As such, the disclosed etch process may increase the concentration of etchant at the etching interfaces, leading to a faster etch rate.
• the etchant 130 is a chemical suitable for etching dielectric material (e.g., the dielectric layer 110) that may be catalyzed by polar molecules retained on exposed surfaces of the dielectric layer 110.
• the etchant 130 is hydrogen fluoride (HF), hydrogen chloride (HC1), the like, or a combination thereof.
• the polar or H-containing gas 140 is a gas that contains polar molecules or creates polar molecules on exposed surfaces of the dielectric layer 110.
• the polar or H-containing gas 140 comprises water vapor (H 2 0), hydrogen peroxide (H 2 0 2 ), hydrogen (H 2 ), a mixture of hydrogen (H 2 ) and oxygen (0 2 ), hydrogen bromide (HBr), the like, or a combination thereof.
• any suitable polar gas or H-containing gas maybe used.
• the phosphorus-halide gas 150 interacts with the polar molecules on exposed surfaces of the dielectric layer 110 to form a catalyst for the etchant 130.
• the phosphorus-halide gas 150 is phosphorus trifluoride (PF 3 ), phosphorus trichloride (PC1 3 ), phosphoryl fluoride (POF 3 ), phosphoryl chloride (POC1 3 ), a phosphorus-containing gas with the formula PX n (where X represents H, F, Cl, Br, or a combination thereof), the like, or a combination thereof.
• the polar or H-containing gas 140 interacts with the phosphorus-halide gas 150 to replace halogen atoms of the phosphorus-halide gas 150 with - OH groups to form a phosphorus-containing acid 160.
• This phosphorus-containing acid 160 acts as a co-adsorbate with polar molecules (e.g., water) and helps retain the etchant 130 on etch interfaces of the dielectric layer 110. The resulting higher density of the etchant 130 on the etch interfaces may advantageously increase the etch rate.
• H-containing polar molecules such as water
• H-containing polar molecules may also be retained on the etch interfaces of the dielectric layer 110, which may further catalyze the reaction of the etchant 130 with the dielectric layer no.
• the etchant 130 is HF
• the retained water on the etch interfaces of the dielectric layer no may react with the HF to produce hydrofluoric acid, thereby increasing the etch rate.
• the phosphorus-containing acid 160 may also further catalyze the reaction of the etchant 130 with the dielectric layer 110.
• Figure 3 illustrates the substrate 100 at a later stage of an etch process for the formation of one or more high aspect ratio features. Openings 170 with high aspect ratios extend into the dielectric layer 110. The illustrated etch process of Figure 3 is anisotropic, so that the openings 170 are produced with high aspect ratios.
• the anisotropic etching is enabled by providing the etchant 130, the polar or H-containing gas 140, and the phosphorus-halide gas 150 with a plasma process that is performed in a suitable plasma processing system, such as described below with respect to Figure 10. Due to the directed plasma bombardment, the phosphorus- containing acid 160 and polar molecules (e.g., water, hydroxyl, or the like) are formed to a greater degree on bottom surfaces of the openings 170 than on sidewalls of the openings 170. The high power of the plasma process may trigger reactions between the polar or H- containing gas 140 and oxygen or nitrogen atoms of the dielectric layer 110 to form polar molecules preferentially on the bottom surfaces of the openings 170.
• a plasma processing system such as described below with respect to Figure 10. Due to the directed plasma bombardment, the phosphorus- containing acid 160 and polar molecules (e.g., water, hydroxyl, or the like) are formed to a greater degree on bottom surfaces of the openings 170 than on side
• the polar molecules on the bottom surfaces of the openings 170 then interact with the phosphorus-halide gas 150 to form the phosphorus-containing acid 160 as a co-adsorbate on the bottom surfaces of the openings 170.
• the plasma process also supplies the etchant 130 to a greater degree on bottom surfaces of the openings 170 than on sidewalls of the openings 170.
• the greater amount of polar molecules on the bottom surfaces of the openings 170 help to further retain the etchant 130. This may cause the catalyzed reaction of the etchant 130 with the material of the dielectric layer 110 to be directed primarily towards the substrate too, enabling anisotropic etching.
• isotropic etching is enabled without plasma processing by tuning flow rates of hydrocarbon gas and phosphorus-containing gases to facilitate adsorption of H 2 0 and etchant 130 on the exposed surfaces of the openings 170. This may catalyze an isotropic etching process with the etchant 130 on exposed surfaces of the openings 170.
• a sufficient etch rate enables the openings 170 to have a high aspect ratio in a short process time compared to conventional high aspect ratio etch methods. Simultaneously, due to a good selectivity to the patterned hardmask layer 120 during the etch process, only a small fraction of the patterned hardmask layer 120 may be consumed.
• the patterned hardmask layer 120 is removed from over the dielectric layer 110 and residues from the etching process are removed.
• the patterned hardmask layer 120 maybe removed with a suitable process, such as a planarization process (e.g., a CMP) or the like.
• residues from the etching process are removed with a suitable cleaning process, such as a rinse with deionized water, hydrogen peroxide, SC-i, the like, or a combination thereof.
• conductive features 180 are formed in the openings 170 (see above, Figure 4).
• the conductive features 180 are high aspect ratio features.
• the conductive features 180 maybe formed to physically and electrically couple with conductive portions of the substrate 100.
• a conformal barrier metal e.g., TiN or TaN
• the openings 170 are filled with a conductive material such as a metal.
• the conductive material may be copper formed using electroplating.
• any suitable conductive material and deposition method may be used. Excess conductive material is then removed from the top surface of the dielectric layer 110 using a planarization process (e.g., a CMP), thereby forming the conductive features 180 inlaid in the dielectric layer 110.
• a planarization process e.g., a CMP
• Figure 6A illustrates modelling of a catalysation of oxide etching by the presence of water, in accordance with various embodiments.
• the various surface energies and reaction barriers may be calculated with a suitable method such as density functional theory.
• an oxide molecular or atomic structure is illustrated.
• the oxide may include silicon atoms (e.g., the oxide maybe a silicon oxide), and the oxide may have hydroxyl (OH) groups on its surface.
• An etchant HF may replace a hydroxyl group and the fluorine atom F may bond with a silicon atom, forming a SiF group. This process may break down the oxide and etch it away.
• the predicted reaction barrier of the chemical reaction of the HF with the oxide is 0.76 eV.
• polar molecules e.g., H 2 0
• the polar molecules may act as a catalyst for the reaction as the adhering of the H 2 0 to the oxide surface is favored (e.g., with an energy state lower than the initial state by 0.24 eV).
• a subsequent reaction of the oxide with adhered H 2 0 to form an etched oxide (e.g., having an SiF group) plus H 2 0 is further favored (e.g., with an energy state lower than the initial state by 0.33 eV).
• Figure 6A illustrates an oxide as a dielectric material, HF as an etchant, and H 2 0 as a polar molecule as an example
• the catalysation may be enabled with other dielectric materials (e.g., a nitride), etchants (e.g., HC1), or polar molecules or H-containing gases (e.g., HBr).
• polar molecules may enable the increasing of etch rates of dielectric materials by reducing the reaction barrier energies.
• Figure 6B illustrates a formation of an acid by the combination of a phosphorushalide with a hydroxyl group, in accordance with various embodiments.
• the phosphorus-halide may react with H 2 0 so that a hydroxyl (-OH) group replaces a halogen atom of the phosphorus-halide to form a phosphorus-containing acid.
• the reaction maybe described by equation (1):
• X represents a halogen atom (e.g., fluorine, chlorine, or the like) and Y represents an atom or atomic group attached to a hydroxyl (-OH) group.
• Y is a hydrogen atom
• Y-OH is a water (H 2 0) molecule
• PX n -iOH represents the phosphorus-containing acid
• Y-X represents the hydrogen atom attaching to one of the halogen atoms X.
• the hydrolysis reaction may have a change of internal energy AE of the system of -0.1 eV.
• the hydrolysis reaction may have a change of internal energy AE of the system of -0.2 eV.
• the hydrolysis reaction may have a change of internal energy AE of the system of -0.3 eV.
• the hydrolysis reaction may have a change of internal energy AE of the system of -0.33 eV.
• any suitable PX n gas may react with a polar or H-containing gas to form a phosphorus-containing acid.
• Figure 6C illustrates modelling data of an increase of surface water retention by the presence of acid molecules, in accordance with various embodiments.
• An oxide e.g., silicon oxide
• a bonded fluorine atom is shown at the top left, such as may be produced during an etch process of an oxide with HF.
• the surface of the oxide may be relatively hydrophobic due to the presence of the fluorine atom.
• On the top right an adsorption reaction of the oxide with water is shown.
• the adsorption energy E a ds(H 2 0) of the water with the oxide surface maybe -0.24 eV.
• the adsorption of water on the oxide surface maybe catalyzed by a co-adsorption of a phosphorus-containing acid.
• an adsorption reaction of the phosphorus-containing acid molecule (ct-OH, where a contains phosphorus) with the oxide is shown.
• the adsorption energy E a ds(H 2 0) of the water with the oxide surface may be -0.50 eV.
• a further adsorption reaction of the oxide having phosphorus-containing acid with water is shown on the lower right, for which the adsorption energy E a ds(H 2 0) is -0.54 eV.
• This increased adsorption energy with the co-adsorbed phosphorus-containing acid may increase the concentration of water (or other polar molecules) adsorbed on the surface of the oxide, which increases the catalysation of the etch reaction and broadens the operational condition of the etch process.
• the increased adsorption of water by the co-adsorption reaction with the phosphorus-containing acid may also lower the water vapor pressure, which can increase the operation temperature region of the catalyzed etch process.
• Figure 6D illustrates experimental results of achieved etch rates versus flow rates for different fluorine-containing gases, in accordance with various embodiments.
• the x-axis shows the relative flow rates of different fluorine-containing gases PF 3 , NF 3 , and SF C) that are flowed during respective etch process on an oxide (e.g., an etch process of silicon oxide with HF), and the y-axis shows the relative etch rates of the respective etch processes on an oxide (Ox E/R).
• the relative etch rate increases the most in proportion to increased flow rate for the phosphorus-containing PF 3 over the non-phosphorus-containing NF 3 and SF C) .
• Figure 6E illustrates experimentally measured normalized quadrupole mass spectrometer (QMS) intensities versus temperature for HF, H2O, and PF2OH during an etch process performed by flowing HF, H2O, and PF 3 over an oxide (e.g., silicon oxide), in accordance with various embodiments.
• the normalized QMS intensities of HF and H2O decrease as temperature is decreased, indicating an increased adsorption of HF and H2O on the oxide surface.
• the normalized QMS intensity of PF2OH increases as temperature is decreased, implying that the greater amount of PF2OH is due to a greater amount of hydrolysis reactions near the surface of the oxide from an increase in the amount of adsorbed H2O.
• FIG. 7 illustrates a process flow chart diagram of a method 200 for continuous catalytic etch processing, in accordance with some embodiments.
• a mask e.g., a patterned hardmask layer 120
• a dielectric layer 110 is patterned over a dielectric layer 110, as described above with respect to Figure 1.
• openings 170 are etched in the dielectric layer 110 by flowing an etchant 130, a polar or H-containing gas 140, and a phosphorus-halide gas 150, as described above with respect to Figures 2-3.
• the etch process is a continuous catalytic etching in which the etchant 130, the polar or H-containing gas 140, and the phosphorus-halide gas 150 are flowed continuously into the process chamber containing the dielectric layer 110.
• the polar or H-containing gas 140 interacts with the phosphorus-halide gas 150 to replace halogen atoms of the phosphorus-halide gas 150 with -OH groups to form a phosphorus-containing acid 160.
• This phosphorus-containing acid 160 acts as a co-adsorbate and helps retain polar molecules (e.g., water, hydroxyl, or the like) with the etchant 130 on etch interfaces of the dielectric layer 110.
• polar molecules e.g., water, hydroxyl, or the like
• the resulting higher density of the etchant 130 and polar molecules (e.g., water, hydroxyl, or the like) on the etch interfaces may catalyze the etch process and increase the etch rate.
• the continuous catalytic etching is an anisotropic plasma etch performed with a plasma processing system (see below, Figure 10).
• the continuous catalytic etching is an isotropic etch.
• the isotropic etch may be performed by tuning flow rates of hydrocarbon gas and phosphorus-containing gases to facilitate adsorption of H 2 0 and etchants 130 on the exposed surfaces of the openings 170, thereby catalyzing the isotropic etching process.
• a flow rate of the etchant 130 is in a range of 1 seem to 1000 seem
• a flow rate of the polar or H-containing gas 140 is in a range of 1 seem to 1000 seem
• a flow rate of the phosphorus-halide gas 150 is in a range of 1 seem to 1000 seem.
• the continuous catalytic plasma etching is performed at a temperature in a range of -200 °C to 250 °C and at a pressure in a range of 0.1 mTorr to 1000 mTorr.
• the continuous catalytic plasma etching is performed with a plasma power in a range of 50 W to 15000 W.
• conductive features 180 are formed by filling the openings 170 with a conductive material, as described above with respect to Figure 5.
• the conductive features 180 maybe high aspect ratio features, such as with aspect ratios greater than 50:1.
• Figure 8 illustrates a process flow chart diagram of a method 300 for quasi-atomic layer catalytic etch processing, in accordance with some embodiments.
• the quasi-atomic layer catalytic etch processing may increase controllability of the etch process, such as to increase the anisotropy of the formed openings 170 (see Figure 3) or to control the etching depth.
• an etchant 130 (e.g., HF, HC1, or the like) is flowed over a dielectric layer 110 in a process chamber.
• a flow rate of the etchant 130 is in a range of 1 seem to 1000 seem.
• the etchant 130 is flowed for a duration in a range of 1 second to 300 seconds, at a temperature in a range of -200 °C to 50 °C and at a pressure in a range of 0.1 mTorr to 1000 mTorr.
• a small amount of etchant 130 (e.g., a monolayer or a bilayer) is formed on the exposed surfaces of the dielectric layer 110.
• a catalyst for the etch process is formed by flowing a polar or H- containing gas 140 (e.g., H 2 0, HBr, or the like) and a phosphorus-halide gas 150 into the process chamber containing the dielectric layer 110.
• the phosphorus-halide gas 150 interacts with the polar or H-containing gas 140 to form a catalyst, such as a phosphorus-containing acid 160 (see above, Figures 2-3) and polar molecules on etch interfaces of the dielectric layer 110.
• the etch process consumes the small amount of the etchant on the exposed surfaces of the dielectric layer 110, leaving the catalyst behind, such as the phosphorus- containing acid 160 and polar molecules.
• forming the catalyst includes a flow rate of the polar or H- containing gas 140 in a range of 1 seem to 1000 seem and a flow rate of the phosphorus-halide gas 150 in a range of 0.1 seem to 1000 seem.
• the polar or H-containing gas 140 and the phosphorus-halide gas 150 are flowed for a duration in a range of 1 second to 300 seconds, at a temperature in a range of -200 °C to 250 °C and at a pressure in a range of 0.1 mTorr to 1000 mTorr.
• step 306 the process chamber is purged to remove the remaining catalyst, such as phosphorus-containing acid 160 and polar molecules. Any remaining etchant 130 may also be purged.
• the purge may be performed by flowing an inert gas (e.g, argon or the like) into the process chamber, by evacuating the process chamber with a vacuum pump, or a combination thereof. Removing the catalyst with the purge may increase the controllability of subsequent steps of the quasi-atomic layer catalytic etch process, e.g. so that a desired amount of the dielectric layer 110 is etched with each step and a desired shape of the formed openings 170 (see above, Figure 3) is achieved.
• an inert gas e.g, argon or the like
• Steps 302 through 306 may be repeated for any suitable number of cycles in order to etch the dielectric layer 110 to a desired depth.
• the quasi-atomic layer catalytic etch processing includes 1 cycle to 1000 cycles of steps 302 through 306.
• Figure 9 illustrates a process flow chart diagram of a method 400 for an etch processing method with temperature tuning, in accordance with some embodiments. Tuning the temperature may decouple the temperature and etch rate so that a desired etch rate may be achieved.
• an etchant 130 e.g., HF or HC1
• a polar or H-containing gas 140 e.g., H 2 0, H2O2, H 2 , HBr, the like, or a combination thereof
• a flow rate of the etchant 130 is in a range of 1 seem to 1000 seem
• a flow rate of the polar or H-containing gas 140 is in a range of 1 seem to 1000 seem.
• the etchant 130 and the polar or H-containing gas 140 are flowed for a duration in a range of 1 second to 300 seconds and at a pressure in a range of 1 mTorr to 1000 mTorr.
• the temperature in the process chamber in step 402 is in a range of -200 °C to 250 °C, which is useful for controlling the amount of polar or H-containing gas 140 retained on the surface of the dielectric layer 110. For example, lower temperatures may increase the amount of polar or H-containing gas 140 retained on the surface of the dielectric layer 110, which is advantageous for increasing the etch rate.
• step 404 the temperature of the process chamber is adjusted in order to provide a desired etch rate.
• the initial process temperature in the first cycle of the method 400 is in a range of -200 °C to 250 °C.
• the temperature may be tuned upwards or downwards as suitable to change the etch rate.
• a phosphorus-halide gas 150 is flowed into the process chamber.
• the phosphorus-halide gas 150 interacts with the polar or H-containing gas to form a catalyst, such as a phosphorus-containing acid 160 (see above, Figures 2-3) and polar molecules, on etch interfaces of the dielectric layer 110. This catalyzes the etch process and increases the etch rate, as described above with respect to Figures 2-3.
• the interaction of the phosphorus- halide gas 150 interacts with the polar or H-containing gas and the subsequent catalysis of the reaction of the etchant 130 with the dielectric layer 110 may be controlled by the temperature of the process temperature set in step 404.
• the phosphorus-halide gas 150 is flowed into the process chamber with a flow rate in a range of 1 seem to 1000 seem, for a duration in a range of 1 second to 300 seconds, at a pressure in a range of 0.1 mTorr to 1000 mTorr.
• the flow rate of the phosphorus-halide gas 150 may be increased or decreased in each repeated step 406 to achieve a desired etch rate.
• Steps 404 and 406 may be repeated for any suitable number of cycles in order to etch the dielectric layer 110 to a desired depth.
• the processing includes i cycle to 1000 cycles of steps 404 and 406.
• the temperature of the process chamber may be tuned in each step 404 to achieve a desired etch rate in step 406.
• Figure 10 illustrates a plasma processing system 500 for performing a process of semiconductor fabrication in accordance with various embodiments.
• Figure 10 illustrates a substrate too placed on a substrate holder 554 (e.g., a circular electrostatic chuck (ESC)) inside a plasma processing chamber 510 near the bottom.
• the substrate too may be optionally maintained at a desired temperature using a heater / cooler 556 that surrounds the substrate holder 554.
• the temperature of the substrate too maybe maintained by a temperature controller 540 connected to the substrate holder 554 and the heater / cooler 556.
• the ESC maybe coated with a conductive material (e.g., a carbon-based or metal-nitride based coating) so that electrical connections may be made to the substrate holder 554.
• a conductive material e.g., a carbon-based or metal-nitride based coating
• the substrate holder 554 may be a bottom electrode of the plasma processing chamber 510.
• the substrate holder 554 is connected to two RF-bias power sources, 570 and 580 through blocking capacitors 590 and 591.
• a conductive circular plate inside the plasma processing chamber 510 near the top is the top electrode 552.
• the top electrode 552 is connected to a DC power source 550 of the plasma processing system 500.
• the gases may be introduced into the plasma processing chamber 510 by a gas delivery system 520.
• the gas delivery system 520 includes multiple gas flow controllers to control the flow of multiple gases into the chamber.
• Each of the gas flow controllers of the gas delivery system 520 may be assigned for each of etchants 130, polar or H-containing gases 140, and/or phosphorus-halide gases 150 (see above, Figures 2-3).
• optional center/ edge splitters may be used to independently adjust the gas flow rates at the center and edge of the substrate too.
• the RF-bias power sources 570 and 580 may be used to supply continuous wave (CW) or pulsed RF power to sustain the plasma, such as a plasma 560.
• the plasma 560 shown between the top electrode 552 and the bottom electrode (also the substrate holder 554), exemplifies direct plasma generated close to the substrate too in the plasma processing chamber 510 of the plasma processing system 500.
• the plasma 560 may include ions from the etchants 130, polar or H-containing gases 140, and/or phosphorus-halide gases 150. Etching may be performed by exposing the substrate too to the plasma 560 while powering the substrate holder 554 with RF-bias power sources 570, 580 and optionally the top electrode 552 with the DC power source 550.
• the etching process performed may be an etching of high aspect ratio features as illustrated above in Figures 2-3, using the method 200 (see above, Figure 7), the method 300 (see above, Figure 8), the method 400 (see above, Figure 9), the like, or a combination thereof.
• the configuration of the plasma processing system 500 described above is by example only. In alternative embodiments, various alternative configurations may be used for the plasma processing system 500.
• ICP inductively coupled plasma
• RF source power coupled to a planar coil over a top dielectric cover
• the gas inlet and/ or the gas outlet may be coupled to the upper wall, etc.
• the RF power, chamber pressure, substrate temperature, gas flow rates and other plasma process parameters maybe selected in accordance with the respective process recipe.
• the plasma processing system 500 may be a resonator such as a helical resonator.
• the substrate holder may be able to support a plurality of wafers that are spun around a central axis as they pass through different plasma zones.
• Example 1 A method of processing a substrate, the method including: patterning a mask over a dielectric layer, the dielectric layer disposed over the substrate; etching openings in the dielectric layer, the etching including flowing an etchant, a polar or H- containing gas, and a phosphorus-halide gas; and forming contacts by filling the openings with a conductive material.
• Example 2 The method of example 1, where the etchant is HF or HC1.
• Example 3 The method of example 1, where the polar or H-containing gas includes water vapor (H 2 0), hydrogen peroxide (H 2 0 2 ), hydrogen (H 2 ), a mixture of hydrogen (H 2 ) and oxygen (0 2 ), or hydrogen bromide (HBr).
• the polar or H-containing gas includes water vapor (H 2 0), hydrogen peroxide (H 2 0 2 ), hydrogen (H 2 ), a mixture of hydrogen (H 2 ) and oxygen (0 2 ), or hydrogen bromide (HBr).
• Example 4 The method of example 1, where the phosphorus-halide gas includes phosphorus trifluoride (PF 3 ), phosphorus trichloride (PC1 3 ), phosphoryl fluoride (POF 3 ), or phosphoryl chloride (POC1 3 ).
• PF 3 phosphorus trifluoride
• PC1 3 phosphorus trichloride
• POF 3 phosphoryl fluoride
• POC1 3 phosphoryl chloride
• Example 5 The method of example 1, where the dielectric layer includes silicon oxide or silicon nitride.
• Example 6 The method of example 5, where the dielectric layer includes an O/N/O/N stack.
• Example 7 The method of example 1, where the etching anisotropically etches the openings in an anisotropic etch process.
• Example 8 The method of example 7, where the anisotropic etch process is performed as a plasma process in a plasma processing system.
• Example 9 The method of example 1, where the contacts have respective aspect ratios greater than 50:1.
• Example 10 A method of processing a substrate, the method including: performing a cyclic etching process, where each cycle of the cyclic etching process includes: flowing an etchant over a dielectric layer on the substrate, the substrate being in a process chamber; forming a catalyst in the process chamber by flowing a polar or H-containing gas and a phosphorus-halide gas over the dielectric layer in the process chamber; and purging the catalyst from the process chamber.
• Example 11 The method of example 10, where the etchant is HF.
• Example 12 The method of example 10, where the phosphorus-halide gas is phosphorus trifluoride (PF 3 ).
• Example 13 The method of example 10, where the catalyst includes PF 2 0H.
• Example 14 The method of example 10, where the etching process is a plasma process.
• Example 15 The method of example 10, where the etching process is anisotropic.
• Example 16 A method of processing a substrate in a process chamber, the method including: flowing an etchant and a polar or H-containing gas over a dielectric layer including an exposed surface of the substrate; and performing a cyclic tuning process, where each cycle of the cyclic tuning process includes: adjusting a temperature of the process chamber; and flowing a phosphorus-halide gas over the dielectric layer.
• Example 17 The method of example 16, where the polar or H-containing gas includes H 2 0.
• Example 18 The method of example 16, where the phosphorus-halide gas includes phosphorus and fluorine.
• Example 19 The method of example 16, where the dielectric layer includes silicon oxide.
• Example 20 The method of example 16, further including forming an opening in the dielectric layer, the opening having an aspect ratio greater than 50:1.

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