WO2023178819A1 - 比较器电路、失配校正方法和存储器 - Google Patents

比较器电路、失配校正方法和存储器 Download PDF

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Publication number
WO2023178819A1
WO2023178819A1 PCT/CN2022/093571 CN2022093571W WO2023178819A1 WO 2023178819 A1 WO2023178819 A1 WO 2023178819A1 CN 2022093571 W CN2022093571 W CN 2022093571W WO 2023178819 A1 WO2023178819 A1 WO 2023178819A1
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Prior art keywords
adjustment
node
signal
transistor
adjustment signal
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PCT/CN2022/093571
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English (en)
French (fr)
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田凯
朱玲
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长鑫存储技术有限公司
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Priority to EP22757469.6A priority Critical patent/EP4280461A4/en
Priority to US17/822,775 priority patent/US20230327656A1/en
Publication of WO2023178819A1 publication Critical patent/WO2023178819A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

Definitions

  • the present disclosure relates to, but is not limited to, a comparator circuit, a mismatch correction method, and a memory.
  • the input circuit of the memory generally adopts a differential input structure.
  • the two input transistors of the differential input structure are of the same size in the design (including width-to-length ratio, threshold voltage and other parameters), the input is formed on the actual silicon chip.
  • mismatch between the two input transistors will be caused by various factors (for example, the dose of doping ion implantation in the process, the angle of exposure, the position of the transistor, etc.).
  • the mismatch caused by the above reasons is very small, but the operating frequency of the memory is very high under normal working conditions.
  • the signal frequency of the memory is very high (for example, the operating frequency of LPDDR4 can be 4266MHz, or even the operating frequency of LPDDR5X The operating frequency can be 8533MHz).
  • Embodiments of the present disclosure provide a comparator circuit, including: a first transistor, one terminal coupled to a first node, the other terminal coupled to a first control node, a gate used to receive a first control signal; a second transistor, a terminal The first node is coupled, the other terminal is coupled to the second control node, the gate is used to receive the second control signal; the transistor doping type of the first transistor and the second transistor is the same; the load unit, one end is coupled to the second node, and the other end is coupled
  • the first control node and the second control node are configured to adjust the level of the second control node based on the level of the first control node, or to adjust the level of the first control node based on the level of the second control node.
  • the adjusted node is used to output the output signal; among the first node and the second node, one is used to receive the high level and the other is used to receive the low level;
  • An adjustment circuit one end coupled to the first node and the other end coupled to the first control node, used to adjust the node potential of the first control node after the first transistor is turned on based on the first control signal according to the first adjustment signal;
  • the second adjustment circuit A circuit, one end coupled to the first node and the other end coupled to the second control node, used to adjust the node potential of the second control node after the second transistor is turned on based on the second control signal according to the second adjustment signal;
  • the first adjustment signal and The second adjustment signal is used to adjust the mismatch between the first transistor and the second transistor.
  • Embodiments of the present disclosure provide a mismatch correction method, applied to the above-mentioned comparator circuit, including: during the calibration phase, controlling the inputs of the first control signal and the second control signal to be the same; initially setting the first adjustment signal to the maximum value, The second adjustment signal is the minimum value; reduce the first adjustment signal and increase the second adjustment signal in turn, and obtain output signals corresponding to different first adjustment signals and second adjustment signals; obtain the first time when the potential of the output signal flips.
  • the first adjustment signal and the second adjustment signal corresponding to the time node; the first adjustment signal and the second adjustment signal corresponding to the first time node are used as the first adjustment signal and the second adjustment signal required to be provided in the working stage.
  • Embodiments of the present disclosure provide a memory that uses the comparator circuit provided in the above embodiments for data input.
  • Figures 1 and 2 are two structural schematic diagrams of a comparator circuit provided by an embodiment of the present disclosure
  • Figures 3 and 4 are two structural schematic diagrams of a comparator circuit under load provided by an embodiment of the present disclosure
  • Figure 5 is a schematic structural diagram of the first adjustment circuit, the second adjustment circuit and the switching MOS transistor provided by an embodiment of the present disclosure
  • Figure 6 is a schematic structural diagram of a first adjustment circuit and a second adjustment circuit provided with a protection transistor according to an embodiment of the present disclosure
  • Figure 7 is a schematic structural diagram of another first adjustment circuit and a second adjustment circuit provided with a protection transistor according to an embodiment of the present disclosure
  • Figure 8 is a schematic structural diagram of a calibration control circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic flowchart of a mismatch correction method provided by another embodiment of the present disclosure.
  • the two input transistors of the differential structure are of the same size in the design, in the process of forming the input transistors on the actual silicon wafer, mismatch between the two input transistors will be caused by various factors.
  • Embodiments of the present disclosure provide a comparator circuit to eliminate the mismatch between two input transistors of a differential structure, thereby improving memory performance.
  • Figures 1 and 2 are two structural schematic diagrams of the comparator circuit provided in this embodiment.
  • Figures 3 and 4 are two structural schematic diagrams of the comparator circuit under load provided in this embodiment.
  • Figure 5 is provided in this embodiment.
  • Figure 6 is a schematic structural diagram of a first regulating circuit and a second regulating circuit with a protection transistor provided in this embodiment.
  • Figure 7 is a schematic structural diagram of this embodiment.
  • the example provides a schematic structural diagram of another first adjustment circuit and a second adjustment circuit provided with a protection transistor.
  • Figure 8 is a schematic structural diagram of the calibration control circuit provided by this embodiment.
  • the comparator circuit provided by this embodiment is described below in conjunction with the accompanying drawings. For further details, as follows:
  • the comparator circuit includes:
  • the first transistor ⁇ 01> has one terminal coupled to the first node J1, the other terminal coupled to the first control node K1, and the gate is used to receive the first control signal R1.
  • the second transistor ⁇ 02> has one terminal coupled to the first node J1, the other terminal coupled to the second control node K2, and the gate is used to receive the second control signal R2.
  • the first transistor ⁇ 01> and the second transistor ⁇ 02> have the same transistor doping type, that is, the first transistor ⁇ 01> and the second transistor ⁇ 02> are two input transistors of a differential structure, and the first control signal R1 and the second control signal R2 as differential input data of the differential structure.
  • the load unit 101 has one end coupled to the second node J2 and the other end coupled to the first control node K1 and the second control node K2.
  • the load unit 101 is configured to adjust the voltage of the second control node K2 based on the level of the first control node K1. level, or adjust the level of the first control node K1 based on the level of the second control node K2.
  • the adjusted node is used to output the output signal S.
  • the output signal S is the output signal of the differential structure.
  • first node J1 and the second node J2 are used to receive the high level, and the other is used to receive the low level.
  • the structural diagram of the comparator circuit refers to Figure 1; when the first node J1 receives a low level, the second node J2 receives When the level is high, refer to Figure 2 for the structural schematic diagram of the comparator circuit.
  • this embodiment uses the load unit 101 to control the level of the second control node K2 based on the level of the first control node K1 as an example for detailed description, which does not constitute a limitation on this embodiment; in other embodiments , those skilled in the art can replace the positions of the first control node and the second control node, thereby realizing a solution in which the load unit controls the level of the first control node based on the level of the second control node.
  • the "high level” mentioned above is the level provided by the internal power supply Vcc of the memory to which the comparator circuit belongs
  • the “low level” mentioned above is the level provided by the ground node GND of the comparator circuit. level provided.
  • the load unit 101 includes:
  • the third transistor ⁇ 03> has one terminal coupled to the second node J2 and the other terminal coupled to the first control node K1.
  • the fourth transistor ⁇ 04> has one terminal coupled to the second node J2 and the other terminal coupled to the second control node K2.
  • the gate of the third transistor ⁇ 03> and the gate of the fourth transistor ⁇ 04> are coupled and coupled to the first control node K1; and the transistor doping type of the third transistor ⁇ 03> and the fourth transistor ⁇ 04> Same, the transistor doping types of the first transistor ⁇ 01> and the third transistor ⁇ 03> are different.
  • Figure 3 corresponds to Figure 1, which is the comparator circuit structure when the first node J1 receives a high level and the second node J2 receives a low level.
  • the first transistor ⁇ 01> and the second transistor ⁇ 02> is a PMOS tube
  • the third transistor ⁇ 03> and the fourth transistor ⁇ 04> are NMOS tubes
  • Figure 4 corresponds to Figure 2, which is the comparator circuit structure when the first node J1 receives a low level and the second node J2 receives a high level.
  • the first transistor ⁇ 01> and the second transistor ⁇ 02> are NMOS transistors
  • the third transistor ⁇ 03> and the fourth transistor ⁇ 04> are PMOS transistors;
  • the first node J1 is used to couple the power node Vcc
  • the second node J2 is used to couple the ground node GND, so that the first node J1 receives a high level
  • the second node J2 Node J2 receives a low level
  • the first node J1 is used to couple to the ground node GND
  • the second node J2 is used to couple to the power node Vcc, so that the first node J1 receives a low level.
  • the second node J2 receives high level.
  • the above example only provides one structure of the load unit 101.
  • the load unit can also be configured in other load forms.
  • the first node J1 is used for coupling the power node Vcc
  • the second node J2 is used for coupling the ground node GND for circuit description, which does not constitute a limitation on this embodiment.
  • the comparator circuit also includes:
  • the first adjustment circuit 100 has one end coupled to the first node J1 and the other end coupled to the first control node K1, for adjusting the first control after the first transistor ⁇ 01> is turned on based on the first control signal R1 according to the first adjustment signal T1. Node potential of node K1.
  • the second adjustment circuit 200 has one end coupled to the first node J1 and the other end coupled to the second control node K2, for adjusting the second transistor ⁇ 02> to conduct the second control based on the second control signal R2 according to the second adjustment signal T2. Node potential of node K2.
  • the first adjustment signal T1 and the second adjustment signal T2 are used to adjust the mismatch between the first transistor ⁇ 01> and the second transistor ⁇ 02>.
  • mismatch means that during the formation process of the input transistor, due to various factors (for example, the dose of doping ion implantation in the process, the angle of exposure, the position of the transistor, etc.), two parameter mismatch between the input transistors.
  • the first transistor ⁇ 01> and the second transistor ⁇ 02> serve as two input transistors of the differential structure.
  • the first transistor ⁇ 01> and the second transistor ⁇ 02> After the transistor ⁇ 01> and the second transistor ⁇ 02> are turned on, the first control node K1 and the first node J1 are indirectly connected, and the current flows from the first node J1 to the first control node K1 through the first transistor ⁇ 01>.
  • the control node K2 is indirectly connected to the first node J1, and the current flows from the first node J1 to the second control node K2 through the second transistor ⁇ 02>.
  • the first control signal R1 and the second control signal R2 are equal, the first The potentials of the control node K1 and the second control node K2 are the same; when the first transistor ⁇ 01> and the second transistor ⁇ 02> are mismatched, the first transistor ⁇ 01> and the second transistor ⁇ 02> are based on the same gate turn-on voltage.
  • the difference in the degree of opening causes a difference in potential between the first control node K1 and the second control node K2, thereby affecting the output of the differential structure.
  • the first adjustment circuit 100 is connected in parallel with the first transistor ⁇ 01>.
  • the first adjustment circuit 100 is turned on based on the first adjustment signal T1.
  • the first node J1 passes through the first adjustment signal.
  • the circuit 100 is connected to the first control node K1 to adjust the potential of the first control node K1; by connecting the second adjustment circuit 200 in parallel with the second transistor ⁇ 02>, the second adjustment circuit 200 is turned on based on the second adjustment signal T2, and the second adjustment circuit 200 is turned on based on the second adjustment signal T2.
  • the first node J1 is connected to the second control node K2 through the second adjustment circuit 200, thereby adjusting the potential of the second control node K2; by adjusting the first adjustment signal T1 and the second adjustment signal T2, So that when the first control signal R1 and the second control signal R2 are equal, the node potentials of the first control node K1 and the second control node K2 are equal, that is, through the first adjustment circuit 100 and the second adjustment circuit 200, the first Mismatch between transistor ⁇ 01> and second transistor ⁇ 02>.
  • the first adjustment signal T1 and the second adjustment signal T2 corresponding to the time point when the potential flip occurs of the output signal S are used as the first adjustment circuit 100 and the correction signal of the second conditioning circuit 200.
  • the comparator circuit also includes:
  • the switching MOS tube ⁇ 31> has one terminal coupled to the power node Vcc or the ground node GND, the other terminal coupled to the first node J1, and the gate is used to receive the switch enable signal.
  • the switching MOS transistor ⁇ 31> is coupled to the power node Vcc; if the first node J1 is used to receive a low level, the switching MOS transistor ⁇ 31> is coupled to the ground node GND.
  • the doping type of the switching MOS transistor ⁇ 31> is the same as that of the first transistor ⁇ 01>.
  • the switch enable signal is used to turn on the switch MOS tube ⁇ 31>.
  • the switch MOS tube ⁇ 31> it is turned on based on the switch enable signal to provide current to the comparator circuit, thereby turning on the comparator circuit, so that the comparator The circuit is turned on when in use and turned off when not in use to save energy consumption; in addition, the switching MOS tube ⁇ 31> is used to reduce the situation where the level is directly loaded on the comparator circuit to breakdown the transistor in the corresponding comparator circuit.
  • the switching MOS tube is used as the connection component between the first node J1 and the power node Vcc or the ground node GND.
  • a current source can also be provided to replace the switching MOS tube as the connecting component. The connection component between the first node J1 and the power node Vcc.
  • the circuit shown in Figure 5 to Figure 7 takes the first node J1 to receive a high level as an example.
  • the switching MOS tube ⁇ 31> and the first transistor ⁇ 01> are PMOS tubes, and one end of the switching MOS tube ⁇ 31> is At the coupling power node Vcc; if the comparator circuit receives a low level at the first node J1, refer to Figure 2 and Figure 4 accordingly.
  • the switching MOS tube and the first transistor ⁇ 01> are NMOS tubes, and the switching MOS tube ⁇ 31 > One end is used to couple the ground node GND.
  • the "coupling" mentioned in the above embodiments includes direct connection and indirect connection.
  • the direct connection means that the lines are directly connected, and the indirect connection means that the indirect electrical connection is realized through other semiconductor devices.
  • This embodiment does not The semiconductor devices in the indirect connection are not limited. As long as they comply with the connection relationship embodied in the above embodiments, they should all fall within the protection scope of the present disclosure.
  • the comparator circuit further includes:
  • the first protection transistor ⁇ B1> is of the same type as the first transistor ⁇ 01>. One terminal is coupled to the first node J1, the other terminal is coupled to the first adjustment circuit 100, and the gate is used to receive the first control signal R1.
  • the second protection transistor ⁇ B2> is of the same type as the second transistor ⁇ 02>. One terminal is coupled to the first node J1, the other terminal is coupled to the second adjustment circuit 200, and the gate is used to receive the second control signal R2.
  • the first protection transistor ⁇ B1> is connected in series with the first adjustment circuit 100, and is turned on based on the first control signal R1, so that when the first transistor ⁇ 01> is working, the branch where the first adjustment circuit 100 is located is also turned on; in addition, the first protection transistor ⁇ B1> is turned on at the same time.
  • a protection transistor ⁇ B1> is of the same type as the first transistor ⁇ 01>.
  • the second protection transistor ⁇ B2> is connected in series with the second adjustment circuit 200, and It is turned on based on the second control signal R2, so that when the second transistor ⁇ 02> is working, the branch where the second regulating circuit 200 is located is also turned on; in addition, the second protection transistor ⁇ B2> is of the same type as the second transistor ⁇ 01> , thereby reducing the over-adjustment of the second control node K2 by the second adjustment circuit 200.
  • this embodiment provides two implementation strategies, as follows:
  • the first adjustment circuit 100 includes: a first adjustment transistor ⁇ 11>, one terminal is coupled to the first node J1, the other terminal is coupled to the first control node K1, and the gate is used to receive the first adjustment signal T1.
  • the first adjustment transistor ⁇ 11> is configured to adjust the magnitude of the source drain current based on the first adjustment signal T1.
  • the second adjustment circuit 200 includes: a second adjustment transistor ⁇ 12>, one terminal is coupled to the first node J1, the other terminal is coupled to the second control node K2, and the gate is used to receive the second adjustment signal T2.
  • the second adjustment transistor ⁇ 12> is configured to adjust the magnitude of the source drain current based on the second adjustment signal T2.
  • the conduction capability of the first adjustment transistor ⁇ 11> can be changed by adjusting the size of the first adjustment signal T1, thereby adjusting the potential impact of the first adjustment circuit 100 on the first control node K1; by adjusting the first adjustment transistor ⁇ 11>
  • the magnitude of the second adjustment signal T2 is used to change the conduction capability of the second adjustment transistor ⁇ 12>, thereby adjusting the influence of the second adjustment circuit 200 on the potential of the second control node K2.
  • the first adjustment transistor ⁇ 11> and the second adjustment transistor ⁇ 12> have the same source-drain conduction capabilities after being turned on based on the same gate voltage. In some embodiments, the same source-drain conduction capabilities of the first adjustment transistor and the second adjustment transistor after they are turned on based on the same gate voltage can be achieved by setting the same transistor size.
  • the conduction degree of the first adjustment transistor ⁇ 11> is controlled, thereby adjusting the first node J1 to be transmitted to the first adjustment circuit 100 through the first adjustment circuit 100.
  • One controls the current size of the node K1, thereby changing the potential influence on the first control node K1 through the first adjustment circuit 100;
  • the second adjustment transistor ⁇ 12> is controlled. 12>, thereby adjusting the magnitude of the current transmitted from the first node J1 to the second control node K2 through the second adjustment circuit 200, thereby changing the influence of the second adjustment circuit 200 on the potential of the second control node K2.
  • the first adjustment circuit 100 includes a first adjustment transistor group.
  • the first adjustment transistor group includes: x first adjustment transistors; one terminal of the x first adjustment transistors is coupled to the first node J1, and the other terminal is coupled to the first control transistor.
  • the gate of node K1 is used to receive the first adjustment signal T1, and the first adjustment signal T1 is used to selectively turn on the first adjustment transistor.
  • the second adjustment circuit 200 includes a second adjustment transistor group.
  • the second adjustment transistor group includes: x second adjustment transistors; one terminal of the x second adjustment transistors is coupled to the first node J1, and the other terminal is coupled to the second control transistor.
  • the gate of node K2 is used to receive the second adjustment signal T2, and the second adjustment signal T2 is used to selectively turn on the second adjustment transistor.
  • x is an integer greater than or equal to 2.
  • the number of first regulating transistors in the first transistor group can be controlled by adjusting the first regulating signal T1 to change the conduction capability of the first regulating transistor group, thereby adjusting the first regulating circuit 100 to the first control node.
  • the x first regulation transistors have the same source-drain conduction capabilities after being turned on based on the same gate voltage
  • the x second regulation transistors have the same source-drain conductivity after being turned on based on the same gate voltage.
  • different first adjustment transistors or second adjustment transistors can have the same source-drain conduction capabilities after being turned on based on the same gate voltage by setting the same transistor size.
  • the source-drain conduction capability of the n-th first adjustment transistor is the source-drain conduction capability of the n-1th first adjustment transistor. Twice the capacity; among the x second regulation transistors, after being turned on based on the same gate voltage, the source-drain conduction capability of the n-th second regulation transistor is the source-drain conduction capability of the n-1 second regulation transistor twice; where n is any integer less than or equal to x and greater than or equal to 2.
  • the source-drain conduction capabilities of different first regulation transistors or second regulation transistors after being turned on based on the same gate voltage can be multiplied by setting transistor sizes that are multiplied.
  • the source-to-drain conduction capability of the second first adjustment transistor ⁇ 22> is twice that of the first first adjustment transistor ⁇ 21>
  • the third The source-drain conduction capability of the first regulating transistor ⁇ 23> (not shown) is twice the source-drain conduction capability of the second first regulating transistor ⁇ 22>...the x-th first regulating transistor ⁇ 2x>
  • the source-drain conduction capability is twice that of the x-1th first regulation transistor ⁇ 2x-1> (not shown);
  • the second second regulation transistor ⁇ The source-drain conduction capability of 32> is twice that of the first second adjustment transistor ⁇ 31>, and the source-drain conduction capability of the third second adjustment transistor ⁇ 33> (not shown) It is twice the source-drain conduction capability of the second second regulation transistor ⁇ 32>...
  • the source-drain conduction capability of the x-th second regulation transistor ⁇ 3x> is that of the x-1 second regulation transistor ⁇ 3x
  • first adjustment signal T1 By adjusting the first adjustment signal T1, different first adjustment transistors in the first transistor group are controlled to be turned on, thereby changing the overall source-drain conduction capability of the first transistor group, thereby adjusting the effect of the first adjustment circuit 100 on the first control node K1.
  • Potential influence By adjusting the second adjustment signal T2, different second adjustment transistors in the second transistor group are controlled to be turned on, thereby changing the overall source-drain conduction capability of the second transistor group, thereby adjusting the second adjustment circuit 200 to the first control
  • the potential influence of node K2 it should be noted that in the example shown in Figure 7, the first adjustment signal T1 and the second adjustment signal T2 are not a separate signal.
  • the first adjustment signal T1 and the second adjustment signal T2 respectively represent A signal group, each signal in the signal group is used to independently control the conduction of corresponding transistors in the first transistor group and the second transistor group.
  • the comparator circuit further includes: a calibration control circuit 300, which is used to provide a first adjustment signal T1 and a second adjustment signal T2, thereby adjusting the first transistor ⁇ 01> and the second transistor ⁇ 01>. Mismatch of two transistors ⁇ 02>.
  • calibration control circuit 300 includes:
  • the clock module 303 is configured to receive the calibration enable signal MR and generate the calibration clock CLK based on the calibration enable signal MR.
  • the calibration enable signal MR is provided during the calibration phase.
  • the first calibration module 301 and the coupled clock module 303 initially set the first adjustment signal T1 to the maximum value and the second adjustment signal T2 to the minimum value, provide the first adjustment signal T1 and the second adjustment signal T2, and gradually set the first adjustment signal T1 and the second adjustment signal T2 based on the calibration clock CLK. Reduce the first adjustment signal T1 and increase the second adjustment signal T2.
  • the judgment module 304 is used to receive the output signal S corresponding to the different first adjustment signal T1 and the second adjustment signal T2, and obtain the first adjustment signal T1 and the second adjustment signal T1 corresponding to the first time node t1 when the potential of the output signal S flips. Adjust signal T2.
  • the storage module 305 and the coupling judgment module 304 are used to obtain the first adjustment signal T1 and the second adjustment signal T2 corresponding to the first time node t1, and provide the first adjustment signal T1 corresponding to the first time node t1 during the working phase. and the second adjustment signal T2.
  • the first calibration module 301 and the coupled clock module 303 initially set the first adjustment signal T1 to a minimum value and the second adjustment signal T2 to a maximum value, and provide the first adjustment signal T1 and the second adjustment signal signal T2, and gradually increases the first adjustment signal T1 and decreases the second adjustment signal T2 based on the calibration clock CLK.
  • Table 2 is adjustment example 2:
  • calibration control circuit 300 further includes:
  • the second calibration module 302 and the coupled clock module 303 initially set the first adjustment signal T1 to the minimum value and the second adjustment signal T2 to the maximum value, provide the first adjustment signal T1 and the second adjustment signal T2, and gradually set the first adjustment signal T1 and the second adjustment signal T2 based on the calibration clock CLK. Increase the first adjustment signal T1 and decrease the second adjustment signal T2.
  • the judgment module 304 is also used to obtain the first adjustment signal T1 and the second adjustment signal T2 corresponding to the second time node t2 when the potential of the output signal S flips.
  • the storage module 305 is also used to obtain the first adjustment signal T1 and the second adjustment signal T2 corresponding to the second time node t2, and use the average value of the first adjustment signal T1 corresponding to the first time node t1 and the second time node t2 as The first adjustment signal T1 that needs to be provided in the working stage is the average of the second adjustment signal T2 corresponding to the first time node t1 and the second time node t2 as the second adjustment signal T2 that needs to be provided in the working stage.
  • the comparator circuit further includes:
  • the first selection circuit 310 receives the input selection signal C, the input signal Din or the reference signal Vref, and is used to provide the first control signal R1.
  • the second selection circuit 320 receives the input selection signal C, the input signal Din or the reference signal Vref, and is used to provide the first control signal R2.
  • the first selection circuit is configured to select the input signal or the reference signal to provide the first control signal based on the input selection signal
  • the second selection circuit is configured to select the input signal or the reference signal to provide the second control signal based on the input selection signal.
  • the input signal Din is the actual input signal input to the comparator circuit shown
  • the reference signal Vref is the reference signal used to determine whether the input is high level or low level.
  • the input selection signal C is used to control the first selection circuit 310 and the second selection circuit 320 to provide the first control signal R1 and the second control signal R2 with the input signal Din, or with the reference signal Vref simultaneously provides the first control signal R1 and the second control signal R2; that is, the first control signal R1 and the second control signal R2 are controlled to be the same signal to obtain the voltage between the first transistor ⁇ 01> and the second transistor ⁇ 02>. mismatch, thereby subsequently completing the compensation for the mismatch between the first transistor ⁇ 01> and the second transistor ⁇ 02>.
  • the input selection signal C is used to control the first selection circuit 310 to provide the first control signal R1 with the input signal Din, and the second selection circuit 320 provides the second control signal R2 with the reference signal Vref; or, in the working phase, the input The selection signal C is used to control the first selection circuit 310 to provide the first control signal R1 with the reference signal Vref, and the second selection circuit 320 to provide the second control signal R2 with the input signal Din.
  • the first adjustment circuit 100 is connected in parallel with the first transistor ⁇ 01>.
  • the first adjustment circuit 100 is turned on based on the first adjustment signal T1.
  • the first node J1 passes through the first adjustment signal.
  • the circuit 100 is connected to the first control node K1 to adjust the potential of the first control node K1; by connecting the second adjustment circuit 200 in parallel with the second transistor ⁇ 02>, the second adjustment circuit 200 is turned on based on the second adjustment signal T2, and the second adjustment circuit 200 is turned on based on the second adjustment signal T2.
  • the first node J1 is connected to the second control node K2 through the second adjustment circuit 200, thereby adjusting the potential of the second control node K2; by adjusting the first adjustment signal T1 and the second adjustment signal T2, So that when the first control signal and the second control signal are equal, the node potentials of the first control node K1 and the second control node K2 are equal, that is, through the first adjustment circuit 100 and the second adjustment circuit 200, the first transistor ⁇ Mismatch between 01> and second transistor ⁇ 02>.
  • Each unit involved in this embodiment is a logical unit.
  • a logical unit can be a physical unit, or a part of a physical unit, or can be implemented as a combination of multiple physical units.
  • units that are not closely related to solving the technical problems raised by the present disclosure are not introduced in this embodiment, but this does not mean that other units do not exist in this embodiment.
  • Another embodiment of the present disclosure provides a mismatch correction method that uses the comparator circuit provided in the above embodiment to eliminate the mismatch between two input transistors in a differential structure, thereby improving memory performance.
  • FIG. 9 is a schematic flow chart of the mismatch correction method provided by this embodiment.
  • the mismatch correction method provided by this embodiment will be further described in detail below with reference to the accompanying drawings, as follows:
  • the mismatch correction method includes:
  • Step 401 initially set the first adjustment signal to the maximum value and the second adjustment signal to the minimum value, successively reduce the first adjustment signal and increase the second adjustment signal, and obtain the values corresponding to different first adjustment signals and second adjustment signals. output signal.
  • Step 402 Obtain the first adjustment signal and the second adjustment signal corresponding to the first time node when the potential of the output signal flips.
  • the inputs of the first control signal and the second control signal are the same; the first adjustment signal is initially set to the maximum value and the second adjustment signal is the minimum value, and the first adjustment signal is sequentially reduced and The second adjustment signal is increased, and output signals corresponding to different first adjustment signals and second adjustment signals are obtained.
  • the first adjustment signal A3 or A2 and the second adjustment signal A2 or A3 corresponding to the first time node t1 are used as the first adjustment signal and the second adjustment signal that need to be provided in the working stage.
  • step 401 may also be configured as follows: initially setting the first adjustment signal to the minimum value and the second adjustment signal to the maximum value, sequentially increasing the first adjustment signal and decreasing the second adjustment signal, and obtaining the corresponding The input signal is different from the first adjustment signal and the second adjustment signal.
  • Table 2 is adjustment example 2:
  • the first adjustment signal A3 or A2 and the second adjustment signal A2 or A3 corresponding to the first time node t1 are used as the first adjustment signal and the second adjustment signal that need to be provided in the working stage.
  • the mismatch correction method further includes:
  • Step 403 initially set the first adjustment signal to the minimum value and the second adjustment signal to the maximum value, sequentially increase the first adjustment signal and decrease the second adjustment signal, and obtain the values corresponding to different first adjustment signals and second adjustment signals. output signal.
  • Step 404 Obtain the first adjustment signal and the second adjustment signal corresponding to the second time node when the potential of the output signal flips.
  • Step 405 Use the average value of the first adjustment signal corresponding to the first time node and the second time node as the first adjustment signal to be provided in the working stage; use the second adjustment signal corresponding to the first time node and the second time node. The average value is used as the second adjustment signal required for the working stage.
  • the method further includes: initially setting the first adjustment signal to a minimum value and the second adjustment signal to a maximum value. value; increase the first adjustment signal and decrease the second adjustment signal in sequence, and obtain output signals corresponding to different first adjustment signals and second adjustment signals; obtain the second time node corresponding to the potential flip of the output signal. an adjustment signal and a second adjustment signal.
  • Using the first adjustment signal and the second adjustment signal corresponding to the first time node as the first adjustment signal and the second adjustment signal required to be provided in the working phase includes: using the first adjustment signal corresponding to the first time node and the second time node.
  • the average value of the signal is used as the first adjustment signal that needs to be provided in the working stage; the average value of the second adjustment signal corresponding to the first time node and the second time node is used as the second adjustment signal that needs to be provided in the working stage.
  • the first adjustment signal T1 is the average value of A1 and A3; the second adjustment signal T2 is the average value of A2 and A4.
  • Yet another embodiment of the present disclosure provides a memory that uses the comparator circuit provided in the above embodiment for data input to eliminate the mismatch between two input transistors in a differential structure, thereby improving memory performance.
  • the memory is a dynamic random access memory (Dynamic Random Access Memory, DRAM) chip, where the memory of the dynamic random access memory DRAM chip complies with DDR2 memory specifications.
  • DRAM Dynamic Random Access Memory
  • the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip complies with DDR3 memory specifications.
  • the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip complies with DDR4 memory specifications.
  • the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip complies with DDR5 memory specifications.
  • Embodiments of the present disclosure provide a comparator circuit, a mismatch correction method and a memory, wherein the comparison circuit includes: a first transistor, one terminal coupled to the first node, the other terminal coupled to the first control node, and the gate is used to receive a first control signal; a second transistor, one terminal coupled to the first node, the other terminal coupled to the second control node, the gate used to receive the second control signal; the transistor doping type of the first transistor and the second transistor is the same; the load The unit has one end coupled to the second node and the other end coupled to the first control node and the second control node, and is configured to adjust the level of the second control node based on the level of the first control node, or to adjust the level of the second control node based on the level of the second control node.
  • the level of the first control node is adjusted flatly.
  • the adjusted node is used to output the output signal; among the first node and the second node, one of them is used to receive the high level, The other is used to receive low level;
  • the first adjustment circuit has one end coupled to the first node and the other end coupled to the first control node, and is used to adjust the first transistor according to the first adjustment signal to turn on based on the first control signal.
  • the node potential of the first control node; the second adjustment circuit, one end coupled to the first node and the other end coupled to the second control node, is used to adjust the second transistor according to the second adjustment signal after it is turned on based on the second control signal.
  • a node potential of the node is controlled; the first adjustment signal and the second adjustment signal are used to adjust the mismatch of the first transistor and the second transistor.
  • the first adjustment circuit by connecting the first adjustment circuit in parallel with the first transistor, the first adjustment circuit is turned on based on the first adjustment signal. After the first adjustment circuit is turned on, the first node communicates with the first control node through the first adjustment circuit. connection, thereby adjusting the potential of the first control node; by connecting the second adjustment circuit in parallel with the second transistor, the second adjustment circuit is turned on based on the second adjustment signal.
  • the first node passes through the second adjustment circuit Connected to the second control node, thereby adjusting the potential of the second control node; by adjusting the first adjustment signal and the second adjustment signal, so that when the first control signal and the second control signal are equal, the first control node and the second control node
  • the node potentials of the nodes are equal, that is, the mismatch between the first transistor and the second transistor is corrected through the first adjustment circuit and the second adjustment circuit, thereby improving memory performance.

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Abstract

本公开涉及半导体电路设计领域，特别涉及一种比较器电路、失配校正方法和存储器，包括：第一晶体管，一端子耦合第一节点，另一端子耦合第一控制节点，栅极用于接收第一控制信号；第二晶体管，一端子耦合第一节点，另一端子耦合第二控制节点，栅极用于接收第二控制信号；负载单元，一端耦合第二节点，另一端耦合第一控制节点和第二控制节点；第一调节电路用于根据第一调节信号，调节第一晶体管基于第一控制信号导通后，第一控制节点的节点电位；第二调节电路用于根据第二调节信号，调节第二晶体管基于第二控制信号导通后，第二控制节点的节点电位，以消除差分结构的两个输入晶体管之间的失配，进而改进存储器性能。

Description

比较器电路、失配校正方法和存储器
相关申请的交叉引用
本公开基于申请号为202210294447.9、申请日为2022年03月23日、申请名称为“比较器电路、失配校正方法和存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本公开。
技术领域
本公开涉及但不限于一种比较器电路、失配校正方法和存储器。
背景技术
存储器的输入电路一般采用差分输入结构，差分输入结构的两个输入晶体管虽然在设计中是相同的尺寸(包括宽长比、阈值电压等参数)，但在实际的硅片(Silicon)上形成输入晶体管的过程中，会由于各种因素(例如，工艺上掺杂离子注入的剂量，曝光的角度，晶体管的位置等)，造成两个输入晶体管之间的失配。
一般来说，由于上述原因所造成的失配很微小，但正常工作状态下存储器的工作频率很高，在存储器的信号频率非常高的情况下(比如LPDDR4的工作频率可以为4266MHz，甚至LPDDR5X的工作频率可以为8533MHz)，此时即使输入晶体管之间存在较小的失配，都会对产品的性能有着明显的影响，而且上述失配的影响，用传统的方法(比如增加差分输入管的大小)是没有办法消除的。
发明内容
本公开实施例提供了一种比较器电路，包括：第一晶体管，一端子耦合第一节点，另一端子耦合第一控制节点，栅极用于接收第一控制信号；第二晶体管，一端子耦合第一节点，另一端子耦合第二控制节点，栅极用于接收第二控制信号；第一晶体管和第二晶体管的晶体管掺杂类型相同；负载单元，一端耦合第二节点，另一端耦合第一控制节点和第二控制节点，被配置为，基于第一控制节点的电平调整第二控制节点的电平，或基于第二控制节点的电平调整第一控制节点的电平，第一控制节点和第二控制节点中，被调节的节点用于输出输出信号；第一节点和第二节点中，其中一者用于接收高电平，另一者用于接收低电平；第一调节电路，一端耦合第一节点，另一端耦合第一控制节点，用于根据第一调节信号，调节第一晶体管基于第一控制信号导通后，第一控制节点的节点电位；第二调节电路，一端耦合第一节点，另一端耦合第二控制节点，用于根据第二调节信号，调节第二晶体管基于第二控制信号导通后，第二控制节点的节点电位；第一 调节信号和第二调节信号用于调节第一晶体管和第二晶体管的失配。
本公开实施例提供了一种失配校正方法，应用于上述比较器电路，包括：在校准阶段，控制第一控制信号和第二控制信号的输入相同；初始设置第一调节信号为最大值，第二调节信号为最小值；依次减小第一调节信号并增大第二调节信号，并获取对应于不同第一调节信号和第二调节信号的输出信号；获取输出信号发生电位翻转的第一时间节点所对应的第一调节信号和第二调节信号；将第一时间节点对应的第一调节信号和第二调节信号作为工作阶段所需提供的第一调节信号和第二调节信号。
本公开实施例提供了一种存储器，应用上述实施例提供的比较器电路进行数据输入。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领缺普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1和图2为本公开一实施例提供的比较器电路的两种结构示意图；
图3和图4为本公开一实施例提供的负载下的比较器电路的两种结构示意图；
图5为本公开一实施例提供的第一调节电路、第二调节电路和开关MOS管的结构示意图；
图6为本公开一实施例提供的具备保护晶体管的一种第一调节电路和第二调节电路的结构示意图；
图7为本公开一实施例提供的具备保护晶体管的另一种第一调节电路和第二调节电路的结构示意图；
图8为本公开一实施例提供的校准控制电路的结构示意图；
图9为本公开另一实施例提供的失配校正方法的流程示意图。
具体实施方式
差分结构的两个输入晶体管虽然在设计中是相同的尺寸，但在实际的硅片上形成输入晶体管的过程中，会由于各种因素，造成两个输入晶体管之间的失配。
由于上述原因所造成的失配很微小，但正常工作状态下存储器的工作频率很高，在存储器的信号频率非常高的情况下，此时即使输入晶体管之间存在较小的失配，都会对产品的性能都有着明显的影响。
本公开实施例提供了一种比较器电路，以消除差分结构的两个输入晶体管之间的失配，进而改进存储器性能。
本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1和图2为本实施例提供的比较器电路的两种结构示意图，图3和图4为本实施例提供的负载下的比较器电路的两种结构示意图，图5为本实施例提供的第一调节电路、第二调节电路和开关MOS管的结构示意图，图6为本实施例提供的具备保护晶体管的一种第一调节电路和第二调节电路的结构示意图，图7为本实施例提供的具备保护晶体管的另一种第一调节电路和第二调节电路的结构示意图，图8为本实施例提供的校准控制电路的结构示意图，以下结合附图对本实施例提供的比较器电路作进一步详细说明，如下：
参考图1～图7，比较器电路，包括：
第一晶体管<01>，一端子耦合第一节点J1，另一端子耦合第一控制节点K1，栅极用于接收第一控制信号R1。
第二晶体管<02>，一端子耦合第一节点J1，另一端子耦合第二控制节点K2，栅极用于接收第二控制信号R2。
其中，第一晶体管<01>和第二晶体管<02>的晶体管掺杂类型相同，即第一晶体管<01>和第二晶体管<02>作为差分结构的两个输入晶体管，第一控制信号R1和第二控制信号R2作为差分结构的差分输入数据。
负载单元101，一端耦合第二节点J2，另一端耦合第一控制节点K1和第二控制节点K2，负载单元101被配置为，基于第一控制节点K1的电平调整第二控制节点K2的电平，或基于第二控制节点K2的电平调整第一控制节点K1的电平，第一控制节点K1和第二控制节点K2中，被调节的节点用于输出输出信号S。
其中，输出信号S即差分结构的输出信号。
其中，第一节点J1和第二节点J2中，其中一者用于接收高电平，另一者用于接收低电平。
在一些实施例中，当第一节点J1接收高电平，第二节点J2接收低电平时，比较器电路的结构示意图参考图1；当第一节点J1接收低电平，第二节点J2接收高电平时，比较器电路的结构示意图参考图2。
需要说明的是，本实施例以负载单元101基于第一控制节点K1的电平控制第二控制节点K2的电平为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，本领域技术人员可以将第一控制节点和第二控制节点的位置进行替换，从而实现负载单元基于第二控制节点的电平控制第一控制节点的电平的方案。
需要说明的是，上述提到的“高电平”，即比较器电路所属存储器的内部电源Vcc所提供的电平，上述提到的“低电平”，即比较器电路地线节点GND所提供的电平。
参考图3和图4，对于图1和图2中所示的负载单元101，负载单元101包括：
第三晶体管<03>，一端子耦合第二节点J2，另一端子耦合第一控制节点K1。
第四晶体管<04>，一端子耦合第二节点J2，另一端子耦合第二控制节点K2。
其中，第三晶体管<03>的栅极和第四晶体管<04>的栅极耦合，并耦合第一控制节点K1；并且第三晶体管<03>和第四晶体管<04>的晶体管掺杂类型相同，第一晶体管<01>和第三晶体管<03>的晶体管掺杂类型不同。
需要说明的是，图3对应于图1为第一节点J1接收高电平，第二节点J2接收低电平时的比较器电路结构，此时第一晶体管<01>和第二晶体管<02>为PMOS管，第三晶体管<03>和第四晶体管<04>为NMOS管；图4对应于图2为第一节点J1接收低电平，第二节点J2接收高电平时的比较器电路结构，此时第一晶体管<01>和第二晶体管<02>为NMOS管，第三晶体管<03>和第四晶体管<04>为PMOS管；
进一步地，参考图5，图5所示电路中，第一节点J1用于耦合电源节点Vcc，第二节点J2用于耦合地线节点GND，从而实现第一节点J1接收高电平，第二节点J2接收低电平；相应地，在一些实施例中，第一节点J1用于耦合地线节点GND，第二节点J2用于耦合电源节点Vcc，从而是实现第一节点J1接收低电平，第二节点J2接收高电平。
另外，上述示例仅给出了一种负载单元101的结构，在其他实施例中，负载单元同样可以采用其他负载形式构成。
需要说明的是，本公开实施例后续以第一节点J1用于耦合电源节点Vcc，第二节点J2用于耦合地线节点GND的图示进行电路说明，并不构成对本实施例的限定。
继续参考图5，比较器电路，还包括：
第一调节电路100，一端耦合第一节点J1，另一端耦合第一控制节点K1，用于根据第一调节信号T1，调节第一晶体管<01>基于第一控制信号R1导通后第一控制节点K1的节点电位。
第二调节电路200，一端耦合第一节点J1，另一端耦合第二控制节点K2，用于根据第二调节信号T2，调节第二晶体管<02>基于第二控制信号R2导通后第二控制节点K2的节点电位。
其中，第一调节信号T1和第二调节信号T2用于调节第一晶体管<01>和第二晶体管<02>的失配。
需要说明的是，上述提到的“失配”，即输入晶体管在形成过程中，由于各种因素(例如，工艺上掺杂离子注入的剂量，曝光的角度，晶体管的位置等)，造成两个输入晶体管之间的参数失配。
在一些实施例中，第一晶体管<01>和第二晶体管<02>作为差分结构的两个输入晶体管，当第一晶体管<01>和第二晶体管<02>不存在失配时，第一晶体管<01>和第二晶体管<02>导通后，第一控制节点K1和第一节点J1间接连接，电流通过第一晶体管<01>从第一节点J1流向第一控制节点K1，第二控制节点K2和第一节点J1间接连接，电流通过第二晶体管<02>从第一节点J1流向第二控制节点K2，此时当第一控制信号R1和 第二控制信号R2相等时，第一控制节点K1和第二控制节点K2的电位相同；当第一晶体管<01>和第二晶体管<02>失配时，第一晶体管<01>和第二晶体管<02>基于相同栅极开启电压开启程度存在差异，造成第一控制节点K1和第二控制节点K2的电位存在差异，从而影响差分结构的输出。
本公开实施例通过与第一晶体管<01>并联第一调节电路100，第一调节电路100基于第一调节信号T1导通，第一调节电路100导通后，第一节点J1通过第一调节电路100与第一控制节点K1连接，从而调整第一控制节点K1的电位；通过与第二晶体管<02>并联第二调节电路200，第二调节电路200基于第二调节信号T2导通，第二调节电路200导通后，第一节点J1通过第二调节电路200与第二控制节点K2连接，从而调整第二控制节点K2的电位；通过调整第一调节信号T1和第二调节信号T2，使得当第一控制信号R1和第二控制信号R2相等时，第一控制节点K1和第二控制节点K2的节点电位相等，即通过第一调节电路100和第二调节电路200，修正了第一晶体管<01>和第二晶体管<02>之间的失配。
在一些实施例中，当第一控制信号R1和第二控制信号R2相等时，将输出信号S的发生电位翻转时间点所对应的第一调节信号T1和第二调节信号T2作为第一调节电路100和第二调节电路200的修正信号。
参考图5～图7，比较器电路，还包括：
开关MOS管<31>，一端子耦合电源节点Vcc或地线节点GND，另一端子耦合第一节点J1，栅极用于接收开关使能信号。
其中，若第一节点J1用于接收高电平，开关MOS管<31>耦合电源节点Vcc，若第一节点J1用于接收低电平，开关MOS管<31>耦合地线节点GND。
另外，开关MOS管<31>与第一晶体管<01>掺杂类型相同。
其中，开关使能信号用于导通开关MOS管<31>，对于开关MOS管<31>，基于开关使能信号导通，以向比较器电路提供电流，从而开启比较器电路，使得比较器电路在使用时开启，不使用时关闭，以节约能耗；另外，通过开关MOS管<31>减少电平直接加载在比较器电路上，以击穿相应比较器电路中的晶体管的情况。
需要说明的是，本实施例以开关MOS管作为第一节点J1与电源节点Vcc或地线节点GND之间的连接元器件，在一些实施例中，还可以通过设置电流源替代开关MOS管作为第一节点J1与电源节点Vcc之间的连接元器件。
图5～图7所示的电路以第一节点J1接收高电平为例，此时开关MOS管<31>与第一晶体管<01>为PMOS管，且开关MOS管<31>的一端用于耦合电源节点Vcc；若比较器电路以第一节点J1接收低电平，相应参考图2和图4，此时开关MOS管与第一晶体管<01>为NMOS管，且开关MOS管<31>的一端用于耦合地线节点GND。
需要说明的是，上述实施例中提到的“耦合”，包括直接连接和间接连接情况，其中，直接连接即线路直接连接，间接连接即通过其他半导体器件实现间接的电连接，本实施例并不对间接连接中的半导体器件进行限定，只要符合上述实施例说体现的连接关 系，都应属于本公开的保护范围内。
在一些实施例中，参考图6和图7，比较器电路，还包括：
第一保护晶体管<B1>，与第一晶体管<01>类型相同，一端子耦合第一节点J1，另一端子耦合第一调节电路100，栅极用于接收第一控制信号R1。
第二保护晶体管<B2>，与第二晶体管<02>类型相同，一端子耦合第一节点J1，另一端子耦合第二调节电路200，栅极用于接收第二控制信号R2。
第一保护晶体管<B1>与第一调节电路100串联，且基于第一控制信号R1导通，使得第一晶体管<01>工作时，同时导通第一调节电路100所在支路；另外，第一保护晶体管<B1>与第一晶体管<01>的类型相同，本领域技术人员理解，对于相同尺寸的第一调节晶体管，在有保护晶体管串联的情况下，在相同调节信号的作用下，晶体管的调节能力变弱，且对电流的调节作用更加精细，从而减少第一调节电路100对第一控制节点K1的过度调节的情况；第二保护晶体管<B2>与第二调节电路200串联，且基于第二控制信号R2导通，使得第二晶体管<02>工作时，同时导通第二调节电路200所在支路；另外，第二保护晶体管<B2>与第二晶体管<01>的类型相同，从而减少第二调节电路200对第二控制节点K2的过度调节的情况。
对于第一调节电路100和第二调节电路100，本实施例给出了两种实施策略，如下：
在一种实施策略中：
第一调节电路100，包括：第一调节晶体管<11>，一端子耦合第一节点J1，另一端子耦合第一控制节点K1，栅极用于接收第一调节信号T1。
第一调节晶体管<11>被配置为基于第一调节信号T1调节源漏电流的大小。
第二调节电路200，包括：第二调节晶体管<12>，一端子耦合第一节点J1，另一端子耦合第二控制节点K2，栅极用于接收第二调节信号T2。
第二调节晶体管<12>被配置为基于第二调节信号T2调节源漏电流的大小。
在本实施策略中，可以通过调节第一调节信号T1的大小来改变第一调节晶体管<11>的导通能力，从而调整第一调节电路100对第一控制节点K1的电位影响；通过调节第二调节信号T2的大小来改变第二调节晶体管<12>的导通能力，从而调整第二调节电路200对第二控制节点K2的电位影响。
在一些实施例中，第一调节晶体管<11>和第二调节晶体管<12>基于相同栅极电压开启后的源漏导通能力相同。在一些实施例中，可以通过设置相同的晶体管尺寸实现第一调节晶体管和第二调节晶体管基于相同栅极电压开启后的源漏导通能力相同。
参考图6，通过输入第一调节晶体管<11>的第一调节信号T1的大小，控制第一调节晶体管<11>的导通程度，从而调整第一节点J1通过第一调节电路100传输到第一控制节点K1的电流大小，从而改变通过第一调节电路100对第一控制节点K1的电位影响；通过输入第二调节晶体管<12>的第二调节信号T2的大小，控制第二调节晶体管<12>的导通程度，从而调整第一节点J1通过第二调节电路200传输到第二控制节点K2的电流大小，从而改变通过第二调节电路200对第二控制节点K2的电位影响。
在另一种实施策略中：
第一调节电路100，包括第一调节晶体管组，第一调节晶体管组中包括：x个第一调节晶体管；x个第一调节晶体管的一端子耦合第一节点J1，另一端子耦合第一控制节点K1，栅极用于接收第一调节信号T1，第一调节信号T1用于选择导通第一调节晶体管。
第二调节电路200，包括第二调节晶体管组，第二调节晶体管组中包括：x个第二调节晶体管；x个第二调节晶体管的一端子耦合第一节点J1，另一端子耦合第二控制节点K2，栅极用于接收第二调节信号T2，第二调节信号T2用于选择导通第二调节晶体管。
其中，x为大于等于2的整数。
在本实施策略中，可以通过调节第一调节信号T1控制第一晶体管组中第一调节晶体管的数量来改变第一调节晶体管组的导通能力，从而调整第一调节电路100对第一控制节点K1的电位影响；通过调节第二调节信号T2控制第二晶体管组中第二调节晶体管的数量来改变第二调节晶体管组的导通能力，从而调整第二调节电路200对第二控制节点K2的电位影响。
在一些实施例中，x个第一调节晶体管基于相同栅极电压开启后的源漏导通能力相同，且x个第二调节晶体管基于相同栅极电压开启后的源漏导通能力相同。在一些实施例中，可以通过设置相同的晶体管尺寸实现不同的第一调节晶体管或第二调节晶体管基于相同栅极电压开启后的源漏导通能力相同。
在一些实施例中，x个第一调节晶体管中，基于相同栅极电压开启后，第n个第一调节晶体管的源漏导通能力是第n-1个第一调节晶体管的源漏导通能力的两倍；x个第二调节晶体管中，基于相同栅极电压开启后，第n个第二调节晶体管的源漏导通能力是第n-1个第二调节晶体管的源漏导通能力的两倍；其中，n为小于等于x，且大于等于2的任意整数。在一些实施例中，可以通过设置成倍变化的晶体管尺寸实现不同的第一调节晶体管或第二调节晶体管基于相同栅极电压开启后的源漏导通能力成倍变化。
参考图7，对于第一晶体管组，第二个第一调节晶体管<22>的源漏导通能力是第一个第一调节晶体管<21>的源漏导通能力的两倍，第三个第一调节晶体管<23>(未图示)的源漏导通能力是第二个第一调节晶体管<22>的源漏导通能力的两倍……第x个第一调节晶体管<2x>的源漏导通能力是第x-1个第一调节晶体管<2x-1>(未图示)的源漏导通能力的两倍；对于第二晶体管组，第二个第二调节晶体管<32>的源漏导通能力是第一个第二调节晶体管<31>的源漏导通能力的两倍，第三个第二调节晶体管<33>(未图示)的源漏导通能力是第二个第二调节晶体管<32>的源漏导通能力的两倍……第x个第二调节晶体管<3x>的源漏导通能力是第x-1个第二调节晶体管<3x-1>(未图示)的源漏导通能力的两倍。
通过调节第一调节信号T1控制第一晶体管组中不同的第一调节晶体管导通，从而改变第一晶体管组整体的源漏导通能力，从而调整第一调节电路100对第一控制节点 K1的电位影响；通过调节第二调节信号T2控制第二晶体管组中不同的第二调节晶体管导通，从而改变第二晶体管组整体的源漏导通能力，从而调整第二调节电路200对第一控制节点K2的电位影响；需要说明的是，在图7所示的示例中，第一调节信号T1和第二调节信号T2并非一个单独的信号，第一调节信号T1和第二调节信号T2分别代表一个信号组，信号组中的每个信号用于独立控制第一晶体管组和第二晶体管组中对应的晶体管导通。
参考图8，在一些实施例中，比较器电路还包括：校准控制电路300，校准控制电路300用于提供第一调节信号T1和第二调节信号T2，从而调节第一晶体管<01>和第二晶体管<02>的失配。
在一些实施例中，校准控制电路300，包括：
时钟模块303，用于接收校准使能信号MR，并基于校准使能信号MR生成校准时钟CLK，校准使能信号MR于校准阶段提供。
第一校准模块301，耦合时钟模块303，初始设置第一调节信号T1为最大值，第二调节信号T2为最小值，提供第一调节信号T1和第二调节信号T2，并基于校准时钟CLK逐步减小第一调节信号T1，增大第二调节信号T2。
判断模块304，用于接收不同第一调节信号T1和第二调节信号T2对应的输出信号S，并获取输出信号S发生电位翻转的第一时间节点t1所对应的第一调节信号T1和第二调节信号T2。
存储模块305，耦合判断模块304，用于获取第一时间节点t1所对应的第一调节信号T1和第二调节信号T2，并在工作阶段提供第一时间节点t1所对应的第一调节信号T1和第二调节信号T2。
参考下表1，表1为调节示例1：
Figure PCTCN2022093571-appb-000001
相应地，在一些实施例中，第一校准模块301，耦合时钟模块303，初始设置第一调节信号T1为最小值，第二调节信号T2为最大值，提供第一调节信号T1和第二调节信号T2，并基于校准时钟CLK逐步增大第一调节信号T1，减小第二调节信号T2。
此时，其调整策略参考下表2，表2为调节示例2：
Figure PCTCN2022093571-appb-000002
在一些实施例中，校准控制电路300还包括：
第二校准模块302，耦合时钟模块303，初始设置第一调节信号T1为最小值，第二调节信号T2为最大值，提供第一调节信号T1和第二调节信号T2，并基于校准时钟CLK逐步增大第一调节信号T1，减小第二调节信号T2。
判断模块304还用于获取输出信号S发生电位翻转的第二时间节点t2所对应的第一调节信号T1和第二调节信号T2。
存储模块305还用于获取第二时间节点t2对应的第一调节信号T1和第二调节信号T2，并将第一时间节点t1和第二时间节点t2对应的第一调节信号T1的平均值作为工作阶段所需提供的第一调节信号T1，将第一时间节点t1和第二时间节点t2对应的第二调节信号T2的平均值作为工作阶段所需提供的第二调节信号T2。
参考下表3，表3为调节示例3：
Figure PCTCN2022093571-appb-000003
Figure PCTCN2022093571-appb-000004
在一些实施例中，比较器电路还包括：
第一选择电路310，接收输入选择信号C、输入信号Din或参考信号Vref，用于提供第一控制信号R1。
第二选择电路320，接收输入选择信号C、输入信号Din或参考信号Vref，用于提供第一控制信号R2。
其中，第一选择电路被配置为，基于输入选择信号选择以输入信号或参考信号提供第一控制信号；
第二选择电路被配置为，基于输入选择信号选择以输入信号或参考信号提供第二控制信号。
其中，输入信号Din为输入所示比较器电路的实际输入信号，参考信号Vref为用于判断输入为高电平或低电平的参考信号。
在一些实施例中，在校准阶段，输入选择信号C用于控制第一选择电路310和第二选择电路320以输入信号Din同时提供第一控制信号R1和第二控制信号R2，或以参考信号Vref同时提供第一控制信号R1和第二控制信号R2；即控制第一控制信号R1和第二控制信号R2为相同信号，以获取第一晶体管<01>和第二晶体管<02>之间的失配，从而后续完成对第一晶体管<01>和第二晶体管<02>之间失配的补偿。
在工作阶段，输入选择信号C用于控制第一选择电路310以输入信号Din提供第一控制信号R1，第二选择电路320以参考信号Vref提供第二控制信号R2；或，在工作阶段，输入选择信号C用于控制第一选择电路310以参考信号Vref提供第一控制信号R1，第二选择电路320以输入信号Din提供第二控制信号R2。
本公开实施例通过与第一晶体管<01>并联第一调节电路100，第一调节电路100基于第一调节信号T1导通，第一调节电路100导通后，第一节点J1通过第一调节电路100与第一控制节点K1连接，从而调整第一控制节点K1的电位；通过与第二晶体管<02>并联第二调节电路200，第二调节电路200基于第二调节信号T2导通，第二调节电路200导通后，第一节点J1通过第二调节电路200与第二控制节点K2连接，从而调整第二控制节点K2的电位；通过调整第一调节信号T1和第二调节信号T2，使得当第一控制信号和第二控制信号相等时，第一控制节点K1和第二控制节点K2的节点电位相等， 即通过第一调节电路100和第二调节电路200，修正了第一晶体管<01>和第二晶体管<02>之间的失配。
本实施例中所涉及到的各单元均为逻辑单元，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本公开的创新部分，本实施例中并没有将与解决本公开所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
需要说明的是，上述实施例所提供的比较器电路中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的比较器电路实施例。
本公开另一实施例提供一种失配校正方法，应用上述实施例提供的比较器电路，以消除差分结构的两个输入晶体管之间的失配，进而改进存储器性能。
图9为本实施例提供的失配校正方法的流程示意图，以下结合附图对本实施例提供的失配校正方法作进一步详细说明，如下：
参考图9，失配校正方法，包括：
步骤401，初始设置第一调节信号为最大值，第二调节信号为最小值，依次减小第一调节信号并增大第二调节信号，获取对应于不同第一调节信号和第二调节信号的输出信号。
步骤402，获取输出信号发生电位翻转的第一时间节点所对应的第一调节信号和第二调节信号。
在一些实施例中，在校准阶段，控制第一控制信号和第二控制信号的输入相同；初始设置第一调节信号为最大值，第二调节信号为最小值，依次减小第一调节信号并增大第二调节信号，并获取对应于不同第一调节信号和第二调节信号的输出信号。获取输出信号发生电位翻转的第一时间节点所对应的第一调节信号和第二调节信号；将第一时间节点对应的第一调节信号和第二调节信号作为工作阶段所需提供的第一调节信号和第二调节信号。
参考下表1，表1为调节示例1：
Figure PCTCN2022093571-appb-000005
此时，将第一时间节点t1对应的第一调节信号A3或A2和第二调节信号A2或A3作为工作阶段所需提供的第一调节信号和第二调节信号。
在一些实施例中，对于步骤401，还可以设置为：初始设置第一调节信号为最小值，第二调节信号为最大值，依次增大第一调节信号并减小第二调节信号，获取对应于不同第一调节信号和第二调节信号的输入信号。
此时，其调整策略参考下表2，表2为调节示例2：
Figure PCTCN2022093571-appb-000006
此时，将第一时间节点t1对应的第一调节信号A3或A2和第二调节信号A2或A3作为工作阶段所需提供的第一调节信号和第二调节信号。
在一些实施例中，继续参考图9，失配校正方法，还包括：
步骤403，初始设置第一调节信号为最小值，第二调节信号为最大值，依次增大第一调节信号并减小第二调节信号，获取对应于不同第一调节信号和第二调节信号的输出信号。
步骤404，获取输出信号发生电位翻转的第二时间节点所对应的第一调节信号和第二调节信号。
步骤405，将第一时间节点和第二时间节点对应的第一调节信号的平均值作为工作阶段所需提供的第一调节信号；将第一时间节点和第二时间节点对应的第二调节信号的平均值作为工作阶段所需提供的第二调节信号。
在一些实施例中，获取输出信号发生电位翻转的第一时间节点所对应的第一调节信号和第二调节信号之后，还包括：初始设置第一调节信号为最小值，第二调节信号为最大值；依次增大第一调节信号并减小第二调节信号，并获取对应于不同第一调节信号和第二调节信号的输出信号；获取输出信号发生电位翻转的第二时间节点所对应的第一调节信号和第二调节信号。
将第一时间节点对应的第一调节信号和第二调节信号作为工作阶段所需提供的第一调节信号和第二调节信号，包括：将第一时间节点和第二时间节点对应的第一调节信号的平均值作为工作阶段所需提供的第一调节信号；将第一时间节点和第二时间节点对 应的第二调节信号的平均值作为工作阶段所需提供的第二调节信号。
参考下表3，表3为调节示例3：
Figure PCTCN2022093571-appb-000007
此时，第一调整信号T1为A1和A3的平均值；第二调整信号T2为A2和A4的平均值。
需要说明的是，上述实施例所提供的失配校正方法中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的失配校正方法实施例。
本公开又一实施例提供一种存储器，应用上述实施例提供的比较器电路进行数据输入，以消除差分结构的两个输入晶体管之间的失配，进而改进存储器性能。
在一些实施例中，存储器为动态随机存取存储器(Dynamic Random Access Memory，DRAM)芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR2内存规格。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR3内存规格。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR4内存规格。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR5内存规格。
本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。
工业实用性
本公开实施例提供一种比较器电路、失配校正方法和存储器，其中，该比较电路包括：第一晶体管，一端子耦合第一节点，另一端子耦合第一控制节点，栅极用于接收第一控制信号；第二晶体管，一端子耦合第一节点，另一端子耦合第二控制节点，栅极用于接收第二控制信号；第一晶体管和第二晶体管的晶体管掺杂类型相同；负载单元，一端耦合第二节点，另一端耦合第一控制节点和第二控制节点，被配置为，基于第一控制节点的电平调整第二控制节点的电平，或基于第二控制节点的电平调整第一控制节点的电平，第一控制节点和第二控制节点中，被调节的节点用于输出输出信号；第一节点和第二节点中，其中一者用于接收高电平，另一者用于接收低电平；第一调节电路，一端耦合第一节点，另一端耦合第一控制节点，用于根据第一调节信号，调节第一晶体管基于第一控制信号导通后，第一控制节点的节点电位；第二调节电路，一端耦合第一节点，另一端耦合第二控制节点，用于根据第二调节信号，调节第二晶体管基于第二控制信号导通后，第二控制节点的节点电位；第一调节信号和第二调节信号用于调节第一晶体管和第二晶体管的失配。本公开实施例中，通过与第一晶体管并联第一调节电路，第一调节电路基于第一调节信号导通，第一调节电路导通后，第一节点通过第一调节电路与第一控制节点连接，从而调整第一控制节点的电位；通过与第二晶体管并联第二调节电路，第二调节电路基于第二调节信号导通，第二调节电路导通后，第一节点通过第二调节电路与第二控制节点连接，从而调整第二控制节点的电位；通过调整第一调节信号和第二调节信号，使得当第一控制信号和第二控制信号相等时，第一控制节点和第二控制节点的节点电位相等，即通过第一调节电路和第二调节电路，修正了第一晶体管和第二晶体管之间的失配，进而改进存储器性能。

Claims (16)

  1. 一种比较器电路，包括：
    第一晶体管，一端子耦合第一节点，另一端子耦合第一控制节点，栅极用于接收第一控制信号；
    第二晶体管，一端子耦合所述第一节点，另一端子耦合第二控制节点，栅极用于接收第二控制信号；
    所述第一晶体管和所述第二晶体管的晶体管掺杂类型相同；
    负载单元，一端耦合第二节点，另一端耦合所述第一控制节点和所述第二控制节点，被配置为，基于所述第一控制节点的电平调整所述第二控制节点的电平，或基于所述第二控制节点的电平调整所述第一控制节点的电平，所述第一控制节点和所述第二控制节点中，被调节的节点用于输出输出信号；
    所述第一节点和所述第二节点中，其中一者用于接收高电平，另一者用于接收低电平；
    第一调节电路，一端耦合所述第一节点，另一端耦合所述第一控制节点，用于根据第一调节信号，调节所述第一晶体管基于所述第一控制信号导通后，所述第一控制节点的节点电位；
    第二调节电路，一端耦合所述第一节点，另一端耦合所述第二控制节点，用于根据第二调节信号，调节所述第二晶体管基于所述第二控制信号导通后，所述第二控制节点的节点电位；
    所述第一调节信号和所述第二调节信号用于调节所述第一晶体管和所述第二晶体管的失配。
  2. 根据权利要求1所述的比较器电路，其中，
    所述第一调节电路，包括：第一调节晶体管，一端子耦合所述第一节点，另一端子耦合所述第一控制节点，栅极用于接收所述第一调节信号；
    所述第一调节晶体管被配置为基于所述第一调节信号调节源漏电流的大小；
    所述第二调节电路，包括：第二调节晶体管，一端子耦合所述第一节点，另一端子耦合所述第二控制节点，栅极用于接收所述第二调节信号；
    所述第二调节晶体管被配置为基于所述第一调节信号调节源漏电流的大小。
  3. 根据权利要求1所述的比较器电路，其中，
    所述第一调节电路，包括：第一调节晶体管组，所述第一调节晶体管组中包括：x个第一调节晶体管；
    其中，x个所述第一调节晶体管的一端子耦合所述第一节点，另一端子耦合所述第一控制节点，栅极用于接收所述第一调节信号，所述第一调节信号用于选择导通所述第一调节晶体管；
    所述第二调节电路，包括：第二调节晶体管组，所述第二调节晶体管组中包括：x个第二调节晶体管；
    其中，x个所述第二调节晶体管的一端子耦合所述第一节点，另一端子耦合所述第二控制节点，栅极用于接收所述第二调节信号，所述第二调节信号用于选择导通所述第二调节晶体管；
    所述x为大于等于2的整数。
  4. 根据权利要求3所述的比较器电路，其中，x个所述第一调节晶体管基于相同栅极电压开启后的源漏导通能力相同，且x个所述第二调节晶体管基于相同栅极电压开启后的源漏导通能力相同。
  5. 根据权利要求3所述的比较器电路，其中，x个所述第一调节晶体管中，基于相同栅极电压开启后，第n个所述第一调节晶体管的源漏导通能力是第n-1个所述第一调节晶体管的源漏导通能力的两倍；x个所述第二调节晶体管中，基于相同栅极电压开启后，第n个所述第二调节晶体管的源漏导通能力是第n-1个所述第二调节晶体管的源漏导通能力的两倍，所述n为小于等于所述x，且大于等于2的任意整数。
  6. 根据权利要求1所述的比较器电路，还包括：
    开关MOS管，一端子用于耦合电源节点或地线节点，另一端子耦合所述第一节点，栅极用于接收开关使能信号；
    其中，若第一节点用于接收所述高电平，所述开关MOS管耦合电源节点，若第一节点用于接收所述低电平，所述开关MOS管耦合所述地线节点；
    所述开关MOS管与所述第一晶体管掺杂类型相同。
  7. 根据权利要求1所述的比较器电路，还包括：
    第一保护晶体管，与所述第一晶体管类型相同，一端子耦合所述第一节点，另一端子耦合所述第一调节电路，栅极用于接收所述第一控制信号；
    第二保护晶体管，与所述第二晶体管类型相同，一端子耦合所述第一节点，另一端子耦合所述第二调节电路，栅极用于接收所述第二控制信号。
  8. 根据权利要求1所述的比较器电路，其中，所述负载单元包括：
    第三晶体管，一端子耦合第二节点，另一端子耦合所述第一控制节点；
    第四晶体管，一端子耦合所述第二节点，另一端子耦合所述第二控制节点；
    所述第三晶体管的栅极和所述第四晶体管的栅极耦合，并耦合所述第一控制节点；
    其中，所述第三晶体管和所述第四晶体管的晶体管掺杂类型相同，且所述第一晶体管和所述第三晶体管的晶体管掺杂类型不同。
  9. 根据权利要求8所述的比较器电路，其中，所述第一节点用于耦合电源节点，所述第二节点用于耦合地线节点，所述第一晶体管和所述第二晶体管为P型晶体管，所述第三晶体管和所述第四晶体管为N型晶体管。
  10. 根据权利要求1所述的比较器电路，还包括：校准控制电路，用于提供所述第一调节信号和所述第二调节信号。
  11. 根据权利要求10所述的比较器电路，其中，所述校准控制电路，包括：
    时钟模块，用于接收校准使能信号，并基于所述校准使能信号生成校准时钟，所述校准使能信号于校准阶段提供；
    第一校准模块，耦合所述时钟模块，初始设置所述第一调节信号为最大值，所述第二调节信号为最小值，提供所述第一调节信号和所述第二调节信号，并基于所述校准时钟，逐步减小所述第一调节信号，增大所述第二调节信号；
    判断模块，用于接收不同所述第一调节信号和所述第二调节信号对应的输出信号，并获取所述输出信号发生电位翻转的第一时间节点所对应的所述第一调节信号和所述第二调节信号；
    存储模块，耦合所述判断模块，用于获取所述第一时间节点所对应的所述第一调节信号和所述第二调节信号，并在工作阶段提供所述第一时间节点所对应的所述第一调节信号和所述第二调节信号。
  12. 根据权利要求11所述的比较器电路，其中，所述校准控制电路，还包括：
    第二校准模块，耦合所述时钟模块，初始设置所述第一调节信号为最小值，所述第二调节信号为最大值，提供所述第一调节信号和所述第二调节信号，并基于所述校准时钟，逐步增大所述第一调节信号，减小所述第二调节信号；
    所述判断模块，还用于获取所述输出信号发生电位翻转的第二时间节点所对应的所述第一调节信号和所述第二调节信号；
    所述存储模块，还用于获取所述第二时间节点所对应的所述第一调节信号和所述第二调节信号，并将所述第一时间节点和所述第二时间节点对应的所述第一调节信号的平均值作为工作阶段所需提供的所述第一调节信号，将所述第一时间节点和所述第二时间节点对应的所述第二调节信号的平均值作为工作阶段所需提供的所述第二调节信号。
  13. 根据权利要求1所述的比较器电路，还包括：
    第一选择电路，接收输入选择信号、输入信号或参考信号，用于提供所述第一控制信号；
    第二选择电路，接收所述输入选择信号、所述输入信号或所述参考信号，用于提供所述第二控制信号；
    所述第一选择电路被配置为，基于所述输入选择信号选择以所述输入信号或所述参考信号提供所述第一控制信号；
    所述第二选择电路被配置为，基于所述输入选择信号选择以所述输入信号或所述参考信号提供所述第二控制信号。
  14. 一种失配校正方法，应用于权利要求1～13中任一项所述比较器电路，包括：
    在校准阶段，控制所述第一控制信号和所述第二控制信号的输入相同；
    初始设置所述第一调节信号为最大值，所述第二调节信号为最小值；
    依次减小所述第一调节信号并增大所述第二调节信号，并获取对应于不同所述第一调节信号和所述第二调节信号的输出信号；
    获取所述输出信号发生电位翻转的第一时间节点所对应的所述第一调节信号和所述第二调节信号；
    将所述第一时间节点对应的所述第一调节信号和所述第二调节信号作为工作阶段所需提供的所述第一调节信号和所述第二调节信号。
  15. 根据权利要求14所述的失配校正方法，其中，所述获取所述输出信号发生电位翻转的第一时间节点所对应的所述第一调节信号和第二调节信号之后，还包括：
    初始设置所述第一调节信号为最小值，所述第二调节信号为最大值；
    依次增大所述第一调节信号并减小所述第二调节信号，并获取对应于不同所述第一调节信号和所述第二调节信号的输出信号；
    获取所述输出信号发生电位翻转的第二时间节点所对应的所述第一调节信号和所述第二调节信号；
    所述将所述第一时间节点对应的所述第一调节信号和所述第二调节信号作为工作阶段所需提供的所述第一调节信号和所述第二调节信号，包括：将所述第一时间节点和所述第二时间节点对应的所述第一调节信号的平均值作为工作阶段所需提供的所述第一调节信号；将所述第一时间节点和所述第二时间节点对应的所述第二调节信号的平均值作为工作阶段所需提供的所述第二调节信号。
  16. 一种存储器，应用权利要求1～13任一项所述比较器电路进行数据输入。
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US20230327656A1 (en) 2023-10-12

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