WO2023178772A1 - Goa电路的驱动方法、栅极驱动器及显示面板 - Google Patents

Goa电路的驱动方法、栅极驱动器及显示面板 Download PDF

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Publication number
WO2023178772A1
WO2023178772A1 PCT/CN2022/087292 CN2022087292W WO2023178772A1 WO 2023178772 A1 WO2023178772 A1 WO 2023178772A1 CN 2022087292 W CN2022087292 W CN 2022087292W WO 2023178772 A1 WO2023178772 A1 WO 2023178772A1
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Prior art keywords
potential
high potential
low potential
goa circuit
low
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English (en)
French (fr)
Inventor
汪丽芳
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US17/771,897 priority Critical patent/US12322312B2/en
Publication of WO2023178772A1 publication Critical patent/WO2023178772A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms

Definitions

  • the present invention relates to the field of display technology, and in particular to a driving method of a GOA circuit, a gate driver and a display panel.
  • the GOA circuit provides a gate signal to the scan line to open each row of pixel units, due to the presence of RC in the scan line loading, so there is a distortion delay in the scanning signal, that is, the rise time Tr1 of the gate signal (scanning signal) received by each pixel unit rises from the off potential VGL to the on potential VGH is not 0, and when a row of pixel units is turned off, the gate
  • the fall time Tf1 for the signal from the turn-on potential VGH to 0 is also not 0, and the rise time Tr1 and fall time Tf1 of the gate signal received by the pixel unit closer to the GOA circuit are smaller, and the pixels further away from the GOA circuit are smaller.
  • the rise time Tr1 and fall time Tf1 of the gate signal received by the unit are both larger, that is, it takes a certain time to open and close each row of pixel units, and the closer to the GOA circuit, the shorter the time required to open and close. The farther away the GOA circuit is, the longer it takes to open and close.
  • embodiments of the present invention provide a driving method, a gate driver and a display panel for a GOA circuit.
  • the driving method of the GOA circuit further includes: during the off stage of each row of pixel units, causing the scanning signal to drop from the second high potential to the second low potential within a second preset time period, Then it rises from the second low potential to the first low potential, and the second low potential is lower than the first low potential; wherein, the second preset duration is when the scan signal changes from the first low potential to the first low potential.
  • the minimum drop of a high potential is the time required for the first low potential.
  • the driving method of the GOA circuit further includes: between the on stage and the off stage of the pixel unit in each row, causing the scanning signal to drop from the second high potential to the first low level. before the potential, the scanning signal is also caused to drop from the second high potential to the first high potential and maintained for a third preset time period; wherein the third preset time period is the most complete time for each pixel unit to turn on. charging time.
  • the driving method of the GOA circuit further includes: after the off stage of the pixel unit in each row, also causing the scanning signal to rise from the second low potential to the first low potential.
  • the first high potential ranges from 20V to 35V, and the first low potential ranges from -5V to -10V.
  • the thin film transistors in the GOA circuit are all N-type thin film transistors.
  • embodiments of the present invention further provide a gate driver.
  • the gate driver includes a GOA circuit, the GOA circuit is used to output a scanning signal; the gate driver is used to cause the GOA circuit to output the
  • the scanning signals are sequentially raised from the first low potential to the first high potential and the second high potential within the first preset time period, and the second high potential is high.
  • the first high potential is higher than the first low potential; wherein, the first preset time period is when the scan signal rises from the first low potential to the highest level of the first low potential.
  • the duration required for a high potential; the first high potential is the turn-on potential of the pixel unit, and the first low potential is the turn-off potential of the pixel unit.
  • the scan signal when the gate driver causes the GOA circuit to output the scan signal, during the off stage of the pixel unit in each row, the scan signal is generated by the first preset time period within a second preset time period.
  • the two high potentials successively drop to the first low potential and the second low potential, and the second low potential is lower than the first low potential; wherein, the second preset duration is when the scanning signal is The minimum decrease of the first high potential is the time required for the first low potential.
  • the gate driver is also used to cause the GOA circuit to output the scan signal, during the off phase of the pixel unit in each row, when the scan signal drops from the second high potential.
  • the scanning signal is also dropped from the second high potential to the first high potential and maintained for a third preset time period; wherein the third preset time period is for each The charging time when the pixel unit is fully turned on.
  • the first high potential ranges from 20V to 35V, and the first low potential ranges from -5V to -10V.
  • embodiments of the present invention further provide a display panel, including a gate driver as described above, the gate driver including a GOA circuit, and the GOA circuit is used to output a scanning signal;
  • the scan signal sequentially rises from a first low level to a first level within a first preset time period.
  • a high potential and a second high potential the second high potential is higher than the first high potential, and the first high potential is higher than the first low potential;
  • the first preset duration is the duration required for the scanning signal to rise from the first low potential to the first high potential
  • the first high potential is the turn-on potential of the pixel unit
  • the first low potential is the turn-off potential of the pixel unit.
  • the gate driver when the gate driver causes the GOA circuit to output the scan signal, during the off stage of the pixel unit in each row, the scan signal is generated by the first preset time period within a second preset time period.
  • the two high potentials decrease to the first low potential and the second low potential in sequence, and the second low potential is lower than the first low potential;
  • the second preset duration is the duration required for the scanning signal to minimum decrease from the first high potential to the first low potential.
  • the gate driver is also used to cause the GOA circuit to output the scan signal, during the off phase of the pixel unit in each row, when the scan signal drops from the second high potential.
  • the scanning signal is also dropped from the second high potential to the first high potential and maintained for a third preset time period; wherein the third preset time period is for each The charging time when the pixel unit is fully turned on.
  • the gate driver when the gate driver is also used to cause the GOA circuit to output the scan signal, it further includes: after the turn-off stage of the pixel unit in each row, also causing the scan signal to be generated by the The second low potential rises to the first low potential.
  • the first high potential ranges from 20V to 35V, and the first low potential ranges from -5V to -10V.
  • the thin film transistors in the GOA circuit are all N-type thin film transistors.
  • the scanning signal is changed from the first low potential to the first high potential.
  • the first low potential rises to the first high potential and the second high potential in sequence, thereby reducing the time for the scanning signal to rise from the first low potential to the first high potential, thereby allowing the pixel unit in the display area of the display panel to move faster Charge earlier to increase the charging rate of the pixel unit; similarly, within the second preset time period required for the scanning signal to drop from the first high potential to the first low potential, the scanning signal is changed from the first high potential to the first low potential.
  • Figure 1 is a timing diagram of a scanning signal in the prior art
  • Figure 2 is a schematic structural diagram of a conventional 1T2C LCD pixel unit driving circuit in the prior art
  • Figure 3 is a schematic structural diagram of a conventional 2T1C OLED pixel unit driving circuit in the prior art
  • Figure 4 is a first timing diagram of scanning signals in the driving method of the GOA circuit provided by the embodiment of the present invention.
  • the writing transistor T1 When the gate-source potential Vgs of the writing transistor T1 > the threshold voltage Vth of the writing transistor, the writing transistor T1 is already turned on until the gate potential of the writing transistor T1 reaches the first When the high potential VGH1 is, the write transistor T1 is fully turned on; similarly, the turn-off potential of each pixel unit is the potential at which the write transistor of the pixel unit drive circuit in the pixel unit is completely turned off, and the turn-off process of each pixel unit is not Transiently, when the gate-source potential Vgs of the writing transistor T1 ⁇ the threshold voltage Vth of the writing transistor T1, the writing transistor T1 is turned off until the gate potential of the writing transistor T1 reaches the first low potential VGL1. , the write transistor is completely turned off, that is, the first high potential VGH1 is the turn-on potential of the write transistor T1, and the first low potential VGL1 is the turn-off potential of the write transistor T1.
  • the solid line is a timing diagram of the scanning signal in the driving method of the GOA circuit provided by the embodiment of the present invention
  • the dotted line is a timing diagram of the scanning signal in the prior art
  • the dotted line is the horizontal and vertical coordinates of each corresponding position.
  • the scanning signal rises from the first low potential VGL1 to the second high potential VGH2.
  • the scanning signal decreases from The time required for the first low potential VGL1 to rise to the turn-on potential of the pixel unit, that is, the first high potential VGH1, thereby enabling the pixel units in the display area of the display panel to be charged faster and earlier, thereby increasing the charging rate of the pixel unit .
  • the scanning signal will fall from the first high potential VGH1 to a minimum level lower than the first low potential.
  • the waveform of the lower potential of VGL1 is steeper than the waveform of the lowest drop to the first low potential VGL1, that is, the slope is larger. Therefore, in the process of the lowest drop to the second low potential VGL2, the scanning signal actually drops to the first lowest level.
  • the time period t2' required for the potential VGL1 is less than the second preset time period t2.
  • the scanning signal drops from the first high potential VGH1 to the second low potential VGL2.
  • the time required for the scan signal to drop from the first high potential VGH1 to the turn-off voltage of the pixel unit, that is, the first low potential VGL1 is reduced. Therefore, This allows the pixel units in the display area of the display panel to be turned off faster and earlier, thereby reducing the risk of mischarge of the pixel units.
  • an embodiment of the present invention provides a driving method for a GOA circuit, which includes: during the turn-on phase of each row of pixel units, the scanning signal sequentially rises from the first low potential VGL1 to The first high potential VGH1 and the second high potential VGH2, the second high potential VGH2 is higher than the first high potential VGH1, the first high potential VGH1 is higher than the first low potential VGL1; wherein, the first preset time length t1 is the scanning signal The time required for the first low potential VGL1 to rise up to the first high potential VGH1; the first high potential VGH1 is the turn-on potential of the pixel unit, and the first low potential VGL1 is the turn-off potential of the pixel unit.
  • the driving method of the GOA circuit is to change the scanning signal from the first low level to the first high level within the first preset time period t1 required for the scanning signal to rise from the first low level VGL1 to the first high level VGH1.
  • the potential VGL1 rises to the first high potential VGH1 and the second high potential VGH2 in sequence, thereby reducing the time period for the scanning signal to rise from the first low potential VGL1 to the first high potential VGH1, thereby enabling the pixel unit in the display area of the display panel to Charge faster and earlier, thereby increasing the pixel unit charging rate;
  • the driving method of the GOA circuit also includes: during the off stage of each row of pixel units, the scanning signal drops from the second high potential VGH2 to the second low potential VGL2 within the second preset time period t2, and then It rises from the second low potential VGL2 to the first low potential VGL1, and the second low potential VGL2 is lower than the first low potential VGL1.
  • the second preset time period t2 is when the scan signal drops from the first high potential VGH1 to the first low. The time required for the potential VGL1.
  • the driving method of the GOA circuit changes the scanning signal from the first high potential to the first low potential VGL1 within the second preset time period t2 required for the scanning signal to drop from the first high potential VGH1 to the first low potential VGL1.
  • VGH1 drops to the second low potential VGL2
  • the pixel units in the display area can be turned off faster and earlier, thereby reducing the risk of mischarge of pixel units.
  • the scanning signal is kept at the second low potential VGL2 during the off stage of the pixel unit, it will also increase the power consumption of the GOA circuit and the display panel. Therefore, after the scanning signal reaches the second low potential VGL2, the scanning signal will also be It rises from the second low potential VGL2 to the first low potential VGL1.
  • the gate driver sets the waveform of the scanning signal output by the GOA circuit, it actually sets the waveform of the scanning signal by directly setting the potential of the scanning signal, that is, it actually sets the second high potential VGH2 and the second low potential VGL2
  • the potential of the scanning signal is set to the waveform of the scanning signal.
  • the highest potential reached by the actually set scanning signal may be higher than the second high potential VGH2 in Figure 4.
  • the potential is high or low, and the lowest potential reached by the actually set scanning signal may be higher or lower than the potential of the second lowest potential VGL2 in Figure 4.
  • the highest potential that the actually set scanning signal reaches is higher than the first high potential VGH1, and the lowest potential that the actually set scanning signal reaches is lower than the first low potential VGL1.
  • the highest potential of the actually set scanning signal is higher than the second high potential VGH2 in Figure 4, or the lowest potential of the actually set scanning signal is lower than the second low potential VGL2 of Figure 4, for example, as shown in Figure 4
  • the highest potential reached by the scanning signal is actually set to the third high potential VGH3, which is higher than the second high potential VGH2.
  • the time period for rising from the first low potential VGL1 to the third high potential VGH3 is longer than the first preset time length t1.
  • the scanning signal rises sequentially from the first low potential VGL1 to the first high potential VGH1 and the third high potential VGH3, then the scanning signal actually rises from the first low potential VGL1 to the first high potential VGH1
  • the required duration t1' is less than the first preset duration t1, which reduces the duration for the scan signal to rise from the first low potential VGL1 to the first high potential VGH1; similarly, the lowest potential the scan signal reaches is actually set to be lower than the second
  • the third low potential VGL3 with the lower potential VGL2 then drops from the first high potential VGH1 to the third low potential VGL3 for longer than the second preset time length t2.
  • the scanning signal changes from the first high potential to the third low potential VGL3.
  • VGH1 drops to the third low potential VGL3 at the lowest, and then rises from the third low potential VGL3 to the first low potential VGL1.
  • the time t2' required for the scanning signal to actually drop from the first high potential VGH1 to the first low potential VGL1 is less than the first low potential VGL1.
  • the second preset time period t2 is to reduce the time period for the scanning signal to drop from the first high potential VGH1 to the first low potential VGL1.
  • the highest potential that the actually set scanning signal reaches is lower than the second highest potential VGH2 in Figure 4, or the lowest potential that the actually set scanning signal reaches is higher than the second low potential VGL2 in Figure 4, for example, in Figure 6
  • the highest potential reached by the scan signal is actually set to the second actual high potential VGH2' which is lower than the second high potential VGH2, then the time period for rising from the first low potential VGL1 to the second actual high potential VGH2' is shorter than the first predetermined time.
  • the scanning signal rises from the first low potential VGL1 to the first high potential VGH1 and the second actual high potential VGH2' in sequence, then the scanning signal actually rises from the first low potential VGL1 to
  • the duration t1' required for the first high potential VGH1 is less than the first preset duration t1, which reduces the duration for the scanning signal to rise from the first low potential VGL1 to the first high potential VGH1; similarly, the actual minimum setting of the scanning signal reaches The second actual low potential VGL2', which has a higher potential than the second low potential VGL2, then the duration of the drop from the first high potential VGH1 to the second actual low potential VGL2' is less than the second preset duration t2.
  • the scanning signal drops from the first high potential VGH1 to the second actual low potential VGL2', and then rises from the second actual low potential VGL2' to the first low potential VGL1, then the scanning signal actually drops from the first high potential VGH1 to
  • the time period t2' required for the first low potential VGL1 is shorter than the second predetermined time period t2, that is, the time period for the scanning signal to drop from the first high potential VGH1 to the first low potential VGL1 is reduced.
  • embodiments of the present invention also provide a gate driver, which includes a GOA circuit.
  • the GOA circuit is used to output a scanning signal; the gate driver is used to cause the GOA circuit to output a scanning signal during the turn-on phase of each row of pixel units. , causing the scanning signal to rise sequentially from the first low potential VGL1 to the first high potential VGH1 and the second high potential VGH2 within the first preset time period t1.
  • the second high potential VGH2 is higher than the first high potential VGH1.
  • the first high potential VGH1 is higher than the first low potential VGL1; wherein, the first preset time length t1 is the time required for the scanning signal to rise from the first low potential VGL1 to the first high potential VGH1; the first high potential VGH1 is the turn-on potential of the pixel unit , the first low potential VGL1 is the turn-off potential of the pixel unit.
  • the gate driver when the gate driver causes the GOA circuit to output a scanning signal, during the off stage of each row of pixel units, the scanning signal sequentially drops from the second high potential VGH2 to the first low potential within the second preset time period t2 VGL1 and the second low potential VGL2, the second low potential VGL2 is lower than the first low potential VGL1; wherein, the second preset time length t2 is the time required for the scanning signal to decrease from the first high potential VGH1 to the first low potential VGL1 .
  • the gate driver is also used to cause the GOA circuit to output a scan signal, during the off stage of each row of pixel units, before the scan signal drops from the second high potential VGH2 to the first low potential VGL1.
  • the signal drops from the second high potential VGH2 to the first high potential VGH1 and remains for a third preset time period t3; wherein the third preset time period t3 is the charging time period when each pixel unit is most completely turned on.
  • embodiments of the present invention also provide a display panel, including the gate driver as described above.
  • the display panel and the gate driver have the same working principles and beneficial effects. Since the above embodiments have already implemented the gate driver, The pole driver is described in detail and will not be repeated here.

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Abstract

一种GOA电路的驱动方法、栅极驱动器及显示面板，能减少扫描信号由第一低电位(VGL1)上升至第一高电位(VGH1)的时长，由此使像素单元能更快更早地进行充电，从而提升像素单元的充电率；并且，还能减少扫描信号由第一高电位(VGH1)下降至第一低电位(VGL1)的时长，由此使像素单元能更快更早地关闭，从而降低像素单元错充的风险。

Description

GOA电路的驱动方法、栅极驱动器及显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路的驱动方法、栅极驱动器及显示面板。
 背景技术
如图1所示，GOA电路提供gate信号给扫描线打开每行像素单元时，由于扫描线存在RC loading，因此扫描信号存在失真延迟，即每个像素单元接收到的gate信号（扫描信号）由关断电位VGL上升到开启电位VGH的上升时间Tr1不为0，而当一行像素单元关闭时，gate信号由开启电位VGH下降至0的下降时间Tf1也不为0，且距离GOA电路越近的像素单元接收到的gate信号的上升时间Tr1和下降时间Tf1均越小，距离GOA电路越远的像素单元接收到的gate信号的上升时间Tr1和下降时间Tf1均越大，即每行像素单元的打开和关闭均需要一定的时间，且距离GOA电路越近，打开和关闭需要的时间越短，距离GOA电路越远，打开和关闭需要的时间越长。
 技术问题
当显示面板的刷新率确定时，每行像素单元的充电时间是固定的，t=1/刷新率。随着显示面板的尺寸和分辨率的增大，每行像素单元的充电时间减少，充电率降低。显示面板在gate信号使每行像素单元打开之后，由源极驱动器IC提供的source信号同时向每行像素单元的每个像素单元充电，因此对于同一行像素单元，距离GOA电路远的像素单元的打开和关闭需要的时间较长，实际充电时间会减少，导致距离GOA电路远近不同的像素单元的亮度出现差异，显示面板的均一性较差，并且随着目前长条形横向面板的广泛应用，这种问题越来越严重。
因此，有必要提出一种GOA电路的驱动方法，用于减少每行像素单元打开和关闭的时间，以增加每行像素单元的实际充电时间，提高显示面板的均一性。
 技术解决方案
为了解决上述问题，本发明实施例提供一种GOA电路的驱动方法、栅极驱动器及显示面板。
第一方面，本发明实施例提供一种GOA电路的驱动方法，包括：
在每行像素单元的开启阶段，使扫描信号在第一预设时长内由第一低电位依次上升至第一高电位和第二高电位，所述第二高电位高于所述第一高电位，所述第一高电位高于所述第一低电位；其中，所述第一预设时长为所述扫描信号由所述第一低电位最高上升为所述第一高电位所需的时长；所述第一高电位为所述像素单元的开启电位，所述第一低电位为所述像素单元的关断电位。
在一些实施例中，该GOA电路的驱动方法还包括：在每行像素单元的关闭阶段，使所述扫描信号在第二预设时长内由所述第二高电位下降至第二低电位，然后由所述第二低电位上升至所述第一低电位，所述第二低电位低于所述第一低电位；其中，所述第二预设时长为所述扫描信号由所述第一高电位最低下降为所述第一低电位所需的时长。
在一些实施例中，该GOA电路的驱动方法还包括：在每行所述像素单元的开启阶段至关闭阶段之间，使得所述扫描信号由所述第二高电位下降至所述第一低电位之前，还使得所述扫描信号由所述第二高电位下降至所述第一高电位并保持第三预设时长；其中，所述第三预设时长为每个像素单元打开最彻底时的充电时长。
在一些实施例中，该GOA电路的驱动方法还包括：在每行所述像素单元的关闭阶段之后，还使得所述扫描信号由所述第二低电位上升至所述第一低电位。
在一些实施例中，所述第一高电位的范围为20V~35V，所述第一低电位的范围为-5V~-10V。
在一些实施例中，所述GOA电路中的薄膜晶体管均采用N型薄膜晶体管。
第二方面，本发明实施例还提供一种栅极驱动器，所述栅极驱动器包括GOA电路，所述GOA电路用于输出扫描信号；所述栅极驱动器用于使所述GOA电路输出所述扫描信号时，在每行像素单元的开启阶段，使所述扫描信号在第一预设时长内由第一低电位依次上升至第一高电位和第二高电位，所述第二高电位高于所述第一高电位，所述第一高电位高于所述第一低电位；其中，所述第一预设时长为所述扫描信号由所述第一低电位最高上升为所述第一高电位所需的时长；所述第一高电位为所述像素单元的开启电位，所述第一低电位为所述像素单元的关断电位。
在一些实施例中，所述栅极驱动器使所述GOA电路输出所述扫描信号时，在每行所述像素单元的关闭阶段，使所述扫描信号在第二预设时长内由所述第二高电位依次下降至所述第一低电位和第二低电位，所述第二低电位低于所述第一低电位；其中，所述第二预设时长为所述扫描信号由所述第一高电位最低下降为所述第一低电位所需的时长。
在一些实施例中，所述栅极驱动器还用于使所述GOA电路输出所述扫描信号时，在每行所述像素单元的关闭阶段，在所述扫描信号由所述第二高电位下降至所述第一低电位之前，还使得所述扫描信号由所述第二高电位下降至所述第一高电位并保持第三预设时长；其中，所述第三预设时长为每个像素单元打开最彻底时的充电时长。
在一些实施例中，所述栅极驱动器还用于使所述GOA电路输出所述扫描信号时，还包括：在每行所述像素单元的关闭阶段之后，还使得所述扫描信号由所述第二低电位上升至所述第一低电位。
在一些实施例中，所述第一高电位的范围为20V~35V，所述第一低电位的范围为-5V~-10V。
第三方面，本发明实施例还提供一种显示面板，包括如上所述的栅极驱动器，所述栅极驱动器包括GOA电路，所述GOA电路用于输出扫描信号；
所述栅极驱动器用于使所述GOA电路输出所述扫描信号时，在每行像素单元的开启阶段，使所述扫描信号在第一预设时长内由第一低电位依次上升至第一高电位和第二高电位，所述第二高电位高于所述第一高电位，所述第一高电位高于所述第一低电位；
其中，所述第一预设时长为所述扫描信号由所述第一低电位最高上升为所述第一高电位所需的时长；
所述第一高电位为所述像素单元的开启电位，所述第一低电位为所述像素单元的关断电位。
在一些实施例中，所述栅极驱动器使所述GOA电路输出所述扫描信号时，在每行所述像素单元的关闭阶段，使所述扫描信号在第二预设时长内由所述第二高电位依次下降至所述第一低电位和第二低电位，所述第二低电位低于所述第一低电位；
其中，所述第二预设时长为所述扫描信号由所述第一高电位最低下降为所述第一低电位所需的时长。
在一些实施例中，所述栅极驱动器还用于使所述GOA电路输出所述扫描信号时，在每行所述像素单元的关闭阶段，在所述扫描信号由所述第二高电位下降至所述第一低电位之前，还使得所述扫描信号由所述第二高电位下降至所述第一高电位并保持第三预设时长；其中，所述第三预设时长为每个像素单元打开最彻底时的充电时长。
在一些实施例中，所述栅极驱动器还用于使所述GOA电路输出所述扫描信号时，还包括：在每行所述像素单元的关闭阶段之后，还使得所述扫描信号由所述第二低电位上升至所述第一低电位。
在一些实施例中，所述第一高电位的范围为20V~35V，所述第一低电位的范围为-5V~-10V。
在一些实施例中，所述GOA电路中的薄膜晶体管均采用N型薄膜晶体管。
 有益效果
本发明实施例提供的GOA电路的驱动方法、栅极驱动器及显示面板中，通过在扫描信号由第一低电位最高上升为第一高电位所需的第一预设时长内，将扫描信号由第一低电位依次上升至第一高电位和第二高电位，从而减少扫描信号由第一低电位上升至第一高电位的时长，由此使得显示面板的显示区内的像素单元能更快更早地进行充电，从而提升像素单元的充电率；同理，在扫描信号由第一高电位最低下降为第一低电位所需的第二预设时长内，将扫描信号由第一高电位下降至第二低电位之后，再由第二低电位上升至第一低电位，从而减少扫描信号由第一高电位下降至第一低电位的时长，由此使得显示面板的显示区内的像素单元能更快更早地关闭，从而降低像素单元错充的风险。
 附图说明
图1为现有技术的扫描信号的时序示意图；
图2为现有技术的常规1T2C LCD像素单元驱动电路的结构示意图；
图3为现有技术的常规2T1C OLED像素单元驱动电路的结构示意图；
图4为本发明实施例提供的GOA电路的驱动方法中扫描信号的第一种时序示意图；
图5为本发明实施例提供的GOA电路的驱动方法中扫描信号的第二种时序示意图；
图6为本发明实施例提供的GOA电路的驱动方法中扫描信号的第三种时序示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需要说明的是，当栅极驱动器中的GOA电路输出扫描信号至一行像素单元时，该行像素单元打开，然后由源极驱动器通过多条数据线分别向该行像素单元同步输入数据信号，即，如图2所示的常规1T2C LCD像素单元驱动电路（其中T1为写入晶体管，Cst为存储电容，Clc为液晶电容）或如图3所示的2T1C OLED像素单元驱动电路（其中T1为写入晶体管，T2为驱动晶体管，C为存储电容）中，写入晶体管T1的栅极受扫描信号（gate信号）控制打开，然后由数据线通过写入晶体管使该像素单元充电，即，像素单元的开启阶段是指该像素单元中像素单元驱动电路的写入晶体管的打开过程，像素单元的关闭阶段是该像素单元中像素单元驱动电路的写入晶体管的关闭过程。需要注意的是，本发明实施例是以写入晶体管为N型薄膜晶体管为例进行说明的。
还需要说明的是，每个像素单元的开启电位为该像素单元中像素单元驱动电路的写入晶体管彻底打开的电位，但是实际上每个像素单元的打开过程并不是瞬态的，若写入晶体管T1为N型薄膜晶体管，则在写入晶体管T1的栅源极电位Vgs＞写入晶体管的阈值电压Vth时，写入晶体管T1就已经开启，直至写入晶体管T1的栅极电位达到第一高电位VGH1时，写入晶体管T1完全开启；同样地，每个像素单元的关断电位为该像素单元中像素单元驱动电路的写入晶体管彻底关闭的电位，每个像素单元的关闭过程也不是瞬态的，当写入晶体管T1的栅源极电位Vgs≤写入晶体管T1的阈值电压Vth时，写入晶体管T1就已经关闭，直至写入晶体管T1的栅极电位达到第一低电位VGL1时，写入晶体管完全关闭，即第一高电位VGH1为写入晶体管T1的开启电位，第一低电位VGL1为写入晶体管T1的关断电位。
图4、图5和图6中，实线为本发明实施例提供的GOA电路的驱动方法中扫描信号的时序示意图，点虚线为现有技术的扫描信号的时序示意图，虚线为各个横纵坐标的对应位置。
本发明实施例中，对于同一栅极驱动器，其包括的GOA电路的驱动能力保持不变，在同一驱动能力下，若扫描信号由第一低电位VGL1最高上升至第一高电位VGH1所需的时长为第一预设时长t1，则扫描信号由第一低电位VGL1最高上升至比第一高电位VGH1更高的电位的波形比最高上升至第一高电位VGH1的波形更陡峭一些，即斜率更大一些，因此扫描信号在最高上升至第二高电位VGH2的过程中，实际上升至第一高电位VGH1所需的时长t1’小于第一预设时长t1，也就是说，若在同样的第一预设时长t1内，扫描信号由第一低电位VGL1最高上升至第二高电位VGH2，相比于扫描信号由第一低电位VGL1最高上升为第一高电位VGH1，减少了扫描信号由第一低电位VGL1上升至像素单元的开启电位即第一高电位VGH1所需的时长，由此使得显示面板的显示区内的像素单元能更快更早地进行充电，从而提升像素单元充电率。
同理，若扫描信号由第一高电位VGH1仅最低下降至第一低电位VGL1所需的时长为第二预设时长t2，则扫描信号由第一高电位VGH1最低下降至比第一低电位VGL1更低的电位的波形比最低下降至第一低电位VGL1的波形更陡峭一些，即斜率更大一些，因此扫描信号在最低下降至第二低电位VGL2的过程中，实际下降至第一低电位VGL1所需的时长t2’小于第二预设时长t2，也就是说，若在同样的第一预设时长t1内，扫描信号由第一高电位VGH1最低下降至第二低电位VGL2，相比于扫描信号由第一高电位VGH1最低下降至第一低电位VGL1，减少了扫描信号由第一高电位VGH1下降至像素单元的关断电压即第一低电位VGL1所需的时长，由此使得显示面板的显示区内的像素单元能更快更早地关闭，从而降低像素单元错充的风险。
如图4所示，本发明实施例提供一种GOA电路的驱动方法，包括：在每行像素单元的开启阶段，使扫描信号在第一预设时长t1内由第一低电位VGL1依次上升至第一高电位VGH1和第二高电位VGH2，第二高电位VGH2高于第一高电位VGH1，第一高电位VGH1高于第一低电位VGL1；其中，第一预设时长t1为扫描信号由第一低电位VGL1最高上升为第一高电位VGH1所需的时长；第一高电位VGH1为像素单元的开启电位，第一低电位VGL1为像素单元的关断电位。
即，本发明实施例提供的GOA电路的驱动方法，通过在扫描信号由第一低电位VGL1最高上升为第一高电位VGH1所需的第一预设时长t1内，将扫描信号由第一低电位VGL1依次上升至第一高电位VGH1和第二高电位VGH2，从而减少扫描信号由第一低电位VGL1上升至第一高电位VGH1的时长，由此使得显示面板的显示区内的像素单元能更快更早地进行充电，从而提升像素单元充电率；
请继续参阅图4，该GOA电路的驱动方法还包括：在每行像素单元的关闭阶段，使扫描信号在第二预设时长t2内由第二高电位VGH2下降至第二低电位VGL2，再由第二低电位VGL2上升至第一低电位VGL1，第二低电位VGL2低于第一低电位VGL1；其中，第二预设时长t2为扫描信号由第一高电位VGH1最低下降为第一低电位VGL1所需的时长。
即，本发明实施例提供的GOA电路的驱动方法，在扫描信号由第一高电位VGH1最低下降为第一低电位VGL1所需的第二预设时长t2内，将扫描信号由第一高电位VGH1下降至第二低电位VGL2之后，再由第二低电位VGL2上升至第一低电位VGL1，从而减少扫描信号由第一高电位VGH1下降至第一低电位VGL1的时长，由此使得显示面板的显示区内的像素单元能更快更早地关闭，从而降低像素单元错充的风险。
进一步地，若在像素单元的开启阶段，使扫描信号一直保持第二高电位VGH2进行充电，会增加GOA电路的功耗，从而使得显示面板能耗增加，因此本发明实施例在扫描信号达到第二高电位VGH2之后，还将扫描信号由第二高电位VGH2下降至第一高电位VGH1之后保持第三预设时长t3，使得像素单元持续充电，第三预设时长t3为每个像素单元打开最彻底时的充电时长。同理，若在像素单元的关闭阶段，使扫描信号一直保持第二低电位VGL2，也会增加GOA电路和显示面板的功耗，因此在扫描信号达到第二低电位VGL2之后，还将扫描信号由第二低电位VGL2上升至第一低电位VGL1。
其中，栅极驱动器设置GOA电路输出的扫描信号的波形时，实际一般是通过直接设置扫描信号的电位来设置扫描信号的波形，即，实际是通过设置第二高电位VGH2和第二低电位VGL2的电位来设置扫描信号的波形，但是由于预先难以确定第二高电位VGH2和第二低电位VGL2的电位，因此实际设置的扫描信号达到的最高电位可能比图4中的第二高电位VGH2的电位高或者低，而实际设置的扫描信号达到的最低电位可能比图4中的第二低电位VGL2的电位高或者低。并且可以理解的是，实际设置的扫描信号达到的最高电位高于第一高电位VGH1，实际设置的扫描信号达到的最低电位低于第一低电位VGL1。
具体地，若实际设置的扫描信号达到的最高电位比图4中的第二高电位VGH2高时，或者实际设置的扫描信号达到的最低电位比图4中的第二低电位VGL2低，例如图5所示，实际设置扫描信号达到的最高电位为比第二高电位VGH2高的第三高电位VGH3，则由第一低电位VGL1上升至第三高电位VGH3的时长大于第一预设时长t1，在第一预设时长t1内，扫描信号由第一低电位VGL1依次上升至第一高电位VGH1和第三高电位VGH3，则扫描信号实际由第一低电位VGL1上升至第一高电位VGH1所需的时长t1’小于第一预设时长t1，即减少了扫描信号由第一低电位VGL1上升至第一高电位VGH1的时长；同理，实际设置扫描信号达到的最低电位比第二低电位VGL2低的第三低电位VGL3，则由第一高电位VGH1下降至第三低电位VGL3的时长大于第二预设时长t2，在第二预设时长t2内，扫描信号由第一高电位VGH1最低下降至第三低电位VGL3，再由第三低电位VGL3上升至第一低电位VGL1，则扫描信号实际由第一高电位VGH1下降至第一低电位VGL1所需的时长t2’小于第二预设时长t2，即减少了扫描信号由第一高电位VGH1下降至第一低电位VGL1的时长。
而若实际设置的扫描信号达到的最高电位比图4中的第二高电位VGH2低时，或者实际设置的扫描信号达到的最低电位比图4中的第二低电位VGL2高，例如图6中所示，实际设置扫描信号达到的最高电位为比第二高电位VGH2低的第二实际高电位VGH2’，则由第一低电位VGL1上升至第二实际高电位VGH2’的时长小于第一预设时长t1，在第一预设时长t1内，扫描信号由第一低电位VGL1依次上升至第一高电位VGH1和第二实际高电位VGH2’，则扫描信号实际由第一低电位VGL1上升至第一高电位VGH1所需的时长t1’小于第一预设时长t1，即减少了扫描信号由第一低电位VGL1上升至第一高电位VGH1的时长；同理，实际设置扫描信号达到的最低电位比第二低电位VGL2高的第二实际低电位VGL2’，则由第一高电位VGH1下降至第二实际低电位VGL2’的时长小于第二预设时长t2，在第二预设时长t2内，扫描信号由第一高电位VGH1最低下降至第二实际低电位VGL2’，再由第二实际低电位VGL2’上升至第一低电位VGL1，则扫描信号实际由第一高电位VGH1下降至第一低电位VGL1所需的时长t2’小于第二预设时长t2，即减少了扫描信号由第一高电位VGH1下降至第一低电位VGL1的时长。
基于上述实施例，本发明实施例还提供一种栅极驱动器，包括GOA电路，GOA电路用于输出扫描信号；栅极驱动器用于使GOA电路输出扫描信号时，在每行像素单元的开启阶段，使扫描信号在第一预设时长t1内由第一低电位VGL1依次上升至第一高电位VGH1和第二高电位VGH2，第二高电位VGH2高于第一高电位VGH1，第一高电位VGH1高于第一低电位VGL1；其中，第一预设时长t1为扫描信号由第一低电位VGL1最高上升为第一高电位VGH1所需的时长；第一高电位VGH1为像素单元的开启电位，第一低电位VGL1为像素单元的关断电位。
在一些实施例中，栅极驱动器使GOA电路输出扫描信号时，在每行像素单元的关闭阶段，使扫描信号在第二预设时长t2内由第二高电位VGH2依次下降至第一低电位VGL1和第二低电位VGL2，第二低电位VGL2低于第一低电位VGL1；其中，第二预设时长t2为扫描信号由第一高电位VGH1最低下降为第一低电位VGL1所需的时长。
在一些实施例中，栅极驱动器还用于使GOA电路输出扫描信号时，在每行像素单元的关闭阶段，在扫描信号由第二高电位VGH2下降至第一低电位VGL1之前，还使得扫描信号由第二高电位VGH2下降至第一高电位VGH1并保持第三预设时长t3；其中，所述第三预设时长t3为每个所述像素单元打开最彻底时的充电时长。
在一些实施例中，栅极驱动器还用于使GOA电路输出扫描信号时，还包括：在每行像素单元的关闭阶段之后，还使得扫描信号由第二低电位VGL2上升至第一低电位VGL1。
基于上述实施例，本发明实施例还提供一种显示面板，包括如上所述的栅极驱动器，该显示面板与该栅极驱动器的工作原理和有益效果相同，由于上述各实施例已经对该栅极驱动器进行了详细描述，此处不再赘述。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (18)

  1. 一种GOA电路的驱动方法，其包括：
    在每行像素单元的开启阶段，使扫描信号在第一预设时长内由第一低电位依次上升至第一高电位和第二高电位，所述第二高电位高于所述第一高电位，所述第一高电位高于所述第一低电位；
    其中，所述第一预设时长为所述扫描信号由所述第一低电位最高上升为所述第一高电位所需的时长；
    所述第一高电位为所述像素单元的开启电位，所述第一低电位为所述像素单元的关断电位。
  2. 如权利要求1所述的GOA电路的驱动方法，其还包括：在每行所述像素单元的关闭阶段，使所述扫描信号在第二预设时长内由所述第二高电位下降至第二低电位，再由所述第二低电位上升至所述第一低电位，所述第二低电位低于所述第一低电位；
    其中，所述第二预设时长为所述扫描信号由所述第一高电位最低下降为所述第一低电位所需的时长。
  3. 如权利要求2所述的GOA电路的驱动方法，其还包括：在每行所述像素单元的开启阶段至关闭阶段之间，使得所述扫描信号由所述第二高电位下降至所述第一低电位之前，还使得所述扫描信号由所述第二高电位下降至所述第一高电位并保持第三预设时长；其中，所述第三预设时长为每个所述像素单元打开最彻底时的充电时长。
  4. 如权利要求2所述的GOA电路的驱动方法，其还包括：在每行所述像素单元的关闭阶段之后，还使得所述扫描信号由所述第二低电位上升至所述第一低电位。
  5. 如权利要求1所述的GOA电路的驱动方法，其中，所述第一高电位的范围为20V~35V，所述第一低电位的范围为-5V~-10V。
  6. 如权利要求1所述的GOA电路的驱动方法，其中，所述GOA电路中的薄膜晶体管均采用N型薄膜晶体管。
  7. 一种栅极驱动器，其包括GOA电路，所述GOA电路用于输出扫描信号；
    所述栅极驱动器用于使所述GOA电路输出所述扫描信号时，在每行像素单元的开启阶段，使所述扫描信号在第一预设时长内由第一低电位依次上升至第一高电位和第二高电位，所述第二高电位高于所述第一高电位，所述第一高电位高于所述第一低电位；
    其中，所述第一预设时长为所述扫描信号由所述第一低电位最高上升为所述第一高电位所需的时长；
    所述第一高电位为所述像素单元的开启电位，所述第一低电位为所述像素单元的关断电位。
  8. 如权利要求7所述的栅极驱动器，其中，所述栅极驱动器使所述GOA电路输出所述扫描信号时，在每行所述像素单元的关闭阶段，使所述扫描信号在第二预设时长内由所述第二高电位依次下降至所述第一低电位和第二低电位，所述第二低电位低于所述第一低电位；
    其中，所述第二预设时长为所述扫描信号由所述第一高电位最低下降为所述第一低电位所需的时长。
  9. 如权利要求8所述的栅极驱动器，其中，所述栅极驱动器还用于使所述GOA电路输出所述扫描信号时，在每行所述像素单元的关闭阶段，在所述扫描信号由所述第二高电位下降至所述第一低电位之前，还使得所述扫描信号由所述第二高电位下降至所述第一高电位并保持第三预设时长；其中，所述第三预设时长为每个所述像素单元打开最彻底时的充电时长。
  10. 如权利要求8所述的栅极驱动器，其中，所述栅极驱动器还用于使所述GOA电路输出所述扫描信号时，还包括：在每行所述像素单元的关闭阶段之后，还使得所述扫描信号由所述第二低电位上升至所述第一低电位。
  11. 如权利要求7所述的栅极驱动器，其中，所述第一高电位的范围为20V~35V，所述第一低电位的范围为-5V~-10V。
  12. 如权利要求7所述的栅极驱动器，其中，所述GOA电路中的薄膜晶体管均采用N型薄膜晶体管。
  13. 一种显示面板，其包括栅极驱动器，所述栅极驱动器包括GOA电路，所述GOA电路用于输出扫描信号；
    所述栅极驱动器用于使所述GOA电路输出所述扫描信号时，在每行像素单元的开启阶段，使所述扫描信号在第一预设时长内由第一低电位依次上升至第一高电位和第二高电位，所述第二高电位高于所述第一高电位，所述第一高电位高于所述第一低电位；
    其中，所述第一预设时长为所述扫描信号由所述第一低电位最高上升为所述第一高电位所需的时长；
    所述第一高电位为所述像素单元的开启电位，所述第一低电位为所述像素单元的关断电位。
  14. 如权利要求13所述的显示面板，其中，所述栅极驱动器使所述GOA电路输出所述扫描信号时，在每行所述像素单元的关闭阶段，使所述扫描信号在第二预设时长内由所述第二高电位依次下降至所述第一低电位和第二低电位，所述第二低电位低于所述第一低电位；
    其中，所述第二预设时长为所述扫描信号由所述第一高电位最低下降为所述第一低电位所需的时长。
  15. 如权利要求14所述的显示面板，其中，所述栅极驱动器还用于使所述GOA电路输出所述扫描信号时，在每行所述像素单元的关闭阶段，在所述扫描信号由所述第二高电位下降至所述第一低电位之前，还使得所述扫描信号由所述第二高电位下降至所述第一高电位并保持第三预设时长；其中，所述第三预设时长为每个所述像素单元打开最彻底时的充电时长。
  16. 如权利要求14所述的显示面板，其中，所述栅极驱动器还用于使所述GOA电路输出所述扫描信号时，还包括：在每行所述像素单元的关闭阶段之后，还使得所述扫描信号由所述第二低电位上升至所述第一低电位。
  17. 如权利要求13所述的显示面板，其中，所述第一高电位的范围为20V~35V，所述第一低电位的范围为-5V~-10V。
  18. 如权利要求13所述的显示面板，其中，所述GOA电路中的薄膜晶体管均采用N型薄膜晶体管。
PCT/CN2022/087292 2022-03-24 2022-04-18 Goa电路的驱动方法、栅极驱动器及显示面板 Ceased WO2023178772A1 (zh)

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