WO2023178753A1 - 显示面板、阵列基板及其制造方法 - Google Patents

显示面板、阵列基板及其制造方法 Download PDF

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Publication number
WO2023178753A1
WO2023178753A1 PCT/CN2022/086644 CN2022086644W WO2023178753A1 WO 2023178753 A1 WO2023178753 A1 WO 2023178753A1 CN 2022086644 W CN2022086644 W CN 2022086644W WO 2023178753 A1 WO2023178753 A1 WO 2023178753A1
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Prior art keywords
electrode
layer
substrate
common electrode
common
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PCT/CN2022/086644
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English (en)
French (fr)
Inventor
刘菁
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Tcl华星光电技术有限公司
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Publication of WO2023178753A1 publication Critical patent/WO2023178753A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel, an array substrate and a manufacturing method thereof.
  • the existing thin film transistor liquid crystal display panel is usually composed of a color filter substrate, a thin film transistor array substrate and a liquid crystal layer arranged between the two substrates. Its working principle is to control the liquid crystal molecules of the liquid crystal layer by applying a driving voltage. Rotate to refract the light from the backlight module to create a picture.
  • Thin film transistor liquid crystal display panels are widely used due to their thinness, environmental protection, high performance and other advantages. In recent years, in order to simplify the manufacturing process of thin film transistor liquid crystal display panels and reduce costs, the application of 4-reticle process technology has become more and more common.
  • the 4-mask process technology combines the photolithography of the semiconductor layer and the second metal layer, so that there is a semiconductor layer under the second metal layer, and the semiconductor layer between the first metal layer and the second metal layer This will cause a difference in positive and negative polarity between the first capacitor plate located on the first metal layer and the second capacitor plate located above the second metal layer, thereby causing a horizontal crosstalk problem.
  • This application provides a display panel, an array substrate and a manufacturing method thereof to solve the problem of horizontal crosstalk.
  • This application provides an array substrate, which includes:
  • the first electrode layer is provided on the substrate, and the first electrode layer includes a first common electrode;
  • a first insulating layer, the first insulating layer is provided on the first electrode layer;
  • a semiconductor layer, the semiconductor layer is provided on the first insulating layer
  • the second electrode layer is provided on the semiconductor layer and covers the first insulating layer;
  • the second electrode layer includes a drain electrode, a source electrode and a second common electrode; the drain electrode and the Source electrodes are respectively connected to the semiconductor layers;
  • a first passivation layer, the first passivation layer is provided on the second electrode layer;
  • a third electrode layer, the third electrode layer is provided on the first passivation layer, the third electrode layer includes a pixel electrode;
  • the orthographic projection of the first common electrode on the substrate and the orthographic projection of the pixel electrode on the substrate at least partially overlap, and the second common electrode is connected to the substrate through the opening on the first insulating layer.
  • the first common electrode is connected.
  • the third electrode layer further includes a first connection electrode connected to the first connection electrode through an opening penetrating the first insulation layer and the first passivation layer.
  • the second common electrode is connected to the first common electrode.
  • the orthographic projection of the first common electrode on the substrate and the orthographic projection of the second common electrode on the substrate at least partially overlap.
  • the second electrode layer further includes a second connection electrode, a plurality of the first common electrodes are arranged in an array, and a plurality of the second common electrodes are arranged in an array, so The second connection electrode is connected to the second common electrode located on the same row.
  • the first electrode layer further includes a third connection electrode, and the third connection electrode is connected to the first common electrode located in the same column.
  • the substrate includes a light-transmitting region and a non-light-transmitting region
  • the light-transmitting region includes a first trunk electrode region, a second trunk electrode region, and a branch electrode region
  • the third Two connection electrodes are provided on the non-light-transmitting area and the first trunk electrode area.
  • the first electrode layer further includes a third common electrode
  • the second electrode layer further includes a fourth common electrode
  • the third common electrode and the fourth common electrode The electrode is arranged in the first trunk electrode area, and the orthographic projection of the third common electrode on the substrate overlaps with the orthographic projection of the fourth common electrode on the substrate.
  • the first electrode layer further includes a fifth common electrode and a fifth connection electrode
  • the second electrode layer further includes a sixth common electrode and a sixth connection electrode
  • the The fifth common electrode and the sixth common electrode are provided in the second trunk electrode area
  • the orthographic projection of the fifth common electrode on the substrate overlaps with the orthographic projection of the sixth common electrode on the substrate.
  • the first electrode layer further includes a fifth common electrode and a fifth connection electrode
  • the second electrode layer further includes a sixth common electrode and a sixth connection electrode
  • the The fifth common electrode and the sixth common electrode are provided in the second trunk electrode area
  • the fifth common electrode is connected to the third common electrode
  • the sixth common electrode is connected to the fourth common electrode
  • the orthographic projection of the fifth common electrode on the substrate and the third common electrode are The orthographic projections of the six common electrodes on the substrate overlap.
  • this application also provides a method for manufacturing an array substrate, which includes:
  • first electrode layer on the substrate, and the first electrode layer includes a first common electrode
  • a second electrode layer is formed on the semiconductor layer, the second electrode layer covers the first insulating layer, the second electrode layer includes a drain electrode, a source electrode and a second common electrode, the drain electrode and the The source electrodes are respectively connected to the semiconductor layer;
  • a third electrode layer is formed on the first passivation layer, and the third electrode layer includes a pixel electrode and a first connection electrode;
  • the orthographic projection of the first common electrode on the substrate and the orthographic projection of the pixel electrode on the substrate at least partially overlap, and the first connection electrode passes through the first insulating layer and the The opening of the first passivation layer is connected to the second common electrode and the first common electrode.
  • the present application also provides a display panel, which includes an array substrate, a color filter substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate;
  • the array substrate includes:
  • the first electrode layer is provided on the substrate, and the first electrode layer includes a first common electrode;
  • a first insulating layer, the first insulating layer is provided on the first electrode layer;
  • a semiconductor layer, the semiconductor layer is provided on the first insulating layer
  • the second electrode layer is provided on the semiconductor layer and covers the first insulating layer;
  • the second electrode layer includes a drain electrode, a source electrode and a second common electrode; the drain electrode and The source electrodes are respectively connected to the semiconductor layers;
  • a first passivation layer, the first passivation layer is provided on the second electrode layer;
  • a third electrode layer, the third electrode layer is provided on the first passivation layer, the third electrode layer includes a pixel electrode;
  • the orthographic projection of the first common electrode on the substrate and the orthographic projection of the pixel electrode on the substrate at least partially overlap, and the second common electrode is connected to the substrate through the opening on the first insulating layer.
  • the first common electrode is connected.
  • the third electrode layer further includes a first connection electrode connected to the first connection electrode through an opening penetrating the first insulation layer and the first passivation layer.
  • the second common electrode is connected to the first common electrode.
  • the orthographic projection of the first common electrode on the substrate and the orthographic projection of the second common electrode on the substrate at least partially overlap.
  • the second electrode layer further includes a second connection electrode, a plurality of the first common electrodes are arranged in an array, and a plurality of the second common electrodes are arranged in an array, so The second connection electrode is connected to the second common electrode located on the same row.
  • the first electrode layer further includes a third connection electrode, and the third connection electrode is connected to the first common electrode located in the same column.
  • the substrate includes a light-transmitting region and a non-light-transmitting region
  • the light-transmitting region includes a first trunk electrode region, a second trunk electrode region, and a branch electrode region
  • the third Two connection electrodes are provided on the non-light-transmitting area and the first trunk electrode area.
  • the first electrode layer further includes a third common electrode
  • the second electrode layer further includes a fourth common electrode
  • the third common electrode and the fourth common electrode The electrode is arranged in the first trunk electrode area, and the orthographic projection of the third common electrode on the substrate overlaps with the orthographic projection of the fourth common electrode on the substrate.
  • the first electrode layer further includes a fifth common electrode and a fifth connection electrode
  • the second electrode layer further includes a sixth common electrode and a sixth connection electrode
  • the The fifth common electrode and the sixth common electrode are provided in the second trunk electrode area
  • the orthographic projection of the fifth common electrode on the substrate overlaps with the orthographic projection of the sixth common electrode on the substrate.
  • the present application provides a display panel, an array substrate and a manufacturing method thereof, wherein the array substrate includes: a substrate; a first electrode layer, the first electrode layer is provided on the substrate, the first electrode layer includes a first common Electrode; a first insulating layer, the first insulating layer is provided on the first electrode layer; a semiconductor layer, the semiconductor layer is provided on the first insulating layer; a second electrode layer, the second electrode A layer is provided on the semiconductor layer and covers the first insulating layer, the second electrode layer includes a drain electrode, a source electrode and a second common electrode, the drain electrode and the source electrode are respectively connected to the semiconductor layer; a first passivation layer, the first passivation layer is provided on the second electrode layer; a third electrode layer, the third electrode layer is provided on the first passivation layer, the third electrode The layer includes a pixel electrode; wherein an orthographic projection of the first common electrode on the substrate and an orthographic projection of the pixel electrode on the substrate at least partially overlap, and the second common electrode passes through the
  • the capacitance of the array substrate is formed between the first common electrode and the pixel electrode, and a second common electrode in the same layer as the drain electrode and the source electrode is provided on the second electrode layer, and the first common electrode and the second common electrode are The electrodes are connected, which can prevent positive and negative polarity differences between the first common electrode located on the first electrode layer and the pixel electrode located on the third electrode layer due to the existence of the semiconductor layer, thereby solving the problem of horizontal crosstalk.
  • Figure 1 is a first structural schematic diagram of the array substrate provided by this application.
  • Figure 2 is a cross-sectional view along line A-A in Figure 1;
  • Figure 3 is a flow chart of the manufacturing method of the array substrate provided by the present application.
  • Figure 4 is a second structural schematic diagram of the array substrate provided by this application.
  • Figure 5 is a third structural schematic diagram of the array substrate provided by this application.
  • Figure 6 is a cross-sectional view along line A-A in Figure 5;
  • Figure 7 is a top view of the first electrode layer in Figure 5;
  • Figure 8 is a top view of the second electrode layer in Figure 5;
  • Figure 9 is a fourth structural schematic diagram of the array substrate provided by the present application.
  • Figure 10 is a cross-sectional view along line A-A in Figure 9;
  • Figure 11 is a top view of the first electrode layer in Figure 9;
  • Figure 12 is a top view of the second electrode layer in Figure 9;
  • Figure 13 is a fifth structural schematic diagram of the array substrate provided by this application.
  • Figure 14 is a cross-sectional view along B-B in Figure 13;
  • Figure 15 is a top view of the first electrode layer in Figure 13;
  • Figure 16 is a top view of the second electrode layer in Figure 13;
  • Figure 17 is a sixth structural schematic diagram of the array substrate provided by the present application.
  • Figure 18 is a top view of the first electrode layer in Figure 17;
  • FIG. 19 is a top view of the second electrode layer in FIG. 17 .
  • This application provides a display panel, an array substrate and a manufacturing method thereof, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.
  • Figure 1 is a first structural schematic diagram of the array substrate 100 provided by the present application
  • Figure 2 is a cross-sectional view along line A-A in Figure 1.
  • This application provides an array substrate 100, which includes a substrate 11, a first electrode layer 12, a first insulating layer 13, a semiconductor layer 14, a second electrode layer 15, a first passivation layer 16 and a third electrode layer 17.
  • the material of the substrate 11 can be selected as needed.
  • a rigid material or a flexible material can be used.
  • the substrate 11 can be set as a rigid substrate or a flexible substrate as needed.
  • the substrate 11 can be a flexible substrate.
  • the flexible substrate includes a single One flexible organic layer or two or more flexible organic layers.
  • the material of the flexible organic layer is selected from polyimide, polyethylene naphthalate, polyethylene terephthalate, polyarylate, polycarbonate, polyetherimide and polyethersulfone. one or more.
  • the material of the first electrode layer 12 , the second electrode layer 15 and the third electrode layer 17 may be an alloy containing one or more of copper, molybdenum, molybdenum titanium, aluminum, titanium and nickel.
  • the material of the semiconductor layer 14 can be an amorphous silicon semiconductor material or a metal oxide semiconductor material.
  • the material of the semiconductor layer 14 is a metal oxide semiconductor material.
  • the metal oxide semiconductor material can be It is any one of indium gallium tin oxide semiconductor material, indium gallium zinc tin oxide semiconductor material and indium gallium zinc oxide semiconductor material.
  • the first electrode layer 12 is provided on the substrate 11, and the first electrode layer 12 includes a first common electrode 121; the first insulating layer 13 is provided on the first electrode layer 12; the semiconductor Layer 14 is provided on the first insulating layer 13; the second electrode layer 15 is provided on the semiconductor layer 14 and covers the first insulating layer 13.
  • the second electrode layer 15 includes a drain electrode 152 and a source electrode. 151 and the second common electrode 153, the drain electrode 152 and the source electrode 151 are respectively connected to the semiconductor layer 14; the first passivation layer 16 is provided on the second electrode layer 15; A three-electrode layer 17 is provided on the first passivation layer 16 , and the third electrode layer 17 includes a pixel electrode 171 .
  • the orthographic projection of the first common electrode 121 on the substrate 11 and the orthographic projection of the pixel electrode 171 on the substrate 11 at least partially overlap, and the second common electrode 153 passes through the first insulation
  • the opening 101 on the layer 13 is connected to the first common electrode 121 .
  • the present application can combine the first common electrode 121 and the pixel electrode 171 The storage capacitance of the array substrate 100 is formed between them.
  • the semiconductor layer 14 may cause a positive and negative polarity difference between the first common electrode 121 and the pixel electrode 171 .
  • the present application also provides a second common electrode 153 in the same layer as the drain electrode 152 and the source electrode 151 on the second electrode layer 15, and the first common electrode 121 is connected to the second common electrode 153, so it can prevent
  • the presence of the semiconductor layer 14 causes a positive and negative polarity difference between the first common electrode 121 located on the first electrode layer 12 and the pixel electrode 171 located on the third electrode layer 17 , thereby solving the problem of horizontal crosstalk.
  • the first electrode layer 12 further includes a gate electrode 122 , the orthographic projection of the gate electrode 122 on the substrate 11 and the orthogonal projection of the semiconductor layer 14 on the substrate 11 The projections overlap.
  • the gate electrode 122 and the first common electrode 121 are provided on the same electrode layer, which can reduce the number of electrode layers.
  • the pixel electrode 171 is connected to one of the source electrode 151 and the drain electrode 152 . Specifically, the pixel electrode 171 is connected to the drain electrode 152 through the opening 102 on the first passivation layer 16 .
  • the third electrode layer 17 further includes a first connection electrode 172 , and the first connection electrode 172 passes through the opening 101 on the first insulation layer 13 and the first passivation layer 16 in sequence. Connected to the second common electrode 153 and the first common electrode 121 .
  • openings are provided on the first insulating layer 13 and the first passivation layer 16, and then the first connection electrode 172 is used to connect to the second common electrode 153 and the first common electrode 121 in sequence. connection, thereby achieving connection between the first common electrode 121 and the second common electrode 153 .
  • the first connection electrode 172 and the pixel electrode 171 are both located on the third electrode layer 17, so the arrangement of electrode layers can be reduced and the processing time can be reduced.
  • the orthographic projection of the first common electrode 121 on the substrate 11 and the orthographic projection of the second common electrode 153 on the substrate 11 at least partially overlap.
  • the aperture ratio of the substrate 11 can be increased.
  • the orthographic projection of the first common electrode 121 on the substrate 11 covers the orthographic projection of the second common electrode 153 on the substrate 11 .
  • the array substrate 100 further includes a color filter layer 18 and a second passivation layer 19.
  • the color filter layer 18 is provided on the first passivation layer 16.
  • the second passivation layer 19 Layer 19 is provided on the color filter layer 18
  • the third electrode layer 17 is provided on the second passivation layer 19 .
  • the first connection electrode 172 is connected to the first insulating layer 13 , the first passivation layer 16 , the color filter layer 18 and the opening 101 in the second passivation layer 19 in sequence.
  • Two common electrodes 153 are connected to the first common electrode 121
  • the pixel electrode 171 is connected to the first passivation layer 16 , the color filter layer 18 and the second passivation layer 19 through the openings 102 .
  • the drain electrode 152 is connected.
  • Figure 3 is a flow chart of a manufacturing method of the array substrate 100 provided by the present application.
  • the present application also provides a manufacturing method of the array substrate 100, which includes:
  • the first electrode layer 12 includes a first common electrode 121;
  • the second electrode layer 15 covers the first insulating layer 13.
  • the second electrode layer 15 includes a drain electrode 152, a source electrode 151 and a second electrode layer 15.
  • the common electrode 153, the drain electrode 152 and the source electrode 151 are respectively connected to the semiconductor layer 14;
  • the third electrode layer 17 includes a pixel electrode 171 and a first connection electrode 172;
  • the orthographic projection of the first common electrode 121 on the substrate 11 and the orthographic projection of the pixel electrode 171 on the substrate 11 at least partially overlap, and the first connection electrode 172 passes through the first
  • the openings 101 of the insulating layer 13 and the first passivation layer 16 are connected to the second common electrode 153 and the first common electrode 121 .
  • the present application also provides a display panel, which includes the above-mentioned array substrate 100, a color filter substrate disposed opposite to the array substrate 100, and a display panel located between the array substrate 100 and the color filter substrate. liquid crystal layer between.
  • the beneficial effects of the display panel provided by the embodiments of the present application are the same as the beneficial effects of the array substrate 100 provided by the above technical solution, and will not be described again here.
  • FIG. 4 is a second structural schematic diagram of the array substrate 100 provided by the present application.
  • the difference between this embodiment and the array substrate 100 provided in FIG. 1 is that the first common electrode 121 is disposed on the substrate 11
  • the orthographic projection, the orthographic projection of the pixel electrode 171 on the substrate 11 and the orthographic projection of the second common electrode 153 on the substrate 11 at least partially overlap.
  • the orthographic projection of the first common electrode 121 on the substrate 11 the orthographic projection of the pixel electrode 171 on the substrate 11 and the orthographic projection of the second common electrode 153 on the substrate 11
  • the projection has an overlapping portion, which can minimize the space occupied by the first common electrode 121 and the second common electrode 153 and improve the aperture ratio of the substrate 11 .
  • Figure 5 is a third structural schematic diagram of the array substrate 100 provided by the present application.
  • Figure 6 is a cross-sectional view of A-A in Figure 5.
  • Figure 7 is a top view of the first electrode layer in Figure 5.
  • Figure 8 is In the top view of the second electrode layer in Figure 5, the difference between this embodiment and the array substrate 100 provided in Figure 1 is that the second electrode layer 15 also includes a second connection electrode 154, and a plurality of the first common electrodes 121 are in the form of Array arrangement, a plurality of second common electrodes 153 are arranged in an array, and the second connection electrodes 154 are connected to the second common electrodes 153 located on the same row.
  • the second common electrodes 153 located on the same row are connected through the second connection electrode 154, so that the first common electrodes 121 located on the same row are connected, thereby improving the potential recovery speed of the first common electrode 121. , further improving the problem of horizontal crosstalk.
  • the substrate 11 includes a light-transmitting region 103 and a non-light-transmitting region 104.
  • the light-transmitting region 103 includes a first trunk electrode region 106, a second trunk electrode region 105 and a branch electrode region. 107.
  • the pixel electrode 171 is located in the light-transmitting area 103, and the second connection electrode 154 is provided on the non-light-transmitting area 104 and the first trunk electrode area 106.
  • the second connection electrode 154 is disposed in the first trunk electrode region 106, which can prevent the second connection electrode 154 from occupying the design space of the substrate 11, thereby improving the aperture ratio of the substrate 11.
  • the first electrode layer 12 further includes a third connection electrode 123, and the third connection electrode 123 is connected to the first common electrode 121 located in the same column.
  • the first common electrodes 121 located in the same row are connected through the third connecting electrode 123, so that The first common electrodes 121 located in the rows and columns are connected to form a grid electrode, thereby further increasing the potential recovery speed of the first common electrode 121 and improving the problem of horizontal crosstalk.
  • Figure 9 is a fourth structural schematic diagram of the array substrate 100 provided by the present application.
  • Figure 10 is a cross-sectional view of A-A in Figure 9.
  • Figure 11 is a top view of the first electrode layer in Figure 9.
  • Figure 12 is The top view of the second electrode layer in Figure 9 shows that the difference between this embodiment and the array substrate 100 provided in Figure 5 is that the first electrode layer 12 also includes a third common electrode 124, and the second electrode layer 15 also includes a third common electrode 124.
  • Four common electrodes 155, the third common electrode 124 and the fourth common electrode 155 are provided in the first trunk electrode area 106, the orthographic projection of the third common electrode 124 on the substrate 11 and the The orthographic projections of the fourth common electrode 155 on the substrate 11 overlap.
  • the third common electrode 124 is disposed in the first trunk electrode region 106 through the first electrode layer 12, and the fourth common electrode 155 is disposed in the first trunk electrode region 106 through the second electrode layer 15, so that The orthographic projections of the third common electrode 124 and the fourth common electrode 155 on the substrate 11 overlap, so a storage capacitor can be formed between the third common electrode 124 and the fourth common electrode 155 , thereby increasing the capacity of the storage capacitor, thereby improving the variable refresh rate effect of the display panel.
  • the first electrode layer 12 further includes a fourth connection electrode 125, the number of the third common electrode 124 and the fourth common electrode 155 is multiple, and the fourth connection electrode 125
  • the electrode 125 connects a plurality of third common electrodes
  • the second connection electrode 154 connects a plurality of fourth common electrodes 155 .
  • the plurality of third common electrodes 124 are arranged in an array
  • the plurality of fourth common electrodes 155 are arranged in an array.
  • Figure 13 is a fifth structural schematic diagram of the array substrate 100 provided by the present application.
  • Figure 14 is a B-B cross-sectional view in Figure 13.
  • Figure 15 is a top view of the first electrode layer in Figure 13.
  • Figure 16 The top view of the second electrode layer in Figure 13.
  • the difference between this embodiment and the array substrate 100 provided in Figure 5 is that the first electrode layer 12 also includes a fifth common electrode 126 and a fifth connection electrode 127.
  • the electrode layer 15 also includes a sixth common electrode 156 and a sixth connection electrode 157.
  • the fifth common electrode 126 and the sixth common electrode 156 are provided in the second trunk electrode area 105.
  • the fifth common electrode The orthographic projection of 126 on the substrate 11 and the orthographic projection of the sixth common electrode 156 on the substrate 11 overlap.
  • the fifth common electrode 126 is disposed in the second trunk electrode region 105 through the first electrode layer 12, and the sixth common electrode 156 is disposed in the second trunk electrode region 105 through the second electrode layer 15, so that The orthographic projections of the fifth common electrode 126 and the sixth common electrode 156 on the substrate 11 overlap, so a storage capacitor can be formed between the fifth common electrode 126 and the fifth common electrode 126 , thereby increasing the capacity of the storage capacitor and improving the variable refresh rate effect of the display panel.
  • Figure 17 is a sixth structural schematic diagram of the array substrate 100 provided by the present application.
  • Figure 18 is a top view of the first electrode layer in Figure 17.
  • Figure 19 is a top view of the second electrode layer in Figure 17.
  • the first electrode layer 12 also includes a fifth common electrode 126 and a fifth connection electrode 127
  • the second electrode layer 15 also includes a sixth common electrode 156 and a sixth connection electrode 157.
  • the fifth common electrode 126 and the sixth common electrode 156 are provided in the second trunk electrode area 105.
  • the fifth common electrode 126 is connected to the third common electrode.
  • the sixth common electrode 156 is connected to the fourth common electrode, the orthographic projection of the fifth common electrode 126 on the substrate 11 and the orthogonal projection of the sixth common electrode 156 on the substrate 11 The projections overlap.
  • the fifth common electrode 126 is provided in the second trunk electrode area 105 through the first electrode layer 12, and the sixth common electrode 156 is provided in the second trunk electrode area 105 through the second electrode layer 15, and the The fifth common electrode 126 is connected to the third common electrode 124, the sixth common electrode 156 is connected to the fourth common electrode 155, and the fifth common electrode 126 and the sixth common electrode 155 are connected to each other.
  • the orthographic projections of the electrodes 156 on the substrate 11 overlap, thereby further increasing the capacity of the storage capacitor and improving the variable refresh rate effect of the display panel.
  • the first electrode layer 12 further includes a fifth connection electrode 127
  • the second electrode layer 15 further includes a sixth connection electrode 157
  • the fifth common electrode 126 and the third connection electrode 157 There are multiple six common electrodes 156
  • the fifth connection electrodes 127 connect a plurality of the fifth common electrodes 126
  • the sixth connection electrodes 157 connect a plurality of the sixth common electrodes 156 .
  • the plurality of fifth common electrodes 126 are arranged in an array
  • the plurality of sixth common electrodes 156 are arranged in an array.

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Abstract

本申请公开一种显示面板、阵列基板及其制造方法。本申请的显示面板通过在第一公共电极和像素电极之间形成阵列基板的电容，并在第二电极层设有与漏电极及源电极同层的第二公共电极，而且第一公共电极与第二公共电极相连接，可以防止第一公共电极与像素电极之间产生正负极性差异，从而解决水平串扰的问题。

Description

显示面板、阵列基板及其制造方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板、阵列基板及其制造方法。
 背景技术
现有的薄膜晶体管液晶显示面板通常是由一彩膜基板、一薄膜晶体管阵列基板以及一配置于两基板间的液晶层所构成，其工作原理是通过施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。薄膜晶体管液晶显示面板由于具有轻薄、环保、高性能等优点而使其具有广泛的应用，近年来为了简化薄膜晶体管液晶显示面板的制程并降低成本，4光罩工艺技术的应用越来越普遍。然而4光罩工艺技术是通过由于将半导体层和第二金属层的光刻合并，使得第二金属层下方均有一层半导体层，而处于第一金属层与第二金属层之间的半导体层会导致位于第一金属层上的第一电容极板与位于第二金属层上方的第二电容极板在正负极性上存在差异，从而引起水平串扰问题。
 技术问题
本申请提供一种显示面板、阵列基板及其制造方法，以解决水平串扰的问题。
 技术解决方案
本申请提供一种阵列基板，其包括：
基板；
第一电极层，所述第一电极层设在所述基板上，所述第一电极层包括第一公共电极；
第一绝缘层，所述第一绝缘层设在所述第一电极层上；
半导体层，所述半导体层设在所述第一绝缘层上；
第二电极层，所述第二电极层设在半导体层上并覆盖所述第一绝缘层，所述第二电极层包括漏电极、源电极和第二公共电极，所述漏电极和所述源电极分别与所述半导体层连接；
第一钝化层，所述第一钝化层设在所述第二电极层上；
第三电极层，所述第三电极层设在所述第一钝化层上，所述第三电极层包括像素电极；
其中，所述第一公共电极在所述基板上的正投影和所述像素电极在所述基板上的正投影至少部分重叠，所述第二公共电极通过所述第一绝缘层上的开口与所述第一公共电极相连接。
可选的，在本申请一些实施例中，所述第三电极层还包括第一连接电极，所述第一连接电极通过贯穿所述第一绝缘层和所述第一钝化层的开口与所述第二公共电极和所述第一公共电极相连接。
可选的，在本申请一些实施例中，所述第一公共电极在所述基板上的正投影和所述第二公共电极在所述基板上的正投影至少部分重叠。
可选的，在本申请一些实施例中，所述第一公共电极在所述基板上的正投影、所述像素电极在所述基板上的正投影和所述第二公共电极在所述基板上的正投影至少部分重叠。
可选的，在本申请一些实施例中，所述第二电极层还包括第二连接电极，多个所述第一公共电极呈阵列设置，多个所述第二公共电极呈阵列设置，所述第二连接电极与位于同一行上的所述第二公共电极相连接。
可选的，在本申请一些实施例中，所述第一电极层还包括第三连接电极，所述第三连接电极与位于同一列上的所述第一公共电极相连接。
可选的，在本申请一些实施例中，所述基板包括透光区域和非透光区域，所述透光区域包括第一主干电极区域、第二主干电极区域以及分支电极区域，所述第二连接电极设置在所述非透光区域和所述第一主干电极区域上。
可选的，在本申请一些实施例中，所述第一电极层还包括第三公共电极，所述第二电极层还包括第四公共电极，所述第三公共电极和所述第四公共电极设在所述第一主干电极区域内，所述第三公共电极在所述基板上的正投影和所述第四公共电极在所述基板上的正投影相重叠。
可选的，在本申请一些实施例中，所述第一电极层还包括第五公共电极和第五连接电极，所述第二电极层还包括第六公共电极和第六连接电极，所述第五公共电极和所述第六公共电极设在所述第二主干电极区域内；
所述第五公共电极在所述基板上的正投影和所述第六公共电极在所述基板上的正投影相重叠。
可选的，在本申请一些实施例中，所述第一电极层还包括第五公共电极和第五连接电极，所述第二电极层还包括第六公共电极和第六连接电极，所述第五公共电极和所述第六公共电极设在所述第二主干电极区域内；
所述第五公共电极与所述第三公共电极相连接，所述第六公共电极与所述第四公共电极相连接，所述第五公共电极在所述基板上的正投影和所述第六公共电极在所述基板上的正投影相重叠。
相对应地，本申请还提供一种阵列基板的制造方法，其包括：
提供一基板，在所述基板上形成第一电极层，所述第一电极层包括第一公共电极；
在所述第一电极层上形成第一绝缘层；
在所述第一绝缘层上形成半导体层；
在所述半导体层上形成第二电极层，所述第二电极层覆盖所述第一绝缘层，所述第二电极层包括漏电极、源电极和第二公共电极，所述漏电极和所述源电极分别与所述半导体层连接；
在所述第二电极层上形成第一钝化层；
在所述第一钝化层形成第三电极层，所述第三电极层包括像素电极和第一连接电极；
其中，所述第一公共电极在所述基板上的正投影和所述像素电极在所述基板上的正投影至少部分重叠，所述第一连接电极通过贯穿所述第一绝缘层和所述第一钝化层的开口与所述第二公共电极和所述第一公共电极相连接。
相对应地，本申请还提供一种显示面板，其包括阵列基板，还包括与所述阵列基板相对设置的彩膜基板，以及位于所述阵列基板和所述彩膜基板之间的液晶层；
其中，所述阵列基板包括：
基板；
第一电极层，所述第一电极层设在所述基板上，所述第一电极层包括第一公共电极；
第一绝缘层，所述第一绝缘层设在所述第一电极层上；
半导体层，所述半导体层设在所述第一绝缘层上；
第二电极层，所述第二电极层设在所述半导体层上并覆盖所述第一绝缘层，所述第二电极层包括漏电极、源电极和第二公共电极，所述漏电极和所述源电极分别与所述半导体层连接；
第一钝化层，所述第一钝化层设在所述第二电极层上；
第三电极层，所述第三电极层设在所述第一钝化层上，所述第三电极层包括像素电极；
其中，所述第一公共电极在所述基板上的正投影和所述像素电极在所述基板上的正投影至少部分重叠，所述第二公共电极通过所述第一绝缘层上的开口与所述第一公共电极相连接。
可选的，在本申请一些实施例中，所述第三电极层还包括第一连接电极，所述第一连接电极通过贯穿所述第一绝缘层和所述第一钝化层的开口与所述第二公共电极和所述第一公共电极相连接。
可选的，在本申请一些实施例中，所述第一公共电极在所述基板上的正投影和所述第二公共电极在所述基板上的正投影至少部分重叠。
可选的，在本申请一些实施例中，所述第一公共电极在所述基板上的正投影、所述像素电极在所述基板上的正投影和所述第二公共电极在所述基板上的正投影至少部分重叠。
可选的，在本申请一些实施例中，所述第二电极层还包括第二连接电极，多个所述第一公共电极呈阵列设置，多个所述第二公共电极呈阵列设置，所述第二连接电极与位于同一行上的所述第二公共电极相连接。
可选的，在本申请一些实施例中，所述第一电极层还包括第三连接电极，所述第三连接电极与位于同一列上的所述第一公共电极相连接。
可选的，在本申请一些实施例中，所述基板包括透光区域和非透光区域，所述透光区域包括第一主干电极区域、第二主干电极区域以及分支电极区域，所述第二连接电极设置在所述非透光区域和所述第一主干电极区域上。
可选的，在本申请一些实施例中，所述第一电极层还包括第三公共电极，所述第二电极层还包括第四公共电极，所述第三公共电极和所述第四公共电极设在所述第一主干电极区域内，所述第三公共电极在所述基板上的正投影和所述第四公共电极在所述基板上的正投影相重叠。
可选的，在本申请一些实施例中，所述第一电极层还包括第五公共电极和第五连接电极，所述第二电极层还包括第六公共电极和第六连接电极，所述第五公共电极和所述第六公共电极设在所述第二主干电极区域内；
所述第五公共电极在所述基板上的正投影和所述第六公共电极在所述基板上的正投影相重叠。
 有益效果
本申请提供一种显示面板、阵列基板及其制造方法，其中阵列基板包括：基板；第一电极层，所述第一电极层设在所述基板上，所述第一电极层包括第一公共电极；第一绝缘层，所述第一绝缘层设在所述第一电极层上；半导体层，所述半导体层设在所述第一绝缘层上；第二电极层，所述第二电极层设在半导体层上并覆盖所述第一绝缘层，所述第二电极层包括漏电极、源电极和第二公共电极，所述漏电极和所述源电极分别与所述半导体层连接；第一钝化层，所述第一钝化层设在所述第二电极层上；第三电极层，所述第三电极层设在所述第一钝化层上，所述第三电极层包括像素电极；其中，所述第一公共电极在所述基板上的正投影和所述像素电极在所述基板上的正投影至少部分重叠，所述第二公共电极通过所述第一绝缘层上的开口与所述第一公共电极相连接。本申请通过在第一公共电极和像素电极之间形成阵列基板的电容，并在第二电极层设有与漏电极及源电极同层的第二公共电极，而且第一公共电极与第二公共电极相连接，可以防止由于半导体层的存在而导致位于第一电极层上的第一公共电极与位于第三电极层上的像素电极之间产生正负极性差异，从而解决水平串扰的问题。
 附图说明
图1为本申请提供的阵列基板的第一结构示意图；
图2为图1中的A-A剖视图；
图3为本申请提供的阵列基板的制造方法的流程图；
图4为本申请提供的阵列基板的第二结构示意图；
图5为本申请提供的阵列基板的第三结构示意图；
图6为图5中的A-A剖视图；
图7为图5中第一电极层的俯视图；
图8为图5中第二电极层的俯视图；
图9为本申请提供的阵列基板的第四结构示意图；
图10为图9中的A-A剖视图；
图11为图9中第一电极层的俯视图；
图12为图9中第二电极层的俯视图；
图13为本申请提供的阵列基板的第五结构示意图；
图14为图13中的B-B剖视图；
图15为图13中第一电极层的俯视图；
图16为图13中第二电极层的俯视图；
图17为本申请提供的阵列基板的第六结构示意图；
图18为图17中第一电极层的俯视图；
图19为图17中第二电极层的俯视图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所得到的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请提供一种显示面板、阵列基板及其制造方法，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1和图2，图1为本申请提供的阵列基板100的第一结构示意图，图2为图1中的A-A剖视图。本申请提供一种阵列基板100，其包括基板11、第一电极层12、第一绝缘层13、半导体层14、第二电极层15、第一钝化层16和第三电极层17。
其中，基板11的材料可以根据需要进行选择，如可以采用刚性材料，也可以采用柔性材料，基板11根据需要可以设置为刚性基板或柔性基板，如基板11为柔性基板，所述柔性基板包括单层柔性有机层或者两层以及以上的柔性有机层。柔性有机层的材料选自聚酰亚胺、聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯、聚芳酯、聚碳酸酯、聚醚酰亚胺和聚醚砜中的一种或多种。
而所述第一电极层12、所述第二电极层15和所述第三电极层17的材料可以为含有铜、钼、钼钛、铝、钛和镍中一种或多种的合金。所述半导体层14的材料可以为非晶硅半导体材料，也可以为金属氧化物半导体材料，在本实施例中，所述半导体层14的材料为金属氧化物半导体材料，金属氧化物半导体材料可以为铟镓锡氧化物半导体材料、铟镓锌锡氧化物半导体材料和铟镓锌氧化物半导体材料中的任一种。
所述第一电极层12设在所述基板11上，所述第一电极层12包括第一公共电极121；所述第一绝缘层13设在所述第一电极层12上；所述半导体层14设在所述第一绝缘层13上；所述第二电极层15设在半导体层14上并覆盖所述第一绝缘层13，所述第二电极层15包括漏电极152、源电极151和第二公共电极153，所述漏电极152和所述源电极151分别与所述半导体层14连接；所述第一钝化层16设在所述第二电极层15上；所述第三电极层17设在所述第一钝化层16上，所述第三电极层17包括像素电极171。
其中，所述第一公共电极121在所述基板11上的正投影和所述像素电极171在所述基板11上的正投影至少部分重叠，所述第二公共电极153通过所述第一绝缘层13上的开口101与所述第一公共电极121相连接。
由于所述第一公共电极121在所述基板11上的正投影和所述像素电极171在所述基板11上的正投影至少部分重叠，因此本申请可以在第一公共电极121和像素电极171之间形成阵列基板100的存储电容。另外由于第一公共电极121位于半导体层14的下方，像素电极171位于半导体层14的上方，因此半导体层14可能使得第一公共电极121和像素电极171之间产生正负极性差异。所以，本申请还在第二电极层15上设有与漏电极152及源电极151同层的第二公共电极153，而且第一公共电极121与第二公共电极153相连接，因此可以防止由于半导体层14的存在而导致位于第一电极层12上的第一公共电极121与位于第三电极层17上的像素电极171之间产生正负极性差异，从而解决水平串扰的问题。
进一步地，在一些实施例中，所述第一电极层12还包括栅电极122，所述栅电极122在所述基板11上的正投影和所述半导体层14在所述基板11上的正投影相重叠。本申请将栅电极122和第一公共电极121设在同一电极层上，可以减少电极层的设置。
另外，所述像素电极171与所述源电极151和漏电极152中的一者连接，具体地，所述像素电极171通过第一钝化层16上的开口102与所述漏电极152连接。
在一些实施例中，所述第三电极层17还包括第一连接电极172，所述第一连接电极172通过所述第一绝缘层13和所述第一钝化层16上的开口101依次与所述第二公共电极153和所述第一公共电极121相连接。
本申请通过在所述第一绝缘层13和所述第一钝化层16上设有开口，然后利用第一连接电极172依次与所述第二公共电极153和所述第一公共电极121相连接，从而实现第一公共电极121和第二公共电极153之间的连接。其中，第一连接电极172和像素电极171都位于第三电极层17，因此可以减少电极层的设置，同时可以降低加工时间。
进一步地，在一些实施例中，所述第一公共电极121在所述基板11上的正投影和所述第二公共电极153在所述基板11上的正投影至少部分重叠。通过将第一公共电极121和第二公共电极153至少部分重叠设置，使得占用空间尽量小，可以提高基板11的开口率。再进一步地，所述第一公共电极121在所述基板11上的正投影覆盖所述第二公共电极153在所述基板11上的正投影。
另外，进一步地，所述阵列基板100还包括彩色滤光层18和第二钝化层19，所述彩色滤光层18设在所述第一钝化层16上，所述第二钝化层19设在所述彩色滤光层18上，所述第三电极层17设在所述第二钝化层19上。所述第一连接电极172通过所述第一绝缘层13、所述第一钝化层16、所述彩色滤光层18和所述第二钝化层19上的开口101依次与所述第二公共电极153和所述第一公共电极121相连接，所述像素电极171通过第一钝化层16、所述彩色滤光层18和所述第二钝化层19上的开口102与所述漏电极152连接。
请参考图3，图3为本申请提供的阵列基板100的制造方法的流程图，相对应地，本申请还提供一种阵列基板100的制造方法，其包括：
S10、提供一基板11，在所述基板11上形成第一电极层12，所述第一电极层12包括第一公共电极121；
S20、在所述第一电极层12上形成第一绝缘层13；
S30、在所述第一绝缘层13上形成半导体层14；
S40、在所述半导体层14上形成第二电极层15，所述第二电极层15覆盖所述第一绝缘层13，所述第二电极层15包括漏电极152、源电极151和第二公共电极153，所述漏电极152和所述源电极151分别与所述半导体层14连接；
S50、在所述第二电极层15上形成第一钝化层16；
S60、在所述第一钝化层16形成第三电极层17，所述第三电极层17包括像素电极171和第一连接电极172；
其中，所述第一公共电极121在所述基板11上的正投影和所述像素电极171在所述基板11上的正投影至少部分重叠，所述第一连接电极172通过贯穿所述第一绝缘层13和所述第一钝化层16的开口101与所述第二公共电极153和所述第一公共电极121相连接。
相对应地，本申请还提供一种显示面板，其包括上述的阵列基板100，还包括与所述阵列基板100相对设置的彩膜基板，以及位于所述阵列基板100和所述彩膜基板之间的液晶层。
与现有技术相比，本申请实施例提供的显示面板的有益效果与上述技术方案提供的阵列基板100的有益效果相同，在此不做赘述。
请参考图4，图4为本申请提供的阵列基板100的第二结构示意图，本实施例与图1提供的阵列基板100不同的是：所述第一公共电极121在所述基板11上的正投影、所述像素电极171在所述基板11上的正投影和所述第二公共电极153在所述基板11上的正投影至少部分重叠。
也即是所述第一公共电极121在所述基板11上的正投影、所述像素电极171在所述基板11上的正投影和所述第二公共电极153在所述基板11上的正投影具有重叠的部分，可以最大限度降低第一公共电极121和第二公共电极153的占用空间，提高基板11的开口率。
请参考图5至图8，图5为本申请提供的阵列基板100的第三结构示意图，图6为图5中的A-A剖视图，图7为图5中第一电极层的俯视图，图8为图5中第二电极层的俯视图，本实施例与图1提供的阵列基板100不同的是：所述第二电极层15还包括第二连接电极154，多个所述第一公共电极121呈阵列设置，多个所述第二公共电极153呈阵列设置，所述第二连接电极154与位于同一行上的所述第二公共电极153相连接。
本申请通过第二连接电极154将位于同一行上的所述第二公共电极153相连接，从而使得位于同一行上的第一公共电极121相连接，从而提高第一公共电极121的电位恢复速度，进一步改善水平串扰的问题。
再进一步地，在一些实施例中，所述基板11包括透光区域103和非透光区域104，所述透光区域103包括第一主干电极区域106、第二主干电极区域105以及分支电极区域107，所述像素电极171位于所述透光区域103内，所述第二连接电极154设置在所述非透光区域104和所述第一主干电极区域106上。
本申请将第二连接电极154设在第一主干电极区域106内，可以避免第二连接电极154占用基板11的设计空间，从而提高基板11的开口率。
在一些实施例中，所述第一电极层12还包括第三连接电极123，所述第三连接电极123与位于同一列上的所述第一公共电极121相连接。
也即是说，本申请在将位于同一行上的第一公共电极121相连接的基础上，再通过第三连接电极123将位于同一列上的所述第一公共电极121相连接，从而使得位于行列上的第一公共电极121相连接形成网格电极，从而进一步提高第一公共电极121的电位恢复速度，而改善水平串扰的问题。
请参考图9至图12，图9为本申请提供的阵列基板100的第四结构示意图，图10为图9中的A-A剖视图，图11为图9中第一电极层的俯视图，图12为图9中第二电极层的俯视图，本实施例与图5提供的阵列基板100不同的是：所述第一电极层12还包括第三公共电极124，所述第二电极层15还包括第四公共电极155，所述第三公共电极124和所述第四公共电极155设在所述第一主干电极区域106内，所述第三公共电极124在所述基板11上的正投影和所述第四公共电极155在所述基板11上的正投影相重叠。
由于半导体层14的存在会影响存储电容的数值，进而导致显示面板的可变刷新率效果差。因此，本申请通过第一电极层12在第一主干电极区域106内设有第三公共电极124，通过第二电极层15在第一主干电极区域106内设有第四公共电极155，并使得所述第三公共电极124和所述第四公共电极155在所述基板11上的正投影相重叠，因此可以在所述第三公共电极124和所述第四公共电极155之间形成存储电容，从而增加存储电容的容量，进而改善显示面板的可变刷新率效果。
进一步地，在一些实施例中，所述第一电极层12还包括第四连接电极125，所述第三公共电极124和所述第四公共电极155的数量为多个，所述第四连接电极125将多个所述第三公共电极相连接，所述第二连接电极154将多个所述第四公共电极155相连接。多个所述第三公共电极124呈阵列布置，多个所述第四公共电极155呈阵列布置。
请参考图13至图16，图13为本申请提供的阵列基板100的第五结构示意图，图14为图13中的B-B剖视图，图15为图13中第一电极层的俯视图，图16为图13中第二电极层的俯视图，本实施例与图5提供的阵列基板100不同的是：所述第一电极层12还包括第五公共电极126和第五连接电极127，所述第二电极层15还包括第六公共电极156和第六连接电极157，所述第五公共电极126和所述第六公共电极156设在所述第二主干电极区域105内，所述第五公共电极126在所述基板11上的正投影和所述第六公共电极156在所述基板11上的正投影相重叠。
由于半导体层14的存在会影响存储电容的数值，进而导致显示面板的可变刷新率效果差。因此，本申请通过第一电极层12在第二主干电极区域105内设有第五公共电极126，通过第二电极层15在第二主干电极区域105内设有第六公共电极156，并使得所述第五公共电极126和所述第六公共电极156在所述基板11上的正投影相重叠，因此可以在所述第五公共电极126和所述第五公共电极126之间形成存储电容，从而增加存储电容的容量，改善显示面板的可变刷新率效果。
请参考图17至图19，图17为本申请提供的阵列基板100的第六结构示意图，图18为图17中第一电极层的俯视图，图19为图17中第二电极层的俯视图，本实施例与图9提供的阵列基板100不同的是：所述第一电极层12还包括第五公共电极126和第五连接电极127，所述第二电极层15还包括第六公共电极156和第六连接电极157，所述第五公共电极126和所述第六公共电极156设在所述第二主干电极区域105内，所述第五公共电极126与所述第三公共电极相连接，所述第六公共电极156与所述第四公共电极相连接，所述第五公共电极126在所述基板11上的正投影和所述第六公共电极156在所述基板11上的正投影相重叠。
由于半导体层14的存在会影响存储电容的数值，进而导致显示面板的可变刷新率效果差。因此，本申请通过第一电极层12在第二主干电极区域105内设有第五公共电极126，通过第二电极层15在第二主干电极区域105内设有第六公共电极156，而且所述第五公共电极126与所述第三公共电极124相连接，所述第六公共电极156与所述第四公共电极155相连接，并使得所述第五公共电极126和所述第六公共电极156在所述基板11上的正投影相重叠，从而进一步增加存储电容的容量，改善显示面板的可变刷新率效果。
进一步地，在一些实施例中，所述第一电极层12还包括第五连接电极127，所述第二电极层15还包括第六连接电极157，所述第五公共电极126和所述第六公共电极156的数量为多个，所述第五连接电极127将多个所述第五公共电极126相连接，所述第六连接电极157将多个所述第六公共电极156相连接。多个所述第五公共电极126呈阵列布置，多个所述第六公共电极156呈阵列布置。
以上对本申请实施例所提供的一种阵列基板、阵列基板的制造方法及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其中，包括：
    基板；
    第一电极层，所述第一电极层设在所述基板上，所述第一电极层包括第一公共电极；
    第一绝缘层，所述第一绝缘层设在所述第一电极层上；
    半导体层，所述半导体层设在所述第一绝缘层上；
    第二电极层，所述第二电极层设在所述半导体层上并覆盖所述第一绝缘层，所述第二电极层包括漏电极、源电极和第二公共电极，所述漏电极和所述源电极分别与所述半导体层连接；
    第一钝化层，所述第一钝化层设在所述第二电极层上；
    第三电极层，所述第三电极层设在所述第一钝化层上，所述第三电极层包括像素电极；
    其中，所述第一公共电极在所述基板上的正投影和所述像素电极在所述基板上的正投影至少部分重叠，所述第二公共电极通过所述第一绝缘层上的开口与所述第一公共电极相连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第三电极层还包括第一连接电极，所述第一连接电极通过贯穿所述第一绝缘层和所述第一钝化层的开口与所述第二公共电极和所述第一公共电极相连接。
  3. 根据权利要求1所述的阵列基板，其中，所述第一公共电极在所述基板上的正投影和所述第二公共电极在所述基板上的正投影至少部分重叠。
  4. 根据权利要求1所述的阵列基板，其中，所述第一公共电极在所述基板上的正投影、所述像素电极在所述基板上的正投影和所述第二公共电极在所述基板上的正投影至少部分重叠。
  5. 根据权利要求1所述的阵列基板，其中，所述第二电极层还包括第二连接电极，多个所述第一公共电极呈阵列设置，多个所述第二公共电极呈阵列设置，所述第二连接电极与位于同一行上的所述第二公共电极相连接。
  6. 根据权利要求5所述的阵列基板，其中，所述第一电极层还包括第三连接电极，所述第三连接电极与位于同一列上的所述第一公共电极相连接。
  7. 根据权利要求5所述的阵列基板，其中，所述基板包括透光区域和非透光区域，所述透光区域包括第一主干电极区域、第二主干电极区域以及分支电极区域，所述第二连接电极设置在所述非透光区域和所述第一主干电极区域上。
  8. 根据权利要求7所述的阵列基板，其中，所述第一电极层还包括第三公共电极，所述第二电极层还包括第四公共电极，所述第三公共电极和所述第四公共电极设在所述第一主干电极区域内，所述第三公共电极在所述基板上的正投影和所述第四公共电极在所述基板上的正投影相重叠。
  9. 根据权利要求7所述的阵列基板，其中，所述第一电极层还包括第五公共电极和第五连接电极，所述第二电极层还包括第六公共电极和第六连接电极，所述第五公共电极和所述第六公共电极设在所述第二主干电极区域内；
    所述第五公共电极在所述基板上的正投影和所述第六公共电极在所述基板上的正投影相重叠。
  10. 根据权利要求7所述的阵列基板，其中，所述第一电极层还包括第五公共电极和第五连接电极，所述第二电极层还包括第六公共电极和第六连接电极，所述第五公共电极和所述第六公共电极设在所述第二主干电极区域内；
    所述第五公共电极与所述第三公共电极相连接，所述第六公共电极与所述第四公共电极相连接，所述第五公共电极在所述基板上的正投影和所述第六公共电极在所述基板上的正投影相重叠。
  11. 一种阵列基板的制造方法，其中，包括：
    提供一基板，在所述基板上形成第一电极层，所述第一电极层包括第一公共电极；
    在所述第一电极层上形成第一绝缘层；
    在所述第一绝缘层上形成半导体层；
    在所述半导体层上形成第二电极层，所述第二电极层覆盖所述第一绝缘层，所述第二电极层包括漏电极、源电极和第二公共电极，所述漏电极和所述源电极分别与所述半导体层连接；
    在所述第二电极层上形成第一钝化层；
    在所述第一钝化层形成第三电极层，所述第三电极层包括像素电极和第一连接电极；
    其中，所述第一公共电极在所述基板上的正投影和所述像素电极在所述基板上的正投影至少部分重叠，所述第一连接电极通过贯穿所述第一绝缘层和所述第一钝化层的开口与所述第二公共电极和所述第一公共电极相连接。
  12. 一种显示面板，其中，包括阵列基板，还包括与所述阵列基板相对设置的彩膜基板，以及位于所述阵列基板和所述彩膜基板之间的液晶层；
    其中，所述阵列基板包括：
    基板；
    第一电极层，所述第一电极层设在所述基板上，所述第一电极层包括第一公共电极；
    第一绝缘层，所述第一绝缘层设在所述第一电极层上；
    半导体层，所述半导体层设在所述第一绝缘层上；
    第二电极层，所述第二电极层设在所述半导体层上并覆盖所述第一绝缘层，所述第二电极层包括漏电极、源电极和第二公共电极，所述漏电极和所述源电极分别与所述半导体层连接；
    第一钝化层，所述第一钝化层设在所述第二电极层上；
    第三电极层，所述第三电极层设在所述第一钝化层上，所述第三电极层包括像素电极；
    其中，所述第一公共电极在所述基板上的正投影和所述像素电极在所述基板上的正投影至少部分重叠，所述第二公共电极通过所述第一绝缘层上的开口与所述第一公共电极相连接。
  13. 根据权利要求12所述的显示面板，其中，所述第三电极层还包括第一连接电极，所述第一连接电极通过贯穿所述第一绝缘层和所述第一钝化层的开口与所述第二公共电极和所述第一公共电极相连接。
  14. 根据权利要求12所述的显示面板，其中，所述第一公共电极在所述基板上的正投影和所述第二公共电极在所述基板上的正投影至少部分重叠。
  15. 根据权利要求12所述的显示面板，其中，所述第一公共电极在所述基板上的正投影、所述像素电极在所述基板上的正投影和所述第二公共电极在所述基板上的正投影至少部分重叠。
  16. 根据权利要求12所述的显示面板，其中，所述第二电极层还包括第二连接电极，多个所述第一公共电极呈阵列设置，多个所述第二公共电极呈阵列设置，所述第二连接电极与位于同一行上的所述第二公共电极相连接。
  17. 根据权利要求16所述的显示面板，其中，所述第一电极层还包括第三连接电极，所述第三连接电极与位于同一列上的所述第一公共电极相连接。
  18. 根据权利要求16所述的显示面板，其中，所述基板包括透光区域和非透光区域，所述透光区域包括第一主干电极区域、第二主干电极区域以及分支电极区域，所述第二连接电极设置在所述非透光区域和所述第一主干电极区域上。
  19. 根据权利要求18所述的显示面板，其中，所述第一电极层还包括第三公共电极，所述第二电极层还包括第四公共电极，所述第三公共电极和所述第四公共电极设在所述第一主干电极区域内，所述第三公共电极在所述基板上的正投影和所述第四公共电极在所述基板上的正投影相重叠。
  20. 根据权利要求18所述的显示面板，其中，所述第一电极层还包括第五公共电极和第五连接电极，所述第二电极层还包括第六公共电极和第六连接电极，所述第五公共电极和所述第六公共电极设在所述第二主干电极区域内；
    所述第五公共电极在所述基板上的正投影和所述第六公共电极在所述基板上的正投影相重叠。
PCT/CN2022/086644 2022-03-25 2022-04-13 显示面板、阵列基板及其制造方法 WO2023178753A1 (zh)

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