WO2023176780A1 - Composant électronique - Google Patents

Composant électronique Download PDF

Info

Publication number
WO2023176780A1
WO2023176780A1 PCT/JP2023/009640 JP2023009640W WO2023176780A1 WO 2023176780 A1 WO2023176780 A1 WO 2023176780A1 JP 2023009640 W JP2023009640 W JP 2023009640W WO 2023176780 A1 WO2023176780 A1 WO 2023176780A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductor layer
conductor
layer
semiconductor substrate
layers
Prior art date
Application number
PCT/JP2023/009640
Other languages
English (en)
Japanese (ja)
Inventor
翔太 安藤
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2023176780A1 publication Critical patent/WO2023176780A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor

Definitions

  • the present invention relates to an electronic component that includes a semiconductor substrate and is configured by providing an inductor or the like on the semiconductor substrate.
  • Patent Document 1 shows a high frequency inductance circuit formed on a semiconductor substrate.
  • this high frequency inductance circuit two types of spiral coil type inductors each having 1.5 turns are formed on an insulating semiconductor substrate so as to be alternately connected. The winding directions of the spiral coils of these two types of spiral coil type inductors are opposite to each other.
  • the magnetic fields of the spiral coil conductors of adjacent inductors do not cancel each other out, so that the inductance required for the desired inductance determined from one one-turn spiral coil type inductor is There is no need to arrange more spiral coil type inductors in series than the actual number.
  • Patent Document 1 describes the above-mentioned spiral coil type inductor, it is not possible to actually manufacture a high frequency inductance circuit using these spiral coil type inductors.
  • spiral coil type inductors When series-connected spiral coil type inductors are arranged side by side, there will always be locations where the spiral coil side inductors partially intersect. The embodiment disclosed in Patent Document 1 does not mention this intersection. If a high-frequency inductance circuit is manufactured based on the diagram shown in Patent Document 1, the spiral coil type conductor pattern will be short-circuited at the above-mentioned intersection points, making it impossible to realize the electrical characteristics of an inductor.
  • An object of the present invention is to provide an electronic device including an inductor or the like having a structure in which magnetic fields generated by current flowing around adjacent opening patterns of a spiral or loop-shaped conductor layer each having an opening pattern do not cancel each other out.
  • Our goal is to provide parts.
  • An electronic component as an example of the present disclosure first includes a semiconductor substrate, a plurality of insulating layers formed on the semiconductor substrate, a plurality of conductive layers insulated by the insulating layer, and a plurality of conductive layers. It includes an interlayer connection conductor that connects different conductor layers among the layers.
  • the plurality of conductor layers include a spiral or loop-shaped first conductor layer having an opening pattern, a spiral or loop-shaped second conductor layer having an opening pattern, and a third conductor layer.
  • the first conductor layer and the second conductor layer are adjacent to each other in the direction along the surface of the semiconductor substrate, and the first conductor layer and the second conductor layer do not overlap with each other.
  • the third conductor layer is electrically connected to the first conductor layer or the second conductor layer via the interlayer connecting conductor, and the third conductor layer is electrically connected to the first conductor layer or the second conductor layer through the interlayer connecting conductor.
  • an electronic device including an inductor or the like having a structure in which magnetic fields generated by current flowing around adjacent opening patterns of spiral or loop-shaped conductor layers each having an opening pattern do not cancel each other out. Parts can be obtained.
  • FIG. 1(A) is a plan view of an electronic component 101 according to the first embodiment
  • FIG. 1(B) is a sectional view taken along the line BB in FIG. 1(A).
  • FIG. 2A is a diagram showing a state of a magnetic field generated when a current flows around the opening pattern CO1 of the first conductive layer and the opening pattern CO2 of the second conductive layer.
  • FIG. 2B is a diagram showing a magnetic field generated when a current flows around an opening pattern CO of a conductive layer as a comparative example.
  • 3(A) is a plan view of the electronic component 102 according to the second embodiment
  • FIG. 3(B) is a sectional view taken along the line BB in FIG. 3(A).
  • FIG. 4(A) is a plan view of the electronic component 103 according to the third embodiment
  • FIG. 4(B) is a sectional view taken along the line BB in FIG. 4(A).
  • FIG. 5 is a circuit diagram of the electronic component 103.
  • FIG. 6 is a block diagram showing the circuit configuration of the transmitter of the communication device.
  • FIG. 7 is a plan view showing the configuration of an inductor region according to the fourth embodiment.
  • FIG. 8 is a plan view showing the configuration of an inductor region according to the fifth embodiment.
  • FIG. 1(A) is a plan view of an electronic component 101 according to the first embodiment
  • FIG. 1(B) is a sectional view taken along the line BB in FIG. 1(A).
  • FIG. 1A is a plan view in a state before formation of a protective film 10, which will be described later.
  • This electronic component 101 includes a semiconductor substrate 1, an insulator layer 2 formed on the semiconductor substrate 1, conductor layers 3A, 3B, 3C1, 3C2 formed on the insulator layer 2, and The conductor layers 3D and 3E formed in , an interlayer connection conductor 6A that connects the conductor layer 3A and the conductor layer 3D, an interlayer connection conductor 6B that connects the conductor layer 3B and the conductor layer 3E, and It includes pad electrodes 9A and 9B formed and a protective film 10 formed on the upper surface side of the semiconductor substrate 1.
  • the semiconductor substrate 1 is, for example, a substrate made of an impurity semiconductor such as a carrier-doped silicon substrate
  • the insulator layer 2 is, for example, a SiN film
  • the conductor layers 3A, 3B, 3C1, 3C2, 3D, and 3E are, for example, an Al film
  • the interlayer connection conductors 6A, 6B. is a Cu film
  • the pad electrodes 9A and 9B are metal films with a Ni base and an Au surface
  • the protective film 10 is an organic film such as a solder resist
  • the lower electrode 8 is a metal film with a base of Cu or Ni and a surface of Au. It is a metal film with a
  • the patterns of the conductor layers 3C1, 3C2, 3D, and 3E are inductor patterns.
  • the conductor layers 3A and 3B constitute extraction electrodes.
  • Pad electrodes 9A and 9B are used, for example, as pads for wire bonding.
  • the conductor layer 3C1 constitutes a spiral-shaped first conductor layer forming an opening pattern CO1
  • the conductor layer 3C2 constitutes a spiral-shaped second conductor layer forming an opening pattern CO2.
  • the "opening pattern” here refers to the case where the electrically connected conductor layers can be regarded as one spiral coil when viewed in the direction perpendicular to the semiconductor substrate 1, that is, the Z-axis direction in FIG. 1(A). This is an opening that is considered to be one coil made of multiple conductor layers. Specifically, in the case of FIG.
  • the opening pattern CO1 refers to a region surrounded by the conductor layer 3C1 and the conductor layer 3D
  • the opening pattern CO2 refers to the region surrounded by the conductor layer 3C2 and the conductor layer 3E. refers to the area
  • the conductor layers 3D and 3E constitute a third conductor layer whose pattern is linear wiring. That is, the first conductor layer, the second conductor layer, and the third conductor layer are electrically connected in series.
  • the swirling direction of the current flowing through the conductor layer 3C1 and the swirling direction of the current flowing through the conductor layer 3C2 are opposite to each other.
  • a current flows through at least a portion of the conductor layer 3D in the same direction as the swirling direction of the current that flows around the opening pattern CO1 of the conductor layer 3C1. Further, a current flows through at least a portion of the conductive layer 3E in the same direction as the direction of the current flowing around the opening pattern CO2 of the conductive layer 3C2.
  • the conductive layer 3C1 and the conductive layer 3C2 are adjacent to each other in the direction along the surface of the semiconductor substrate 1 (the X direction in the examples shown in FIGS. 1(A) and 1(B)), and the conductive layer 3C1 and The conductor layer 3C2 is arranged in parallel with the conductor layer 3C2 so as not to overlap with each other.
  • the first end of the conductor layer 3D is electrically connected to the first end of the conductor layer 3C1 via the interlayer connection conductor 6C1, and the first end of the conductor layer 3E is electrically connected to the first end of the conductor layer 3C2.
  • Conductivity is established via the interlayer connection conductor 6C2.
  • the second end of the conductor layer 3D is electrically connected to the conductor layer 3A via the interlayer connection conductor 6A
  • the second end of the conductor layer 3E is electrically connected to the conductor layer 3B via the interlayer connection conductor 6B. conduction.
  • the second end of the conductor layer 3C1 and the second end of the conductor layer 3C2 described above are formal virtual ends.
  • the first end of the conductor layer 3C1 and the first end of the conductor layer 3C2 respectively refer to the other end different from the continuous end.
  • FIG. 2(A) is a diagram showing a state of a magnetic field generated when a current flows around the opening pattern CO1 of the first conductive layer and the opening pattern CO2 of the second conductive layer.
  • FIG. 2B is a diagram showing a magnetic field generated when a current flows around an opening pattern CO of a conductive layer as a comparative example.
  • the conductor layer as a comparative example shown in FIG. 2(B) is a single spiral conductor layer or a single loop conductor layer.
  • dot symbols and cross symbols indicate the direction of current, and broken lines indicate magnetic flux.
  • eddy currents are induced in the semiconductor substrate 1 by the high frequency magnetic field.
  • the magnetic fields generated by current flowing around adjacent opening patterns of the openings in the conductive layer do not cancel each other out, so the inductance is small even though it is small.
  • a high inductor can be obtained.
  • the magnetic flux passing through the opening pattern CO1 and the opening pattern CO2 surrounds the adjacent portions of the conductive layer 3C1 and the conductive layer 3C2, so the magnetic flux moves away from the semiconductor substrate 1. Since eddy currents generated in the semiconductor substrate 1 are suppressed, an inductor with low ESR can be obtained.
  • the pad electrodes 9A, 9B and the conductor layers 3C1, 3C2 forming the coil are arranged on a straight line, the conductor layers 3C1, 3C2 and the pad electrodes 9A, 9B are connected to each other.
  • Layers 3D and 3E can also be used as part of the coil, and a high inductance value can be obtained despite the small size.
  • the second embodiment will exemplify an electronic component in which the structure of the conductor layer constituting the inductor is different from the example shown in the first embodiment.
  • FIG. 3(A) is a plan view of the electronic component 102 according to the second embodiment
  • FIG. 3(B) is a sectional view taken along the line BB in FIG. 3(A).
  • FIG. 3A is a plan view in a state before the protective film 10 is formed.
  • This electronic component 102 includes a semiconductor substrate 1, an insulator layer 2 formed on the semiconductor substrate 1, and conductor layers 3A, 3B, 3C1, 3C2, 3D, and 3E formed on the insulator layer 2.
  • An interlayer connection conductor 6C1 that connects the conductor layer 3C1 and the conductor layer 3D
  • an interlayer connection conductor 6C2 that connects the conductor layer 3C2 and the conductor layer 3E, and the conductor layer 3A and the conductor layer 3D.
  • the conductor layer 3C1 constitutes a spiral-shaped first conductor layer forming an opening pattern CO1
  • the conductor layer 3C2 constitutes a spiral-shaped second conductor layer forming an opening pattern CO2.
  • the conductor layers 3D and 3E constitute a third conductor layer whose pattern is a linear wiring.
  • the conductor layers 3D and 3E are formed on the surface of the semiconductor substrate 1, but in the example shown in FIG. 3B, the conductor layers 3D and 3E are made of insulators. It is formed within the layer of layer 2. That is, the conductor layers 3D and 3E are formed at positions insulated from the semiconductor substrate 1.
  • the third conductor layers 3D and 3E may be arranged at a position away from the semiconductor substrate 1.
  • the eddy current induced in the semiconductor substrate 1 is further suppressed, and the ESR of the inductor can be further reduced.
  • an inductor with low ESR can be obtained regardless of the doping concentration of the semiconductor substrate 1, various functions can be added using the semiconductor substrate.
  • FIG. 4(A) is a plan view of the electronic component 103 according to the third embodiment
  • FIG. 4(B) is a sectional view taken along the line BB in FIG. 4(A).
  • FIG. 4A is a plan view in a state before the protective film 10 is formed.
  • This electronic component 103 includes a semiconductor substrate 1, an insulator layer 2 formed on the semiconductor substrate 1, and conductor layers 3B, 3C1, 3C2, 3D, 3E, 3F, and 3G formed on the insulator layer 2. , a dielectric layer 4 formed on the semiconductor substrate 1, a conductor layer 3K formed on the dielectric layer 4, a dielectric layer 5 formed in the insulator layer 2, and a conductor layer 3G. , 3B, a protective film 10 formed on the upper surface of the semiconductor substrate 1, and a lower surface electrode 8 formed on the lower surface of the semiconductor substrate 1.
  • the semiconductor substrate 1 is, for example, a carrier-doped silicon substrate
  • the insulator layer 2 is, for example, a SiN film
  • the conductor layers 3C1, 3C2, 3D, 3E are, for example, an Al film
  • the conductor layers 3B, 3F, 3G are, for example, a Cu film
  • 4 and 5 are SiO 2 films
  • pad electrodes 9A and 9B are metal films with Ni as the base and Au as the surface
  • protective film 10 is an organic film such as solder resist
  • lower electrode 8 is made of Cu or Ni as the base, for example. It is a metal film whose surface is made of Au.
  • the patterns of the conductor layers 3C1, 3C2, 3D, and 3E constitute an inductor.
  • the conductor layers 3H and 3J constitute capacitor electrodes formed in the insulator layer 2.
  • the conductor layer 3K constitutes a capacitor electrode formed on the dielectric layer 4.
  • the conductor layers 3F, 3G, and 3B constitute extraction electrodes.
  • Pad electrodes 9A and 9B are used, for example, as pads for wire bonding.
  • the lower surface electrode 8 is used, for example, as an electrode for die bonding.
  • the patterns of the conductor layers 3C1, 3C2, 3D, and 3E are inductor patterns, and the conductor layers 3C1, 3C2, 3D, and 3E form an inductor region ZL in the semiconductor substrate 1. Further, in the semiconductor substrate 1, the region where the conductor layer 3K and the dielectric layer 4 as capacitor electrodes are formed is a capacitor region ZC.
  • the configuration of the inductor region ZL is similar to the example shown in FIGS. 3(A) and 3(B) in the second embodiment.
  • a conductor portion 7 is formed in the capacitor region ZC of the semiconductor substrate 1.
  • the conductor portion 7 is arranged below the dielectric layer 4. That is, the conductor portions 7 are arranged in a higher proportion in the capacitor region ZC of the semiconductor substrate 1 than in the inductor region ZL.
  • the conductor portion 7 is made of conductive polysilicon, for example, and has higher conductivity than the semiconductor substrate 1.
  • the conductor portion 7 is formed by digging a plurality of trenches in the semiconductor substrate 1 and filling the trenches with the conductive polysilicon or the like.
  • the conductor layer 3K, dielectric layer 4, semiconductor substrate 1, conductor portion 7, and bottom electrode 8 constitute a capacitor.
  • the conductor layer 3K is the first electrode of the capacitor
  • the semiconductor substrate 1, the conductor portion 7, and the lower surface electrode 8 are the second electrodes of the capacitor.
  • the conductor portions 7 having higher conductivity than the semiconductor substrate 1 are arranged in the capacitor region ZC in the semiconductor substrate 1 at a higher rate than in the inductor region ZL.
  • the conductivity of the entire semiconductor substrate 1 is lowered, and the eddy current induced in the semiconductor substrate 1 due to the high frequency magnetic field generated by the inductor pattern by the conductor layers 3A and 3B is suppressed, resulting in an inductor with a high Q value. is obtained.
  • the conductivity of the capacitor electrode in the capacitor region ZC can be increased, and a capacitor with a high Q value can be obtained.
  • FIG. 5 is a circuit diagram of the electronic component 103.
  • the ports P1 and P2 shown in FIG. 5 correspond to the pad electrodes 9A and 9B of the electronic component 103 shown in FIGS. 4(A) and 4(B), respectively, and the ground shown in FIG. This corresponds to the lower surface electrode 8 in 4(B).
  • a capacitor C1 shown in FIG. 5 is a capacitor configured by a conductor layer 3K, a dielectric layer 4, a conductor portion 7, a semiconductor substrate 1, and a bottom electrode 8.
  • a capacitor C2 shown in FIG. 5 is a capacitor composed of conductor layers 3H, 3J and a dielectric layer 5.
  • the inductor L1 shown in FIG. 5 is an inductor composed of conductor layers 3C1, 3C2, 3D, and 3E. Such an LC circuit constitutes an impedance matching circuit.
  • FIG. 6 is a block diagram showing the circuit configuration of the transmitter of the communication device.
  • This transmitting section includes a transmitting circuit that inputs a transmitting signal, modulates it, and outputs a high-frequency transmitting signal, a power amplifier PA, and an impedance matching circuit MC that matches impedance between the transmitting circuit and the power amplifier PA.
  • the output signal of power amplifier PA is guided to an antenna.
  • a communication device including the transmitter shown in FIG. 6 is provided in a base station, for example.
  • the fourth embodiment will exemplify an electronic component in which the configuration of the conductor portion disposed in the inductor region is different from the examples shown in the previous embodiments.
  • FIG. 7 is a plan view showing the configuration of an inductor region according to the fourth embodiment. However, illustration of the insulator layer and the protective film is omitted.
  • the conductive layers 3C11 and 3C12 are adjacent to each other in the direction along the surface of the semiconductor substrate, and the conductive layers 3C11 and 3C12 are juxtaposed so as not to overlap each other.
  • the conductor layer 3C11 is electrically connected to the conductor layer 3D1 through the interlayer connection conductor, and the conductor layer 3C12 is electrically connected to the conductor layer 3E1 through the interlayer connection conductor.
  • the conductor layers 3C21 and 3C22 are adjacent to each other in the direction along the surface of the semiconductor substrate, and the conductor layers 3C21 and 3C22 are juxtaposed so as not to overlap each other.
  • the conductor layer 3C21 is electrically connected to the conductor layer 3D2 through the interlayer connection conductor, and the conductor layer 3C22 is electrically connected to the conductor layer 3E2 through the interlayer connection conductor.
  • arrow lines indicate the direction of current flowing through each conductor layer in a certain phase.
  • the direction of the current flowing around the opening pattern CO11 of the conductor layer 3C11 and the direction of the current flowing around the opening pattern CO12 of the conductor layer 3C12 are opposite to each other.
  • the direction of the current flowing around the opening pattern CO21 of the conductor layer 3C21 and the direction of the current flowing around the opening pattern CO22 of the conductor layer 3C22 are opposite to each other.
  • the direction of the current flowing around the opening pattern CO12 of the conductor layer 3C12 and the direction of the current flowing around the opening pattern CO21 of the conductor layer 3C21 are opposite to each other.
  • the direction of the current flowing around the opening pattern CO11 of the conductor layer 3C11 and the direction of the current flowing around the opening pattern CO22 of the conductor layer 3C22 are opposite to each other.
  • an inductor may be configured by having three or more spiral or loop-shaped conductor layers each having an opening pattern and electrically connecting them in series.
  • the fifth embodiment will exemplify an electronic component in which the configuration of the conductor portion disposed in the inductor region is different from the examples shown in the previous embodiments.
  • FIG. 8 is a plan view showing the configuration of an inductor region according to the fifth embodiment. However, illustration of the insulator layer and the protective film is omitted.
  • the conductive layers 3C11 and 3C12 are adjacent to each other in the direction along the surface of the semiconductor substrate, and the conductive layers 3C11 and 3C12 are juxtaposed so as not to overlap each other.
  • the conductor layer 3C11 is electrically connected to the conductor layer 3D1 through the interlayer connection conductor, and the conductor layer 3C12 is electrically connected to the conductor layer 3E1 through the interlayer connection conductor.
  • the conductor layers 3C21 and 3C22 are adjacent to each other in the direction along the surface of the semiconductor substrate, and the conductor layers 3C21 and 3C22 are juxtaposed so as not to overlap each other.
  • the conductor layer 3C21 is electrically connected to the conductor layer 3D2 through the interlayer connection conductor, and the conductor layer 3C22 is electrically connected to the conductor layer 3E2 through the interlayer connection conductor.
  • the conductor layer 3D1 and the conductor layer 3D2 are electrically connected, and the conductor layer 3E1 and the conductor layer 3E2 are electrically connected.
  • arrow lines indicate the direction of current flowing through each conductor layer in a certain phase.
  • the direction of the current flowing around the opening pattern CO11 of the conductor layer 3C11 and the direction of the current flowing around the opening pattern CO12 of the conductor layer 3C12 are opposite to each other.
  • the direction of the current flowing around the opening pattern CO21 of the conductor layer 3C21 and the direction of the current flowing around the opening pattern CO22 of the conductor layer 3C22 are opposite to each other.
  • the direction of the current flowing around the opening pattern CO12 of the conductor layer 3C12 and the direction of the current flowing around the opening pattern CO22 of the conductor layer 3C22 are opposite to each other.
  • the direction of the current flowing around the opening pattern CO11 of the conductor layer 3C11 and the direction of the current flowing around the opening pattern CO21 of the conductor layer 3C21 are opposite to each other.
  • an inductor may be constructed by including three or more spiral or loop-shaped conductor layers each having an opening pattern and electrically connecting them in parallel.
  • the conductor layer having an opening pattern is formed in a spiral shape or a loop shape with more than one turn but less than two turns, but the present invention is not limited to this. do not have.
  • the conductor layer having an opening pattern may be formed in a spiral shape having more than two turns.
  • the first conductor layer and the second conductor layer are formed in the same layer in the insulator layer, but the first conductor layer and the second conductor layer are formed in different layers. It may be formed into layers. Furthermore, in each of the embodiments described above, an example was shown in which the third conductor layer that is electrically connected to the first conductor layer or the second conductor layer is formed in the same layer. The third conductor layer and the third conductor layer electrically connected to the second conductor layer may be formed in different layers.
  • the conductive layer 3C1 and the conductive layer 3C2 shown in FIGS. 1(A) and 1(B) may be formed in different layers in the insulating layer 2, and the conductive layers 3D and 3E may They may be formed in different layers in the insulator layer 2.
  • each embodiment shows an electronic component including a capacitor and an inductor as a passive component
  • the present invention can be similarly applied to an electronic component including an active component as well as a passive component.
  • a resistive element may be configured with a spiral or loop-shaped conductor layer having an opening pattern.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

Ce composant électronique (101) comprend un substrat semi-conducteur (1), de multiples couches isolantes (2) formées sur ce substrat semi-conducteur (1), de multiples couches conductrices isolées par les couches isolantes (2), ainsi que des conducteurs de connexion entre couches (6C1, 6C2) pour une connexion entre les différentes couches conductrices. Les multiples couches conductrices comprennent une couche conductrice en spirale (3C1) présentant un motif d'ouverture (CO1), une couche conductrice en spirale (3C2) présentant un motif d'ouverture (CO2), ainsi que des couches conductrices (3D, 3E). Des couches conductrices (3C1, 3C2) sont adjacentes dans une direction le long de la surface du substrat semi-conducteur (1) et agencées côte à côte de façon à ne pas se chevaucher l'une l'autre. La direction dans laquelle un courant circule autour du motif d'ouverture (CO1) de la couche conductrice (3C1) et la direction dans laquelle un courant circule autour du motif d'ouverture (CO2) de la couche conductrice (3C2) sont opposées l'une à l'autre.
PCT/JP2023/009640 2022-03-16 2023-03-13 Composant électronique WO2023176780A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022041437 2022-03-16
JP2022-041437 2022-03-16

Publications (1)

Publication Number Publication Date
WO2023176780A1 true WO2023176780A1 (fr) 2023-09-21

Family

ID=88023784

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/009640 WO2023176780A1 (fr) 2022-03-16 2023-03-13 Composant électronique

Country Status (1)

Country Link
WO (1) WO2023176780A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157507A (ja) * 1987-09-29 1989-06-20 Toshiba Corp 平面インダクタ
JPH01303706A (ja) * 1988-06-01 1989-12-07 Fujitsu Ltd Ｍｍｉｃ用インダクタンス
JPH0645148A (ja) * 1992-02-26 1994-02-18 Amorphous Denshi Device Kenkyusho:Kk 高周波用インダクタンス回路
US5477204A (en) * 1994-07-05 1995-12-19 Motorola, Inc. Radio frequency transformer
JP2015530752A (ja) * 2012-09-20 2015-10-15 マーベル ワールド トレード リミテッド 八の字及び双八の字の入れ子構造の変圧器を有する変圧器回路
JP2017147321A (ja) * 2016-02-17 2017-08-24 Tdk株式会社 コイル部品、コイル部品を内蔵した回路基板、並びに、コイル部品を備える電源回路
US20180082947A1 (en) * 2014-10-06 2018-03-22 Realtek Semiconductor Corporation Structure of integrated inductor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157507A (ja) * 1987-09-29 1989-06-20 Toshiba Corp 平面インダクタ
JPH01303706A (ja) * 1988-06-01 1989-12-07 Fujitsu Ltd Ｍｍｉｃ用インダクタンス
JPH0645148A (ja) * 1992-02-26 1994-02-18 Amorphous Denshi Device Kenkyusho:Kk 高周波用インダクタンス回路
US5477204A (en) * 1994-07-05 1995-12-19 Motorola, Inc. Radio frequency transformer
JP2015530752A (ja) * 2012-09-20 2015-10-15 マーベル ワールド トレード リミテッド 八の字及び双八の字の入れ子構造の変圧器を有する変圧器回路
US20180082947A1 (en) * 2014-10-06 2018-03-22 Realtek Semiconductor Corporation Structure of integrated inductor
JP2017147321A (ja) * 2016-02-17 2017-08-24 Tdk株式会社 コイル部品、コイル部品を内蔵した回路基板、並びに、コイル部品を備える電源回路

Similar Documents

Publication Publication Date Title
US20200243240A1 (en) Isolated power converter with magnetics on chip
US9978512B2 (en) Circuit device
JP4059498B2 (ja) 半導体装置
US7671714B2 (en) Planar inductive component and a planar transformer
US8592944B2 (en) Semiconductor electronic device with an integrated device with an integrated galvanic isolator element and related assembly process
US6188306B1 (en) On-chip transformers
TWI666663B (zh) 微製造線圈結構、隔離器及於基板上製造線圈結構之方法
US7064411B2 (en) Spiral inductor and transformer
US7978043B2 (en) Semiconductor device
US20100314713A1 (en) Integrated Circuit Inductors with Reduced Magnetic Coupling
CN109686549B (zh) 一种具有多个绕组线圈通过微纳加工制作的集成变压器
US20030234436A1 (en) Semiconductor device with a spiral inductor and magnetic material
WO2023176780A1 (fr) Composant électronique
WO2012144360A1 (fr) Transformateur haute fréquence, composants haute fréquence et appareil de terminal de communication
EP4002402A1 (fr) Transformateur planaire fendu symétrique
EP4012733A2 (fr) Transformateur à bobinage divisé symétrique pour la réduction des interférences électromagnétiques
JP2019169907A (ja) 複合アンテナ装置及び電子機器
JP2012227352A (ja) 高周波トランス、高周波部品および通信端末装置
WO2007086278A1 (fr) Dispositif de circuit intégré
WO2023181803A1 (fr) Composant électronique et dispositif de circuit
CN115841914A (zh) 绝缘器件以及隔离器
CN112133540A (zh) 绕线型线圈部件以及使用该部件的直流电流叠加电路
CN112447357A (zh) 电感器部件
KR20030007545A (ko) 자심 내에 전기 연결을 포함하는 다층 변압기

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23770735

Country of ref document: EP

Kind code of ref document: A1