WO2023176780A1

WO2023176780A1 - Electronic component

Info

Publication number: WO2023176780A1
Application number: PCT/JP2023/009640
Authority: WO
Inventors: 翔太安藤
Original assignee: 株式会社村田製作所
Priority date: 2022-03-16
Filing date: 2023-03-13
Publication date: 2023-09-21

Abstract

This electronic component (101) comprises a semiconductor substrate (1), multiple insulator layers (2) formed on this semiconductor substrate (1), multiple conductor layers insulated by the insulator layers (2), and interlayer connection conductors (6C1, 6C2) for connecting between the different conductor layers. The multiple conductor layers include spiral conductor layer (3C1) having opening pattern (CO1), spiral conductor layer (3C2) having opening pattern (CO2), and conductor layers (3D, 3E). Conductor layers (3C1, 3C2) adjoin in a direction along the surface of the semiconductor substrate (1) and are arranged side by side so as not to overlap with each other. The direction in which a current flows around opening pattern (CO1) of conductor layer (3C1) and the direction in which a current flows around opening pattern (CO2) of conductor layer (3C2) are opposite to each other.

Description

electronic components

The present invention relates to an electronic component that includes a semiconductor substrate and is configured by providing an inductor or the like on the semiconductor substrate.

Patent Document 1 shows a high frequency inductance circuit formed on a semiconductor substrate. In this high frequency inductance circuit, two types of spiral coil type inductors each having 1.5 turns are formed on an insulating semiconductor substrate so as to be alternately connected. The winding directions of the spiral coils of these two types of spiral coil type inductors are opposite to each other.

According to the high frequency inductance circuit as shown in Patent Document 1, the magnetic fields of the spiral coil conductors of adjacent inductors do not cancel each other out, so that the inductance required for the desired inductance determined from one one-turn spiral coil type inductor is There is no need to arrange more spiral coil type inductors in series than the actual number.

Japanese Patent Application Publication No. 6-45148

Although Patent Document 1 describes the above-mentioned spiral coil type inductor, it is not possible to actually manufacture a high frequency inductance circuit using these spiral coil type inductors. When series-connected spiral coil type inductors are arranged side by side, there will always be locations where the spiral coil side inductors partially intersect. The embodiment disclosed in Patent Document 1 does not mention this intersection. If a high-frequency inductance circuit is manufactured based on the diagram shown in Patent Document 1, the spiral coil type conductor pattern will be short-circuited at the above-mentioned intersection points, making it impossible to realize the electrical characteristics of an inductor.

An object of the present invention is to provide an electronic device including an inductor or the like having a structure in which magnetic fields generated by current flowing around adjacent opening patterns of a spiral or loop-shaped conductor layer each having an opening pattern do not cancel each other out. Our goal is to provide parts.

An electronic component as an example of the present disclosure first includes a semiconductor substrate, a plurality of insulating layers formed on the semiconductor substrate, a plurality of conductive layers insulated by the insulating layer, and a plurality of conductive layers. It includes an interlayer connection conductor that connects different conductor layers among the layers. The plurality of conductor layers include a spiral or loop-shaped first conductor layer having an opening pattern, a spiral or loop-shaped second conductor layer having an opening pattern, and a third conductor layer. The first conductor layer and the second conductor layer are adjacent to each other in the direction along the surface of the semiconductor substrate, and the first conductor layer and the second conductor layer do not overlap with each other. The third conductor layer is electrically connected to the first conductor layer or the second conductor layer via the interlayer connecting conductor, and the third conductor layer is electrically connected to the first conductor layer or the second conductor layer through the interlayer connecting conductor. When electricity is applied to the conductor layer, the direction of the current flowing around the opening pattern of the first conductor layer and the direction of the current flowing around the opening pattern of the second conductor layer are mutually opposite directions. It is characterized by

According to the present invention, an electronic device including an inductor or the like having a structure in which magnetic fields generated by current flowing around adjacent opening patterns of spiral or loop-shaped conductor layers each having an opening pattern do not cancel each other out. Parts can be obtained.

FIG. 1(A) is a plan view of an electronic component 101 according to the first embodiment, and FIG. 1(B) is a sectional view taken along the line BB in FIG. 1(A). FIG. 2A is a diagram showing a state of a magnetic field generated when a current flows around the opening pattern CO1 of the first conductive layer and the opening pattern CO2 of the second conductive layer. FIG. 2B is a diagram showing a magnetic field generated when a current flows around an opening pattern CO of a conductive layer as a comparative example. 3(A) is a plan view of the electronic component 102 according to the second embodiment, and FIG. 3(B) is a sectional view taken along the line BB in FIG. 3(A). 4(A) is a plan view of the electronic component 103 according to the third embodiment, and FIG. 4(B) is a sectional view taken along the line BB in FIG. 4(A). FIG. 5 is a circuit diagram of the electronic component 103. FIG. 6 is a block diagram showing the circuit configuration of the transmitter of the communication device. FIG. 7 is a plan view showing the configuration of an inductor region according to the fourth embodiment. FIG. 8 is a plan view showing the configuration of an inductor region according to the fifth embodiment.

Hereinafter, a plurality of embodiments for carrying out the present invention will be described with reference to the drawings and some specific examples. In each figure, the same parts are given the same reference numerals. In consideration of easiness of explanation or understanding of the main points, the embodiment is shown divided into a plurality of embodiments for convenience of explanation, but it is possible to partially replace or combine the configurations shown in different embodiments. In the second embodiment and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only different points will be described. In particular, similar effects due to similar configurations will not be mentioned for each embodiment.

《First embodiment》
FIG. 1(A) is a plan view of an electronic component 101 according to the first embodiment, and FIG. 1(B) is a sectional view taken along the line BB in FIG. 1(A). However, FIG. 1A is a plan view in a state before formation of a protective film 10, which will be described later.

This electronic component 101 includes a semiconductor substrate 1, an insulator layer 2 formed on the semiconductor substrate 1,

conductor layers

3A, 3B, 3C1, 3C2 formed on the insulator layer 2, and The

conductor layers

3D and 3E formed in , an interlayer connection conductor 6A that connects the conductor layer 3A and the conductor layer 3D, an interlayer connection conductor 6B that connects the conductor layer 3B and the conductor layer 3E, and It includes

pad electrodes

9A and 9B formed and a protective film 10 formed on the upper surface side of the semiconductor substrate 1.

The semiconductor substrate 1 is, for example, a substrate made of an impurity semiconductor such as a carrier-doped silicon substrate, the insulator layer 2 is, for example, a SiN film, the

conductor layers

3A, 3B, 3C1, 3C2, 3D, and 3E are, for example, an Al film, and the interlayer connection conductors 6A, 6B. is a Cu film, for example, the

pad electrodes

9A and 9B are metal films with a Ni base and an Au surface, the protective film 10 is an organic film such as a solder resist, and the lower electrode 8 is a metal film with a base of Cu or Ni and a surface of Au. It is a metal film with a

The patterns of the conductor layers 3C1, 3C2, 3D, and 3E are inductor patterns. The

conductor layers

3A and 3B constitute extraction electrodes.

Pad electrodes

9A and 9B are used, for example, as pads for wire bonding.

The conductor layer 3C1 constitutes a spiral-shaped first conductor layer forming an opening pattern CO1, and the conductor layer 3C2 constitutes a spiral-shaped second conductor layer forming an opening pattern CO2. There is. The "opening pattern" here refers to the case where the electrically connected conductor layers can be regarded as one spiral coil when viewed in the direction perpendicular to the semiconductor substrate 1, that is, the Z-axis direction in FIG. 1(A). This is an opening that is considered to be one coil made of multiple conductor layers. Specifically, in the case of FIG. 1(A), the opening pattern CO1 refers to a region surrounded by the conductor layer 3C1 and the conductor layer 3D, and the opening pattern CO2 refers to the region surrounded by the conductor layer 3C2 and the conductor layer 3E. refers to the area where

The

conductor layers

3D and 3E constitute a third conductor layer whose pattern is linear wiring. That is, the first conductor layer, the second conductor layer, and the third conductor layer are electrically connected in series.

A current flows through the conductor layer 3C1 constituting the spiral-shaped first conductor layer so as to swirl around the opening pattern CO1. A current flows through the conductor layer 3C2 constituting the spiral-shaped second conductor layer so as to swirl around the opening pattern CO2. The swirling direction of the current flowing through the conductor layer 3C1 and the swirling direction of the current flowing through the conductor layer 3C2 are opposite to each other.

A current flows through at least a portion of the conductor layer 3D in the same direction as the swirling direction of the current that flows around the opening pattern CO1 of the conductor layer 3C1. Further, a current flows through at least a portion of the conductive layer 3E in the same direction as the direction of the current flowing around the opening pattern CO2 of the conductive layer 3C2.

The conductive layer 3C1 and the conductive layer 3C2 are adjacent to each other in the direction along the surface of the semiconductor substrate 1 (the X direction in the examples shown in FIGS. 1(A) and 1(B)), and the conductive layer 3C1 and The conductor layer 3C2 is arranged in parallel with the conductor layer 3C2 so as not to overlap with each other.

The first end of the conductor layer 3D is electrically connected to the first end of the conductor layer 3C1 via the interlayer connection conductor 6C1, and the first end of the conductor layer 3E is electrically connected to the first end of the conductor layer 3C2. Conductivity is established via the interlayer connection conductor 6C2. Further, the second end of the conductor layer 3D is electrically connected to the conductor layer 3A via the interlayer connection conductor 6A, and the second end of the conductor layer 3E is electrically connected to the conductor layer 3B via the interlayer connection conductor 6B. conduction.

In this embodiment, since the conductor layer 3C1 and the conductor layer 3C2 are continuous, the second end of the conductor layer 3C1 and the second end of the conductor layer 3C2 described above are formal virtual ends. The first end of the conductor layer 3C1 and the first end of the conductor layer 3C2 respectively refer to the other end different from the continuous end. When the conductor layer 3C1 and the conductor layer 3C2 are energized, the direction of the current flowing around the opening pattern CO1 and the direction of the current flowing around the opening pattern CO2 are opposite to each other.

FIG. 2(A) is a diagram showing a state of a magnetic field generated when a current flows around the opening pattern CO1 of the first conductive layer and the opening pattern CO2 of the second conductive layer. FIG. 2B is a diagram showing a magnetic field generated when a current flows around an opening pattern CO of a conductive layer as a comparative example. The conductor layer as a comparative example shown in FIG. 2(B) is a single spiral conductor layer or a single loop conductor layer.

In FIGS. 2(A) and 2(B), dot symbols and cross symbols indicate the direction of current, and broken lines indicate magnetic flux. In the comparative example shown in FIG. 2(B), eddy currents are induced in the semiconductor substrate 1 by the high frequency magnetic field. In contrast, in the present embodiment shown in FIG. 2A, the magnetic fields generated by current flowing around adjacent opening patterns of the openings in the conductive layer do not cancel each other out, so the inductance is small even though it is small. A high inductor can be obtained. Further, as shown in FIG. 2A, the magnetic flux passing through the opening pattern CO1 and the opening pattern CO2 surrounds the adjacent portions of the conductive layer 3C1 and the conductive layer 3C2, so the magnetic flux moves away from the semiconductor substrate 1. Since eddy currents generated in the semiconductor substrate 1 are suppressed, an inductor with low ESR can be obtained.

Further, since the

pad electrodes

9A, 9B and the conductor layers 3C1, 3C2 forming the coil are arranged on a straight line, the conductor layers 3C1, 3C2 and the

pad electrodes

9A, 9B are connected to each other.

Layers

3D and 3E can also be used as part of the coil, and a high inductance value can be obtained despite the small size.

《Second embodiment》
The second embodiment will exemplify an electronic component in which the structure of the conductor layer constituting the inductor is different from the example shown in the first embodiment.

FIG. 3(A) is a plan view of the electronic component 102 according to the second embodiment, and FIG. 3(B) is a sectional view taken along the line BB in FIG. 3(A). However, FIG. 3A is a plan view in a state before the protective film 10 is formed.

This electronic component 102 includes a semiconductor substrate 1, an insulator layer 2 formed on the semiconductor substrate 1, and conductor layers 3A, 3B, 3C1, 3C2, 3D, and 3E formed on the insulator layer 2. An interlayer connection conductor 6C1 that connects the conductor layer 3C1 and the conductor layer 3D, an interlayer connection conductor 6C2 that connects the conductor layer 3C2 and the conductor layer 3E, and the conductor layer 3A and the conductor layer 3D. an interlayer connection conductor 6A for interlayer connection between the conductor layers 3B and 3E; an interlayer connection conductor 6B for interlayer connection between the conductor layers 3B and 3E;

pad electrodes

9A and 9B formed on the conductor layers 3A and 3B; 1, and a protective film 10 formed on the upper surface side of the device.

The conductor layer 3C1 constitutes a spiral-shaped first conductor layer forming an opening pattern CO1, and the conductor layer 3C2 constitutes a spiral-shaped second conductor layer forming an opening pattern CO2. There is. Further, the conductor layers 3D and 3E constitute a third conductor layer whose pattern is a linear wiring.

In the electronic component 101 shown in FIG. 1B, the conductor layers 3D and 3E are formed on the surface of the semiconductor substrate 1, but in the example shown in FIG. 3B, the conductor layers 3D and 3E are made of insulators. It is formed within the layer of layer 2. That is, the conductor layers 3D and 3E are formed at positions insulated from the semiconductor substrate 1.

As shown in this embodiment, the third conductor layers 3D and 3E may be arranged at a position away from the semiconductor substrate 1. As a result, the eddy current induced in the semiconductor substrate 1 is further suppressed, and the ESR of the inductor can be further reduced. Further, since an inductor with low ESR can be obtained regardless of the doping concentration of the semiconductor substrate 1, various functions can be added using the semiconductor substrate.

《Third embodiment》
In the third embodiment, an electronic component including a passive component other than an inductor will be exemplified.

FIG. 4(A) is a plan view of the electronic component 103 according to the third embodiment, and FIG. 4(B) is a sectional view taken along the line BB in FIG. 4(A). However, FIG. 4A is a plan view in a state before the protective film 10 is formed.

This electronic component 103 includes a semiconductor substrate 1, an insulator layer 2 formed on the semiconductor substrate 1, and conductor layers 3B, 3C1, 3C2, 3D, 3E, 3F, and 3G formed on the insulator layer 2. , a dielectric layer 4 formed on the semiconductor substrate 1, a conductor layer 3K formed on the dielectric layer 4, a dielectric layer 5 formed in the insulator layer 2, and a conductor layer 3G. , 3B, a protective film 10 formed on the upper surface of the semiconductor substrate 1, and a lower surface electrode 8 formed on the lower surface of the semiconductor substrate 1.

The semiconductor substrate 1 is, for example, a carrier-doped silicon substrate, the insulator layer 2 is, for example, a SiN film, the conductor layers 3C1, 3C2, 3D, 3E are, for example, an Al film, and the conductor layers 3B, 3F, 3G are, for example, a Cu film, a dielectric layer. 4 and 5 are SiO ₂ films, for example,

pad electrodes

9A and 9B are metal films with Ni as the base and Au as the surface, protective film 10 is an organic film such as solder resist, and lower electrode 8 is made of Cu or Ni as the base, for example. It is a metal film whose surface is made of Au.

The patterns of the conductor layers 3C1, 3C2, 3D, and 3E constitute an inductor. The conductor layers 3H and 3J constitute capacitor electrodes formed in the insulator layer 2. The conductor layer 3K constitutes a capacitor electrode formed on the dielectric layer 4. The conductor layers 3F, 3G, and 3B constitute extraction electrodes.

Pad electrodes

9A and 9B are used, for example, as pads for wire bonding. The lower surface electrode 8 is used, for example, as an electrode for die bonding.

The patterns of the conductor layers 3C1, 3C2, 3D, and 3E are inductor patterns, and the conductor layers 3C1, 3C2, 3D, and 3E form an inductor region ZL in the semiconductor substrate 1. Further, in the semiconductor substrate 1, the region where the conductor layer 3K and the dielectric layer 4 as capacitor electrodes are formed is a capacitor region ZC. The configuration of the inductor region ZL is similar to the example shown in FIGS. 3(A) and 3(B) in the second embodiment.

A conductor portion 7 is formed in the capacitor region ZC of the semiconductor substrate 1. In this example, the conductor portion 7 is arranged below the dielectric layer 4. That is, the conductor portions 7 are arranged in a higher proportion in the capacitor region ZC of the semiconductor substrate 1 than in the inductor region ZL. The conductor portion 7 is made of conductive polysilicon, for example, and has higher conductivity than the semiconductor substrate 1. The conductor portion 7 is formed by digging a plurality of trenches in the semiconductor substrate 1 and filling the trenches with the conductive polysilicon or the like.

The conductor layer 3K, dielectric layer 4, semiconductor substrate 1, conductor portion 7, and bottom electrode 8 constitute a capacitor. Here, the conductor layer 3K is the first electrode of the capacitor, and the semiconductor substrate 1, the conductor portion 7, and the lower surface electrode 8 are the second electrodes of the capacitor.

As shown above, the conductor portions 7 having higher conductivity than the semiconductor substrate 1 are arranged in the capacitor region ZC in the semiconductor substrate 1 at a higher rate than in the inductor region ZL. As a result, the conductivity of the entire semiconductor substrate 1 is lowered, and the eddy current induced in the semiconductor substrate 1 due to the high frequency magnetic field generated by the inductor pattern by the conductor layers 3A and 3B is suppressed, resulting in an inductor with a high Q value. is obtained. Further, the conductivity of the capacitor electrode in the capacitor region ZC can be increased, and a capacitor with a high Q value can be obtained.

FIG. 5 is a circuit diagram of the electronic component 103. The ports P1 and P2 shown in FIG. 5 correspond to the

pad electrodes

9A and 9B of the electronic component 103 shown in FIGS. 4(A) and 4(B), respectively, and the ground shown in FIG. This corresponds to the lower surface electrode 8 in 4(B). A capacitor C1 shown in FIG. 5 is a capacitor configured by a conductor layer 3K, a dielectric layer 4, a conductor portion 7, a semiconductor substrate 1, and a bottom electrode 8. A capacitor C2 shown in FIG. 5 is a capacitor composed of conductor layers 3H, 3J and a dielectric layer 5. The inductor L1 shown in FIG. 5 is an inductor composed of conductor layers 3C1, 3C2, 3D, and 3E. Such an LC circuit constitutes an impedance matching circuit.

FIG. 6 is a block diagram showing the circuit configuration of the transmitter of the communication device. This transmitting section includes a transmitting circuit that inputs a transmitting signal, modulates it, and outputs a high-frequency transmitting signal, a power amplifier PA, and an impedance matching circuit MC that matches impedance between the transmitting circuit and the power amplifier PA. The output signal of power amplifier PA is guided to an antenna. A communication device including the transmitter shown in FIG. 6 is provided in a base station, for example.

《Fourth embodiment》
The fourth embodiment will exemplify an electronic component in which the configuration of the conductor portion disposed in the inductor region is different from the examples shown in the previous embodiments.

FIG. 7 is a plan view showing the configuration of an inductor region according to the fourth embodiment. However, illustration of the insulator layer and the protective film is omitted.

The conductive layers 3C11 and 3C12 are adjacent to each other in the direction along the surface of the semiconductor substrate, and the conductive layers 3C11 and 3C12 are juxtaposed so as not to overlap each other. The conductor layer 3C11 is electrically connected to the conductor layer 3D1 through the interlayer connection conductor, and the conductor layer 3C12 is electrically connected to the conductor layer 3E1 through the interlayer connection conductor.

Similarly, the conductor layers 3C21 and 3C22 are adjacent to each other in the direction along the surface of the semiconductor substrate, and the conductor layers 3C21 and 3C22 are juxtaposed so as not to overlap each other. The conductor layer 3C21 is electrically connected to the conductor layer 3D2 through the interlayer connection conductor, and the conductor layer 3C22 is electrically connected to the conductor layer 3E2 through the interlayer connection conductor.

In FIG. 7, arrow lines indicate the direction of current flowing through each conductor layer in a certain phase. The direction of the current flowing around the opening pattern CO11 of the conductor layer 3C11 and the direction of the current flowing around the opening pattern CO12 of the conductor layer 3C12 are opposite to each other. Further, the direction of the current flowing around the opening pattern CO21 of the conductor layer 3C21 and the direction of the current flowing around the opening pattern CO22 of the conductor layer 3C22 are opposite to each other. Further, the direction of the current flowing around the opening pattern CO12 of the conductor layer 3C12 and the direction of the current flowing around the opening pattern CO21 of the conductor layer 3C21 are opposite to each other. Furthermore, the direction of the current flowing around the opening pattern CO11 of the conductor layer 3C11 and the direction of the current flowing around the opening pattern CO22 of the conductor layer 3C22 are opposite to each other.

As in this embodiment, an inductor may be configured by having three or more spiral or loop-shaped conductor layers each having an opening pattern and electrically connecting them in series.

《Fifth embodiment》
The fifth embodiment will exemplify an electronic component in which the configuration of the conductor portion disposed in the inductor region is different from the examples shown in the previous embodiments.

FIG. 8 is a plan view showing the configuration of an inductor region according to the fifth embodiment. However, illustration of the insulator layer and the protective film is omitted.

The conductor layer 3D1 and the conductor layer 3D2 are electrically connected, and the conductor layer 3E1 and the conductor layer 3E2 are electrically connected.

In FIG. 8, arrow lines indicate the direction of current flowing through each conductor layer in a certain phase. The direction of the current flowing around the opening pattern CO11 of the conductor layer 3C11 and the direction of the current flowing around the opening pattern CO12 of the conductor layer 3C12 are opposite to each other. Further, the direction of the current flowing around the opening pattern CO21 of the conductor layer 3C21 and the direction of the current flowing around the opening pattern CO22 of the conductor layer 3C22 are opposite to each other. Further, the direction of the current flowing around the opening pattern CO12 of the conductor layer 3C12 and the direction of the current flowing around the opening pattern CO22 of the conductor layer 3C22 are opposite to each other. Furthermore, the direction of the current flowing around the opening pattern CO11 of the conductor layer 3C11 and the direction of the current flowing around the opening pattern CO21 of the conductor layer 3C21 are opposite to each other.

By arranging and connecting the coils in parallel as shown in FIG. 8, it is possible to maintain low ESR while magnetically coupling multiple inductors, thereby increasing the allowable current amount.

As in this embodiment, an inductor may be constructed by including three or more spiral or loop-shaped conductor layers each having an opening pattern and electrically connecting them in parallel.

Finally, the present invention is not limited to the embodiments described above. Appropriate modifications and changes can be made by those skilled in the art. The scope of the invention is indicated by the claims rather than the embodiments described above. Furthermore, the scope of the present invention includes modifications and changes from the embodiments within the scope of the claims and equivalents.

For example, in each of the embodiments described above, the conductor layer having an opening pattern is formed in a spiral shape or a loop shape with more than one turn but less than two turns, but the present invention is not limited to this. do not have. The conductor layer having an opening pattern may be formed in a spiral shape having more than two turns.

Further, in each of the embodiments described above, the first conductor layer and the second conductor layer are formed in the same layer in the insulator layer, but the first conductor layer and the second conductor layer are formed in different layers. It may be formed into layers. Furthermore, in each of the embodiments described above, an example was shown in which the third conductor layer that is electrically connected to the first conductor layer or the second conductor layer is formed in the same layer. The third conductor layer and the third conductor layer electrically connected to the second conductor layer may be formed in different layers. For example, the conductive layer 3C1 and the conductive layer 3C2 shown in FIGS. 1(A) and 1(B) may be formed in different layers in the insulating layer 2, and the

conductive layers

3D and 3E may They may be formed in different layers in the insulator layer 2.

Further, although each embodiment shows an electronic component including a capacitor and an inductor as a passive component, the present invention can be similarly applied to an electronic component including an active component as well as a passive component.

Furthermore, in each of the embodiments described above, an example is shown in which the inductor is provided with a spiral or loop-shaped conductor layer having an opening pattern, but it is possible to The present invention is applicable when configuring an element having a structure in which the generated magnetic fields do not cancel each other out. Therefore, for example, a resistive element may be configured with a spiral or loop-shaped conductor layer having an opening pattern.

C1, C2... Capacitor CO, CO1, CO11, CO12, CO2, CO21, CO22... Opening pattern L1... Inductor MC... Impedance matching circuit P1, P2... Port PA... Power amplifier ZC... Capacitor region ZL... Inductor region 1... Semiconductor substrate 2...

Insulator layer

3A, 3B, 3F, 3G, 3H, 3J, 3K...Conductor layer 3C1, 3C11, 3C12...Conductor layer 3C2, 3C21, 3C22...Conductor layer 3D, 3D1, 3D2...Conductor layer 3E , 3E1, 3E2... Conductor layer 4, 5...

Dielectric layer

6A, 6B, 6C1, 6C2... Interlayer connection conductor 7... Conductor portion 8...

Bottom electrode

9A, 9B... Pad electrode 10...

Protective film

101, 102, 103... electronic components

Claims

a semiconductor substrate;
a plurality of insulator layers formed on the semiconductor substrate;
a plurality of conductor layers insulated by the insulator layer;
an interlayer connection conductor that connects different conductor layers among the plurality of conductor layers;
Equipped with
The plurality of conductor layers include a spiral or loop-shaped first conductor layer having an opening pattern, a spiral or loop-shaped second conductor layer having an opening pattern, and a third conductor layer. ,
The first conductor layer and the second conductor layer are adjacent to each other in a direction along the surface of the semiconductor substrate,
the first conductor layer and the second conductor layer are juxtaposed so as not to overlap each other,
The third conductor layer is electrically connected to the first conductor layer or the second conductor layer via the interlayer connection conductor,
When current is applied to the first conductor layer and the second conductor layer, the direction of current flowing around the opening pattern of the first conductor layer and the direction of current flowing around the opening pattern of the second conductor layer The direction of current is opposite to each other,
electronic components.
The first conductor layer, the second conductor layer, and the third conductor layer are connected in series,
The electronic component according to claim 1.
The first conductor layer and the second conductor layer are located farther from the semiconductor substrate than the third conductor layer.
The electronic component according to claim 1 or 2.
A current swirling in at least a portion of the third conductor layer in the same direction as a swirling direction of the current flowing through the first conductor layer or the second conductor layer with respect to the opening pattern flows.
The electronic component according to any one of claims 1 to 3.
There are a plurality of third conductor layers, and the third conductor layer includes a conductor layer connected to the first conductor layer via the interlayer connection conductor and a conductor layer connected to the second conductor layer via the interlayer connection conductor. a connecting conductor connected to the conductive layer;
The electronic component according to any one of claims 1 to 3.
The semiconductor substrate is a substrate made of an impurity semiconductor,
The first conductor layer and the second conductor layer are disposed on a first insulator layer among the plurality of insulator layers, and the first conductor layer and the second conductor layer are disposed on a first insulator layer among the plurality of insulator layers, and the first conductor layer and the second conductor layer are disposed on a first insulator layer among the plurality of insulator layers, and a third conductor layer is disposed;
The electronic component according to any one of claims 1 to 5.
comprising a dielectric layer formed on the semiconductor substrate and a capacitor electrode formed on the dielectric layer,
A capacitor is configured by the capacitor electrode, the dielectric layer, and the semiconductor substrate.
The electronic component according to any one of claims 1 to 6.
a lower surface electrode is formed on the lower surface of the semiconductor substrate;
The electronic component according to claim 7.