WO2023173985A1 - 一种电源检测复位电路、集成电路及电子设备 - Google Patents

一种电源检测复位电路、集成电路及电子设备 Download PDF

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Publication number
WO2023173985A1
WO2023173985A1 PCT/CN2023/076125 CN2023076125W WO2023173985A1 WO 2023173985 A1 WO2023173985 A1 WO 2023173985A1 CN 2023076125 W CN2023076125 W CN 2023076125W WO 2023173985 A1 WO2023173985 A1 WO 2023173985A1
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WIPO (PCT)
Prior art keywords
module
reset
power supply
control signal
power
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Application number
PCT/CN2023/076125
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English (en)
French (fr)
Inventor
叶学锋
刘帅锋
Original Assignee
合肥市芯海电子科技有限公司
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Publication of WO2023173985A1 publication Critical patent/WO2023173985A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Definitions

  • the present application relates to the field of electronic circuit technology, and in particular to a power detection reset circuit, integrated circuits and electronic equipment.
  • the power-on reset module is a relatively important module.
  • the analog module inside the chip may not work properly and stably, and the digital circuit may not operate normally, causing the system to crash.
  • the power-on reset module can transmit a reset signal to each module when the power supply voltage is lower than the voltage required for normal operation of the system. After the power supply reaches the expected value, the reset is performed. At the same time, when the power supply voltage drops to the system's minimum stable operating voltage, the power-on reset module will also generate a reset signal to turn off the relevant module enable bits.
  • power domain systems are divided into single power supply systems and multi-power supply systems.
  • the power-on reset module does not need to be designed very complicatedly. Most of them only need one self-detection module to meet the system requirements.
  • the power supply sequence needs to be fixed, which is restricted when users use it and affects the user experience.
  • this application provides a power detection reset circuit, integrated circuit and electronic device, which solves the problem of users being restricted by usage scenarios due to the need to limit the power-on sequence when multiple power supplies are powered on.
  • This application provides a power detection reset circuit, including
  • a first detection module configured to detect a first power supply voltage and a second power supply voltage, and output a first reset control signal based on the first power supply voltage and the second power supply voltage;
  • a second detection module configured to detect the first power supply voltage and output a second reset control signal based on the first power supply voltage
  • the processing module is configured to perform operations on the first reset control signal and the second reset control signal to obtain a target reset control signal, where the target reset control signal is used to control circuit reset.
  • the first detection module is specifically configured to:
  • the first reset control signal output by the first detection module follows the first supply voltage, the first The reset control signal is at the first level; when the second power supply voltage reaches the threshold preset by the first detection module, the first reset control signal output by the first detection module is at the second level.
  • the second detection module is specifically configured to:
  • the second reset control signal follows the first power supply voltage, and the second reset control signal is a third level; when The first power supply voltage reaches the threshold preset by the second detection module, and the second reset control signal is a fourth level.
  • the power detection reset circuit further includes a first logic control unit, the input terminal of the first logic control unit is used to receive a first input signal and a second input signal, wherein the second input The signal is the first reset control signal; the first logic control unit is configured as:
  • the first logic control unit When the first input signal is set to low level, the first logic control unit outputs high level to control the operation of the second detection module, and the second detection module is normally open;
  • the first logic control unit When the first input signal is set to a high level, the first logic control unit is controlled by the first reset signal and outputs a signal capable of controlling the operation of the second detection module; when the second power supply voltage When the threshold value preset by the first detection module is not reached, the second detection module is turned on. When the second power supply voltage reaches the threshold value preset by the first detection module, the second detection module is turned off.
  • the power detection reset circuit further includes:
  • a voltage monitoring unit configured to monitor whether the first reset control signal and the second reset control signal follow the first power supply voltage before the first power supply and the second power supply are powered on; if the first reset control signal If the reset control signal and the second reset control signal do not follow the first power supply voltage, the voltage monitoring unit generates the first power supply voltage following signal and transmits it to the processing module.
  • the power detection reset circuit further includes:
  • the second logic control unit is configured to perform level conversion on the target reset control signal and output a second target reset control signal, where the second target reset control signal is used to control circuit reset.
  • the power detection reset circuit further includes:
  • a delay unit configured to delay transmission of the target reset control signal output by the processing module to the second logic control unit.
  • the power detection reset circuit further includes:
  • the battery power detection module is configured to detect a third power supply voltage, output a third reset control signal based on the third power supply voltage, and transmit the third reset control signal to the second logic control unit for level conversion.
  • the battery power detection module is further configured to:
  • the third reset control signal is used to control circuit reset.
  • the power detection reset circuit further includes:
  • the programmable voltage detection module performs programmatic control on the power-down threshold of the first detection module.
  • the programmable voltage detection module is integrated with the first detection module.
  • the first detection module includes a first power interface, a second power interface, a first resistor string, a first circuit connection control module, a first comparison module and a first capacitor.
  • the interface is used to connect the first power supply
  • the second power supply interface is used to connect the second power supply
  • the first resistor string is connected to the first power supply interface and the second power supply interface
  • the first circuit connection control module is connected to all
  • the first resistor string, the first comparison module is connected to the first circuit connection control module, and the first capacitor is connected between the first circuit connection control module and the first comparison module;
  • a comparison module outputs the first reset control signal.
  • the second detection module includes a second resistor string, a second circuit connection control module, a second comparison module and a second capacitor, and the second resistor string is connected to the first comparison module, so The second circuit connection control module is connected to the second resistor string, the second comparison module is connected to the second circuit connection control module, and the second capacitor is connected to the second circuit connection control module and the second circuit connection control module. Between the two comparison modules, the second comparison module outputs the second reset control signal.
  • the programmable voltage detection module includes a third resistor string, a threshold level selection module, a third comparison module and a third capacitor
  • the third resistor string is connected to the first resistor string
  • the The threshold level selection module is connected to the third resistor string
  • the third comparison module is connected to the threshold level selection module
  • the third capacitor is connected between the threshold level selection module and the third comparison module, so The third comparison module outputs a programming control signal for the power-down threshold of the first detection module.
  • the second logic control unit includes: a first logic NOT gate module, a level conversion module, an anti-leakage module, and a second logic NOT gate module;
  • the first logic NOT gate module is connected to the delay unit, the level conversion module is connected to the first logic NOT gate module, the leakage prevention module is connected to the level conversion module, and the third level conversion module is connected to the first logic NOT gate module.
  • Two logic NOT gate modules are connected to the anti-leakage module, and the second logic NOT gate module outputs a second target reset control signal and a third target reset control signal.
  • This application provides an integrated circuit, including the above-mentioned power detection reset circuit.
  • This application provides an electronic device, including a device body and an integrated circuit as described above provided in the device body.
  • the power detection reset circuit, integrated circuit and electronic equipment provided by this application can be implemented in a multi-power domain system, and users can flexibly configure them according to actual application requirements, thus supporting the multi-power domain system to be powered on in any order.
  • the first logic control unit can control the second detection module to turn on or off, thereby reducing system power consumption.
  • the programmable voltage detection module circuit supports programmable control of the power-down threshold of the first detection module.
  • Figure 1 is a block diagram of a power detection reset circuit provided by the first embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a power detection reset circuit provided by the first embodiment of the present application.
  • Figure 3 is a circuit schematic diagram of the first detection module in Figure 1;
  • Figure 4 is a circuit schematic diagram of the second detection module in Figure 1;
  • Figure 5 is a block diagram of a power detection reset circuit provided by the second embodiment of the present application.
  • Figure 6 is a schematic structural diagram of a power detection reset circuit provided by the second embodiment of the present application.
  • Figure 7 is a schematic diagram of the logic functions of the first logic control unit in Figure 5;
  • Figure 8 is a block diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 9 is a schematic structural diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 10 is a logical functional schematic diagram of the voltage monitoring unit in Figure 8.
  • Figure 11 is a block diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 13 is a circuit schematic diagram of the second logic control unit in Figure 11;
  • Figure 14 is a block diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 15 is a schematic structural diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 16 is a block diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 17 is a schematic structural diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 18 is a block diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 19 is a schematic structural diagram of a power detection reset circuit provided by an embodiment of the present application.
  • Figure 20 is a circuit schematic diagram of the programmable voltage detection module PVD and the first detection module POR integrated together;
  • Figure 21 is a schematic diagram of the first power supply AVDD powering on and resetting first
  • Figure 22 is a schematic diagram of the second power supply voltage DVDD powering on and resetting first
  • Figure 23 is a schematic diagram of an integrated circuit provided by an embodiment of the present application.
  • Figure 24 is a schematic diagram of an electronic device provided by an embodiment of the present application.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • FIG. 1 A block diagram of a power detection reset circuit provided by the first embodiment of the present application is shown in Figure 1.
  • a schematic structural diagram of a power detection reset circuit provided by the first embodiment is shown in Figure 2.
  • the power detection reset circuit includes :
  • the first detection module POR is configured to detect the first power supply voltage AVDD and the second power supply voltage DVDD, and output the first reset control signal por_rstf based on the first power supply voltage AVDD and the second power supply voltage DVDD;
  • a circuit schematic diagram of the first detection module POR is shown in Figure 3, including a first power interface, a second power interface, a first resistor string, a first circuit connection control module, and a first comparison module. and a first capacitor, wherein the first power interface is used to receive the first power supply voltage AVDD, the second power interface is used to receive the second power supply voltage DVDD, and the first resistor string includes a first resistor R11, a second resistor R12, a third resistor R13, the first circuit connection control module includes a switch S11 and a switch S12. One end of the first resistor R11 is used to receive the second power supply voltage DVDD.
  • the other end of the first resistor R11 is grounded through the second resistor R12 and the third resistor R13 connected in series.
  • One end of the switch S11 is connected between the first resistor R11 and the second resistor R12, and one end is connected to the first input terminal of the first comparison module.
  • One end of the switch S12 is connected between the second resistor R12 and the third resistor R13, and one end is connected to the first input terminal of the first comparison module.
  • a first input terminal of a comparison module is used to receive the first reference voltage VBG1
  • the first comparison module is used to detect the voltage at the connection node of the first resistor R11 and the second resistor R12 and It is compared with the first reference voltage VBG1, or the voltage at the connection node of the second resistor R12 and the third resistor R13 is detected and compared with the first reference voltage VBG1.
  • the voltage of the first input terminal of the first comparison module rises with the second power supply voltage DVDD,
  • the first reset control signal por_rstf output by the first comparison module may be flipped, for example, from the first level to the second level.
  • One end of the first capacitor is connected between the switch S11, the switch S12 and the first comparison module, and the other end of the first capacitor is connected to ground.
  • the first comparison module is also connected to the first power supply to use the first power supply voltage AVDD as the supply voltage.
  • the number of resistors in the first resistor string can be increased or decreased, and accordingly the number of switches in the first circuit connection control module can also be increased or decreased.
  • the connection node between each two adjacent resistors in the first resistor string may be connected to the first input terminal of the first comparison module through a switch respectively.
  • the connection relationship between the components may be direct connection or indirect connection.
  • one end of the first resistor string can be directly connected to the second power interface or indirectly connected to the second power interface through other components.
  • the other end of the first resistor string can also be directly connected to the ground or indirectly connected to the ground through other components. .
  • the second detection module PDR is configured to detect the first power supply voltage AVDD and output a second reset control signal pdr_rstf based on the first power supply voltage AVDD.
  • a circuit schematic diagram of the second detection module PDR is shown in Figure 4, including a second resistor string, a second circuit connection control module, a second comparison module and a second capacitor, where the The two resistor strings include a fourth resistor R21, a fifth resistor R22, and a sixth resistor R23.
  • the second circuit connection control module includes a switch S21 and a switch S22.
  • One end of the fourth resistor R21 is used to receive the first power supply voltage AVDD, the fifth resistor R22 is connected to the fourth resistor R21, the sixth resistor R23 is connected to the fifth resistor R22, and the fifth resistor R23 is connected to the fifth resistor R22.
  • Six resistors R23 are grounded, one end of the switch S21 is connected between the fourth resistor R21 and the fifth resistor R22, one end is connected to the first input end of the second comparison module, and one end of the switch S22 is connected to the first input end of the second comparison module.
  • the second input terminal of the second comparison module is used to receive the second reference voltage VBG2, and the second comparison module is used to detect The voltage at the connection node of the fourth resistor R21 and the fifth resistor R22 is compared with the second reference voltage VBG2, or the voltage at the connection node of the fifth resistor R22 and the sixth resistor R23 is detected and compared with the second reference voltage VBG2.
  • Reference voltage VBG2 is used for comparison.
  • the voltage of the first input terminal of the second comparison module rises with the first power supply voltage AVDD.
  • the second comparison module When the voltage of the first input terminal of the second comparison module is greater than or equal to the second reference voltage, the second comparison module
  • the second reset control signal por_rstf output by the module may be flipped, for example, from the third level to the fourth level.
  • One end of the first capacitor is connected between the switch S21, the switch S22 and the second comparator, and the other end of the second capacitor is connected to ground.
  • the number of resistors in the second resistor string can be increased or decreased, and accordingly the number of switches in the second circuit connection control module can also be increased or decreased.
  • the connection node between each two adjacent resistors in the second resistor string can be connected to the first input terminal of the second comparison module through a switch respectively.
  • connection relationship between the components may be direct connection or indirect connection.
  • one end of the second resistor string can be directly connected to the first power interface or indirectly connected to the first power interface through other components.
  • the other end of the second resistor string can also be directly connected to the ground or indirectly connected to the ground through other components. .
  • a processing module configured to perform operations on the first reset control signal por_rstf and the second reset control signal pdr_rstf to obtain a target reset control signal power_rstf, the target reset control signal power_rstf Used to control circuit reset.
  • the first reset control signal por_rstf and the second reset control signal pdr_rstf are NAND-processed, and then the NAND-processed signal is NAND-processed to obtain the target reset signal power_rstf of the control circuit.
  • the first detection module POR is configured to: when the first power supply and the second power supply are powered on, when the second power supply voltage does not reach the threshold preset by the first detection module, the first detection module outputs the third A reset control signal follows the first power supply voltage, and the first reset control signal is the first level; when the second power supply voltage reaches the threshold preset by the first detection module, the first reset control signal output by the first detection module is the second level. level. Specifically, taking the first level as a low level and the second level as a high level as an example, with reference to Figure 3, when the first power supply and the second power supply are powered on, the switch S11 is open and the switch S12 is closed.
  • the first input terminal voltage of the comparator COM0 in the first comparison module is less than the first reference voltage VBG1, and the first detection module
  • the first reset control signal por_rstf output by POR follows the voltage of the first power supply AVDD.
  • the first reset control signal por_rstf is high level and the circuit is in a power-on reset state; when the voltage of the second power supply DVDD reaches the required
  • the threshold value preset by the first detection module POR is set, that is, when the first input terminal voltage of the comparator COM0 reaches the first reference voltage VBG1, the first reset control signal por_rstf output by the comparator COM0 flips to low level, and the power-on reset is performed.
  • the circuit begins to enter the working state.
  • the control switch S11 is closed and the switch S12 is opened, so that the voltage of the first input terminal of the comparator COM0 remains greater than the first reference voltage VBG1, thereby maintaining the circuit in a normal operating state.
  • the second detection module PDR is configured to: when the first power supply voltage does not reach the threshold preset by the second detection module, the second reset control signal follows the first power supply voltage, and the second reset control signal is the first power supply voltage. Three levels; when the first power supply voltage reaches the threshold preset by the second detection module, the second reset control signal is the fourth level. Specifically, taking the third level as a high level and the fourth level as a low level as an example, with reference to Figure 4, when the first power supply is powered on, the switch S21 is turned off and the switch S22 is turned on.
  • the first input terminal voltage of the comparator COM1 in the second comparison module is less than the second reference voltage VBG2, and the second reset control signal pdr_rstf follows the The first power supply voltage AVDD, the second reset control signal pdr_rstf is high level, and the circuit is in a power-on reset state; when the voltage of the first power supply AVDD reaches the preset threshold of the second detection module PDR, that is, When the voltage of the first input terminal of the comparator COM1 reaches the second reference voltage VBG2, the second reset control signal pdr_rstf output by the comparator COM1 flips to low level, the power-on reset is released, and the circuit begins to enter the working state.
  • the control switch S21 is closed and the switch S22 is opened, so that the voltage of the first input terminal of the comparator COM1 remains greater than the second reference voltage VBG2, thereby maintaining the circuit in a normal
  • the first power supply AVDD is powered on first and the second power supply DVDD is powered on later, or the first power supply AVDD and the second power supply DVDD are powered on at the same time, then the first power supply AVDD is powered on until the second power supply DVDD is powered on.
  • the second reset control signal pdr_rstf follows the first power supply AVDD and outputs a low level after reaching the threshold; when the second power supply DVDD is powered on to the first Detection module POR reset release threshold
  • the first reset control signal por_rstf follows the first power supply AVDD, and outputs a low level after reaching the threshold value.
  • the first reset control signal por_rstf and the second reset control signal pdr_rstf are OR logically processed to generate a target reset control signal power_rstf that controls circuit reset.
  • the target reset control signal power_rstf is used to reset the circuits of the AVDD power domain and DVDD power domain.
  • the first reset control signal por_rstf will always remain at a low level.
  • the second reset control signal pdr_rstf follows the first power supply AVDD.
  • the second reset control signal pdr_rstf outputs a low level.
  • the first reset control signal por_rstf and the second reset control signal pdr_rstf are OR logically processed to generate a target reset control signal power_rstf that controls circuit reset.
  • the target reset control signal power_rstf is used to reset the circuit.
  • the embodiment of the present application can support the first power supply and the second power supply to be powered on in any order.
  • Figure 5 is a block diagram of a power detection reset circuit
  • Figure 6 is a schematic structural diagram of a power detection reset circuit corresponding to Figure 5.
  • the power detection reset circuit also It includes a first logic control unit Logic1, and the input end of the first logic control unit Logic1 is used to receive a first input signal pdr_enb and a second input signal, wherein the second input signal is the first reset control signal por_rstf. ;Configured to control the second detection module PDR to turn on or off, including:
  • the first logic control unit Logic1 When the first input signal pdr_enb is set to low level, the first logic control unit Logic1 outputs a high level to control the operation of the second detection module PDR, and the second detection module is normally open;
  • the first logic control unit Logic1 When the first input signal pdr_enb is set to high level, the first logic control unit Logic1 outputs a signal for controlling the operation of the second detection module PDR according to the first reset signal por_rstf; when the second power supply voltage When DVDD does not reach the preset threshold of the first detection module POR, the second detection module PDR is turned on. When the voltage of the second power supply DVDD reaches the preset threshold of the first detection module POR, the second detection module PDR is turned off. The second detection module PDR.
  • FIG. 7 is a schematic diagram of the logic function of the first logic control unit Logic1, if the first power supply AVDD is powered on first and the second power supply DVDD is powered on later, or the first power supply AVDD and the second power supply DVDD When powered on at the same time, the first input signal pdr_enb of the first logic control unit Logic1 is set to high level, and the signal pdr_en of the second detection module PDR is controlled to follow the first reset control signal por_rstf.
  • the second detection module PDR is turned on.
  • the second power supply voltage DVDD reaches the preset threshold of the first detection module POR, , close the second detection module PDR to reduce power consumption.
  • the first input signal pdr_enb of the first logic control unit Logic1 is set to low level to control the second detection
  • the signal pdr_en of the module PDR is high level, and the second detection module PDR is in a normally open state.
  • Figure 8 is a block diagram of a power detection reset circuit
  • Figure 9 is a schematic structural diagram of a power detection reset circuit.
  • the power detection reset circuit also includes:
  • the voltage monitoring unit Monitor is configured to monitor whether the first reset control signal por_rstf and the second reset control signal pdr_rstf follow the first power supply voltage AVDD before the first power supply AVDD and the second power supply DVDD are powered on. ; If the first reset control signal por_rstf and the second reset control signal pdr_rstf do not follow the first power supply voltage AVDD, the voltage monitoring unit Monitor generates a first power supply voltage following signal avdd_monitor and transmits it to the processing module.
  • the first reset control signal por_rstf and the second reset control signal pdr_rstf may be processed by a NAND gate first, and then processed by a NOT gate.
  • Figure 10 shows a schematic diagram of the logic function of the voltage monitoring unit Monitor.
  • the voltage monitoring unit Monitor is used to monitor whether the first reset control signal por_rstf and the second reset control signal pdr_rstf follow the first power supply voltage AVDD. ;
  • the first detection module POR and the second detection PDR are reset and released, that is, before t1 in Figure 10, the first detection module POR and the The output signal of the second detection PDR should theoretically follow the first power supply voltage AVDD.
  • the system may undergo three processes of reset release ⁇ reset ⁇ reset release; when the first power supply AVDD and the second power supply AVDD Before power supply DVDD is powered on, if the voltage monitoring unit Monitor detects that the first reset control signal por_rstf and the second reset control signal pdr_rstf do not follow the voltage of the first power supply AVDD; then the voltage monitoring unit The Monitor will output the first power supply voltage AVDD following signal avdd_monitor that almost completely follows the first power supply voltage AVDD, thus avoiding the possible three processes of reset release ⁇ reset ⁇ reset release in the system.
  • Figure 11 is a block diagram of a power detection reset circuit
  • Figure 12 is a schematic structural diagram of a power detection reset circuit.
  • the power detection reset circuit also includes:
  • the second logic control unit Logic2 is configured to perform level conversion on the target reset control signal power_rstf and output the second target reset control signal dvdd_rstf.
  • the second target reset control signal dvdd_rstf is used to switch between the AVDD power domain and the DVDD power domain. circuit for reset control.
  • the preferred second logic control unit Logic2 includes: a first logic NOT gate module, a level conversion module, an anti-leakage module, and a second logic NOT gate module.
  • the first logic NOT gate module includes a first logic NOT gate 1, a second logic NOT gate 2, a third logic NOT gate 3, and a fourth logic NOT gate 4;
  • the anti-leakage module includes an NMOS transistor M1 , M2, M4, M5, M8, M9, M13, M14, M15; PMOS tubes M3, M6, M7, M11, M12, M16;
  • the second logic NOT gate module includes a fifth logic NOT gate 5, a sixth logic NOT gate 6.
  • the input terminal of the first logical NOT gate 1 is the target reset signal power_rstf, and the output terminal is connected to the second Logic NOT gate 2, the gate of the NMOS transistor M1, the gate of the NMOS transistor M4 and the gate of the PMOS transistor M7;
  • the output end of the second logic NOT gate 2 is connected to the first level conversion module 7;
  • the output end of the first level conversion module 7 is connected to the gate of the NMOS transistor M2 and the gate of the PMOS transistor M3;
  • the source level of the NMOS transistor M1 and the source level of the NMOS transistor M4 are grounded; the drain of the PMOS transistor M7 is connected to the input end of the fifth logic NOT gate 5;
  • the drain of the NMOS transistor M2 and the drain of the PMOS transistor M3 are connected to the gate of the PMOS transistor M6 and the gate of the NMOS transistor M5;
  • the source of the NMOS transistor M2 is connected to the drain of the NMOS transistor M1;
  • the drain of the NMOS transistor M5 and the drain of the PMOS transistor M6 are connected to the fifth logic NOT gate 5;
  • the source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M4;
  • the source level of the PMOS transistor M3, the source level of the PMOS transistor M6, and the source level of the PMOS transistor M7 are connected to each other;
  • the output terminal of the fifth logic NOT gate 5 is the second target reset control signal avdd_rstf;
  • the input terminal of the third logical NOT gate 3 is the target reset signal power_rstf, and the output terminal is connected to the fourth logical NOT gate 4, the gate of the NMOS transistor M8, the gate of the NMOS transistor M15 and the gate of the NMOS transistor M15.
  • the output end of the fourth logic NOT gate 4 is connected to the second level conversion module 8;
  • the output terminal of the second level conversion module 8 is connected to the gate of the NMOS tube M9 and the gate of the PMOS tube M10;
  • the source level of the NMOS transistor M8 and the source level of the NMOS transistor M15 are grounded;
  • the source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M8;
  • the drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M10;
  • the drain of the NMOS transistor M9 and the drain of the PMOS transistor M10 are connected to the gate of the PMOS transistor M11 and the gate of the NMOS transistor M14;
  • the drain of the PMOS transistor M11 is connected to the input terminal of the sixth logic NOT gate 6;
  • the source of the NMOS transistor M14 is connected to the drain of the NMOS transistor M15;
  • the drain of the PMOS transistor M16 is connected to the input terminal of the sixth logic NOT gate 6;
  • the source of the NMOS transistor M13 is connected to the drain of the NMOS transistor M14;
  • the input terminals of the PMOS tube M12 and the NMOS tube M13 are both the third reset control signal
  • the drain of the PMOS transistor M12 is connected to the drain of the NMOS transistor M13;
  • the source level of the PMOS transistor M10, the source level of the PMOS transistor M11, the source level of the PMOS transistor M12 and the source level of the PMOS transistor M16 are connected to each other;
  • the sixth logical NOT gate 6 outputs a third target reset control signal.
  • the first input of the first logic control unit Logic1 The signal pdr_enb is set to high level, then before the target reset signal power_rstf is reset and released, the signal S1 output by the first logical NOT gate 1 is low level, and the signal S3 output by the third logical NOT gate 3 is Low level controls NMOS transistors M1, M4, M8, and M15 to close and weak pull-up PMOS transistors M7 and M16 to conduct, and the second target reset control signal dvdd_rstf remains at low level. Then, after the target reset signal power_rstf is reset and released, the second target reset control signal dvdd_rstf follows the voltage of the second power supply DVDD.
  • the first power supply AVDD is powered on.
  • the signal S1 output by the first logical NOT gate 1, the signal S2 output by the second logical NOT gate 2, the signal S3 output by the third logical NOT gate 3, and the signal S4 output by the fourth logical NOT gate 4 are all low level, control the NMOS transistors M1, M4, M8, and M15 to close and the weak pull-up PMOS transistors M7 and M16 to conduct, so as to avoid the failure of the first level conversion module 7 and the second level conversion module.
  • the floating output of 8 causes the second logic control unit Logic2 to have a large leakage current, and the second target reset control signal dvdd_rstf remains at a low level. Then when the target reset signal power_rstf is reset and released, the signal S1 output by the first logical NOT gate 1 and the signal S3 output by the third logical NOT gate 3 are pulled up to high level, controlling the NMOS tubes M1, M4, M8 and M15 are turned on, and the output of the second target reset control signal dvdd_rstf is high level.
  • Figure 14 is a block diagram of a power detection reset circuit
  • Figure 15 is a schematic structural diagram of a power detection reset circuit.
  • the power detection reset circuit also includes:
  • the delay unit Delay is configured to delay the target reset control signal power_rstf of the processing module and transmit the delayed target reset control signal por_delay to the second logic control unit Logic2.
  • the delay unit Delay can ensure that when the target reset control signal power_rstf is transmitted to each module of the system, the power supply voltage has reached a relatively high level and can operate normally.
  • the delay time of the delay unit may be several ms. As an example, the delay time can be 3ms.
  • FIG 16 is a block diagram of a power detection reset circuit
  • Figure 17 is a schematic structural diagram of a power detection reset circuit
  • the power detection reset circuit also includes:
  • the battery power detection module VBAT_POR is configured to detect the third power supply VBAT voltage, output a third reset control signal vbat_rstn based on the third power supply VBAT voltage, and transmit the third reset control signal vbat_rstn to the second logic control unit Logic2 performs level conversion, and the third reset control signal after level conversion is vbat_rstf, which is used to control the circuit of the VBAT power domain.
  • Outputting the third reset control signal vbat_rstn based on the third power supply VBAT voltage includes:
  • the third reset control signal vbat_rstn is high level and the power-on reset is released;
  • the third reset control signal vbat_rstn is low level, indicating a power-on reset.
  • the third reset control signal vbat_rstn is input to the gates of the PMOS transistor M12 and the NMOS transistor M13, and the sixth logic NOT gate outputs a third target reset control signal vbat_rstf.
  • the first input of the first logic control unit Logic1 The signal pdr_enb is set to a high level.
  • the third power supply VBAT is powered on before the second power supply DVDD, then before the target reset signal power_rstf is reset and released, the PMOS transistor M12 is turned on, and the PMOS transistors M11,
  • the signal L4 output by M16 follows the third power supply VBAT voltage, and the third target reset control signal vbat_rstf remains low level.
  • the NMOS transistors M8 and M15 are turned on, and the third target reset control signal vbat_rstf is pulled up to a high level;
  • the NMOS tubes M8 and M15 are turned on before the third reset control signal vbat_rstn is reset and released, and the second level conversion module 8 outputs a low level, so
  • the signal L3 output by the NMOS transistor M9 and the PMOS transistor M10 is pulled up to a high level, the NMOS transistor M14 is turned on, and the third reset control signal vbat_rstn output by the battery power detection module VBAT_POR can be directly transmitted.
  • the first input signal pdr_enb of the first logic control unit Logic1 is set to low level.
  • the third power supply VBAT is on
  • the second power supply DVDD is powered on before, then before the target reset signal power_rstf is reset and released, the PMOS transistor M12 is turned on, and the signal L4 output by the PMOS transistors M11 and M16 follows the voltage of the third power supply VBAT.
  • the three-target reset control signal vbat_rstf remains low.
  • the NMOS transistors M8 and M15 are turned on, and the third target reset control signal vbat_rstf is pulled up to a high level;
  • the NMOS tubes M8 and M15 are turned on before the third reset control signal vbat_rstn is reset and released, and the second level conversion module 8 outputs a low level, so
  • the signal L3 output by the NMOS transistor M9 and the PMOS transistor M10 is pulled up to a high level, the NMOS transistor M14 is turned on, and the third reset control signal vbat_rstn output by the battery power detection module VBAT_POR can be directly transmitted.
  • Figure 18 is a block diagram of a power detection reset circuit
  • Figure 19 is a schematic structural diagram of a power detection reset circuit.
  • the power detection reset circuit also includes:
  • Programmable voltage detection module PVD the programmable voltage detection module PVD performs programmatic control on the power-down threshold of the first detection module POR.
  • the programmable voltage detection module PVD and the first detection module POR are integrated together.
  • Figure 20 shows a schematic circuit diagram of the programmable voltage detection module PVD and the first detection module POR integrated together.
  • the programmable voltage detection module PVD includes a third resistor string, a threshold level selection module, and a third comparison module. block and a third capacitor, the third resistor string is connected to the first resistor string, the threshold level selection module is connected to the third resistor string, the third comparison module is connected to the threshold level selection module, the A third capacitor is connected between the threshold level selection module and the third comparison module, and the third comparison module outputs a programming control signal for the power-down threshold of the first detection module.
  • the third resistor string includes a plurality of resistors connected in series, and the connection node between each two adjacent resistors is a voltage dividing node, that is, the third resistor string includes one or more voltage dividing nodes.
  • the threshold level selection module is selected as a selector, and the selector is connected to different voltage dividing nodes of the third resistor string to select the corresponding threshold. The user can select a threshold as the power-down of the first detection module according to actual needs. threshold.
  • Figure 21 shows a schematic logic diagram of the first power supply AVDD powering on and resetting first
  • Figure 22 shows a schematic logic diagram of the second power supply voltage DVDD powering on and resetting first.
  • an embodiment of the present application also provides a schematic diagram of an integrated circuit 200 , which includes the above-mentioned power detection reset circuit 100 .
  • the integrated circuit provided by the embodiment of the present application includes a first detection module POR configured to detect a first power supply voltage AVDD and a second power supply voltage DVDD, and output a third power supply voltage based on the first power supply voltage AVDD and the second power supply voltage DVDD.
  • a reset control signal por_rstf a reset control signal por_rstf
  • a second detection module PDR configured to detect the first power supply voltage and output a second reset control signal pdr_rstf based on the first power supply voltage AVDD
  • a processing module configured to detect the first power supply voltage AVDD
  • a reset control signal por_rstf and the second reset control signal pdr_rstf are operated to obtain a target reset control signal power_rstf, and the target reset control signal power_rstf is used to control circuit reset.
  • this embodiment of the present application also provides a schematic diagram of an electronic device 300.
  • the electronic device 300 includes a device body 310 and the above-mentioned integrated circuit 200. Among them, the integrated circuit 200 is provided in the device body 310 .
  • the electronic device includes a first detection module POR configured to detect the first power supply voltage AVDD and the second power supply voltage DVDD, and output based on the first power supply voltage AVDD and the second power supply voltage DVDD.
  • the first reset control signal por_rstf and the second reset control signal pdr_rstf are operated to obtain a target reset control signal power_rstf, and the target reset control signal power_rstf is used to control circuit reset.
  • users can flexibly configure it according to actual application needs, and can support multi-power domain systems to be powered on in any order.

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Abstract

本申请提供了一种电源检测复位电路，包括第一检测模块，被配置为检测第一电源电压、第二电源电压，并基于所述第一电源电压和所述第二电源电压输出第一复位控制信号；第二检测模块，被配置为检测所述第一电源电压，并基于所述第一电源电压输出第二复位控制信号；处理模块，被配置为对所述第一复位控制信号和所述第二复位控制信号进行运算，得到目标复位控制信号，所述目标复位控制信号用于控制电路复位。在多电源域系统中，用户可根据实际应用需求灵活配置，可以支持多电源域系统任意顺序上电。

Description

一种电源检测复位电路、集成电路及电子设备
本申请要求于2022年3月17日提交中国专利局、申请号为202210265884.8，申请名称为″一种电源检测复位电路、集成电路及电子设备″的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子电路技术领域，尤其涉及一种电源检测复位电路、集成电路及电子设备。
背景技术
对于集成电路来说，上电复位模块是比较重要的模块。当电源电压过低时，芯片内部模拟模块可能无法正常稳定工作，数字电路可能也无法正常运转，导致系统出现死机现象。上电复位模块可实现当电源电压低于系统正常工作所需要的电压时，传递一个复位信号给各个模块，待电源达到期望值之后，再进行解复位。同时，当电源电压掉电到系统最小稳定工作电压时，上电复位模块也会生成复位信号关闭相关模块使能位。
在很多系统应用中，电源域系统多分为单电源系统和多电源系统。单电源系统中，上电复位模块不用设计得很复杂，大多数只需要一个自检测模块就可以满足系统要求。而多电源域系统中，需要固定电源上电顺序，在用户使用时受到限制，影响用户使用体验。
发明内容
基于此，本申请提供了一种电源检测复位电路、集成电路及电子设备，解决了多电源上电时因需要限制上电顺序而导致用户受到使用场景限制的问题。
本申请的技术方案如下：
本申请提供的一种电源检测复位电路，包括
第一检测模块，被配置为检测第一电源电压、第二电源电压，并基于所述第一电源电压和所述第二电源电压输出第一复位控制信号；
第二检测模块，被配置为检测所述第一电源电压，并基于所述第一电源电压输出第二复位控制信号；
处理模块，被配置为对所述第一复位控制信号和所述第二复位控制信号进行运算，得到目标复位控制信号，所述目标复位控制信号用于控制电路复位。
在一些实施例中，所述第一检测模块具体被配置为：
在第一电源、第二电源上电时，当所述第二电源电压未达到所述第一检测模块预设的阈值，所述第一检测模块输出的所述第一复位控制信号跟随所述第一电源电压，所述第一 复位控制信号为第一电平；当所述第二电源电压达到所述第一检测模块预设的阈值，所述第一检测模块输出的所述第一复位控制信号为第二电平。
在一些实施例中，所述第二检测模块具体被配置为：
当所述第一电源电压未达到所述第二检测模块预设的阈值时，所述第二复位控制信号跟随所述第一电源电压，所述第二复位控制信号为第三电平；当所述第一电源电压达到所述第二检测模块预设的阈值，所述第二复位控制信号为第四电平。
在一些实施例中，所述电源检测复位电路还包括第一逻辑控制单元，所述第一逻辑控制单元的输入端用于接收第一输入信号、第二输入信号，其中，所述第二输入信号为所述第一复位控制信号；所述第一逻辑控制单元被配置为：
当所述第一输入信号置为低电平时，所述第一逻辑控制单元输出高电平以控制所述第二检测模块工作，所述第二检测模块常开；
当所述第一输入信号置为高电平时，所述第一逻辑控制单元受控于所述第一复位信号而输出能够控制所述第二检测模块工作的信号；当所述第二电源电压未达到所述第一检测模块预设的阈值时，开启所述第二检测模块，当所述第二电源电压达到所述第一检测模块预设的阈值后，关闭所述第二检测模块。
在一些实施例中，所述电源检测复位电路还包括：
电压监测单元，被配置为在第一电源和第二电源上电完成前，监测所述第一复位控制信号和所述第二复位控制信号是否跟随所述第一电源电压；若所述第一复位控制信号和所述第二复位控制信号没有跟随所述第一电源电压，则所述电压监测单元生成所述第一电源电压跟随信号传输至所述处理模块。
在一些实施例中，所述电源检测复位电路还包括：
第二逻辑控制单元，被配置为对所述目标复位控制信号进行电平转换，输出第二目标复位控制信号，所述第二目标复位控制信号用于控制电路复位。
在一些实施例中，所述电源检测复位电路还包括：
延时单元，被配置为将所述处理模块输出的所述目标复位控制信号延时传输至所述第二逻辑控制单元。
在一些实施例中，所述电源检测复位电路还包括：
电池电源检测模块，被配置为检测第三电源电压，并基于所述第三电源电压输出第三复位控制信号，并将第三复位控制信号传输至所述第二逻辑控制单元进行电平转换。
在一些实施例中，所述电池电源检测模块还被配置为：
当所述第三电源电压未达到电池电源检测模块预设的阈值时，输出第五电平的所述第三复位控制信号；
当所述第三电源电压达到电池电源检测模块预设的阈值时，输出第六电平的所述第三 复位控制信号；
所述第三复位控制信号用于控制电路复位。
在一些实施例中，所述电源检测复位电路还包括：
可编程电压检测模块，所述可编程电压检测模块对所述第一检测模块的掉电阈值进行编程控制。
在一些实施例中，所述可编程电压检测模块与所述第一检测模块集成在一起。
在一些实施例中，所述第一检测模块，包括第一电源接口、第二电源接口、第一电阻串、第一电路连接控制模块、第一比较模块和第一电容，所述第一电源接口用于连接第一电源，所述第二电源接口用于连接第二电源，所述第一电阻串连接所述第一电源接口、第二电源接口，所述第一电路连接控制模块连接所述第一电阻串，所述第一比较模块连接所述第一电路连接控制模块，所述第一电容连接于所述第一电路连接控制模块与所述第一比较模块之间；所述第一比较模块输出所述第一复位控制信号。
在一些实施例中，所述第二检测模块，包括第二电阻串、第二电路连接控制模块、第二比较模块和第二电容，所述第二电阻串连接所述第一比较模块，所述第二电路连接控制模块连接所述第二电阻串，所述第二比较模块连接所述第二电路连接控制模块，所述第二电容连接于所述第二电路连接控制模块与所述第二比较模块之间，所述第二比较模块输出所述第二复位控制信号。
在一些实施例中，所述可编程电压检测模块，包括第三电阻串、阈值等级选择模块、第三比较模块和第三电容，所述第三电阻串连接所述第一电阻串，所述阈值等级选择模块连接所述第三电阻串，所述第三比较模块连接所述阈值等级选择模块，所述第三电容连接于所述阈值等级选择模块与所述第三比较模块之间，所述第三比较模块输出对所述第一检测模块的掉电阈值进行编程控制信号。
在一些实施例中，所述第二逻辑控制单元包括：第一逻辑非门模块、电平转换模块、防漏电模块与第二逻辑非门模块；
所述第一逻辑非门模块连接于所述延时单元，所述电平转换模块连接于所述第一逻辑非门模块，所述防漏电模块连接于所述电平转换模块，所述第二逻辑非门模块连接于所述防漏电模块，所述第二逻辑非门模块输出第二目标复位控制信号和第三目标复位控制信号。
本申请提供的一种集成电路，包括上述的电源检测复位电路。
本申请提供的一种电子设备，包括设备主体以及设于所述设备主体内的如上所述的集成电路。
本申请提供的电源检测复位电路、集成电路及电子设备，可实现在多电源域系统中，用户能够根据实际应用需求灵活配置，从而支撑多电源域系统任意顺序上电。进一步地， 根据用户实际应用需求，所述第一逻辑控制单元可以控制所述第二检测模块打开或者关闭，降低了系统功耗。同时可编程电压检测模块电路支持第一检测模块的掉电阈值可编程控制。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施例提供的一种的电源检测复位电路框图；
图2为本申请第一实施例提供的一种的电源检测复位电路结构示意图；
图3为图1中第一检测模块一种电路示意图；
图4为图1中第二检测模块一种电路示意图；
图5为本申请第二实施例提供的一种电源检测复位电路框图；
图6为本申请第二实施例提供的一种电源检测复位电路结构示意图；
图7为图5中第一逻辑控制单元的逻辑功能示意图；
图8为本申请实施例提供的一种电源检测复位电路框图；
图9为本申请实施例提供的一种电源检测复位电路结构示意图；
图10为图8中电压监测单元的一种逻辑功能示意图；
图11为本申请实施例提供的一种电源检测复位电路框图；
图12为本申请实施例提供的一种电源检测复位电路结构示意图；
图13为图11中第二逻辑控制单元的一种电路示意图；
图14为本申请实施例提供的一种电源检测复位电路框图；
图15为本申请实施例提供的一种电源检测复位电路结构示意图；
图16为本申请实施例提供的一种电源检测复位电路框图；
图17为本申请实施例提供的一种电源检测复位电路结构示意图；
图18为本申请实施例提供的一种电源检测复位电路框图；
图19为本申请实施例提供的一种电源检测复位电路结构示意图；
图20为可编程电压检测模块PVD与第一检测模块POR集成在一起的电路示意图；
图21为第一电源AVDD先上电复位逻辑示意图；
图22为第二电源电压DVDD先上电复位逻辑示意图；
图23为本申请实施例提供的一种集成电路示意图；
图24为本申请实施例提供的一种电子设备示意图。
具体实施方式
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同；本文中在申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请；本申请的说明书和权利要求书及上述附图说明中的术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。本申请的说明书和权利要求书或上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
为了使本申请的目的、技术方案及优点更加清楚明白，下面结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明的是，在后续的描述中，使用用于表示元件的诸如“模块”、“部件”或“单元”的后缀仅为了有利于本申请的说明，其本身并没有特定的意义。
本申请第一实施例提供的一种的电源检测复位电路框图如图1所示，第一实施例提供的一种的电源检测复位电路结构示意图如图2所示，所述电源检测复位电路包括：
第一检测模块POR，被配置为检测第一电源电压AVDD、第二电源电压DVDD，并基于所述第一电源电压AVDD和所述第二电源电压DVDD输出第一复位控制信号por_rstf；
其中，作为一种示例，第一检测模块POR的一种电路示意图如图3所示，包括第一电源接口、第二电源接口、第一电阻串、第一电路连接控制模块、第一比较模块和第一电容，其中第一电源接口用于接收第一电源电压AVDD，第二电源接口用于接收第二电源电压DVDD，第一电阻串包括第一电阻R11、第二电阻R12、第三电阻R13，第一电路连接控制模块包括开关S11、开关S12，第一电阻R11的一端用于接收第二电源电压DVDD，第一电阻R11的另一端通过串联的第二电阻R12、第三电阻R13接地。开关S11一端连接在第一电阻R11和第二电阻R12之间，一端连接在第一比较模块第一输入端，开关S12一端连接在第二电阻R12和第三电阻R13之间，一端连接在第一比较模块第一输入端，第一比较模块的第二输入端用于接收第一参考电压VBG1，第一比较模块用于检测第一电阻R11与第二电阻R12的连接节点处的电压并将其与第一参考电压VBG1进行比较，或者检测第二电阻R12与第三电阻R13的连接节点处的电压并将其与第一参考电压VBG1进行比较。在第二电源上电过程中，第一比较模块的第一输入端的电压随第二电源电压DVDD上升， 当第一比较模块的第一输入端的电压大于或等于第一参考电压时，第一比较模块输出的第一复位控制信号por_rstf可以发生翻转，例如从第一电平翻转为第二电平。其中，第一电容的一端连接在开关S11、开关S12与第一比较模块之间，第一电容的另一端接地。第一比较模块还连接第一电源以将第一电源电压AVDD作为供电电压。可选地，第一电阻串中的电阻数量可以增加或减少，相应地第一电路连接控制模块中的开关数量也可以增加或减少。第一电阻串中每相邻两个电阻之间的连接节点可分别通过开关连接到第一比较模块的第一输入端。可以理解，在本示例中，各元器件的连接关系可以是直接连接或间接连接。例如，第一电阻串的一端可以是直接连接于第二电源接口或通过其他元器件间接地连接于第二电源接口，第一电阻串的另一端也可以是直接接地或通过其他元器件间接接地。
第二检测模块PDR，被配置为检测所述第一电源电压AVDD，并基于所述第一电源电压AVDD输出第二复位控制信号pdr_rstf。其中，作为一种示例，所述第二检测模块PDR的一种电路示意图如图4所示，包括第二电阻串、第二电路连接控制模块、第二比较模块和第二电容，其中，第二电阻串包括第四电阻R21、第五电阻R22、第六电阻R23，第二电路连接控制模块包括开关S21、开关S22。所述第四电阻R21的一端用于接收所述第一电源电压AVDD，所述第五电阻R22连接所述第四电阻R21，所述第六电阻R23连接所述第五电阻R22，所述第六电阻R23接地，所述开关S21一端连接在所述第四电阻R21和所述第五电阻R22之间，一端连接在第二比较模块第一输入端，所述开关S22一端连接在所述第五电阻R22和所述第六电阻R23之间，一端连接在第二比较模块第一输入端，第二比较模块的第二输入端用于接收第二参考电压VBG2，第二比较模块用于检测第四电阻R21与第五电阻R22的连接节点处的电压并将其与第二参考电压VBG2进行比较，或者检测第五电阻R22与第六电阻R23的连接节点处的电压并将其与第二参考电压VBG2进行比较。在第一电源上电过程中，第二比较模块的第一输入端的电压随第一电源电压AVDD上升，当第二比较模块的第一输入端的电压大于或等于第二参考电压时，第二比较模块输出的第二复位控制信号por_rstf可以发生翻转，例如从第三电平翻转为第四电平。其中，第一电容的一端连接开关S21、开关S22与第二比较器之间，第二电容的另一端接地。可选地，第二电阻串中的电阻数量可以增加或减少，相应地第二电路连接控制模块中的开关数量也可以增加或减少。第二电阻串中每相邻两个电阻之间的连接节点可分别通过开关连接到第二比较模块的第一输入端。可以理解，在本示例中，各元器件的连接关系可以是直接连接或间接连接。例如，第二电阻串的一端可以是直接连接于第一电源接口或通过其他元器件间接地连接于第一电源接口，第二电阻串的另一端也可以是直接接地或通过其他元器件间接接地。
处理模块，被配置为对所述第一复位控制信号por_rstf和所述第二复位控制信号pdr_rstf进行运算，得到目标复位控制信号power_rstf，所述目标复位控制信号power_rstf 用于控制电路复位。
作为一种实施方式，将第一复位控制信号por_rstf和所述第二复位控制信号pdr_rstf进行与非处理，然后将与非处理后的信号进行非处理，得到控制电路的目标复位信号power_rstf。
在一些实施例中，第一检测模块POR被配置为：在第一电源、第二电源上电时，当第二电源电压未达到第一检测模块预设的阈值，第一检测模块输出的第一复位控制信号跟随第一电源电压，第一复位控制信号为第一电平；当第二电源电压达到第一检测模块预设的阈值，第一检测模块输出的第一复位控制信号为第二电平。具体地，以第一电平为低电平、第二电平为高电平为例，结合图3，在第一电源、第二电源上电时，开关S11断开，开关S12闭合，当所述第二电源电压DVDD未达到所述第一检测模块POR预设的阈值时，第一比较模块中的比较器COM0的第一输入端电压小于第一参考电压VBG1，所述第一检测模块POR输出的所述第一复位控制信号por_rstf跟随所述第一电源AVDD电压，此时第一复位控制信号por_rstf为高电平，电路处于上电复位状态；当所述第二电源DVDD电压达到所述第一检测模块POR预设的阈值时，即比较器COM0的第一输入端电压达到第一参考电压VBG1时，比较器COM0输出的第一复位控制信号por_rstf翻转为低电平，上电复位释放，电路开始进入工作状态。控制开关S11闭合，开关S12断开，使比较器COM0的第一输入端电压保持大于第一参考电压VBG1，从而使电路保持在正常工作状态。
在一些实施例中，第二检测模块PDR被配置为：当第一电源电压未达到第二检测模块预设的阈值时，第二复位控制信号跟随第一电源电压，第二复位控制信号为第三电平；当第一电源电压达到所述第二检测模块预设的阈值，所述第二复位控制信号为第四电平。具体地，以第三电平为高电平、第四电平为低电平为例，结合图4，在第一电源上电时，开关S21断开，开关S22闭合，当所述第一电源电压AVDD未达到所述第二检测模块PDR预设的阈值时，第二比较模块中的比较器COM1的第一输入端电压小于第二参考电压VBG2，所述第二复位控制信号pdr_rstf跟随所述第一电源电压AVDD，所述第二复位控制信号pdr_rstf为高电平，电路处于上电复位状态；当所述第一电源AVDD电压达到所述第二检测模块PDR预设的阈值时，即比较器COM1的第一输入端电压达到第二参考电压VBG2时，比较器COM1输出的第二复位控制信号pdr_rstf翻转为低电平，上电复位释放，电路开始进入工作状态。控制开关S21闭合，开关S22断开，使比较器COM1的第一输入端电压保持大于第二参考电压VBG2，从而使电路保持在正常工作状态。
若所述第一电源AVDD先上电，所述第二电源DVDD后上电，或者所述第一电源AVDD、第二电源DVDD同时上电，则所述第一电源AVDD上电到所述第二检测模块PDR复位释放预设的阈值之前，所述第二复位控制信号pdr_rstf跟随所述第一电源AVDD，达到阈值后输出低电平；当所述第二电源DVDD上电到所述第一检测模块POR复位释放阈 值之前，所述第一复位控制信号por_rstf跟随所述第一电源AVDD，达到阈值后输出低电平。第一复位控制信号por_rstf和第二复位控制信号pdr_rstf经过或逻辑处理产生控制电路复位的目标复位控制信号power_rstf，目标复位控制信号power_rstf用于对AVDD电源域与DVDD电源域的电路进行复位控制。
若当所述第二电源DVDD先上电，所述第一电源AVDD后上电，所述第一复位控制信号por_rstf将一直保持为低电平，所述第一电源AVDD上电完成之前，所述第二复位控制信号pdr_rstf跟随所述第一电源AVDD，待所述第一电源AVDD上电完成后，所述第二复位控制信号pdr_rstf输出低电平。第一复位控制信号por_rstf和第二复位控制信号pdr_rstf经过或逻辑处理产生控制电路复位的目标复位控制信号power_rstf，目标复位控制信号power_rstf用于对电路进行复位控制。
因此，本申请实施例可以支持第一电源和第二电源以任意顺序上电。
在一个可选的实施方式中，如图5所示为一种电源检测复位电路框图，如图6所示为与图5对应的一种电源检测复位电路结构示意图，所述电源检测复位电路还包括第一逻辑控制单元Logic1，所述第一逻辑控制单元Logic1的输入端用于接收第一输入信号pdr_enb和第二输入信号，其中，所述第二输入信号为所述第一复位控制信号por_rstf；被配置为控制所述第二检测模块PDR打开或关闭，包括：
当所述第一输入信号pdr_enb置为低电平时，所述第一逻辑控制单元Logic1输出高电平以控制所述第二检测模块PDR工作，所述第二检测模块常开；
当第一输入信号pdr_enb置为高电平时，所述第一逻辑控制单元Logic1根据所述第一复位信号por_rstf输出用于控制所述第二检测模块PDR工作的信号；当所述第二电源电压DVDD未达到所述第一检测模块POR预设的阈值时，开启所述第二检测模块PDR，当所述第二电源DVDD电压达到所述第一检测模块POR预设的阈值后，关闭所述第二检测模块PDR。
如图7所示为第一逻辑控制单元Logic1的逻辑功能示意图，若所述第一电源AVDD先上电，所述第二电源DVDD后上电，或者所述第一电源AVDD、第二电源DVDD同时上电，则将所述第一逻辑控制单元Logic1的第一输入信号pdr_enb置为高电平，控制所述第二检测模块PDR的信号pdr_en跟随所述第一复位控制信号por_rstf，当所述第二电源电压DVDD未达到所述第一检测模块POR预设的阈值时，开启所述第二检测模块PDR，当所述第二电源电压DVDD达到所述第一检测模块POR预设的阈值后，关闭所述第二检测模块PDR，降低功耗。
若当所述第二电源DVDD先上电，所述第一电源AVDD后上电，则将所述第一逻辑控制单元Logic1的第一输入信号pdr_enb置为低电平，控制所述第二检测模块PDR的信号pdr_en为高电平，所述第二检测模块PDR处于常开状态。
在一个可选的实施方式中，如图8所示为一种电源检测复位电路框图，如图9所示为一种电源检测复位电路结构示意图，所述电源检测复位电路还包括：
电压监测单元Monitor，被配置为在第一电源AVDD和第二电源DVDD上电完成前，监测所述第一复位控制信号por_rstf和所述第二复位控制信号pdr_rstf是否跟随所述第一电源电压AVDD；若所述第一复位控制信号por_rstf和所述第二复位控制信号pdr_rstf没有跟随所述第一电源电压AVDD，则所述电压监测单元Monitor生成第一电源电压跟随信号avdd_monitor，并传输至所述处理模块。
其中，所述第一复位控制信号por_rstf和所述第二复位控制信号pdr_rstf可以先通过与非门处理，接着通过非门处理。
如图10所示为电压监测单元Monitor逻辑功能示意图，所述电压监测单元Monitor是用于监测所述第一复位控制信号por_rstf和所述第二复位控制信号pdr_rstf是否跟随所述第一电源电压AVDD；在第一电源AVDD、第二电源DVDD上电，所述第一检测模块POR和所述第二检测PDR复位释放之前，即在图10中t1之前，所述第一检测模块POR和所述第二检测PDR的输出信号理论上应该跟随所述第一电源电压AVDD，但是在实际中可能会出现所述第一电源电压AVDD、第二电源电压DVDD上电到了系统正常工作所需要的电压，但所述第一检测模块POR和所述第二检测PDR的输出信号依旧保持在低电平，这时系统可能会出现复位释放→复位→复位释放三个过程；在第一电源AVDD和第二电源DVDD上电完成前，若所述电压监测单元Monitor是监测到所述第一复位控制信号por_rstf和所述第二复位控制信号pdr_rstf没有跟随所述第一电源AVDD电压；则所述电压监测单元Monitor就会输出几乎完全跟随所述第一电源电压AVDD的第一电源电压AVDD跟随信号avdd_monitor，避免系统出现系统可能的出现复位释放→复位→复位释放三个过程。
在一个可选的实施方式中，如图11所示为一种电源检测复位电路框图，如图12所示为一种电源检测复位电路结构示意图，所述电源检测复位电路还包括：
第二逻辑控制单元Logic2，被配置为对所述目标复位控制信号power_rstf进行电平转换，输出第二目标复位控制信号dvdd_rstf，第二目标复位控制信号dvdd_rstf用于对AVDD电源域与DVDD电源域的电路进行复位控制。
进一步地，如图13所示，优选的第二逻辑控制单元Logic2包括：第一逻辑非门模块，电平转换模块，防漏电模块，第二逻辑非门模块。
一些示例中，所述第一逻辑非门模块包括第一逻辑非门1、第二逻辑非门2、第三逻辑非门3、第四逻辑非门4；所述防漏电模块包括NMOS管M1、M2、M4、M5、M8、M9、M13、M14、M15；PMOS管M3、M6、M7、M11、M12、M16；所述第二逻辑非门模块包括第五逻辑非门5、第六逻辑非门6。
所述第一逻辑非门1的输入端为所述目标复位信号power_rstf，输出端连接所述第二 逻辑非门2、所述NMOS管M1的栅极、所述NMOS管M4的栅极和所述PMOS管M7的栅极；
所述第二逻辑非门2的输出端连接所述第一电平转换模块7；
所述第一电平转换模块7的输出端连接所述NMOS管M2的栅极和所述PMOS管M3的栅极；
所述NMOS管M1的源级和所述NMOS管M4的源级接地；所述PMOS管M7的漏极连接所述第五逻辑非门5的输入端；
所述NMOS管M2的漏极和所述PMOS管M3的漏极连接所述PMOS管M6的栅极和NMOS管M5的栅极；
所述NMOS管M2的源级连接所述NMOS管M1的漏极；
所述NMOS管M5的漏极和所述PMOS管M6的漏极连接所述第五逻辑非门5；
所述NMOS管M5的源极连接所述NMOS管M4的漏极；
所述PMOS管M3的源级、PMOS管M6的源级和PMOS管M7的源级相互连接；
所述第五逻辑非门5的输出端为第二目标复位控制信号avdd_rstf；
所述第三逻辑非门3输入端为为所述目标复位信号power_rstf，输出端连接所述第四逻辑非门4、所述NMOS管M8的栅极、所述NMOS管M15的栅极和所述PMOS管M16的栅极；
所述第四逻辑非门4的输出端连接所述第二电平转换模块8；
所述第二电平转换模块8输出端连接所述NMOS管M9的栅极和所述PMOS管M10的栅极；
所述NMOS管M8的源级和所述NMOS管M15的源级接地；
所述NMOS管M9的源级连接所述NMOS管M8的漏极；
所述NMOS管M9的漏极和所述PMOS管M10的漏极连接；
所述NMOS管M9的漏极和所述PMOS管M10的漏极连接所述PMOS管M11的栅极和NMOS管M14的栅极；
所述PMOS管M11的漏极连接所述第六逻辑非门6的输入端；
所述NMOS管M14的源级连接所述NMOS管M15的漏极；
所述PMOS管M16的漏极连接所述第六逻辑非门6的输入端；
所述NMOS管M13的源级连接所述NMOS管M14的漏极；
所述PMOS管M12和所述NMOS管M13的输入端均为第三复位控制信号；
所述PMOS管M12的漏极连接所述NMOS管M13的漏极；
所述PMOS管M10的源级、PMOS管M11的源级、PMOS管M12的源级和PMOS管M16的源级相互连接；
所述第六逻辑非门6的输出第三目标复位控制信号。
若所述第一电源AVDD先上电，所述第二电源DVDD后上电，或者所述第一电源AVDD、第二电源DVDD同时上电，将所述第一逻辑控制单元Logic1的第一输入信号pdr_enb置为高电平，则在所述目标复位信号power_rstf复位释放之前，所述第一逻辑非门1输出的信号S1为低电平，所述第三逻辑非门3输出的信号S3为低电平，控制NMOS管M1、M4、M8、M15关闭和弱上拉PMOS管M7、M16导通，第二目标复位控制信号dvdd_rstf保持为低电平。则当所述目标复位信号power_rstf复位释放后，第二目标复位控制信号dvdd_rstf跟随所述第二电源DVDD电压。
若当所述第二电源DVDD先上电，所述第一电源AVDD后上电，将所述第一逻辑控制单元Logic1的第一输入信号pdr_enb置为低电平，则在所述第一电源AVDD上电之前，所述第一逻辑非门1输出的信号S1、第二逻辑非门2输出的信号S2、第三逻辑非门3输出的信号S3和第四逻辑非门4输出的信号S4均为低电平，控制NMOS管M1、M4、M8、M15关闭和弱上拉PMOS管M7、M16导通，以避免因所述第一电平转换模块7和所述第二电平转换模块8输出浮空导致所述第二逻辑控制单元Logic2漏电较大，第二目标复位控制信号dvdd_rstf保持为低电平。则当所述目标复位信号power_rstf复位释放后，所述第一逻辑非门1输出的信号S1、第三逻辑非门3输出的信号S3被上拉到高电平，控制NMOS管M1、M4、M8、M15导通，第二目标复位控制信号dvdd_rstf输出为高电平。
在一个可选的实施例中，如图14所示为一种电源检测复位电路框图，如图15所示为一种电源检测复位电路结构示意图，所述电源检测复位电路还包括：
延时单元Delay，被配置为对所述处理模块的所述目标复位控制信号power_rstf延时，将延时的目标复位控制信号por_delay传输至所述第二逻辑控制单元Logic2。通过所述延时单元Delay可以保证目标复位控制信号power_rstf传递给系统各模块时电源电压已经达到比较高的水平，可以正常运行。可选地，延时单元的延时时间可以是若干ms。作为一种示例，延时时间可以为3ms。
在一个可选的实施方式中，如图16所示为一种电源检测复位电路框图，如图17所示为一种电源检测复位电路结构示意图，所述电源检测复位电路还包括：
电池电源检测模块VBAT_POR，被配置为检测第三电源VBAT电压，并基于所述第三电源VBAT电压输出第三复位控制信号vbat_rstn，并将第三复位控制信号vbat_rstn传输至所述第二逻辑控制单元Logic2以进行电平转换，电平转换后的第三复位控制信号为vbat_rstf，用于对VBAT电源域的电路进行控制。
基于所述第三电源VBAT电压输出第三复位控制信号vbat_rstn包括：
当所述第三电源VBAT电压未达到电池电源检测模块VBAT_POR预设的阈值时，所述第三复位控制信号vbat_rstn为高电平，上电复位释放；
当所述第三电源VBAT电压达到电池电源检测模块VBAT_POR预设的阈值时，所述第三复位控制信号vbat_rstn为低电平，上电复位。
所述第三复位控制信号vbat_rstn输入所述PMOS管M12和所述NMOS管M13的栅极，所述第六逻辑非门的输出第三目标复位控制信号vbat_rstf。
若所述第一电源AVDD先上电，所述第二电源DVDD后上电，或者所述第一电源AVDD、第二电源DVDD同时上电，将所述第一逻辑控制单元Logic1的第一输入信号pdr_enb置为高电平，当第三电源VBAT在第二电源DVDD之前上电完成，则在则在所述目标复位信号power_rstf复位释放之前，PMOS管M12管导通，所述PMOS管M11、M16输出的信号L4跟随所述第三电源VBAT电压，第三目标复位控制信号vbat_rstf保持低电平。当所述第一电源AVDD和所述电源DVDD都上电完成复位释放后，所述NMOS管M8、M15打开，第三目标复位控制信号vbat_rstf被上拉到高电平；当所述第三电源VBAT在所述第二电源DVDD之后上电，所述NMOS管M8、M15在所述第三复位控制信号vbat_rstn复位释放之前就已经打开，所述第二电平转换模块8输出低电平，所述NMOS管M9和所述PMOS管M10输出的信号L3被上拉到高电平，所述NMOS管M14导通，电池电源检测模块VBAT_POR输出的第三复位控制信号vbat_rstn可直接传递。
若当所述第二电源DVDD先上电，所述第一电源AVDD后上电，将所述第一逻辑控制单元Logic1的第一输入信号pdr_enb置为低电平，当第三电源VBAT在第二电源DVDD之前上电完成，则在则在所述目标复位信号power_rstf复位释放之前，PMOS管M12管导通，所述PMOS管M11、M16输出的信号L4跟随所述第三电源VBAT电压，第三目标复位控制信号vbat_rstf保持低电平。当所述第一电源AVDD和所述电源DVDD都上电完成复位释放后，所述NMOS管M8、M15打开，第三目标复位控制信号vbat_rstf被上拉到高电平；当所述第三电源VBAT在所述第二电源DVDD之后上电，所述NMOS管M8、M15在所述第三复位控制信号vbat_rstn复位释放之前就已经打开，所述第二电平转换模块8输出低电平，所述NMOS管M9和所述PMOS管M10输出的信号L3被上拉到高电平，所述NMOS管M14导通，电池电源检测模块VBAT_POR输出的第三复位控制信号vbat_rstn可直接传递。
在一个可选的实施例中，如图18所示为一种电源检测复位电路框图，如图19所示为一种电源检测复位电路结构示意图，所述电源检测复位电路还包括：
可编程电压检测模块PVD，所述可编程电压检测模块PVD对所述第一检测模块POR的掉电阈值进行编程控制。
进一步地，所述可编程电压检测模块PVD与所述第一检测模块POR集成在一起。
如图20所示为可编程电压检测模块PVD与第一检测模块POR集成在一起的电路示意图。所述可编程电压检测模块PVD，包括第三电阻串、阈值等级选择模块、第三比较模 块和第三电容，所述第三电阻串连接所述第一电阻串，所述阈值等级选择模块连接所述第三电阻串，所述第三比较模块连接所述阈值等级选择模块，所述第三电容连接于所述阈值等级选择模块与所述第三比较模块之间，所述第三比较模块输出对所述第一检测模块的掉电阈值进行编程控制信号。其中，第三电阻串包括多个互相串联的电阻，每相邻两个电阻之间的连接节点为一个分压节点，即第三电阻串中包括一个或多个分压节点。在本实施例中选择阈值等级选择模块为选择器，通过选择器连接到第三电阻串的不同分压节点以选择对应的阈值，用户可以根据实际需要选择一个阈值作为第一检测模块的掉电阈值。
如图21所示为第一电源AVDD先上电复位逻辑示意图，如图22所示为第二电源电压DVDD先上电复位逻辑示意图。
如图23所示，本申请实施例还提供了一种集成电路200的示意图，该集成电路200包括上述的电源检测复位电路100。
本申请实施例提供的集成电路包括第一检测模块POR，被配置为检测第一电源电压AVDD、第二电源电压DVDD，并基于所述第一电源电压AVDD和所述第二电源电压DVDD输出第一复位控制信号por_rstf；第二检测模块PDR，被配置为检测所述第一电源电压，并基于所述第一电源电压AVDD输出第二复位控制信号pdr_rstf；处理模块，被配置为对所述第一复位控制信号por_rstf和所述第二复位控制信号pdr_rstf进行运算，得到目标复位控制信号power_rstf，所述目标复位控制信号power_rstf用于控制电路复位。在多电源域系统中，用户可根据实际应用需求灵活配置，可以支撑多电源域系统任意顺序上电。
如图24所示，本申请实施例还提供一种电子设备300的示意图，该电子设备300包括设备主体310以及上述的集成电路200。其中，集成电路200设于设备主体310内。
本申请实施例提供的电子设备，包括第一检测模块POR，被配置为检测第一电源电压AVDD、第二电源电压DVDD，并基于所述第一电源电压AVDD和所述第二电源电压DVDD输出第一复位控制信号por_rstf；第二检测模块PDR，被配置为检测所述第一电源电压，并基于所述第一电源电压AVDD输出第二复位控制信号pdr_rstf；处理模块，被配置为对所述第一复位控制信号por_rstf和所述第二复位控制信号pdr_rstf进行运算，得到目标复位控制信号power_rstf，所述目标复位控制信号power_rstf用于控制电路复位。在多电源域系统中，用户可根据实际应用需求灵活配置，可以支撑多电源域系统任意顺序上电。
以上所述的仅是本申请的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本申请创造构思的前提下，还可以做出改进，但这些均属于本申请的保护范围。

Claims (17)

  1. 一种电源检测复位电路，其中，包括
    第一检测模块，被配置为检测第一电源电压、第二电源电压，并基于所述第一电源电压和所述第二电源电压输出第一复位控制信号；
    第二检测模块，被配置为检测所述第一电源电压，并基于所述第一电源电压输出第二复位控制信号；
    处理模块，被配置为对所述第一复位控制信号和所述第二复位控制信号进行运算，得到目标复位控制信号，所述目标复位控制信号用于控制电路复位。
  2. 根据权利要求1所述的一种电源检测复位电路，其中，所述第一检测模块具体被配置为：
    在第一电源、第二电源上电时，当所述第二电源电压未达到所述第一检测模块预设的阈值，所述第一检测模块输出的所述第一复位控制信号跟随所述第一电源电压，所述第一复位控制信号为第一电平；当所述第二电源电压达到所述第一检测模块预设的阈值，所述第一检测模块输出的所述第一复位控制信号为第二电平。
  3. 根据权利要求1所述的一种电源检测复位电路，其中，所述第二检测模块具体被配置为：
    当所述第一电源电压未达到所述第二检测模块预设的阈值时，所述第二复位控制信号跟随所述第一电源电压，所述第二复位控制信号为第三电平；当所述第一电源电压达到所述第二检测模块预设的阈值，所述第二复位控制信号为第四电平。
  4. 根据权利要求1所述的一种电源检测复位电路，其中，所述电源检测复位电路还包括第一逻辑控制单元，所述第一逻辑控制单元的输入端用于接收第一输入信号、第二输入信号，其中，所述第二输入信号为所述第一复位控制信号；所述第一逻辑控制单元被配置为：
    当所述第一输入信号置为低电平时，所述第一逻辑控制单元输出高电平以控制所述第二检测模块工作，所述第二检测模块常开；
    当所述第一输入信号置为高电平时，所述第一逻辑控制单元根据所述第一复位信号输出用于控制所述第二检测模块工作的信号；当所述第二电源电压未达到所述第一检测模块预设的阈值时，开启所述第二检测模块，当所述第二电源电压达到所述第一检测模块预设的阈值后，关闭所述第二检测模块。
  5. 根据权利要求4所述的一种电源检测复位电路，其中，所述电源检测复位电路还包括：
    电压监测单元，被配置为在第一电源和第二电源上电完成前，监测所述第一复位控制信号和所述第二复位控制信号是否跟随所述第一电源电压；若所述第一复位控制信号和所述第二复位控制信号没有跟随所述第一电源电压，则所述电压监测单元生成所述第一电源电压跟随信号传输至所述处理模块。
  6. 根据权利要求5所述的一种电源检测复位电路，其中，所述电源检测复位电路还包括：
    第二逻辑控制单元，被配置为对所述目标复位控制信号进行电平转换，输出第二目标复位控制信号，所述第二目标复位控制信号用于控制电路复位。
  7. 根据权利要求6所述的一种电源检测复位电路，其中，所述电源检测复位电路还包括：
    延时单元，被配置为将所述处理模块输出的所述目标复位控制信号延时传输至所述第二逻辑控制单元。
  8. 根据权利要求6所述的一种电源检测复位电路，其中，所述电源检测复位电路还包括：
    电池电源检测模块，被配置为检测第三电源电压，并基于所述第三电源电压输出第三复位控制信号，并将第三复位控制信号传输至所述第二逻辑控制单元进行电平转换。
  9. 根据权利要求8所述的一种电源检测复位电路，其中，所述电池电源检测模块还被配置为：
    当所述第三电源电压未达到电池电源检测模块预设的阈值时，输出第五电平的所述第三复位控制信号；
    当所述第三电源电压达到电池电源检测模块预设的阈值时，输出第六电平的所述第三复位控制信号；
    所述第三复位控制信号用于控制电路复位。
  10. 根据权利要求1所述的一种电源检测复位电路，其中，所述电源检测复位电路还包括：
    可编程电压检测模块，所述可编程电压检测模块对所述第一检测模块的掉电阈值进行编程控制。
  11. 根据权利要求10所述的一种电源检测复位电路，其中，所述可编程电压检测模块与所述第一检测模块集成在一起。
  12. 根据权利要求1所述的一种电源检测复位电路，其中，所述电源检测复位电路包括第一电源接口、第二电源接口，所述第一电源接口用于连接第一电源，所述第二电源接口用于连接第二电源；
    所述第一检测模块，包括第一电阻串、第一电路连接控制模块、第一比较模块和第一电容，所述第一电阻串的一端连接所述第二电源接口，所述第一比较模块的输入端通过所述第一电路连接控制模块连接于所述第一电阻串，所述第一电容的一端连接于所述第一电路连接控制模块与所述第一比较模块之间、所述第一电容的另一端接地；所述第一比较模 块输出所述第一复位控制信号。
  13. 根据权利要求1所述的一种电源检测复位电路，其中，所述电源检测复位电路包括第一电源接口，所述第一电源接口用于连接第一电源；
    所述第二检测模块，包括第二电阻串、第二电路连接控制模块、第二比较模块和第二电容，所述第二电阻串的一端连接所述第一电源接口，所述第二电路连接控制模块连接所述第二电阻串，所述第二比较模块通过所述第二电路连接控制模块连接于所述第二电阻串，所述第二电容的一端连接于所述第二电路连接控制模块与所述第二比较模块之间、所述第二电容的另一端接地，所述第二比较模块输出所述第二复位控制信号。
  14. 根据权利要求10所述的一种电源检测复位电路，其中，所述可编程电压检测模块，包括第三电阻串、阈值等级选择模块、第三比较模块和第三电容，所述第三电阻串连接所述第一电阻串，所述阈值等级选择模块连接所述第三电阻串，所述第三比较模块连接所述阈值等级选择模块，所述第三电容连接于所述阈值等级选择模块与所述第三比较模块之间，所述第三比较模块输出对所述第二检测模块的阈值进行编程控制信号。
  15. 根据权利要求9所述的一种电源检测复位电路，其中，所述第二逻辑控制单元包括：第一逻辑非门模块、电平转换模块、防漏电模块与第二逻辑非门模块；
    所述第一逻辑非门模块连接于所述延时单元，所述电平转换模块连接于所述第一逻辑非门模块，所述防漏电模块连接于所述电平转换模块，所述第二逻辑非门模块连接于所述防漏电模块，所述第二逻辑非门模块输出第二目标复位控制信号和第三目标复位控制信号。
  16. 一种集成电路，其中，包括权利要求1至15任一项所述的电源检测复位电路。
  17. 一种电子设备，其中，包括设备主体以及设于所述设备主体内的如权利要求16所述的集成电路。
PCT/CN2023/076125 2022-03-17 2023-02-15 一种电源检测复位电路、集成电路及电子设备 WO2023173985A1 (zh)

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CN110427089A (zh) * 2019-09-11 2019-11-08 深圳市富满电子集团股份有限公司 适用于led显示屏芯片中的上电复位系统及方法

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JP2008187475A (ja) * 2007-01-30 2008-08-14 Toshiba Corp パワーオンリセット回路
US20100156479A1 (en) * 2008-12-22 2010-06-24 Elpida Memory, Inc. Power-on reset circuit and adjusting method therefor
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